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Srinu schrieb: > Hi, > > I have one doubt : What is the need of parallelism/concurrency in the > hardware description language ? I have seen some topics which says, C > in its purest form is not suitable for the hardware description. The > main reason is lack of parallelism in C. I am new to HDLs. It will be > very nice if somebody can explain which feature of HDL really needs > parallelism support. Thanks a lot. > > > Srinivas > Hi Srinu, C is a language to describe sequential algorithms for computers. Thus it got transfered in a series of small instructions to be processed one at a time by a device we call processor. (Forget for a moment the existance of multicore processors.) This basic principle caused C just to be able to solve one problem at a time. In contrast HDLs are made to create real physical hardware. And if you want to create multiple function blocks that can work at the same time on different problems/algorithms you need a way to describe this. Verilog and VHDL offer this feature and are provided with tools that convert these descriptins into a single piece of silicon, either ASIC or FPGA. To give you an example about how important it can be to have parallel working devices take a look at my office: On my desk there are two monitors connected top two different computers. For the computers one might say they can be replaced by a faster one with two graphic cards. But for the monitors, they have to exist in parallel so I can view two independant pictures for my working purposes. No way to constantly switch the pictures on one monitor, there have to be two. Ok, this example was very simple but you can also take a look at some numbers: e.g. Cryptographic algorithms like AES. Even the fastest full speed running processor has only about 10% of the performance that can be acheived with a simple FPGA. And the FPGA saves a lot of energy compared to the CPU too. This gain in performace comes from the fact that a processor has only a single ALU and a fixed bus width, while the FPGA can use as much calculating ressources and signal lines as needed/possible. In order to do so you need a language that can describe this. And that can only be done by language elements that support concurrency. Now back to your original question: why not C for hardware design? Well, there are synthesis tools that promise to do so: Handel-C , Catapult-C. But how is that done? By extensions to the language. Either adding new functions to support concurrency and special signal types, or by using synthesis constraints. Both approches have their advantage and drawbacks, but in both cases you can't copy your sources from "numerical recipes" and expect good hardware results. You just need more than plain C. best regards EilertArticle: 115351
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:usldi6v9n.fsf@trw.com... > "EEngineer" <maricic@gmail.com> writes: > >> Is there a way of generating VHDL code from Matlab code for DSP, more >> precisely image processing using wavelet transform? >> I want to implement a small 8X8 image processing layout that will use >> wavelet transform and it is not easy to come up with the VHDL code for >> that. Any help would be highly appreciated! > > If you're targetting Xilinx AccelDSP may be of use. > Another solution could be to use Catalytic MCS which translate M-code to "Catapult compatible C" followed by Catapult which synthesises the code to VHDL. These are professional tools and as such come with the usual price tag :-) http://www.catalitic.com/product-mcs.html http://www.mentor.com/products/c-based_design/catapult_c_synthesis/index.cfm Hans www.ht-lab.com > Otherwise, write a spec, and give it to a human VHDL-code-generator > :-) > > You don't say how fast you need it to run and on what image sizes - > this may affect the feasibility of the conversion. > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technology > http://www.conekt.net/electronics.html > >Article: 115352
"EEngineer" <maricic@gmail.com> writes: > I am interested in image processing of 128x128 image using wavelet > transform compression, 12 bits per pixel, monochrome. At what sort of frame rate? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 115353
On 8 feb, 05:00, John Williams <jwilli...@itee.uq.edu.au> wrote: > Hi Pablo, > > Pablo wrote: > > download uClinux-dist > > download uClinux-2.4.x > > cd uClinux-dist > > ln -s ../uClinux-2.4.x linux-2.4.x > > copy auto-config.in to arch/microblaze/platform.... > > PATH=$PATH:/usr/local/microblaze-elf-tools > > Instead of this, I recommend you start using PetaLinux: > > http://developer.petalogix.com > > We've bundled together the kernel and dist sources, tools, BSP > generation and hardware reference designs into a single downloadable > package. > > There is lots of documentation and scripts to ease the process of > working with Embedded Linux on the MicroBlaze platform. > > I hope you find it useful. > > Regards, > > John > > > > > make clean (an error occurr with images/CVS, I have to delete > > manually) > > make menuconfig > > > I can pass this. I have an error in arch/microblaze/config.in > > > Does I need to do something else???? Thanks. Only one question. I want to use "Condition Variables" implemented in pthread.h. I have tried to use Xilkernel, but its pthread has not functions like "pthread_cond_init" or "pthread_cond_wait". Does petalinux support for this kind of functions?? Thanks again.Article: 115354
On 8 feb, 05:00, John Williams <jwilliams@itee.uq.edu.au> wrote: > Hi Pablo, > > Pablo wrote: > > download uClinux-dist > > download uClinux-2.4.x > > cd uClinux-dist > > ln -s ../uClinux-2.4.x linux-2.4.x > > copy auto-config.in to arch/microblaze/platform.... > > PATH=$PATH:/usr/local/microblaze-elf-tools > > Instead of this, I recommend you start using PetaLinux: > > http://developer.petalogix.com > > We've bundled together the kernel and dist sources, tools, BSP > generation and hardware reference designs into a single downloadable > package. > > There is lots of documentation and scripts to ease the process of > working with Embedded Linux on the MicroBlaze platform. > > I hope you find it useful. > > Regards, > > John > > > > > make clean (an error occurr with images/CVS, I have to delete > > manually) > > make menuconfig > > > I can pass this. I have an error in arch/microblaze/config.in > > > Does I need to do something else???? Sorry for the structure of my question. I am trying to explain as better as I could: I want to implement an application over a FPGA. In the app I need to use "Condition Variables" with Pthread, but Xilkernel does not support for this. So I have thought in uClinux. Could I compile my app with functions such as "pthread_cond_init", "pthread_cond_wait" over uClinux?? Thank you very much for your help.Article: 115355
Hi, I have an DPRAM which has writes taking place at a certain freq on port A (100 Mhz) & reads with a gated clock which is derived from the 100 Mhz clock(from port B) . The signal generating the gated clock does not follow a uniform pattern. How can I calculate the size of DPRAM reqd? Thanks in advanceArticle: 115356
On Feb 7, 1:58 pm, bijoy <pbi...@rediffmail.com> wrote: > Hi sumesh > > Could you please tell me more details of your requirement, like do you need to make new boards or fpga design or etc. so that i can suggest some companies working in this area. > > rgds bijoy We need to make new board with all the above requirement. Also i need another fpga which can controll all other functonalities of the board like video in/out DDR controller etc.....Article: 115357
On Feb 8, 3:38 pm, "vlsi_learner" <baj...@gmail.com> wrote: > Hi, > > I have an DPRAM which has writes taking place at a certain freq on > port A (100 Mhz) & reads with a gated clock which is derived from the > 100 Mhz clock(from port B) . The signal generating the gated clock > does not follow a uniform pattern. How can I calculate the size of > DPRAM reqd? > > Thanks in advance Sorry had to repost it.There is a correction . The enable signal for the clock does not follow a uniform patternArticle: 115358
On 7 Feb 2007 03:34:28 -0800, "Tony Thai" <tony.uniquify@gmail.com> wrote: >Hi All, > >Hopefully this is a simple fix... >I complied Xilinx simulation libraries with COMPXLIB... and it seemed >to worked fine. >The modelsim.ini was changed to point to the new libraries. Which modelsim.ini? Typically modelsim creates one in each working directory; that in force when you invoked compxlib may NOT be the same as the one in your project working directory. You may need to edit the unisim library mapping into your project's modelsim.ini, or even delete an incorrect one if you acquired the project from somebody else... - BrianArticle: 115359
"vlsi_learner" <bajajk@gmail.com> wrote in message
news:1170931235.360649.31850@v33g2000cwv.googlegroups.com...
> On Feb 8, 3:38 pm, "vlsi_learner" <baj...@gmail.com> wrote:
>> Hi,
>>
>> I have an DPRAM which has writes taking place at a certain freq on
>> port A (100 Mhz) & reads with a gated clock which is derived from the
>> 100 Mhz clock(from port B) . The signal generating the gated clock
>> does not follow a uniform pattern. How can I calculate the size of
>> DPRAM reqd?
>
> Sorry had to repost it.There is a correction . The enable signal for
> the clock does not follow a uniform pattern
That makes all the difference.
How about this: an LVCMOS output stage drives a 48MHz signal over a 12-inch
stretch of FR4 terminated with a 10K resistor to Vcc and a 100pF capacitor
to Gnd. What colour is the PCB?
-Ben-
Article: 115360Daniel O'Connor wrote: > I am also considering taking the 50MHz clock on my board and multiplying it > up to, say, 150MHz and sychronising/one-shotting all of the signals from > the other board to that. Yep. That's the what you have to do. All other routes lead to madness. Synchronize the incoming signals and as much of the rest as possible. I would look hard at making the FIFO synchronous.Article: 115361
Well, the experience I have is that I have successfully installed it on two such machines (both installed to /opt/Xilinx91i as root, which of course shoudn't make any difference). If I remember correctly, at least one installation run complained that there was too little space to install which wasn't true, so I installed anyway. I haven't used it much yet, but have done a trial rerun of one smaller design which ran ok. Have you looked at your /var/log/messages? >Article: 115362
"Ben Jones" <ben.jones@xilinx.com> wrote in message news:eqf1tc$p4q1@cnn.xilinx.com... > > "vlsi_learner" <bajajk@gmail.com> wrote in message > news:1170931235.360649.31850@v33g2000cwv.googlegroups.com... >> On Feb 8, 3:38 pm, "vlsi_learner" <baj...@gmail.com> wrote: >>> Hi, >>> >>> I have an DPRAM which has writes taking place at a certain freq on >>> port A (100 Mhz) & reads with a gated clock which is derived from the >>> 100 Mhz clock(from port B) . The signal generating the gated clock >>> does not follow a uniform pattern. How can I calculate the size of >>> DPRAM reqd? >> >> Sorry had to repost it.There is a correction . The enable signal for >> the clock does not follow a uniform pattern > > That makes all the difference. > > How about this: an LVCMOS output stage drives a 48MHz signal over a > 12-inch stretch of FR4 terminated with a 10K resistor to Vcc and a 100pF > capacitor to Gnd. What colour is the PCB? > > -Ben- > You driving a bus with three signal. At the first connector, 2 get off, but 6 get on. At the next connector 4 alight, and 3 mount. The bus terminates at the third stop. What colour is the bear? HTH, Syms.Article: 115363
Hi, I'm trying to fix the location of some primitive cells (apex20ke_lcell) in a post-synthesis netlist for an Altera APEX20KE FPGA. I have synthesized (quartus_map) and placed&routed (quartus_map) my Verilog HDL design using Quartus II. Then I have created a Verilog Quartus Mapping File (VQM), which contains the instantiated primitive cells of the device and I have back-annotated the location constraints into the Quartus settings file (QSF). In the QSF, there are a lot of location constraints, a la set_instance_assignment -name LL_NODE_LOCATION LC3_13_J4 -to "HDAND2D1:inv_i_10|Z~116_B" -section_id aes_sbox_canright When I use the VQM and QSF file for a new fitting attempt, I get warnings for each location constraint like Warning: Node "HDAND2D1:inv_i_10|Z~116_B" is assigned to location or region, but does not exist in design Either I'm doing something terribly wrong or Quartus isn't able to understand its own back-annotation. I hope that somebody can shed some light on this. Regards, Stefan TillichArticle: 115364
I have a hardware core that needs to be able to generate interrupts for all processors in the system (maximum of two PPC's and two MB's). In the core I have a port defined as: Preemption_Interrupt : out std_logic_vector(0 to C_NUM_CPUS - 1); The idea is that the number of interrupt lines in dependent on a user generic (C_NUM_CPUS) which can range from 1-4. Now the opb_intc in the mhs file: # ######################################################################################### # ## Interrupt Controller for PPC_0 # ######################################################################################### BEGIN opb_intc PARAMETER INSTANCE = opb_intc_0 PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0x41200000 PARAMETER C_HIGHADDR = 0x4120ffff PARAMETER C_NUM_INTR_INPUTS = 4 BUS_INTERFACE SOPB = opb PORT Irq = EICC405EXTINPUTIRQ_0 PORT Intr = RS232_Uart_1_Interrupt & opb_central_dma_0_DMA_Interrupt & access_intr & premt_intr END BEGIN custom_core PORT Preemption_Interrupt = premt_intr END The problem is that the PORT Intr sees premt_intr (Preemption_Interrupt from above) as a vector and I need to break out only the first index of this vector. Then, for the second PPC I would have a separate opb_intc that needs only the second index of premt_intr and so on. Is there a way to do this? I would like to keep it very general as it is now. Can I do something like: PORT Preemption_Interrupt(0) = premt_intr_0 PORT Preemption_Interrupt(1) = premt_intr_1 ....Article: 115365
Hello, I have recently installed ISE9.1, since that moment I am no longer able to start EDK 8.2 . Has anybody had a similar problem? best regards, KarelArticle: 115366
Hi guys, I need your FPGA/DSP expertness in the following issue: I want to create a RADAR pulse detector (in FPGA) to work in an unlicensed environment at the 5G band (such as wi-fi). This pulse will be connected to an A/D (at the IF band) and will try to detect the pulses power and also measure their repetition period (to be sent to my host processor). The host processor will then test the repetition period and look for a RADAR pattern. Does any of you know of relevant material that I can get for this issue. Any tips will be appreciated .. Thanks in advance, Mordehay.Article: 115367
Symon wrote: > news:eqf1tc$p4q1@cnn.xilinx.com... > >>"vlsi_learner" <bajajk@gmail.com> wrote in message >>news:1170931235.360649.31850@v33g2000cwv.googlegroups.com... >> >>>On Feb 8, 3:38 pm, "vlsi_learner" <baj...@gmail.com> wrote: >>> >>>>Hi, >>>> >>>>I have an DPRAM which has writes taking place at a certain freq on >>>>port A (100 Mhz) & reads with a gated clock which is derived from the >>>>100 Mhz clock(from port B) . The signal generating the gated clock >>>>does not follow a uniform pattern. How can I calculate the size of >>>>DPRAM reqd? > "Ben Jones" <ben.jones@xilinx.com> wrote in message >>How about this: an LVCMOS output stage drives a 48MHz signal over a ... >> > Symon wrote: > You driving a bus with three signal. At the first connector, 2 get off ... > Sheesh, How can this guy learn with examples like that? Try this: My teammate and I run a race. He runs the mile 5 seconds faster than I do. What size hat should I buy? --- Joe Samson P.S. to the O.P.: No one can calculate your memory size if the only info given is the clock speed.Article: 115368
On Feb 8, 2:40 am, "vlsi_learner" <baj...@gmail.com> wrote: > On Feb 8, 3:38 pm, "vlsi_learner" <baj...@gmail.com> wrote: > > > Hi, > > > I have an DPRAM which has writes taking place at a certain freq on > > port A (100 Mhz) & reads with a gated clock which is derived from the > > 100 Mhz clock(from port B) . The signal generating the gated clock > > does not follow a uniform pattern. How can I calculate the size of > > DPRAM reqd? > > > Thanks in advance > > Sorry had to repost it.There is a correction . The enable signal for > the clock does not follow a uniform pattern If I understand your problem correctly, you have data coming in faster that it is going out. To answer your question, I need to know how long the DPRAM will be running.Article: 115369
On Wed, 07 Feb 2007 23:48:49 -0800, Subroto Datta wrote: > For ByteBlaster( II or MV), you can use the /dev/parport? driver. Be > sure to have permission to use that device. In addition, there is a > ByteBlaster kernel driver to speed up the access. > For the USBBlaster, no additional usb driver is needed. However, a > bit configuration is needed. See http://www.altera.com/support/ > software/drivers/dri-usb_b-lnx.html > For MasterBlaster (serial port only), /dev/ttyS? driver is used. > For EthernetBlaster, it works with the TCP/IP stack. > > In summary, no additional kernel driver is needed for all blasters. > > - Subroto Datta > Altera Corp. > > > > On Feb 7, 3:11 pm, General Schvantzkoph <schvantzk...@yahoo.com> > wrote: >> On Wed, 07 Feb 2007 14:50:38 -0800, rekha.arun wrote: >> > On Feb 7, 8:45 am, General Schvantzkoph <schvantzk...@yahoo.com> >> > wrote: >> >> Is the Byte Blaster Cable and Signal Tap supported on Linux and more >> >> specifically on Fedora Core 5 or 6? All of my experience has been with >> >> Xilinx tools, this will be my first use of the Altera debug tools. >> >> Xilinx's ChipScope has only marginal Linux support. There is a kernel >> >> specific driver that only runs on the RHEL version of the kernel which is >> >> so old as to be useless on a laptop. I was wondering if Altera has the >> >> same sort of limitations or if their tools are kernel independent. >> >> >> Thanks, >> >> > Yes, SignalTap is supported on Linux. With regard to ByteBlaster, it >> > is supported on 32-bit Linux but not on 64-bit Linux. But, the 64-bit >> > Linux does however support Ethernet Blaster. >> >> Are there any kernel issues?- Hide quoted text - >> >> - Show quoted text - ThanksArticle: 115370
I've read some of the heated discussions regarding Virtex 4 and SATA, but I'm still not sure what the answers are. My understanding is that with a modest amount of external circuitry (NOT an external phy) I can build a SATA interface. Some of the Xilinx answer database links regarding SATA are dead. Hopefully someone here can give me some pointers. 1) What about V4 fails to work for SATA? 2) Has anyone made it work, and willing to explain how it was done? 3) Can 3Gbps speeds be used? 4) Is there another programable device that would be easier (V5 still needs to age a bit). Thanks SamArticle: 115371
On Feb 8, 3:41 am, Tim <s...@nooospam.roockyloogic.com> wrote: > Daniel O'Connor wrote: > > I am also considering taking the 50MHz clock on my board and multiplying it > > up to, say, 150MHz and sychronising/one-shotting all of the signals from > > the other board to that. > > Yep. That's the what you have to do. All other routes lead to madness. > Synchronize the incoming signals and as much of the rest as possible. I > would look hard at making the FIFO synchronous. Since you have to synchronize to a new clock anyhow, make the whole FIFO synchronous (same clock for write and read, but with separate Enables). That makes the FIFO design very simple, and avoids all the tricky circuitry requires for asynchronous operation. Peter Alfke, XilinxArticle: 115372
On Feb 8, 9:11 am, "Dolphin" <Karel.Dep...@gemidis.be> wrote: > Hello, > > I have recently installed ISE9.1, since that moment I am no longer > able to start EDK 8.2 . > Has anybody had a similar problem? > > best regards, > Karel That will not work. The version of EDK must match the version of ISE. EDK 8.2 will only work with ISE 8.2, and you need to use EDK 9.1 with ISE 9.1. I do not know when EDK 9.1 will be released. Regards, John McCaskill www.fastertechnology.comArticle: 115373
On 2007-02-08, santner@gmail.com <santner@gmail.com> wrote: > The problem is that the PORT Intr sees premt_intr > Is there a way to do this? I would like to keep it very general as it > is now. Can I do something like: > PORT Preemption_Interrupt(0) = premt_intr_0 > PORT Preemption_Interrupt(1) = premt_intr_1 Well, you could send all the interrupts to all processors and have them each ignore the lines they don't care about. You could use one of those util_bus_split things (probably more than one) and whittle off bits. The existance of this Xilinx block makes me think that generic bus indexing does not work in a MHS file. You could make a custom module to split up the bits. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 115374
To add to what was posted, you can keep both ISE installs (8.2i and 9.1i) on your PC (or Linux box), but you will need to change the XILINX variable to the 8.2i location to be able to use EDK 8.2i "John McCaskill" <junkmail@fastertechnology.com> wrote in message news:1170956277.805177.118930@m58g2000cwm.googlegroups.com... > On Feb 8, 9:11 am, "Dolphin" <Karel.Dep...@gemidis.be> wrote: >> Hello, >> >> I have recently installed ISE9.1, since that moment I am no longer >> able to start EDK 8.2 . >> Has anybody had a similar problem? >> >> best regards, >> Karel > > > That will not work. The version of EDK must match the version of > ISE. EDK 8.2 will only work with ISE 8.2, and you need to use EDK 9.1 > with ISE 9.1. I do not know when EDK 9.1 will be released. > > > Regards, > > John McCaskill > www.fastertechnology.com >
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