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On Feb 12, 10:37 pm, "werty" <w...@swissinfo.org> wrote: > On Feb 12, 2:30 pm, "john jardine" <j...@jjdesigns.fsnet.co.uk> wrote: > > > > > "Geronimo Stempovski" <geronimo.stempov...@arcor.de> wrote in message > > >news:45d04b34$0$27624$9b4e6d93@newsspool2.arcor-online.net...> I think transmitting high-speed signals is very easy when you have a > > > 360-degree ground reference, round conductors, > > > and no other nearby signals like in coaxial cables. My aim is to design > > PCB > > > tracks as much like a coaxial cable as > > > possible. Anyone tried this before? Is it possible with regular FR4, > > anyway? > > > Thanks for your help. > > > > Gero > > > Had trouble with crosstalk on a mass of video signals. Cured with a > > multilayer board where each signal was 'boxed in' by ground plane to the > > sides, above and below. Sort of square coax. > > > -- > > Posted via a free Usenet account fromhttp://www.teranews.com > > ---------------------------------------------------------- > > Boxed ! the wavelength is far greater than > your dimensions , thus higher modes can not > exist , thus you do NOT need sides . > When you reach 10 Ghz , then maybe > you need sides in ur boxed "coax" . > > But the big joke , is in the real world , > they use cheap PCB to xmit 2.5 Ghz . > No strip line , no microstrip , nada .. > It works well , so quit arguing reality . > > BTW , i saw some novice , trying to > use juice cans to launch WiFi . > He figured the more cans , the more > gain . He had 3 cans , T'd . > to divide the power . > Gain is not in cans , its in size of > the dish . > > Another book worm said all i needed > was $26 for 100 meters of blah blah > coax at 2.5 Ghz .. > > 10 times that price ! > and 1.8" dia hard line ! > > At these wavelengths , its lower loss > to send it TEM and thru the air , > not thru a coax . > > This is goin to FPGA ? Do those relics > still exist ?! Oh well , i supose ya gotta > try to "protect" your firmware by reinventing > the CPU ! Ah, yes, reality. The reality is that we do need the vias for our work. I can imagine that John J. may well also. When you're aiming at 100+dB isolation among traces, you do have to be pretty careful, even at "low" frequencies. Cheers, TomArticle: 115526
werty wrote: > On Feb 12, 2:30 pm, "john jardine" <j...@jjdesigns.fsnet.co.uk> wrote: > >>"Geronimo Stempovski" <geronimo.stempov...@arcor.de> wrote in message >> >>news:45d04b34$0$27624$9b4e6d93@newsspool2.arcor-online.net...> I think transmitting high-speed signals is very easy when you have a >> >>>360-degree ground reference, round conductors, >>>and no other nearby signals like in coaxial cables. My aim is to design >> >>PCB >> >>>tracks as much like a coaxial cable as >>>possible. Anyone tried this before? Is it possible with regular FR4, >> >>anyway? >> >>>Thanks for your help. >> >>>Gero >> >>Had trouble with crosstalk on a mass of video signals. Cured with a >>multilayer board where each signal was 'boxed in' by ground plane to the >>sides, above and below. Sort of square coax. >> > ---------------------------------------------------------- > > Boxed ! the wavelength is far greater than > your dimensions , thus higher modes can not > exist , thus you do NOT need sides . > When you reach 10 Ghz , then maybe > you need sides in ur boxed "coax" . <snip> Seems video distribution is not one of your areas of expertise ? Note that John was talking about crosstalk, in the analog domain, and yes, what he did certainly will have a measurable improvement, and is somewhat 'industry practise' when minimising crosstalk. Note he says 'cured', that means he is on both sides of the problem, and it is a brave (or something else?) person that counters such direct experience I imagine in extreme digital cases, such as where you are worried not only about sending the clock, but also about the ps/fs of jitter, then this design approach would also help : it's not hard to do. -jgArticle: 115527
thank you for all replies. i tried to post a reply earlier but did't work. the substraction is just one operation. actually what i need is to do a convolution of two images. i did't think about doing it as the data arives, as it seems very complicated. the project im working on is not a commrcial one. i need to prove a concept. so i dont mind using the whole FPGA (Xilinx spartan 3, 400K version), just to implement this, as long as i get the result of the convolution very fast. thank you.Article: 115528
On 13 Feb 2007 00:14:30 -0800, "CMOS" <manusha@millenniumit.com> wrote: >the substraction is just one operation. actually what i need is to do >a convolution of two images. I don't think you mean that. I think you mean the difference of two images. > i did't think about doing it as the data >arives, as it seems very complicated. I promise you, it is MUCH easier than trying to do it on two complete images. You need the old image in memory, and you probably need a second store for the difference image. For each pixel, you perform difference_image[row][col] := new_pixel - old_image[row][col]; old_image[row][col] := new_pixel; before going on to increment the column address. Note that this requires two memory areas, and one read and two writes for each pixel. You'll also need to budget for the read accesses that some CPU or whatever must make to the result. >the project im working on is not a commrcial one. i need to prove a >concept. so i dont mind using the whole FPGA (Xilinx spartan 3, 400K >version), just to implement this, as long as i get the result of the >convolution very fast. As others have pointed out, it's hard to get it any faster than this: the difference image is constructed in real-time whilst the second of your two fields is being acquired. Do you really mean CONVOLUTION? That's a spatial filtering operation, in the usual meaning. Taking the difference of two successive images is a temporal filtering operation - I suppose it's a convolution in the time domain with the kernel (+1, -1) ..... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 115529
> I don't think you mean that. I think you mean the difference of > two images. yes i mean it. its convolution. im doin it to calculate the motion vector by comparing two consecutive images.Article: 115530
Hi Eilert, Thank you very much for your idea. i am using a IC XC3S400. I know it get a Picoblaze inside. First, i only test program PCCOOMP to sure it runs well. "open failed" means PCCOMP can not open file( for example, I downloaded a file from the place i loaded PCCOMP soft). I open these files with Borland C, and they are Ok. But when i compiled in PCCOMP , it always failed. I have no occassion to get a code to load into Picobalze. By the way, i think you get much knowledge about FPGA, can you make me clear somethings? i would like to program for Picoblaze In C, i have to include "Spartan3.h" to be able to use Picoblaze languege in C, wouldn't I? Please tell me with my stupid questions. have a nice day! Him LamArticle: 115531
On 13 Feb, 01:45, "Say Joe" <ngsay...@gmail.com> wrote: > On Feb 13, 6:53 am, "Jon Beniston" <j...@beniston.com> wrote: > > > > Lame. It'll always amount to a religious war. Besides, my personal > > > choice (Hard-C) isn't present, so I can't vote. > > > No EDIF option either. > > > Cheers, > > Jon > > EDIF and Hard-C should reside under "Others", since they're not really > mainstream language used. So you know the outcome of the poll before you started? Cheers, JonArticle: 115532
On Tue, 13 Feb 2007 04:55:03 GMT, Robert Baer <robertbaer@earthlink.net> wrote: >John Fields wrote: > >> On Mon, 12 Feb 2007 12:10:43 +0100, "Geronimo Stempovski" >> <geronimo.stempovski@arcor.de> wrote: >> >> >>>I think transmitting high-speed signals is very easy when you have a >>>360-degree ground reference, round conductors, >>>and no other nearby signals like in coaxial cables. My aim is to design PCB >>>tracks as much like a coaxial cable as >>>possible. Anyone tried this before? Is it possible with regular FR4, anyway? >>>Thanks for your help. >> >> >> --- >> http://en.wikipedia.org/wiki/Microstrip >> >> > He said "coax"... --- No, he said: ...:"as much like a coaxial cable as possible.", which I took to mean electrically. Otherwise, why not just use a piece of micro-coax and treat it like just another component on the PCB? -- JFArticle: 115533
On 12 Feb 2007 17:26:54 -0800, it was posted by ghelbig@lycos.com :
"On Feb 9, 7:06 am, "wojt" <wojtek.bo...@gmail.com> wrote:
> Hi
>
> Does anyone here know, how to explicitly set which VHDL standard
> should be used by Xilinx ISE (actually, by XST I think)?
>
> Cheers
> Wojtek
You don't.
XST doesn't care whether it's compiling VHDL or Verilog. You can
happily intermix them in the same project."
The person who posted with ghelbig@lycos.com in a From field missed the point:
the point is not about Verilog and VHDL; but about choosing between different
versions of VHDL (dated 1987; 1993; 2002; and 2006). XST does not have a way to
allow a user to select one of these in particular from a selection of at least
two options. This is in contrast to other vendors' tools. E.g. ncvhdl:
05.70-s005: (c) Copyright 1995-2006 Cadence Design Systems, Inc.,
which has a mode intended for VHDL87; another mode intended to "Enable
VHDL93 features"; and the -V200X command line switch (which has no
graphical counterpart in the NCLaunch GUI) to "Enable VHDL200X and
VHDL93 features". Another example, from the "Version Y-2006.06 HDL
Compiler (Presto VHDL) Reference Manual":
"[..]
The VHDL language is specified in IEEE 1076, which is updated
continually, with IEEE 1076-1993 being the most recent revision[sic,
this is from documentation from Synopsys dated May 2006]. To
support these updates and provide other improvements, Synopsys
developed the HDL Compiler (Presto VHDL) tool, which is described
in this manual and turned on by default. The original VHDL Compiler
is described in the HDL Compiler for VHDL Reference Manual.
For a list of supported VHDL-93 features,
[..]
Table 7-4 Variables
Name Default Description
[..]
hdlin_vhdl_87 False When true, directs Presto VHDL to use the
VHDL-87 standard.
[..]"
For XST, one's code may be treated as VHDL93 or VHDL87 but the choice
is made by XST while it examines the code instead of by a user or
enforced company policy, from
HTTP://toolbox.Xilinx.com/docsan/xilinx9/books/docs/xst/xst.pdf
: "[..]
VHDL IEEE Conflicts
VHDL IEEE std 1076-1987 constructs are accepted if they do not
conflict with VHDL IEEE
std 1076-1993. In case of a conflict, VHDL IEEE Std 1076-1993 behavior
overrides VHDL
IEEE std 1076-1987.
In cases where:
. VHDL IEEE std 1076-1993 requires a construct to be an erroneous
case, but
. VHDL IEEE std 1076-1987 accepts it,
XST issues a warning instead of an error. (An error would stop
analysis.)
[..]"
Regards,
Colin Paul Gloster
Article: 115534Ok guys, I have added EDIF which I may have overlooked. But I'm sorry, what is Hard-C? If you mean C programming language, then it's under C/C ++ ...Article: 115535
On 13 Feb 2007 01:41:05 -0800, "CMOS" <manusha@millenniumit.com> wrote: >> I don't think you mean that. I think you mean the difference of >> two images. > >yes i mean it. its convolution. im doin it to calculate the motion >vector by comparing two consecutive images. OK, when you said "the subtraction is just one operation" you meant that it is one of many operations that need to be performed. Sorry I misunderstood. I reckon the subtraction is trivial by comparison with the feature-detecting convolution operations, on various scales, that you probably need to do. Or the DCT. Or the correlation. Why is the subtraction such a big deal? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 115536
On Mon, 12 Feb 2007 12:10:43 +0100, Geronimo Stempovski <geronimo.stempovski@arcor.de> wrote: > I think transmitting high-speed signals is very easy when you have a > 360-degree ground reference, round conductors, > and no other nearby signals like in coaxial cables. My aim is to design > PCB > tracks as much like a coaxial cable as > possible. Anyone tried this before? Is it possible with regular FR4, > anyway? Hello, the technology used to build multilayer PCB does not allow to build a round coaxial transmission line. You may have structured planes of copper foil separated by insulation material, but nothing like the shield of a coaxial cable. Even a rectangular shield around a center conductor is not possible with the existing methods to build multilayer PCB. byeArticle: 115537
On Mon, 12 Feb 2007 22:30:39 +0100, john jardine <john@jjdesigns.fsnet.co.uk> wrote: > Had trouble with crosstalk on a mass of video signals. Cured with a > multilayer board where each signal was 'boxed in' by ground plane to the > sides, above and below. Sort of square coax. Hello, but how about a real closed square shield around the center conductor? ByeArticle: 115538
"Say Joe" <ngsayjoe@gmail.com> wrote in message news:1171369259.098531.217270@v33g2000cwv.googlegroups.com... > > Ok guys, I have added EDIF which I may have overlooked. I think that EDIF suppose to be a joke, I don't believe engineers are actually writing EDIF themselves unless they like pain :-) > But I'm sorry, what is Hard-C? I had to look it up as well, I found this info: A C-like language for synchronous parallel programs, mostly inspired by Timogriffer C, with a nod to Handel-C. The compiler generates Verilog and some designs have been tested on Xilinx Spartan FPGA, using Xess' XSA-100 development board and the Xilix ISE WebPack. The linked file is an old snapshot of the development with many features missing. http://not.meko.dk/Hacks/hacks.html Hans www.ht-lab.comArticle: 115539
On 12 Feb 2007 09:26:09 -0800, Joe posted in
news:1171301169.694797.165170@s48g2000cws.googlegroups.com
:"I'm currently running a series of polls on Verilog, SystemVerilog,
VHDL, and SystemC. I'd like to get you guys to vote for your favorite
FPGA language [..]
So, here's the link to the poll:
http://zeemz.com/forum/viewtopic.php?t=6
[..]"
A few minutes ago the webpage's radio buttons could be found amongst:
"[..]
Which is your favorite FPGA language?
Verilog
100% [ 2 ]
VHDL
0% [ 0 ]
C/C++
0% [ 0 ]
Other
0% [ 0 ]
[..]"
Joe, as with many people including people who devised the standard's
title, seems to have confused the SystemC(R) library specification
with a language. As with multitudes more, Joe uses the term "C/C++"
unhelpfully. From
FTP://FTP.NetLab.CS.RPI.edu/pub/comp.lang.c++.moderated/acllcfaq.txt
:"[..]
2: What is C/C++?
First of all, C and C++ are different languages. [..] C++ can be
considered to be a
superset of C, but there are real differences between them.
3: So, are C and C++ not so similar after all?
[..] The differences
between the two languages are significant enough to ensure that
one has to be clear about the language being used. [..]
[..]"
In news:1171369259.098531.217270@v33g2000cwv.googlegroups.com
, Joe posted a few minutes ago on 13 Feb 2007 04:20:59 -0800:
"Ok guys, I have added EDIF which I may have overlooked."
Unfortunately Joe did so by removing the option "Other" altogether...
so now the webpage's contents have changed to contain:
"[..]
Which is your favorite FPGA language?
Verilog
100% [ 2 ]
VHDL
0% [ 0 ]
C/C++
0% [ 0 ]
EDIF
0% [ 0 ]
[..]"
Tommy Thorn posted in
news:1171319830.501951.320330@v45g2000cwv.googlegroups.com
:
"[..] Besides, my personal
choice (Hard-C) isn't present, so I can't vote."
In news:1171369259.098531.217270@v33g2000cwv.googlegroups.com
, Joe responded:
" But I'm sorry,
what is Hard-C? If you mean C programming language, then it's under
C/C
++ ..."
I do not know what Hard-C is. Perhaps it is something to do with C and
hardware. The incompatibilities between different Verilog (or VHDL)
pseudo-implementations are insignificant in relation to the
incompatibilities between any two of CDL (C-Development Language and
later Chip Design Language and CDL TradeMark) (not to be confused
with CDL (Computer Design Language)); Cx; HardwareC; Handel-C;
Spec C+; Esterel C; SystemC++ (not to be confused with
the SystemC(R) library); SpecC; CynApps and CLevelDesign. As Verilog
has syntax derived from C, why is it not lumped in with these at the
C/C++ radio button?
Joe, I applaud your willingness to try to improve the poll as a result
of feedback in this newsgroup. Perhaps instead of having simply
"Others", it could allow someone to write something: e.g. "Others
(please elaborate): I use ABEL and Java". However, perhaps someone who
wanted to give such details could simply reply on your forum. A number
of other points: many people will not bother to create an account just
to vote on a forum which they can simply use Usenet for. You seem to
appreciate some significance corresponds to Usenet: you tried to
promote an alternative to Usenet via Usenet.
Another thing: one may prefer to not have a single language or to
always use the same one.
Regards,
Colin Paul Gloster
Article: 115540"CMOS" <manusha@millenniumit.com> wrote in message news:1171354470.823662.277430@p10g2000cwp.googlegroups.com... > thank you for all replies. i tried to post a reply earlier but did't > work. > > the substraction is just one operation. actually what i need is to do > a convolution of two images. Much bigger deal. > i did't think about doing it as the data > arives, as it seems very complicated. > the project im working on is not a commrcial one. i need to prove a > concept. so i dont mind using the whole FPGA (Xilinx spartan 3, 400K > version), just to implement this, as long as i get the result of the > convolution very fast. Good luck. You'll proably be faster doing a 2D-FFT on both images, multiplying them, then doing the inverse transfom. One clock? Hah!Article: 115541
Hi, I've been wondering for a while if there is any data about typical clock frequencies of FPGA designs for various FPGA devices. What I'm curious about is if there is any sort of published statistics about the clock frequencies used in different FPGA designs on different FPGA architectures. Basically I'd like to have some empirical data as to what to consider absurdly low, low, normal or high or extremely high in terms of clock frequency in a certain FPGA device. This is of course more complicated if you consider multiple clock domains, design complexity, hard IP cores running at speeds much higher than the surrounding logic, etc. From the limited experience I have I would consider designs running at over say 200 MHz in a Virtex-4 to be high speed designs and designs running at lower than 100 MHz in such a device to be low speed but I may be off the mark here by a significant margin :) That is why I'd really like to hear if anyone knows of any published statistics about this subject. /AndreasArticle: 115542
On 12 Feb 2007 22:37:14 -0800, "werty" <werty@swissinfo.org> wrote: > This is goin to FPGA ? Do those relics > still exist ?! Oh well , i supose ya gotta > try to "protect" your firmware by reinventing > the CPU ! > When you need, say, 40x the crunch power of a decent DSP processor, those relics come in handy. JohnArticle: 115543
Dear all, I have a requirement to configure one Spartan 3 using another over SelectMAP8. I am struggling to get anything working at all, so I have attempted to construct a simple readback test. I am basing my test on the command sequence given in Table 17 in XAPP452. Unfortuantely, even this test doesn't work, and I find the application note a little ambiguous. I will attempt to describe what I am doing. I have one FPGA (configured with my driving logic) attached to an unconfigured FPGA. Both are Spartan 3 1000s. I am running a continuous 20MHz configuration clock. On the falling edge of the configuration clock I set up the data ready for the unconfigured FPGA to clock the data in on the rising edge. On the first falling edge of interest I assert CS_B and RDWR_B low and I present the most significant byte of the first data word (0xFF) to the SelectMAP interface. The byte is bit-reversed as specified by the Spartan 3 datasheet. I then continue to present bytes with CS_B and RDWR_B asserted. Each word is presented most significant byte first, with the bits reversed within each byte. After sending 5 words (0xFFFFFFFF, 0xAA995566, 0x2800E002, 0x00000000, 0x00000000) I deassert CS_B on the next falling edge. On the following falling edge I assert CS_B whilst deasserting RDWR_B, this ensures that RDWR_B does not change whilst CS_B is asserted, causing an abort. I should now be able to read back the response to my command. Unfortunately, as soon as I deassert CS_B, the FPGA asserts BUSY, indicating an abort. I am clearly doing something wrong, I just have no idea what it is. The application note does not make clear where in the process of Table 17 the actual read operation takes place. I have also tried waiting until all 9 words have been written before attempting to read back. Exactly the same problem occurs. I am currently tearing my hair out over this, so any help or advice anyone can give me would be greatly appreciated. Thanks in advance, -- PeterArticle: 115544
On Tue, 13 Feb 2007 20:46:04 +1300, Jim Granville <no.spam@designtools.maps.co.nz> wrote: >werty wrote: >> On Feb 12, 2:30 pm, "john jardine" <j...@jjdesigns.fsnet.co.uk> wrote: >> >>>"Geronimo Stempovski" <geronimo.stempov...@arcor.de> wrote in message >>> >>>news:45d04b34$0$27624$9b4e6d93@newsspool2.arcor-online.net...> I think transmitting high-speed signals is very easy when you have a >>> >>>>360-degree ground reference, round conductors, >>>>and no other nearby signals like in coaxial cables. My aim is to design >>> >>>PCB >>> >>>>tracks as much like a coaxial cable as >>>>possible. Anyone tried this before? Is it possible with regular FR4, >>> >>>anyway? >>> >>>>Thanks for your help. >>> >>>>Gero >>> >>>Had trouble with crosstalk on a mass of video signals. Cured with a >>>multilayer board where each signal was 'boxed in' by ground plane to the >>>sides, above and below. Sort of square coax. >>> >> ---------------------------------------------------------- >> >> Boxed ! the wavelength is far greater than >> your dimensions , thus higher modes can not >> exist , thus you do NOT need sides . >> When you reach 10 Ghz , then maybe >> you need sides in ur boxed "coax" . ><snip> > >Seems video distribution is not one of your areas of expertise ? > > Note that John was talking about crosstalk, in the analog domain, >and yes, what he did certainly will have a measurable improvement, and >is somewhat 'industry practise' when minimising crosstalk. > Note he says 'cured', that means he is on both sides of the problem, >and it is a brave (or something else?) person that counters such direct >experience > >I imagine in extreme digital cases, such as where you are worried not >only about sending the clock, but also about the ps/fs of jitter, then >this design approach would also help : it's not hard to do. > >-jg > I do stuff down to a few ps RMS jitter on a regular 6 or 8-layer board, microstrip traces, with switching supplies and uPs and display drivers on the same board. Picoseconds aren't tough these days. JohnArticle: 115545
> > I know, it sounds kind of tricky, but a lot of designers are using > circuits like this. > Seems like a natural way to do it. I do it all the time. Actually, I would not even use the internal RAM unless I needed a spatial operation as it seems is the original poster's problem. I wasn't sure if you were talking about applying your solution to all the array elements simultaneously. Best, SanjayArticle: 115546
The answer is yes: Synplify DSP from Synplicity. It generates generic RTL code (VHDL, Verilog) from Simulink models and m scripts.Article: 115547
On Feb 13, 8:58 am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> wrote: > On 12 Feb 2007 09:26:09 -0800, Joe posted innews:1171301169.694797.165170@s48g2000cws.googlegroups.com > :"I'm currently running a series of polls on Verilog, SystemVerilog, > VHDL, and SystemC. I'd like to get you guys to vote for your favorite > FPGA language [..] > > So, here's the link to the poll: > > http://zeemz.com/forum/viewtopic.php?t=6 > > [..]" > > A few minutes ago the webpage's radio buttons could be found amongst: > "[..] > > Which is your favorite FPGA language? > Verilog > 100% [ 2 ] > VHDL > 0% [ 0 ] > C/C++ > 0% [ 0 ] > Other > 0% [ 0 ] > > [..]" > > Joe, as with many people including people who devised the standard's > title, seems to have confused the SystemC(R) library specification > with a language. As with multitudes more, Joe uses the term "C/C++" > unhelpfully. From > FTP://FTP.NetLab.CS.RPI.edu/pub/comp.lang.c++.moderated/acllcfaq.txt > :"[..] > > 2: What is C/C++? > > First of all, C and C++ are different languages. [..] C++ can be > considered to be a > superset of C, but there are real differences between them. > > 3: So, are C and C++ not so similar after all? > > [..] The differences > between the two languages are significant enough to ensure that > one has to be clear about the language being used. [..] > > [..]" > > Innews:1171369259.098531.217270@v33g2000cwv.googlegroups.com > , Joe posted a few minutes ago on 13 Feb 2007 04:20:59 -0800: > "Ok guys, I have added EDIF which I may have overlooked." > > Unfortunately Joe did so by removing the option "Other" altogether... > so now the webpage's contents have changed to contain: > "[..] > Which is your favorite FPGA language? > Verilog > 100% [ 2 ] > VHDL > 0% [ 0 ] > C/C++ > 0% [ 0 ] > EDIF > 0% [ 0 ] > [..]" > > Tommy Thorn posted innews:1171319830.501951.320330@v45g2000cwv.googlegroups.com > : > "[..] Besides, my personal > choice (Hard-C) isn't present, so I can't vote." > > Innews:1171369259.098531.217270@v33g2000cwv.googlegroups.com > , Joe responded: > > " But I'm sorry, > what is Hard-C? If you mean C programming language, then it's under > C/C > ++ ..." > > I do not know what Hard-C is. Perhaps it is something to do with C and > hardware. The incompatibilities between different Verilog (or VHDL) > pseudo-implementations are insignificant in relation to the > incompatibilities between any two of CDL (C-Development Language and > later Chip Design Language and CDL TradeMark) (not to be confused > with CDL (Computer Design Language)); Cx; HardwareC; Handel-C; > Spec C+; Esterel C; SystemC++ (not to be confused with > the SystemC(R) library); SpecC; CynApps and CLevelDesign. As Verilog > has syntax derived from C, why is it not lumped in with these at the > C/C++ radio button? > > Joe, I applaud your willingness to try to improve the poll as a result > of feedback in this newsgroup. Perhaps instead of having simply > "Others", it could allow someone to write something: e.g. "Others > (please elaborate): I use ABEL and Java". However, perhaps someone who > wanted to give such details could simply reply on your forum. A number > of other points: many people will not bother to create an account just > to vote on a forum which they can simply use Usenet for. You seem to > appreciate some significance corresponds to Usenet: you tried to > promote an alternative to Usenet via Usenet. > > Another thing: one may prefer to not have a single language or to > always use the same one. > > Regards, > Colin Paul Gloster And where's the button to vote for "whatever language my employer forces down my throat"?Article: 115548
Andreas, I would love to get my hands on a good (in a statistical sense) set of data on clocks speeds. Generally speaking, there are some "magic" frequencies that one sees very frequently that are likely to be on some of the 32 global clock resources (in Virtex 4 and 5): - PCI (33, 66, 100, or 133 MHz - SONET/SDH (19.44, 77.76, 155.52, 311.04 MHz) - DDR xRAM (100, 133, 166, 200, 233, 266, 300 MHz) - PCIe (125 MHz) - 405PPC (400,200,100 MHz) ... plus all of the various digital video, and other "standards" that are out there for frequencies used by ASIC/ASSP chips that we commonly find ourselves talking to. I know that the frequencies have jumped dramatically on the IO interfaces, by the number of hits the website gets for signal integrity issues. I strongly suspected this was going to happen six years ago, so I helped put in place the field SI experts for Xilinx, so we could actually help our customers (rather than just pointing them to a page of recommended consultants). Fighting the trend for increased frequencies, is the desire for lower power. I would say that the average power per "socket" is falling, rather than increasing. If you would have asked me five years ago what the median power was in the Virtex FPGA, I would have said 12 watts. Today I would guess 9 watts. It seems that when a major component of the cost of running something is the air conditioning, customers recognize that they have to design more efficient systems. Where this "lower power is better" scheme is most evident is in the microprocessor wars between AMD and Intel. Increasing the clock speed is no longer the goal, rather lowering power is the selling factor. AustinArticle: 115549
>>> Perhaps instead of having simply "Others", it could allow someone to write something: e.g. "Others (please elaborate): I use ABEL and Java". Ohh, yes I forgot about ABEL, but it isn't supported in major FPGA software Quartus and ISE, so what's the point? I try to include languages supported by vendor software only. But Java??? Isn't this a computer language. I try not to include too many computer languages, as in theory if I do then most computer languages can be used for FPGA, ues even PERL. Yes, C and C++ not the same, but group them for brevity sake, since the later is superset. >>> However, perhaps someone who wanted to give such details could simply reply on your forum. There's a difference. Usenet postings will be archived after a few months, but my forum poll is mean to run FOREVER. So, people can keep growing the poll results in time. >>>A number of other points: many people will not bother to create an account just to vote on a forum ... Registration is simple, there's no email activation required. Please help grow the poll vote count if you care, it takes less than i minute to insert your "nickname" and "password" :) >>> Another thing: one may prefer to not have a single language or to always use the same one. Yes, this is true. But there must be one that you like (favorite)
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