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Threads Starting Aug 1999

17496: 99/08/02: Gordon Hollingworth: Xilinx Readback Problems
    17501: 99/08/02: Peter Alfke: Re: Xilinx Readback Problems
17502: 99/08/02: Bob Perlman: Re: Warning! The eclipse approaches... {5.3a}
17503: 99/08/02: Jonas Thor: Re: Warning! The eclipse approaches... {5.3a}
17504: 99/08/03: wqg: help about PCI bridge
17505: 99/08/03: Hendrik De Vloed: Xilinx Virtex configuration in chunks
    17507: 99/08/03: Randy Robinson: Re: Xilinx Virtex configuration in chunks
17508: 99/08/03: <z0rbaf@newsguy.com>: looking for software
    17512: 99/08/04: Edwin Naroska: Re: looking for software
    17515: 99/08/04: Don Matson: Re: looking for software
17514: 99/08/04: <takehiro@rr.iij4u.or.jp>: RLOC constraint not interpreted correctly?
    17546: 99/08/09: Philip Freidin: Re: RLOC constraint not interpreted correctly?
    17547: 99/08/09: Steven Casselman: Re: RLOC constraint not interpreted correctly?
17516: 99/08/04: muzo: ECL IO to Virtex or APEX ?
    17517: 99/08/05: Rickman: Re: ECL IO to Virtex or APEX ?
17518: 99/08/05: Ilia Oussorov: serial multiplier with LogiCore scaled 1/2 accumulator
    17521: 99/08/05: Ray Andraka: Re: serial multiplier with LogiCore scaled 1/2 accumulator
        17526: 99/08/06: Ilia Oussorov: Re: serial multiplier with LogiCore scaled 1/2 accumulator
            17528: 99/08/06: Ray Andraka: Re: serial multiplier with LogiCore scaled 1/2 accumulator
                17543: 99/08/09: Ilia Oussorov: Re: serial multiplier with LogiCore scaled 1/2 accumulator
                17555: 99/08/10: Ilia Oussorov: Re: serial multiplier with LogiCore scaled 1/2 accumulator
17519: 99/08/05: Sabri Berisha: Re: Watch! [2.2di7.49n]
17520: 99/08/05: B.Thierry: [FRANCE] we need "help" with programming a FPGA
17522: 99/08/05: Josan Moreno: Support of XS40 in Jbits new version
17525: 99/08/06: Johan Ditmar: carry logic for implementing wide logic functions
    17530: 99/08/06: Ray Andraka: Re: carry logic for implementing wide logic functions
        17532: 99/08/06: Peter Alfke: Re: carry logic for implementing wide logic functions
            17533: 99/08/06: Ed Mcgettigan: Re: carry logic for implementing wide logic functions
17527: 99/08/06: <raderrl@my-deja.com>: Xilinx vs. Lucent vs. XX FPGA comparison
    17529: 99/08/06: Ray Andraka: Re: Xilinx vs. Lucent vs. XX FPGA comparison
17531: 99/08/06: Sandra Dominikus: XILINX Implementation Problem
    17551: 99/08/10: Simeon Furrer: Re: XILINX Implementation Problem
    17553: 99/08/10: gerald coe: Re: XILINX Implementation Problem
17535: 99/08/06: Gopal Iyer: help!
    17548: 99/08/09: Andy Peters: Re: help!
17536: 99/08/06: <hdunn@my-deja.com>: Intellectual Property
17537: 99/08/07: John Cooley: Re: comparison with xxxx
    17538: 99/08/07: B. Joshua Rosen: Re: comparison with xxxx
    17542: 99/08/09: Jos De Laender: Re: comparison with xxxx
17539: 99/08/08: Richard B. Katz: Registration is Open and Program - 1999 MAPLD International Conference
17540: 99/08/08: Margaret Dailey: Designers wanted
17541: 99/08/09: Utku Ozcan: Xilinx w/ClearCase
17545: 99/08/09: <droberts@cam-orl.co.uk>: Max+Plus II Verilog Parameters
17549: 99/08/09: Simon Moon: Lattice cable for 2032?
    17550: 99/08/10: Mankit Wong: Re: Lattice cable for 2032?
17552: 99/08/10: david braendler: Analog FPGA's
17554: 99/08/10: Ram Meenakshisundaram: Newbie - what are the limitations of the student edition
    17561: 99/08/10: Anna Acevedo: Re: Newbie - what are the limitations of the student edition
        17586: 99/08/11: <ldoolitt@recycle>: Re: Newbie - what are the limitations of the student edition
17556: 99/08/10: Ram Meenakshisundaram: Emulating a transputer on FPGA
    17557: 99/08/10: Wade D. Peterson: Re: Emulating a transputer on FPGA
    17558: 99/08/10: Jan Gray: Re: Emulating a transputer on FPGA
    17559: 99/08/10: James Wolffe: Re: Emulating a transputer on FPGA
        17563: 99/08/10: David Kessner: Re: Emulating a transputer on FPGA
            17570: 99/08/10: Ray Andraka: Re: Emulating a transputer on FPGA
                17579: 99/08/11: David Kessner: Re: Emulating a transputer on FPGA
                    17591: 99/08/11: Ray Andraka: Re: Emulating a transputer on FPGA
        17565: 99/08/10: Ram Meenakshisundaram: Re: Emulating a transputer on FPGA
    17562: 99/08/10: Alec Cawley: Re: Emulating a transputer on FPGA
    17566: 99/08/10: Alec Cawley: Re: Emulating a transputer on FPGA
    17574: 99/08/11: Jan Vorbrueggen: Re: Emulating a transputer on FPGA
    17581: 99/08/11: Ray Andraka: Re: Emulating a transputer on FPGA
17560: 99/08/10: Asher C. Martin: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
    17567: 99/08/10: <phil_jackson@my-deja.com>: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
        17568: 99/08/10: Adam J. Elbirt: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
        17569: 99/08/10: Phil Hays: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
    17571: 99/08/11: Asher C. Martin: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
        17583: 99/08/11: Ray Andraka: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
        17644: 99/08/18: Dongho Chung: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
            17650: 99/08/18: Brian Boorman: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
17572: 99/08/11: =?iso-8859-1?Q?=C8=AB=C0=BA=C1=BE?=: PCI core
    17575: 99/08/11: Edwin Naroska: Re: PCI core
    17604: 99/08/13: MPU: Re: PCI core
17573: 99/08/11: Freund Laurent: Java and XS40 board
    17576: 99/08/11: Eduardo Augusto Bezerra: Re: Java and XS40 board
17577: 99/08/11: Shardendu Pandey: Clock multiplexing
    17582: 99/08/11: Keith Jasinski, Jr.: Re: Clock multiplexing
        17587: 99/08/11: Peter Alfke: Re: Clock multiplexing
        17588: 99/08/11: Peter Alfke: Re: Clock multiplexing
17578: 99/08/11: jakab tanko: Xilinx: Verilog only???
    17584: 99/08/11: Ed Mcgettigan: Re: Xilinx: Verilog only???
17580: 99/08/11: Tim Warnes: UART
    17585: 99/08/11: Edwin Naroska: Re: UART
17589: 99/08/11: Artur Leung: Annapolis Micro WildForce analog interface
17590: 99/08/11: Greg Miller: Jedec to VHDL
17592: 99/08/12: G.Harrison: A problem with ORCAD/VHDL
17593: 99/08/12: Boumjin Park: VSS error : couldn't find root
17594: 99/08/12: Alexander Sherstuk: Foundation F1.5i Floorplanner document - ?
    17595: 99/08/12: Ray Andraka: Re: Foundation F1.5i Floorplanner document - ?
17597: 99/08/12: Kenneth Currie: Philips Semiconductors (NL) seeks digital designers
    17606: 99/08/13: Brian Boorman: Re: Philips Semiconductors (NL) seeks digital designers
    17608: 99/08/13: srikanth.b: Re: Philips Semiconductors (NL) seeks digital designers
    17611: 99/08/13: <madhurk@my-deja.com>: Re: Philips Semiconductors (NL) seeks digital designers
    17612: 99/08/13: <pboonen@my-deja.com>: Re: Philips Semiconductors (NL) seeks digital designers
17598: 99/08/12: <z0rbaf@newsguy.com>: looking for info on programing XILINX 4000 series
    17599: 99/08/12: Peter Alfke: Re: looking for info on programing XILINX 4000 series
    17637: 99/08/17: Rickman: Re: looking for info on programing XILINX 4000 series
    17653: 99/08/18: Andy Peters: Re: looking for info on programing XILINX 4000 series
17600: 99/08/12: Mike Treseler: port name reg_input won't sim.
    17601: 99/08/12: Mike Treseler: Re: port name reg_input won't sim.
        17602: 99/08/12: Steven Casselman: Re: port name reg_input won't sim.
17603: 99/08/12: Steven Casselman: Hollywood Blonde and Reconfigurable Computing
17605: 99/08/13: <wardrg@my-deja.com>: FIREFLY Embeddable MicroController Cores
17607: 99/08/13: cuong: Virtx' Configuration with the Xchecker cable
    17613: 99/08/14: Johan Frödin: Re: Virtx' Configuration with the Xchecker cable
    17633: 99/08/16: Steven Casselman: Re: Virtx' Configuration with the Xchecker cable
        17636: 99/08/17: <wdblyth@my-deja.com>: Re: Virtx' Configuration with the Xchecker cable
17609: 99/08/13: Donna Simms: Computers & Causes
17610: 99/08/13: Tom McDermott: Xilinx FPGA FIR filter number format?
17614: 99/08/14: Jonathan Cutting: Free UART
17615: 99/08/14: Peter: Xilinx purchase of Philips CoolRunner PLDs - good or bad, any views?
    17616: 99/08/15: Roger Hulsmans: Re: Xilinx purchase of Philips CoolRunner PLDs - good or bad, any views?
17617: 99/08/15: <mx3000@my-deja.com>: VHDL/Verilog? - Can of Worms
    17618: 99/08/15: Stuart Clubb: Re: VHDL/Verilog? - Can of Worms
    17621: 99/08/15: Simon Ramirez: Re: VHDL/Verilog? - Can of Worms
    17624: 99/08/15: B. Joshua Rosen: Re: VHDL/Verilog? - Can of Worms
    17627: 99/08/16: Wade D. Peterson: Re: VHDL/Verilog? - Can of Worms
17619: 99/08/15: Steve McDowell: Best synthesis tools for virtex?
    17623: 99/08/15: B. Joshua Rosen: Re: Best synthesis tools for virtex?
    17625: 99/08/15: Phil Hays: Re: Best synthesis tools for virtex?
17620: 99/08/15: Richard Erlacher: file format conversion for obsolete 3000-series XILINX parts?
17622: 99/08/16: Chi Fung: Constant port map in component instantiation
    17638: 99/08/17: Paulo Dutra: Re: Constant port map in component instantiation
17626: 99/08/16: Utku Ozcan: input offset constraint to Xilinx IOB's
    17667: 99/08/22: Rickman: Re: input offset constraint to Xilinx IOB's
    17685: 99/08/24: Darrin Nagy: Re: input offset constraint to Xilinx IOB's
        17713: 99/08/26: Nicolas Bier: Re: input offset constraint to Xilinx IOB's
17628: 99/08/16: Pieter Op de Beeck: fpga board : make it or buy it?
    17630: 99/08/16: Simon Ramirez: Re: fpga board : make it or buy it?
    17631: 99/08/16: brad ree: Re: fpga board : make it or buy it?
    17635: 99/08/17: Leon: Re: fpga board : make it or buy it?
    17646: 99/08/18: Jamil Khaib: Re: fpga board : make it or buy it?
    17665: 99/08/21: SIGTEK: Re: fpga board : make it or buy it?
        17961: 99/09/19: Richard Erlacher: Re: fpga board : make it or buy it?
17629: 99/08/16: Kevin Toliver: VHDL to debounce & latch input from a switch
    17738: 99/08/28: Clyde R. Shappee: Re: VHDL to debounce & latch input from a switch
17632: 99/08/16: <rajesh52@hotmail.com>: Verilog FAQ
17634: 99/08/16: Andrew Montreuil: We have everything from websites to hardware to software. All to save you money.
17639: 99/08/17: greg clifford: New Product Announcement: Flash Based XILINX Configurator
17641: 99/08/18: Chi Fung: VHDL'93 on Xilinx Foundation
    17648: 99/08/18: Andy Peters: Re: VHDL'93 on Xilinx Foundation
        17652: 99/08/19: Chi Fung: Re: VHDL'93 on Xilinx Foundation
17642: 99/08/18: blacksheep: programmable switching for telecommunications
17643: 99/08/18: #YEO WEE KWONG#: Xilinx DPM error : FE-PADMAP-02 error
17645: 99/08/18: Pieter Op de Beeck: multiplier Virtex
    17731: 99/08/27: Ray Andraka: Re: multiplier Virtex
17647: 99/08/18: Andrew Bunsick: FPGA/ASIC Design Engineers Available
17649: 99/08/18: Bob Pearson: map hang
    17655: 99/08/19: Leon Heller: Re: map hang
    17720: 99/08/27: Tobi Delbruck: Re: map hang
        17739: 99/08/28: Philip Freidin: Re: map hang
            17743: 99/08/29: Tobi Delbruck: Re: map hang
17651: 99/08/18: Stan Baker: VSIA SoC Forum&Meeting
17654: 99/08/19: Dfrancis@ihug.com.au: Money
17656: 99/08/19: Heinrich Fonfara: constrain into one XC4000 CLB
    17730: 99/08/27: Ray Andraka: Re: constrain into one XC4000 CLB
17657: 99/08/19: M Murphy: Digital Design Engineer needed - Please read
17658: 99/08/19: schwarz@informatik: nallatech virtex pci boards
17659: 99/08/19: David Kessner: New 6502 and DES cores available.
17660: 99/08/20: Gordon Hollingworth: Jbits
17661: 99/08/20: Joshua Lamorie: Smallest Configurator for Xilinx
    17670: 99/08/22: Rickman: Re: Smallest Configurator for Xilinx
        17673: 99/08/23: Ulf Samuelsson: Re: Smallest Configurator for Xilinx
        17688: 99/08/24: Joshua Lamorie: Re: Smallest Configurator for Xilinx
            17747: 99/08/30: jim granville: Re: Smallest Configurator for Xilinx
    17671: 99/08/22: Rickman: Re: Smallest Configurator for Xilinx
17662: 99/08/20: Bob Pearson: Know how to instnatiate a LUT for Virtex?
17663: 99/08/21: Daniel Figuerola Estrada: microcontroller vs FPGA
    17664: 99/08/21: Krister Wikstrom: Re: microcontroller vs FPGA
    17678: 99/08/23: Richard Erlacher: Re: microcontroller vs FPGA
        17700: 99/08/25: Joshua Schwartz: Re: microcontroller vs FPGA
            17763: 99/09/01: Richard Erlacher: Re: microcontroller vs FPGA
        17775: 99/09/02: Daniel Figuerola Estrada: Re: microcontroller vs FPGA
    17680: 99/08/23: M.Simon: Re: microcontroller vs FPGA
    17699: 99/08/24: Dave Vanden Bout: Re: microcontroller vs FPGA
        17732: 99/08/27: Ray Andraka: Re: microcontroller vs FPGA
    17728: 99/08/27: Joshua Lamorie: Re: microcontroller vs FPGA
        17962: 99/09/19: Richard Erlacher: Re: microcontroller vs FPGA
            18157: 99/10/04: Ulf Samuelsson: Re: microcontroller vs FPGA
    17848: 99/09/13: <vortekdoug@my-deja.com>: A mix is best
        17851: 99/09/13: Ray Andraka: Re: A mix is best
        17853: 99/09/14: <gregneff@my-deja.com>: Re: A mix is best
        17932: 99/09/17: Steven K. Knapp: Re: A mix is best (Microcontrollers and Programmable Logic)
17666: 99/08/21: muzo: synthesis comparion between Synplify and FPGA express
    17668: 99/08/22: Phil Hays: Re: synthesis comparion between Synplify and FPGA express
        17677: 99/08/23: David Kessner: Re: synthesis comparion between Synplify and FPGA express
            17682: 99/08/23: Phil Hays: Re: synthesis comparion between Synplify and FPGA express
                17862: 99/09/14: <dr0ne@my-deja.com>: free/demo/low cost verilog synthesis tools available?
                    17865: 99/09/14: Ray Andraka: Re: free/demo/low cost verilog synthesis tools available?
                    17871: 99/09/14: Dave Vanden Bout: Re: free/demo/low cost verilog synthesis tools available?
                    17902: 99/09/16: Steven K. Knapp: Re: free/demo/low cost verilog synthesis tools available?
            17792: 99/09/03: Bruce Nepple: Re: synthesis comparion between Synplify and FPGA express
                17794: 99/09/04: <a@z.com>: Re: synthesis comparion between Synplify and FPGA express
                    17816: 99/09/07: Bruce Nepple: Re: synthesis comparion between Synplify and FPGA express
                        17820: 99/09/07: Andy Peters: Re: synthesis comparion between Synplify and FPGA express
                17806: 99/09/06: David Kessner: Re: synthesis comparion between Synplify and FPGA express
                    17817: 99/09/07: Bruce Nepple: Re: synthesis comparion between Synplify and FPGA express
                    17821: 99/09/07: B. Joshua Rosen: Re: synthesis comparion between Synplify and FPGA express
                        17825: 99/09/08: David Kessner: Re: synthesis comparion between Synplify and FPGA express
                            17826: 99/09/08: Andy Peters: Re: synthesis comparion between Synplify and FPGA express
                    17830: 99/09/08: Nicolas Bier: Re: synthesis comparion between Synplify and FPGA express
                        17841: 99/09/11: Utku Ozcan: Re: synthesis comparion between Synplify and FPGA express
    17868: 99/09/14: Stuart Clubb: Re: synthesis comparion between Synplify and FPGA express
        17884: 99/09/15: David Kessner: Re: synthesis comparion between Synplify and FPGA express
            17888: 99/09/15: Stuart Clubb: Re: synthesis comparion between Synplify and FPGA express
17669: 99/08/23: Sukandar Kartadinata: looking for image processing hardware
    17676: 99/08/23: brad ree: Re: looking for image processing hardware
    17715: 99/08/26: Jonathan Feifarek: Re: looking for image processing hardware
        17727: 99/08/27: Sukandar Kartadinata: Re: looking for image processing hardware
    17733: 99/08/27: Ray Andraka: Re: looking for image processing hardware
        17736: 99/08/28: Sukandar Kartadinata: Re: looking for image processing hardware
        17737: 99/08/28: Sukandar Kartadinata: Re: looking for image processing hardware
            17749: 99/08/30: walter: Re: looking for image processing hardware
17672: 99/08/23: Grant Sargent: Altera MAX2PLUS/MAX700s BIDIR problem...
    17675: 99/08/23: <stuart_wilson@my-deja.com>: Re: Altera MAX2PLUS/MAX700s BIDIR problem...
17674: 99/08/23: ShtlChen: Help: Passing constriants from SYNOPSYS FPGA compiler to XILINX M1
17679: 99/08/23: Joshua Lamorie: JTAG 1149 Info
    17681: 99/08/23: <ar679deja@my-deja.com>: Re: JTAG 1149 Info
        17686: 99/08/24: <gorkw@my-deja.com>: Re: JTAG 1149 Info
    17684: 99/08/24: Steve Rencontre: Re: JTAG 1149 Info
    17691: 99/08/24: Alain Cloet: Re: JTAG 1149 Info
        17695: 99/08/24: Neil Glenn Jacobson: Re: JTAG 1149 Info
17683: 99/08/24: Richard Schwarz: FAST CORRELATOR 4096 by 1 40 Mhz
17687: 99/08/24: Tim Warnes: Parallel in Serial out
    17689: 99/08/24: Robert Fairlie: Re: Parallel in Serial out
        17692: 99/08/24: Tim Warnes: Re: Parallel in Serial out
            18022: 99/09/24: Also-Antal Csaba: only test
    17694: 99/08/24: Mark Lancaster: Re: Parallel in Serial out
        17704: 99/08/25: Robert Fairlie: Re: Parallel in Serial out
            17706: 99/08/25: Tim Warnes: Re: Parallel in Serial out
                17707: 99/08/25: muzo: Re: Parallel in Serial out
                17709: 99/08/25: Mark Lancaster: Re: Parallel in Serial out
17690: 99/08/24: Herman Schmit: CFP: FPGA 2000
17693: 99/08/24: Jean-Luc danger: APEX20K boards
17696: 99/08/25: Swapnajit Mittra: Verilog PLI website
17697: 99/08/25: <chadlamb@my-deja.com>: Virtex BRAM Initialization
    17702: 99/08/25: Paul Butler: Re: Virtex BRAM Initialization
        17705: 99/08/25: Steve Kinkead: Re: Virtex BRAM Initialization
            17708: 99/08/25: Brad Ree: Re: Virtex BRAM Initialization
            17710: 99/08/25: <chadlamb@my-deja.com>: Re: Virtex BRAM Initialization
                17716: 99/08/26: Steven Casselman: Re: Virtex BRAM Initialization
                    17724: 99/08/27: Winzker: Re: Virtex BRAM Initialization
                        17832: 99/09/09: David Newman: Re: Virtex BRAM Initialization
            17761: 99/09/01: utilisateur: Re: Virtex BRAM Initialization
    17768: 99/09/01: <vlogvin@my-deja.com>: Re: Virtex BRAM Initialization
17698: 99/08/25: Josan Moreno: Jbits for XS40?
17701: 99/08/25: Sukandar Kartadinata: Virtex dev boards
    17703: 99/08/25: Daryl Bradley: Re: Virtex dev boards
        17711: 99/08/26: Sukandar Kartadinata: Re: Virtex dev boards
            17712: 99/08/26: Daryl Bradley: Re: Virtex dev boards
                17722: 99/08/27: Tim Tyler: Re: Virtex dev boards
                17725: 99/08/27: Sukandar Kartadinata: Re: Virtex dev boards
                17834: 99/09/09: Steve Nordhauser: Re: Virtex dev boards
    17719: 99/08/27: Bill Blyth: Re: Virtex dev boards
        17726: 99/08/27: Sukandar Kartadinata: Re: Virtex dev boards
    17764: 99/09/01: Allan James Cantle: Virtex dev boards
    17776: 99/09/02: Jeff Streznetcky: Re: Virtex dev boards
    17777: 99/09/02: Jeff Streznetcky: Re: Virtex dev boards
    17778: 99/09/02: Jeff Streznetcky: Re: Virtex dev boards
17714: 99/08/26: Adam Biniszkiewcz: F 1.5
    18023: 99/09/24: user: Re: F 1.5
17717: 99/08/27: <thiru1457@my-deja.com>: Feasibility of 200 MHz, 12K design on FPGA
    17721: 99/08/27: <avms@my-deja.com>: Re: Feasibility of 200 MHz, 12K design on FPGA
    17729: 99/08/27: Ray Andraka: Re: Feasibility of 200 MHz, 12K design on FPGA
    17740: 99/08/27: Phil Hays: Re: Feasibility of 200 MHz, 12K design on FPGA
        17756: 99/08/31: <vermon1055@my-deja.com>: Re: Feasibility of 200 MHz, 12K design on FPGA
            17760: 99/08/31: Phil Hays: Re: Feasibility of 200 MHz, 12K design on FPGA
                17770: 99/09/01: Ray Andraka: Re: Feasibility of 200 MHz, 12K design on FPGA
                    17782: 99/09/02: Phil Hays: Re: Feasibility of 200 MHz, 12K design on FPGA
        17831: 99/09/09: Dongho Chung: Re: Feasibility of 200 MHz, 12K design on FPGA
    17759: 99/09/01: Anthony Ellis - LogicWorks: Re: Feasibility of 200 MHz, 12K design on FPGA
17718: 99/08/27: ragon: Short path check in Virtex M2.1i
17723: 99/08/27: Joshua Lamorie: FPGA Express: Not enough storage...(etc.)
    17742: 99/08/28: Andy Peters: Re: FPGA Express: Not enough storage...(etc.)
    17750: 99/08/30: <koen.gadeyne@barco.company>: Xilinx Synopsis bug (with exploit :-) [ was: Re: FPGA Express: Not enough storage...(etc.)]
17734: 99/08/27: George: test!
17735: 99/08/27: George: PLL cascading in VIRTEX
    17741: 99/08/28: Ray Andraka: Re: PLL cascading in VIRTEX
17744: 99/08/29: Asa Kalavade: size of configuration data?
    17745: 99/08/29: Philip Freidin: Re: size of configuration data?
17746: 99/08/29: Tim Tyler: UK programmable logic companies
17748: 99/08/30: jim granville: AMD Athlon CPU Speed at Simulates
17751: 99/08/30: <steves@traclabs.com>: Virtex LPCILOGIC site??
    17753: 99/08/31: Bill Blyth: Re: Virtex LPCILOGIC site??
17752: 99/08/30: <a1734@dis.ulpgc.es>: Problem with VHDL in MAX+Plus II / Flex10k
    17755: 99/08/31: Carlhermann Schlehaus: Re: Problem with VHDL in MAX+Plus II / Flex10k
        17787: 99/09/03: <german_acosta@my-deja.com>: Re: Problem with VHDL in MAX+Plus II / Flex10k
17754: 99/08/31: <sharad@bisquare.com>: Xilinx Spartan Configuration Prom
    17762: 99/09/01: Brian Boorman: Re: Xilinx Spartan Configuration Prom
17757: 99/08/31: <lemnaj55@bellsouth.net>: MONEY!


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