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In article <37df23d3.140311086@mindmeld.idcomm.com>, Richard Erlacher <edick@hotmail.com> wrote: >I have some reseration about these unquantified statements where cost >is concerned. For what ONE large XILINX FPGA costs, you can buy a >VERY well-equipped PC. What I can't understand is that these $800-900 >parts keep popping up in things costing much less than that. Can >anyone explain that? >Dick They lose money on each system, but make it up in volume. :-) There is a lot of elasticity in the price, once you start talking production volumes (100+ or 1000+ parts per month) . Also, elasticity seems to be enhanced by mentioning competitors names, and how price is real important.Article: 17876
Hai,
I am working on a project where we have a DSP(TMS320C549) connected to a
FLASH memory and two XILINX VIRTEX FPGAs(XCV600). for configuring them we are
planning to use parallel mode(select map mode).I have to write the firmware for
the FPGA configuration.I am not able to get how the DSP controls the
configuration process.
****Will the DSP read from the flash and write to the FPGA data bus? or it has
to just send appropriate control signals to FPGA so that it can directly load
the configuration data from the FLASH.In such a case there should be some
registers in the FPGA which will help it to configure for download.
If anybody has worked with a similar situation please help me providing some
info.
Cheers.
Mohan.
Article: 17877I had a similar problem with Xilinx - all I/Os were removed because they weren't connected to anything in the EDIF netlist. If I remember correctly, I had to to set an option in my synthesis tool. The problem was something t= o do with ports in my VHDL source design not being translated into I/O in the EDIF netlist. Sorry I can't be more specific. Mark Harvey > -----Messaggio originale----- > Da:=09Rickman [SMTP:spamgoeshere4@yahoo.com] > Inviato:=09marted=EC 14 settembre 1999 6.48 > A:=09comp.arch.fpga@list.deja.com > Oggetto:=09Re: PROBLEMS WITH ORCA >=20 > Message from the Deja.com forum:=20 > comp.arch.fpga > Your subscription is set to individual email delivery > >=20 > "Jos=E9 Luis Ayala" wrote: > >=20 > > Hi, > > Anyone have any experience with FPGAs from Lucent (ORCA FPGA)? > > I have a problem with the mapping process because the ORCA's software > > clips and removes all my output ports, giving error messages like: > > '<output_register_name>/NEOBUF (NEOINV) undriven or does not drive > > anything', '<output_register_name>/NEOLATCH (NEOLATCH) undriven or does > > not drive anything', '<pad_name>.PAD (NEOPAD) undriven or does not driv= e > > anything'. > > Thanks a lot > >=20 > > Jose Luis Ayala > > Electronic Engineering Department > > Technical University of Madrid > > Spain > >=20 > > Sent via Deja.com http://www.deja.com/ > > Share what you know. Learn what you don't. >=20 > I am not an expert, but I might be able to help. But you will need to > provide a little more info. What are you using for design entry, an HDL > or schematic? If you think your IOs are being clipped, have you traced > the netlist back to see what step is clipping them? Is it possible that > your net list out of your front end tool is not really connecting the IO > port to the rest of the circuit? >=20 > The error messages you give indicate that perhaps the rest of the > circuit has been clipped. Or are those messages from the tool that is > clipping the unconnected elements? >=20 >=20 > --=20 >=20 > Rick Collins >=20 > rick.collins@XYarius.com >=20 > remove the XY to email me. >=20 >=20 >=20 > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design >=20 > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX >=20 > Internet URL http://www.arius.com >=20 >=20 >=20 > _____________________________________________________________ > Deja.com: Share what you know. Learn what you don't. > http://www.deja.com/ > * To modify or remove your subscription, go to > http://www.deja.com/edit_sub.xp?group=3Dcomp.arch.fpga > * Read this thread at > http://www.deja.com/thread/%3C37DDD363.32FD1DD9%40yahoo.com%3E Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17878
Hello You must manage the control signals of the flash and of the virtex. See http://www.xilinx.com/xapp/xapp137.pdf which is an application note for "Configuring Virtex FPGAs from Parallel EPROMs with a CPLD" and replace the CPLD with your DSP. Good luck. Michel Le Mer Gerpi sa http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi. htm dnkmohan <dnkmohan@lucent.com> a écrit dans le message : 37DF42B3.224351C9@lucent.com... > Hai, > I am working on a project where we have a DSP(TMS320C549) connected to a > FLASH memory and two XILINX VIRTEX FPGAs(XCV600). for configuring them we are > planning to use parallel mode(select map mode).I have to write the firmware for > the FPGA configuration.I am not able to get how the DSP controls the > configuration process. > ****Will the DSP read from the flash and write to the FPGA data bus? or it has > to just send appropriate control signals to FPGA so that it can directly load > the configuration data from the FLASH.In such a case there should be some > registers in the FPGA which will help it to configure for download. > > If anybody has worked with a similar situation please help me providing some > info. > Cheers. > Mohan.Article: 17879
Breaking the bus into individual pins always works for me - bit of a
hassle when you've got big buses though !
PAT.
In article <37DEA351.96C5FCE9@nac.net>, Adam J. Elbirt <aelbirt@nac.net>
writes
>As far as I know the only solution is to break the bus into individual pins.
>
>Adam
>
>Ingo Purnhagen wrote:
>
>> Hi all,
>>
>> to fix/define the ACTEL pinning already in ViewDraw the PIN Attribute on
>> signals can be used (PIN= [ACTEL_Pin_Nr.]).
>> It works on single signals but not on busses.
>> PIN=[x:z] or PIN= x,y,z does not work.
>>
>> Thanx for solutions!
>
>--
>"Sometimes I think the surest sign that there's intelligent life on
>other planets is that none of it has tried to contact us."
> - Calvin, "Calvin and Hobbes"
>
>
--
Pat
Article: 17880Does anybody know when xilinx v2.1i will be available?Article: 17881
In article <37DF42B3.224351C9@lucent.com>, dnkmohan <dnkmohan@lucent.com> wrote: > Hai, > I am working on a project where we have a DSP(TMS320C549) connected to a > FLASH memory and two XILINX VIRTEX FPGAs(XCV600). for configuring them we are > planning to use parallel mode(select map mode).I have to write the firmware for > the FPGA configuration.I am not able to get how the DSP controls the > configuration process. > ****Will the DSP read from the flash and write to the FPGA data bus? or it has > to just send appropriate control signals to FPGA so that it can directly load > the configuration data from the FLASH.In such a case there should be some > registers in the FPGA which will help it to configure for download. > > If anybody has worked with a similar situation please help me providing some > info. > Cheers. > Mohan. > I think the application note from Xilinx can help you : http://www.xilinx.com/xapp/xapp138.pdf and http://www.xilinx.com/support/techsup/journals/config/index.htm Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17882
Forgot to mention... I would prefer a non-proprietary tool. Something that I can use to program components from different vendors. Additionally, the tool must handle even the simplest of PAL devices (16V8's).. Thanks... Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17883
"Ray Almond" <raya@noral.co.uk> wrote: > T = D * /B + /D * /S (Earth shattering stuff eh!) > The problem I'm having is in the form of a low going glitch on the T output > for a low to high change in the D input when both B and S are low. Here's something you might try: Since the 9500 is a sum-of-products architecture, what you really want is: T = D*/B + /D*/S + /B*/S The trick is how to coax VHDL to generate this, and prevent Xilinx software from optimizing away the /B*/S term. You can try just specifying the equation as-is in VHDL: T <= (D and not B) or (not D and not S) or (not B and not S); and then try applying the NO_REDUCE attribute to signal T. Something like: attribute NO_REDUCE : boolean; attribute NO_REDUCE of T : signal is TRUE; You'll probably have to struggle with the VHDL for a while. It helps to be able to view the EDIF file to see that it's doing what you want. Once the synthesized logic and attributes appear properly in the EDIF file, then the Xilinx software might do what you want. (If B, D, or S are also combinatorial outputs, then you might have to attach the NOMERGE attribute to them.) Good luck. -- Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby Fermi National Accelerator Lab Phone: 630-840-3668 Batavia, IL 60510 Fax: 630-840-5406Article: 17884
Stuart Clubb wrote: > Now, as I'm a good British "Subject" I have not seen what the Free-DES > core contains but if we assume that they do both implement the same > basic functionality, we should not infer that the two benchmarked > synthesis tools are appalling, should we? > > No. Instead we should perhaps assume that one designer has a more > "elegant" solution than the other and that one synthesis tool makes a > better job with a "less optimal" design than the other. You can't make that conclusion. The comparison between FPGA Express and Synplify was made using a 64x4 ROM. Synplify did this ROM in 10 slices, while FPGA Express did it in 30-33 slices. The ROM was designed using a basic VHDL case statement. It just happens that this inefficiency of FPGA Express manifested itself greatly in the fast version of the Free-DES core, where 64 of those ROM's are being used. If the Free-DES core itself was used as the benchmark, then I might agree with your conclusions. But since it was done with a simple ROM... Now, as for the inefficiency of the Free-DES core... What do you expect for a free core?!?!? But seriously... Since doing the Free-DES core, I've learned a thing or two about Xilinx constraint files. I think that the fast version could probably be constrained better to reach 60+ MHz with no modifications to the VHDL source. Perhaps there is some modifications that will help it reach 100 MHz. One such modification is mentioned on the Customization page, accessible from the Free-DES main page. The size of the Fast-DES core is actually very close to optimal. If you add up all the slices required for the various registers, ROM's, and XOR's then you get a figure that is within 5% of what the fast core really is. There might be some optimization left in it, but size is close to optimal. The small DES core could be made better. The key generation part of that core is not very optimal and could be pipelined for additional speed and optimized to make it much smaller. It certainly appears that the small core could be made to fit into 255 slices. That certainly sounds like something to put on my task list (right after the other 30+ things on my task list). David Kessner davidk@free-ip.com http://www.free-ip.comArticle: 17885
Yekta Ayduk wrote in message <37DF8499.A2E376CC@netas.com.tr>... >Does anybody know when xilinx v2.1i will be available? A few weeks ago. I've already installed it - and service pack 1. -- a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ eduArticle: 17886
In article <37DF8499.A2E376CC@netas.com.tr>, Yekta Ayduk <yekta@netas.com.tr> wrote: > Does anybody know when xilinx v2.1i will be available? > > Not only is M2.1i already available, SR1 is up on the Xilinx web site. -- Greg Neff VP Engineering Microsym Computers Inc. Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17887
Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.angelfire.com/in/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services What's New section outlines the changes in different versions and announcements. Links connects you to related informative links in internet. Your suggestions to make this FAQ more informative are welcome. Rajesh Bawankule (Also Visit Verilog & EDA Page : http://www.angelfire.com/in/rajesh52/verilog.html ) Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17888
On Wed, 15 Sep 1999 10:16:57 -0600, David Kessner <davidk@free-ip.com>
wrote:
>You can't make that conclusion. The comparison between FPGA Express
>and Synplify was made using a 64x4 ROM. Synplify did this ROM in
>10 slices, while FPGA Express did it in 30-33 slices. The ROM was
>designed using a basic VHDL case statement.
OK, but why 10 slices? As far as I can see (sorry, I know) an S box is
a 6 input, 4 output function ROM. Schneier (and most other texts) even
put it in 4 blocks of 16 numbers using the central bits and outside
pair to index the four rows.
So for each output bit of an S-Box you would would require four 16 bit
LUTs (4 bit input) muxed with a 4:1 multiplexer using the other two
bits. Now, any Xilinx Virtex "guru" will say:
"Right, that's four LUTS, two MUXF5's and a MUXF6. Fast, and area
efficient. 32 outputs should therefore be 32*4 = 128 LUTs. and 64
slices"
I have the S-Boxes lying around as a constant (array of integers) so
that I could just index it with conv_integer (big case staement
otherwise) to check.
In Spectrum 1999.1e I get what the Xilinx "guru" would expect : 64
slices total after map. Are you still saying Synplify was (10*8) = 80
for the S-boxes?
BTW, you are right, the really tough stuff for area is in the key
generation.
A round of DES can actually be done in exactly 208 Virtex LUTs. The
critical path should be as follows:
LUT2 (XOR post expansion permutation with key)
LUT4 (part of S-Box)
MUXF5 (part of S-Box)
LUT4 (part of S-Box and final XOR with LH Side of text in)
(this is why you can run it real fast in a -6)
The number count goes as follows:
Initial XOR (2ip * 48-bit) = 48 LUTs
S-Boxes (32 * 4LUT) = 128 LUTs
Final XOR stage (32-bit) = 32 LUTS
---
208 LUTs
Mine is (courtesy of Spectrum) all of the above :-)
The final stage is interesting as you shouldn't use a MUXF6 for the
S-Box, as you will still need a stand-alone XOR for the final xor out
of the P-Boxes, so better to avoid the F6 additional delay. Wow!
aren't some synthesis tools clever?
Cheers
Stuart
For Email remove "NOSPAM" from the address
Article: 17889On Wed, 15 Sep 1999 17:01:34 GMT, Greg Neff <gregneff@my-deja.com> wrote: >Not only is M2.1i already available, SR1 is up on the Xilinx web site. And it's great with Virtex. Shame about the new coregen though. What a pain, all that configuration stuff for simulation :-( Cheers Stuart For Email remove "NOSPAM" from the addressArticle: 17890
Stuart Clubb wrote in message <37dffa9f.5193029@nntp.netcomuk.co.uk>... >On Wed, 15 Sep 1999 17:01:34 GMT, Greg Neff <gregneff@my-deja.com> >wrote: > >>Not only is M2.1i already available, SR1 is up on the Xilinx web site. > >And it's great with Virtex. Shame about the new coregen though. What a >pain, all that configuration stuff for simulation :-( that configuration stuff in the CORE libraries lead to my thread about configurations on comp.lang.vhdl. however, now I actually understand configurations, so I guess it was a couple of days' pain for a lifetime of gain! or something like that ... -- a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ eduArticle: 17891
This is a multi-part message in MIME format. --------------F876CDB41B57B1E207AFE39E Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Mike, thanks for a very good description of partial evaluation. As for FPGAs, you correctly point out that current place and route technology is not suitable for implementing partial evaluation in a straight-forward manner. A project at the University of Glasgow's Computing Science Department explored performing partial evaluation on XC6200 FPGAs by effectively doing constant propagation at run-time. We developed our own model of the FPGA resources and because we know representation of the programming information we could simplify cells and coalesce short wires into long wires. Yes, this does not save space, only time (if you're lucky). This is the work that I presented at the summer school you mention (I moved from Glasgow to be assimilated by Xilinx). Several papers have been written about how this system was implemented, tested and formally verified to prove that the right thing will happen at run-time. A good place to start looking is http://www.dcs.gla.ac.uk/~tfm/dynhw/ or I would be happy to answer any more specific questions or supply PDFs of papers or reports. Kind regards, Satnam Singh Xilinx Labs, San Jose, CA. Mike Thyer wrote: > wudong99_1998@my-deja.com writes: > > I read the phase "Partial Evaluation" from many papers but I don't know > > the exact meaning of it. Who can tell me the meaning or where I can > > find the meaning. Thanks! > > I'd be interested to know in which papers you've come across > this term. I wasn't aware much work had been done on applying > partial evaluation in the context of FPGAs, although I know > that someone at Xilinx has been working on it, (they presented > work at the Partial Evaluation Summer School in 1998). > > Anyway to answer your question, Partial Evaluation (PE) is a > technique, applicable to pretty much any programming language, > where you supply some input to the program earlier than other > input. An example would be a cryptographic encoder, where you > supply the encryption key and the data to encode. A general > purpose algorithm will work slowly as it repeatedly consults > the key to figure out what it needs to do. Partial evaluation > takes the general purpose program and a key but not the data > to encrypt and "partially evaluates" it, that is it evaluates > the expressions it can and leaves the expressions it cannot. > The left over expressions, known as the residual code, then > constitutes a program that is dedicated to encrypting data > with just that key. This code is thus hard wired to the key > that was given to the partial evaluator, many "if" expressions > will have already been evaluated during partial evaluation > and will not exist in the residual code and the residual code > may run many times faster. > > Partial evaluation can be applied to more complicated programs > such as interpreters. Partially evaluating an interpreter > with respect to some program can effectively compile that > program thus eliminating the interpretive overhead without > a compiler ever having been written. > > FPGAs can also be seen as removing interpretive layers in that > they remove the need to have a microprocessor repeatedly interpret > its instructions when in a loop. > > Combining these two ideas together makes it possible to make > very much faster solutions to things like encryption where the > gates being used in the FPGA will vary dynamically depending on > the key being used. > > I should perhaps mention I don't know very much about FPGAs past > the general concept, but as I understand it the length of time > taken by the place+route algorithm hinders the application of > partial evaluation. The work at Xilinx involved eliminating > gates and reducing the number of hops in connecting wires after > the place+route algorithm had been applied, thus the resulting > circuit may be faster but wouldn't occupy any less space. > Perhaps a cheap'n'cheerful place+route strategy would be useful > for such dynamically generated circuits. It needn't be as optimal > as existing strategies to outperform them, as existing strategies > would only be applied to the general solution to the encryption > circuit, the cheap'n'cheerful one could be applied dynamically to > the residual circuit. Given my relative lack of knowledge of FPGAs > you shouldn't construe this paragraph as comming from someone who > entirely knows what they are talking about. > > Mike > > ps. this book [1] is a good introduction to partial evaluation, > I don't believe it mentions FPGAs once though. > > [1] Partial Evaluation and Automatic Program Generation, > Neil Jones, Carsten Gomard and Peter Sestoft, Prentice Hall 1993. --------------F876CDB41B57B1E207AFE39E Content-Type: text/x-vcard; charset=us-ascii; name="Satnam.Singh.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Satnam Singh Content-Disposition: attachment; filename="Satnam.Singh.vcf" begin:vcard n:Singh;Satnam tel;pager:4087182588@messaging.cellone-sf.com tel;cell:(408) 718 2588 tel;fax:(408) 559 7114 tel;home:(408) 377 9982 tel;work:(408) 879 4693 x-mozilla-html:TRUE org:<br><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx"> adr:;;2100 Logic Drive;San Jose;CA;95124-3450;USA version:2.1 email;internet:Satnam.Singh@xilinx.com title:Senior Staff Engineer x-mozilla-cpt:;-28032 fn:Satnam Singh end:vcard --------------F876CDB41B57B1E207AFE39E-- Article 24986 of comp.lang.vhdl:Article: 17892
Does anyone know of commercial PMC cards with Xilinx FPGA capability? (Ideally I need a card with DMA or FIFO capability). If you have any leads, please drop me a line at pclapis@pantheon.yale.edu. Thanks!Article: 17893
Non-proprietary sw packages will cost much more than vendor-specific tools. Synplify from Synplicity, FPGA Express from Synopsys and Leonardo from Exemplar are three popular tools, but to get one of these that supports multiple vendors is going to run $5K-$20K. Lattice/Vantis has a tool called Design Direct Vista that includes VHDL and Verilog support for all devices using the Exemplar engine. ($1500) (this targets the Vantis mach and pal devices) Lattice/Vantis also has a tool with the Synplicity tool included for $995 Xilinx has Foundations Base Express with Synopsys FPGA Express as the engine for $95. But if you want support for 16V8s, 22V10s, etc, you'll have to go to Lattice/Vantis unless you want to spend more for a non-proprietary package. Ken leejp@my-deja.com wrote in message <7ro3mg$a8u$1@nnrp1.deja.com>... >Forgot to mention... I would prefer a non-proprietary tool. Something >that I can use to program components from different vendors. >Additionally, the tool must handle even the simplest of PAL devices >(16V8's).. > >Thanks... > > >Sent via Deja.com http://www.deja.com/ >Share what you know. Learn what you don't.Article: 17894
> now I actually understand > configurations, so I guess it was a couple of days' pain for a lifetime of > gain! How about a brief on what you learned....Article: 17895
"Harford Communications, Inc." wrote: > But if you want support for 16V8s, 22V10s, etc, you'll have to go to > Lattice/Vantis unless you want to spend > more for a non-proprietary package. Or you could decide not to go with VHDL for those applications. VHDL will give you a degree of portability which depends upon the amount of thought you put into designing for portability in the first place. However, Vantis Design Direct Base is FREE, positively pleasant to use (especially if you're accustomed to PALASM/MACHXL), and allows you to build designs using ABEL HDL, schematic capture, or a combination of the two. And later on you can upgrade to Vista, and add VHDL support to the combination as well. However, the original poster was interested in using VHDL for educational purposes, and also asked about books. As has already been pointed out, I doubt you're going to find a cheap product with multi-vendor support, so you might want to look at your educational aims and immediate design goals as separate issues. The book "VHDL for Programmable Logic" by Kevin Skahill is a good educational text, with a strong emphasis on synthesis, which comes complete with a copy of Cypress' Warp software (my copy is quite dated now -- I'm not sure if there's a new update). This will target PAL-type devices, but not Vantis MACH devices. Also, the latest edition of "Digital Design: Principles and Practices," by Wakerly now covers VHDL and includes the Xilinx student edition software. I haven't seen a copy of this book myself yet, but the previous edition is a very good book, so I'd expect that the new edition is worth checking out. MarkArticle: 17896
Hi,
I am trying to use rloc constraints in my UCF file, and for that I use
the 'hset' constraint:
INST "cam/encoder" hset = "set1";
Now M1 gives the error shown below:
ERROR:NgdHelpers:32 - Invalid UCF/NCF file entry value detected while
reading
UCF file "interface_board.ucf" at line number 18. Value is "hset".
ERROR:NgdBuild:31 - Errors found while parsing .ucf file
"interface_board.ucf".
Please check for syntax errors in the UCF file. For more
information on
legal UCF constraints, please see the "Attributes, Constraints, and
Carry
Logic" section of the Libraries Guide.
Does anyone know what the problem is?
Johan
Article: 17897Interesting, but where to find the service pack 1? The following URL http://www.xilinx.com/support/techsup/sw_updates/ states, that there is no service Pack for 2.1i so far Best Regards Ansgar Bambynek Andy Peters schrieb in Nachricht <7roi3u$29nu$1@noao.edu>... >Yekta Ayduk wrote in message <37DF8499.A2E376CC@netas.com.tr>... >>Does anybody know when xilinx v2.1i will be available? > >A few weeks ago. I've already installed it - and service pack 1. > > >-- a >----------------------------------------- >Andy Peters >Sr Electrical Engineer >National Optical Astronomy Observatories >950 N Cherry Ave >Tucson, AZ 85719 >apeters (at) noao \dot\ edu > > >Article: 17898
Hi again, hope somebody can help me. I am looking for a simple SCHEMATIC UART (not vhdl) for ACTEL FPGAs with 1 start, 8 data, parity (even, odd, no), 1 stop bit.Article: 17899
I have Design Direct Base installed on my machine and while I find it rich in features, I don't find the documentation and the tutorials straightforward at all as with the previous generation products that I have used PALASM and MACHXL... especially when it comes to ABEL-HDL (I am new to ABEL-HDL as well). Further, my desire is to go to a more widely accepted language... VHDL or Verilog. The book "VHDL for Programmable Logic" by Kevin Skahill has been recommended to me by many.. along with the Warp software. My Cypress rep is sending me both and offering to run a 1 day VHDL class for us. So I'm kind of leaning towards this route... The price is right and I understand that the Warp software can generate output for simple PLD's from multiple vendors... 26V12's 22V10's and 16V8's for example. Is this true? Additionally... you can compile, simulate your designs using Warp and target to a non Cypress part using a fitter from that vendor... True as well? Thanks... Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.
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