Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Tippawan Aranwattananon wrote: > > I have design a small core in VHDL and I would like to know if I use > difference tools to synthesize my VHDL code, will the numbers of CLB from > those tools be difference. Yes, different tools will build the same design into different numbers of CLBs, and the results will run at different maximum clock rates. Even with the same tool, some reduction in size can sometimes be made by reducing the speed at which the design runs, and some increase in speed can be obtained by an increase in area. Some reduction in size and/or increase in speed can also sometimes be made by directives to the tool as to how to build the design. > And if you know any excellent tools for synthesize please recommend. I use and recommend "Synplify" by http://www.synplicity.com. Another good tool is "Leonardo Spectrum" by http://www.exemplar.com, which I have evaluated with a trial license. If you can get a trial license for one or both, try them and see how they work with your design. -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principle." Carl SaganArticle: 16276
basaro wrote: > Hellow Everyone. > > I'm T.Koyama > > Can use Pullup in XC9500XL when user operation. > > XC9500 does not use Pullup, but XC9500XL? > Currently you cannot use internal IOB pullups during normal user operation of the 9500/9500XL/9500XV. Please take a look at the following solution record located at: http://www.xilinx.com/techdocs/3026.htm > > If it can use, Please teuch me how use. > > Thank you > T.Koyama (basaro@fa2.so-net.ne.jp) Mamoon Xilinx ApplicationsArticle: 16277
In article <37370789.1F614E9D@xilinx.com>, Peter Alfke <peter@xilinx.com> writes >Because hardly anybody asks for the data. Thanks, Peter, for doing this work anyway, in spite of hardly anybody asking. But apart from the Apps group, it would be nice if there was some indication that this issue was taken seriously by the company as a whole. Perhaps a different question to ask is: How much market share would Xilinx lose if the devices had just a single clock pin? I'd suspect there'd not be many customers left. And if customers are using more than one clock pin, they need the metastability data. It just might be useful also if there were development tools to support the synchronising flip-flops, so that simulators simulated the actual behaviour instead of complaining about failure to meet setup and hold times. Sorry to whinge, but with SoCs and multiple clock domains in almost anything these days, this issue really needs to be addressed. Paul -- 140 MBaud asynchronous communications, with FIFOs, flow-control and autobaud, in a Spartan XCS05. IEEE 1355 solutions from 4Links. Paul Walker 4Links phone/fax paul@4Links.co.uk P O Box 816, Two Mile Ash +44 1908 http://www.4Links.co.uk Milton Keynes MK8 8NS, UK 566253Article: 16278
> roman pollak wrote: > > Hi, > > I'm currently develope a graphic interface for my 68040 board at home > using FPGA and VDRAM. > But I got a very fancy problem with it, which I can't get of it. > When the CPU is writing to the RAM, sometimes it also overwrite other > locations as well. > For example when the cpu is writing on the line X pos Y, it overwrites > also some other location on the same line. Could it be some kind of > reflection problem? Or some other effects, which I don't know about it? > I saw in other designs, they use resistors between DRAM and Mux on the > address lines. But some other designs don't. Some use thouse on RAS/CAS, > some don't. What is the point of thouse resistors? I recommends to use a REGISTERED address and control outputs. Address and control lines of DRAM connected with FPGA outputs through 30 Ohm resistors. And check the address distribution in design, ROW and COL address sizes. DmitryArticle: 16279
If your target is Altera 10K or Xilinx Virtex, the lookup is the best and easiest solution for the input and output sizes you specify. For other FPGA without the large memory blocks, the choice is not as obvious. If I am reading this right, you need the output on the clock cycle after the input is presented. You do not mention the required clock frequency. Division is normally done with a shift-subtract type of algorithm. If it is unrolled and not pipelined, the combinatorial delay will be quite large. If you can pipeline it, you can improve the throughput at the expense of clock latency. In tbat case, you get a result every clock cycle, but it will take a number of clocks for a giver result to come out. If your clock frequency requirements are not high, you could set it up as an iterative process clocked by a multiple of your data clock. If you really need to process in a single clock, the best solution is probably a look up table. If the FPGA does not have large memory blocks you'll need to construct the lookup from the 4-LUTs in the FPGA fabric (each of which provides a 16x1 ROM cell). YOu'll need 256 4LUTs (128 xilinx CLBs) plus logic for either tristate decodes or multiplexers. satish_me@hotmail.com wrote: > HELO SIR, > The input a single byte(8-bits). Out put should be of 15 bits. Later I > will normalize to standard form. The data input rate is in one clock 1 > byte has to enter the reciprocator, In the other clock the reciprocal > has to come out. > Satish Kumar. > In article <3730482D.6C7CAD88@ids.net>, > Ray Andraka <randraka@ids.net> wrote: > > How many bits accuracy do you need?, what is bit width of the input > and output?. > > What is the required data rate and the available clocks (ie. how many > clocks are > > allowed to do this). These parameters will greatly affect the > implementation. > > > > satish_me@hotmail.com wrote: > > > > > Hai, > > > I am research fellow from India. For one of my VHDL project I need > a > > > reciprocator. Like If I give Input 10, The out put should be 1/10 > that is 0.1, > > > For 3 it should be 0.33. For this I need a VHDL code, or implemented > FPGA. > > > This should be true for all numbers. > > > Any suggestion or code is highly appreciable. Thanks in advance. > > > Please communicate to my email:satish_me@hotmail.com > > > > > > -----------== Posted via Deja News, The Discussion Network > ==---------- > > > http://www.dejanews.com/ Search, Read, Discuss, or Start Your > Own > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka > > > > > > --== Sent via Deja.com http://www.deja.com/ ==-- > ---Share what you know. Learn what you don't.--- -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16280
Hans Christian Lønstad wrote: > > Tony Kirke wrote: > > > There seems to be more support/usage of Xilinx than Altera Devices for DSP > > Designs (FIRs, FFTs, Cordic, etc). > > My company already has Altera tools but I don't want to be limited by that > > choice. > > Please let me know if you think Altera is better or equivalent for DSP > > designs (or if you Xilinx is definitely superior). > > Thanks, > > I'll sumarise later for the group. > > Tony > > > > **** Posted from RemarQ - http://www.remarq.com - Discussions Start Here (tm) **** > > First of all, you CAN do large DSP designs in Altera 10K. I've successfully ...snip... > Opinion: > > Xilinx 4k may give you a performance edge if you are willing to invest more time in > floorplanning. > The Virtex family with its vector based interconnect has the potential to be synthesis > friendly. It also adds resources enabling multipliers to run at higher speeds. > > Givens good synthesis tool support, the Xilinx Virtex family seems most apt to DSP > development. > > -- > Hans Christian Lønstad Data Respons AS It sounds like you have done your homework well. I see that the original poster did not ask about Lucent, but I am considering using the OR3T series of parts for a board I am designing. How do you think that there parts stack up in this comparison? As far as I can tell, for a given price, the Lucent parts give you more logic, run as fast and more I/Os, even in the same package. My current design is rather I/O bound, needing over 200 I/Os. In the Xilinx family I have to go to bigger parts just to get the higher I/O counts. Has anyone used the Lucent parts and software? Lucent is giving away an entry level development system which will support all of their devices up to the 30K gate devices. This includes a VHDL compiler, I believe (unfortuately, it is FPGA Express from Synopsis). Any opinions on this software? -- Rick Collins rick.collins@XYarius.com remove the XY to email me.Article: 16281
> roman pollak wrote: > > Hi, > > I'm currently develope a graphic interface for my 68040 board at home > using FPGA and VDRAM. > But I got a very fancy problem with it, which I can't get of it. > When the CPU is writing to the RAM, sometimes it also overwrite other > locations as well. > For example when the cpu is writing on the line X pos Y, it overwrites > also some other location on the same line. Could it be some kind of > reflection problem? Or some other effects, which I don't know about it? > I saw in other designs, they use resistors between DRAM and Mux on the > address lines. But some other designs don't. Some use thouse on RAS/CAS, > some don't. What is the point of thouse resistors? I recommends to use a REGISTERED address and control outputs. Address and control lines of DRAM connected with FPGA outputs through 30 Ohm resistors. And check the address distribution in design, ROW and COL address sizes. DmitryArticle: 16282
EuroEDA Limited and Logical Devices Inc. are pleased to announce an attractively priced trade-in offer for users of ABEL, MINC or Synario wishing to upgrade to V5.0 of the popular, low-cost universal PLD, CPLD & FPGA design tool CUPL. The new 32-bit version of CUPL allows design entry by schematics, graphical state diagrams, high-level equations or VHDL and includes powerful design simulation and partitioning capability. CUPL provides comprehensive support for many leading programmable device technologies and manufacturers. Email info@euro-eda.com for full details, or visit the "PLD & FPGA Design Software" page of our web site at http://www.euro-eda.com -- EuroEDA Limited Phone: +44 (0)1933 676373 Fax: +44 (0)1933 676372 Email: info@euro-eda.com Web: http://www.euro-eda.comArticle: 16283
Hi,
I have bought the Xilinx demo board containing two FPGAs: one XC3020A
and XC4003A. I haven't received any sample LCA design to try on it: on
the manual "Hardware.pdf" I found at the Xilinx Web site I'm asked to
find it in : \xact\examples\core\xchecker directory.
I have recently installed a copy of Alliance 1.5 and can't find nothing
similar: can you tell me where may I find something similar ?
Thank you very much.
Davide
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Davide Falchieri
VLSI & Fuzzy Logic Research Group
Physics Department, Bologna University
40127,Viale Berti Pichat 6/2, Bologna(ITALY)
TEL:+39-51-6305077, FAX:+39-51-6305297
URL:http://sunvlsi4.bo.infn.it/~davide
e-mail : davide.falchieri@bo.infn.it
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Article: 16284I would like a trivial example of a circuit written in Verilog that can be synthesized with Exemplar and loaded onto a Xilinx part. I just need something that shows typical pin instantiations, etc. I have searched both Exemplar's web site and Xilinx's web site and have found nothing of the sort. If anyone can help, that would be most appreciated. --== Sent via Deja.com http://www.deja.com/ ==-- ---Share what you know. Learn what you don't.---Article: 16285
To paraphrase from a different realm: Any young engineer who hasn't dreamt up a circuit to overcome metastability, lacks imagination. Any experienced engineer who still dreams of one, has no brains. Peter Alfke, Xilinx Applications ( who thought of several perpetual motion schemes in his early youth ). Mark Summerfield wrote: > Peter Alfke wrote: > > > There is no way ( NO WAY ! ) to avoid metastability... > > I used to teach a course in digital design in which I covered > metastability. I would stand there in class and say "there is no way > (NO WAY!) to avoid metastability", and I would refer the students > to the same statement and explanation in their textbook, and every > year at least one student would come to me with a circuit s/he > claimed would be metastable-free. I would patiently explain why > it wouldn't work, but there are always a few who won't believe. > > I'm sure they're the same students who are designing perpetual-motion > machines for their thermodynamics lecturers, too! ;-) > > MarkArticle: 16286
Different tools deliver different results. Different versions of the same tool will also give different results. Further, the results can vary by the type of design, style of VHDL coding, and target vendor and device. You received other emails pointing you towards Synplify from Synplicity and Leonardo from Exemplar. You should also look at FPGA Express, which is engineered by Synopsys and distributed through Viewlogic, VeriBest and Xilinx. You can go to the Viewlogic (www.viewlogic.com) to get evaluation software; you can also get evaluation software from VeriBest and Xilinx. Regards, -Jim Tippawan Aranwattananon wrote: > I have design a small core in VHDL and I would like to know if I use > difference tools to synthesize my VHDL code, will the numbers of CLB from > those tools be difference. > And if you know any excellent tools for synthesize please recommend. > > realk@thaimail.com -- -------------------------------------------------------- James R. Kipps FPGA Marketing Manager jkipps@viewlogic.com Phone: (508) 303-5246 --------------------------------------------------------Article: 16287
This is a multi-part message in MIME format. --------------06C6787FE5C710DC25E70B9B Content-Type: multipart/alternative; boundary="------------2654E095BE321C796ED2B772" --------------2654E095BE321C796ED2B772 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Try: http://support.xilinx.com/support/techsup/tutorials/index.htm#Exemplar Hope this is what you are looking for. -- Brian Timothy Miller wrote: > I would like a trivial example of a circuit written in Verilog that can > be synthesized with Exemplar and loaded onto a Xilinx part. I just need > something that shows typical pin instantiations, etc. > > I have searched both Exemplar's web site and Xilinx's web site and have > found nothing of the sort. > > If anyone can help, that would be most appreciated. > > --== Sent via Deja.com http://www.deja.com/ ==-- > ---Share what you know. Learn what you don't.--- -- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 ------------------------------------------------------------------- --------------2654E095BE321C796ED2B772 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>Try: <A HREF="http://support.xilinx.com/support/techsup/tutorials/index.htm#Exemplar">http://support.xilinx.com/support/techsup/tutorials/index.htm#Exemplar</A> <p>Hope this is what you are looking for. <br> <p>-- Brian <br> <br> <p>Timothy Miller wrote: <blockquote TYPE=CITE>I would like a trivial example of a circuit written in Verilog that can <br>be synthesized with Exemplar and loaded onto a Xilinx part. I just need <br>something that shows typical pin instantiations, etc. <p>I have searched both Exemplar's web site and Xilinx's web site and have <br>found nothing of the sort. <p>If anyone can help, that would be most appreciated. <p>--== Sent via Deja.com <a href="http://www.deja.com/">http://www.deja.com/</a> ==-- <br>---Share what you know. Learn what you don't.---</blockquote> <pre>-- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 -------------------------------------------------------------------</pre> </html> --------------2654E095BE321C796ED2B772-- --------------06C6787FE5C710DC25E70B9B Content-Type: text/x-vcard; charset=us-ascii; name="brianp.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brianp.vcf" begin:vcard n:Philofsky;Brian tel;fax:(408) 879-4442 tel;work:1-800-255-7778 x-mozilla-html:TRUE org:<BR><H1 ALIGN="CENTER"><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx" ALIGN="CENTER"> Design Center version:2.1 email;internet:brianp@xilinx.com title:<H3 ALIGN="CENTER"><img src="http://bennyhills.fortunecity.com/deadparrot/108/homer.gif" alt="Homer" align="center"> Application Engineer adr;quoted-printable:;;2100 Logic Drive=0D=0ADept. 2510;San Jose;CA;95124-3450;USA x-mozilla-cpt:;15200 fn:<H3 ALIGN="CENTER">Brian Philofsky end:vcard --------------06C6787FE5C710DC25E70B9B--Article: 16288
I'm not sure what you are asking...do you want to take a C program and convert that into another C program that works for fixed point numbers? or do you want this software to 'automatically' convert a C program and convert that into a FPGA implementation in fixed point (say VHDL)...the latter one is too far fetched...the first one - I can't think of any software that will do this...but you can do it yourself if you are willing to put in some effort... you need to take the results of every arithmetic operation and let's say you want 24 bit precision, you have to divide by 2^24 and the do a 'fix' operation on it and save that result. The result will now be in 24 bit fixed point. This changes a little if you want signed fractional notation for the fixed point numbers (You'll need to use 2^23 instead). Cheers Bhaskar In article <373A1966.3C3B@bell.info.uqam.ca>, Jean-Francois Richard <richard@bell.info.uqam.ca> wrote: > I did an algorithm in C language and I want to do > the implementation on a FPGA. The algorithm is on > floating points and I would like to > transfert that on fixed points. > > Any good software that do the conversion AUTOMATICALY ? > Do they calculate the quantization error ? > --== Sent via Deja.com http://www.deja.com/ ==-- ---Share what you know. Learn what you don't.---Article: 16289
On Thu, 13 May 1999 16:25:42 +0100, info <info@euro-eda.com> wrote: >EuroEDA Limited and Logical Devices Inc. are pleased to announce an >attractively priced trade-in offer for users of ABEL, MINC or Synario >wishing to upgrade to V5.0 of [blah, blah] CUPL. > >The new 32-bit version of CUPL allows design entry by schematics, >graphical state diagrams, high-level equations or VHDL and includes >powerful design simulation and partitioning capability. CUPL provides >comprehensive support for many leading programmable device technologies >and manufacturers. It is of course left as an exercise for the customer to decide whether CUPL is a better design environment than Synario. I can't speak for MINC, I don't get on well with ABEL, but I have some experience of both Synario and CUPL and I thought perhaps the question was worth asking (;->) Suggestion: Try before you buy. There's a free version of CUPL, for TI PLDs only, available via TI's website. I got it working without any bother, which was not true of the evaluation copy of CUPL I subsequently asked for. In fairness, that latter problem might just be a perversity of WinNT. Own Opinions Only. Jonathan BromleyArticle: 16290
roman pollak wrote: > > Hi, > > I'm currently develope a graphic interface for my 68040 board at home > using FPGA and VDRAM. > But I got a very fancy problem with it, which I can't get of it. > When the CPU is writing to the RAM, sometimes it also overwrite other > locations as well. > For example when the cpu is writing on the line X pos Y, it overwrites > also some other location on the same line. Could it be some kind of > reflection problem? Or some other effects, which I don't know about it? > I saw in other designs, they use resistors between DRAM and Mux on the > address lines. But some other designs don't. Some use thouse on RAS/CAS, > some don't. What is the point of thouse resistors? > > thanks Roman First, I assume that you are using an actual PCB, and not a wire-wrap or similar prototyping system. It is difficult to get such a system to work properly, to avoid undershoot/overshoot, ringing, and other such 'analog' effects. As others have suggested, check your logic very carefully. Ensure that you meet the timing requirements of the DRAM between all different types of cycles (e.g. between read and write cycles, read and refresh, refresh and read ...). In particular, check that you are meeting the cycle time requirements, address and data set up and hold times, RAS and CAS precharge time requirements, and that you hold the read/write signal the proper length of time after a read cycle before asserting the write signal. Further, check that your memory cycles are being terminated correctly for all sizes of cycles (both read and write). Also, get a good, fast oscilloscope with appropriately fast probes, and look at the signals that are present on the memory chips. Nothing beats direct observation, other than perhaps good diagnostics. -- PhilArticle: 16291
Peter Alfke wrote: > Any young engineer who hasn't dreamt up a circuit to overcome metastability, > lacks imagination. Any experienced engineer who still dreams of one, has no > brains. ;-) The discussion in that other thread suggests that there are plenty of imaginitive engineers with no brains -- otherwise *why* aren't more people asking for metastability parameters? As Paul Walker has pointed out, just about everybody *needs* them, they just don't know (or care?) that they need them. On the other hand, I know very few engineers of any age who are socialists... MarkArticle: 16292
On Fri, 14 May 1999 08:57:26 +1000, Mark Summerfield <m.summerfield@ee.mu.oz.au> wrote: >The discussion in that other thread suggests that there are plenty of >imaginitive engineers with no brains -- otherwise *why* aren't more >people asking for metastability parameters? As Paul Walker has pointed >out, just about everybody *needs* them, they just don't know (or care?) >that they need them. For more engineers to believe in metastability, more engineers must get bitten by it. And for more engineers to get bitten, the MTBF of a poorly-designed circuit must drop below the MTBJ (mean time between jobs). I'm only half kidding; it's amazing how many metastability problems are solved by some poor soul who's taken over a design after the designer has left for another company. Such is life in the valley, anyway. Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 16293
FPGA express is not currently as capable as SYnplicity and Exemplar, at least from a standpoint of creating relatively placed macros. I do alot of structural instantiation with relative placement to get the performance and density I need. I previously was constrained to schematics to do this, but with the capability to support and pass user attributes through to the EDIF output, I know I can get the results I need from Synplicity, and while I haven't tried it in exemplar, I understnd their tool will do it too. FPGA express definitely does not. Jim Kipps wrote: > Different tools deliver different results. Different versions of the same > tool will also give different results. Further, the results can vary by the > type of design, style of VHDL coding, and target vendor and device. > > You received other emails pointing you towards Synplify from Synplicity > and Leonardo from Exemplar. You should also look at FPGA Express, > which is engineered by Synopsys and distributed through Viewlogic, > VeriBest and Xilinx. You can go to the Viewlogic (www.viewlogic.com) > to get evaluation software; you can also get evaluation software from > VeriBest and Xilinx. > > Regards, > -Jim > > Tippawan Aranwattananon wrote: > > > I have design a small core in VHDL and I would like to know if I use > > difference tools to synthesize my VHDL code, will the numbers of CLB from > > those tools be difference. > > And if you know any excellent tools for synthesize please recommend. > > > > realk@thaimail.com > > -- > -------------------------------------------------------- > James R. Kipps FPGA Marketing Manager > jkipps@viewlogic.com Phone: (508) 303-5246 > -------------------------------------------------------- -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16294
Don Husby wrote: > > Ray Andraka <randraka@ids.net> wrote: > > There are a few devices out there that support partial reconfiguration to > > varying degrees. Currently sold devices include Atmel 6K and 40K, Xilinx > > 6200 and Virtex. > > And Lucent. You always forget Lucent. > Am I the only one in the world using these chips? There you are. I knew there must be someone using Lucent FPGAs. I am looking really hard at using an OR3T chip for the main FPGA on a board I am designing and I would like to find out how you like the software. I have read the data sheet on both the OR2t and OR3T parts and like the chips alot, but I haven't had time yet to play with the software. I have been using the Xilinx parts off and on for several years. I also did a design once using an OR1C (ATT1C?) part. At that time the ODS tools (as well as the Xilinx) were really pretty bad. The current Xilinx tools are much improved over what they were even just a couple of years ago. Can you compare the current Lucent tools with the current Xilinx tools? I will be installing the free version of their tool set (limited to 30K gate parts) over the next week or so. I have to commit to a chip line as I design the configuration logic. Although they program much the same, the Xilinx parts have a few less available I/Os and I must compensate by adding more logic for data busses around the chip instead of through it. So it ends up affecting the configuation design. I don't plan to use VHDL very much as I have found that Ray Andraka and some of the other "Schematic or die!" advocates are pretty much on target if you are trying to fully utilize the parts. I may still use VHDL for some state machine entry since it is much easier to make modifications to. But otherwise, I plan on using primarily schematic entry. Can you offer any cavets or point out any special bonuses to using the Lucent tools over the Xilinx tools? For example, how do they handle timing constraints? Do they use a constraints file like Xilinx? Or do they have some sort of GUI as the latest Xilinx software supports? -- Rick Collins rick.collins@XYarius.com remove the XY to email me.Article: 16295
Paul Walker wrote: > > In article <37370789.1F614E9D@xilinx.com>, Peter Alfke > <peter@xilinx.com> writes > >Because hardly anybody asks for the data. I use the metastability data. Thanks. I have not needed to ask because it was published. > How much market share would Xilinx lose if the devices had just a > single clock pin? I don't think that this is quite fair. Clock pins and buffers are used and needed for signals other than clocks. Any large fanout signal on a critical path of a design might gain significantly from using a buffer. An example would be the I/O enable for a bus. Also, a design may well have multiple clocks with no metastability issue if the clocks are harmonically related frequencies, or are simply different phases of the same clock. In my designs at least, such uses of clock pins and BUFGs are more common than unrelated clocks. -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principle." Carl SaganArticle: 16296
In my current project I am confronted with many
on-chip (FPGA or ASIC) interconnection problems.
Of course I know a lot of concepts (bus, xbar,
segmented routing etc.) but would like to have
a survey paper.
I know the thesis by Andre DeHon and the work in
toronto, but would like to have a more general
point of view.
Most of the design textbooks only touch the topic.
But this is such a constant and recurring issue,
there should be something.
Andreas
--
---------------------------------------------------------------
Andreas C. Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Ratzeburger Allee 160
D-23538 Luebeck Germany
Tel.: +49 451 500-3741, Fax: -3687
Email: doering@iti.mu-luebeck.de
Home: http://www.iti.mu-luebeck.de/~doering
quiz, papers, VHDL, music
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------
Article: 16297In article <373b3d73.14911274@news.u-net.com>, Jonathan Bromley <jonathan@oxfordbromley.u-net.com> writes >On Thu, 13 May 1999 16:25:42 +0100, info <info@euro-eda.com> wrote: > >>EuroEDA Limited and Logical Devices Inc. are pleased to announce an >>attractively priced trade-in offer for users of ABEL, MINC or Synario >>wishing to upgrade to V5.0 of [blah, blah] CUPL. >> >>The new 32-bit version of CUPL allows design entry by schematics, >>graphical state diagrams, high-level equations or VHDL and includes >>powerful design simulation and partitioning capability. CUPL provides >>comprehensive support for many leading programmable device technologies >>and manufacturers. > >It is of course left as an exercise for the customer to decide >whether CUPL is a better design environment than Synario. > >I can't speak for MINC, I don't get on well with ABEL, but >I have some experience of both Synario and CUPL and I thought >perhaps the question was worth asking (;->) > >Suggestion: Try before you buy. There's a free version of >CUPL, for TI PLDs only, available via TI's website. I got >it working without any bother, which was not true of the >evaluation copy of CUPL I subsequently asked for. In >fairness, that latter problem might just be a perversity >of WinNT. I don't disagree with the try before you buy suggestion but do look at the latest product and not an older restricted version. We offer demonstration CD's of CUPL 5.0 via our web site. The version you refer to would indeed be fairly limited and is certainly not the latest 32-bit 95/NT product. -- Duncan Crowther EuroEDA LimitedArticle: 16298
Dear all, I have a question regarding implementing the fuse map of an PLA device. If I have a configuration: +v +v +v A x | | B x | | C | x | | | | 0v------x-------x-----------o/p f= A.B + C How do you implement the fuse map physically? Thanks in advance. email: csoolan@dso.org.sgArticle: 16299
RAS/CAS *must* come directly from a register to be reliable in a FPGA due
to variations in routing between different synthesis runs, and even
process variations. I made the fault of generating RAS/CAS by decoding the
state machine registres in my first controller design (...some years
ago...), and got errors very similar to the ones metioned ("random"
destruction of data when doing an access).
The cause was sub 1ns spikes in the RAS signal that sometimes occurred
inbetween state changes. Took me quite some time (and a good scope!) to
identify the cause. These did not show up in simulations, as these only
covered worst case delays.
If your FPGA allows it, also place the RAS/CAS registers in the I/O block
to get much better control of the timing.
- Olaf
>
> I recommends to use a REGISTERED address and control
> outputs. Address and control lines of DRAM connected with FPGA
> outputs through 30 Ohm resistors.
> And check the address distribution in design, ROW and COL address
> sizes.
>
> Dmitry
>
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z