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I have looked your VHDL. I am quite sure the with such latching algorithm you latch one READ period before the valid data comes on data bus (because the valid address comes at the end of early READ period by HC11). In article <849cam$t69$1@cleavage.canuck.com>, jonathan@canuck.com (Susan Deike) wrote: * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 19526
I have a XCV1000 which I have been trying to program through the JTAG interface. I can scan out the device ID without a problem. When it's programmed with something as simple as a clock divider I don't get an output at all. I am currently using the constraints editor to specify IO type (lvttl). I have checked the voltages and they are fine. Does anyone have any suggestions ? Should I instantiate the io's in the code or does the p&r use the constraints file info just fine? Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19527
Hello
Does anybody know what is the meaning of the DEVICE timing parameter
in
VITAL? I have a SDF file shown below with the DEVICE parameter, but the
VITAL model doesn't have the tdevice_ generic needed. What would be the
timing error if I simply deleted from EDIF the DELAY/ABSOLUTE/DEVICE lines?
(CELL
(CELLTYPE "FDC")
(INSTANCE COUNT_LIN/COUNT_8_FIM_1_FF)
(TIMINGCHECK
(SETUP D (posedge C) (1.338:1.338:1.338))
(HOLD D (posedge C) (0.200:0.200:0.200))
(WIDTH (posedge C) (1.658:1.658:1.658))
(WIDTH (negedge C) (1.479:1.479:1.479))
(RECOVERY (negedge CLR) (posedge C) (1.300:1.300:1.300))
(HOLD CLR (posedge C) (0.200:0.200:0.200))
(WIDTH (posedge CLR) (0.863:0.863:0.863))
(WIDTH (negedge CLR) (0.001:0.001:0.001))
)
(DELAY
(ABSOLUTE
(DEVICE Q (0.161:0.161:0.161) (0.222:0.222:0.222))
)
)
Thanks in advance and Happy New Year for all readers!
PS: I did an overview of VITAL Ref Manual, but I am still in doubt...
--
| Walter Soto Encinas Jr |
| PhD Student |
| IFSC / USP |
| Brazil |
Article: 19528Hi Folks, Does anybody know where I can find an algorithm for Radix-2 online division (Radix-2 serial Signed Digit arithmetic) with a constant divisor. I need such a unit for a hardware implementation onXC4000 FPGA. I had a look at Ercegovac's book entitled " Digit Recurrence algorithms and implementations" but have not found a special algorithm for constant divisor. If someone can point me directly to an FPGA implementation, that would be great! :-) Any help is very much appreciated. Cheers.Article: 19529
Timothy Miller wrote: > > I have a XCV1000 which I have been trying to program through the JTAG > interface. I can scan out the device ID without a problem. When it's > programmed with something as simple as a clock divider I don't get an > output at all. I am currently using the constraints editor to specify > IO type (lvttl). I have checked the voltages and they are fine. Does > anyone have any suggestions ? Should I instantiate the io's in the code > or does the p&r use the constraints file info just fine? Hi Does the JTAG programmer tell you that the device is configured? If not, you may have a problem with the startup clock (see one of my previous posts) Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 19530
On Wed, 29 Dec 1999 15:45:20 -0000, J.R. <j_robby@hotmail.com> wrote: >Does anybody know where I can find an algorithm for Radix-2 online division >(Radix-2 serial Signed Digit arithmetic) with a constant divisor. I need >such a unit for a hardware implementation onXC4000 FPGA. I had a look at >Ercegovac's book entitled " Digit Recurrence algorithms and implementations" >but have not found a special algorithm for constant divisor. If someone can >point me directly to an FPGA implementation, that would be great! :-) If you are dividing by a constant, can't you just multiply by the reciprocal instead? Implementing a constant multiplier boils down into some adder trees with various shifts of the input word. KellyArticle: 19531
mcjy@my-deja.com wrote in message <84cs87$k4m$1@nnrp1.deja.com>... >For PCI core, now the market is moving >to PCI-133. But prototyping (for testing) >can be a big problem. Most FPGAs/CPLDs only >support up to PCI 66. In addition, I think >that we need to "buy" PCI specification >document. Is it still true? Methinks you're confusing the PC-133 memory standard with PCI. The fastest PCI standard is 66 MHz and a 64-bit-wide data/address bus. -- a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu The secret of Slurm is on a need-to-know basis.Article: 19532
In article <386A2E5F.87E72F27@dotcom.fr>, Nicolas Matringe <nicolas@dotcom.fr> wrote: > Timothy Miller wrote: > > > > I have a XCV1000 which I have been trying to program through the JTAG > > interface. I can scan out the device ID without a problem. When it's > > programmed with something as simple as a clock divider I don't get an > > output at all. I am currently using the constraints editor to specify > > IO type (lvttl). I have checked the voltages and they are fine. Does > > anyone have any suggestions ? Should I instantiate the io's in the code > > or does the p&r use the constraints file info just fine? > > Hi > Does the JTAG programmer tell you that the device is configured? > If not, you may have a problem with the startup clock (see one of my > previous posts) Actually, it does tell me that the device is configured. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19533
Lourens,
Anything that corrupts the ICP data stream can potentially render
the (MAX7K) program target unprogrammable. Enabling the JTAG port is a
programmable feature. Parts shipped from the factory are programmed
(default) to enable the JTAG port, but once the JTAG port is disabled,
the device is no longer programmable via the JTAG port.
What can corrupt the JTAG programming operation:
1. Active clock on the dedicated clock input, degrades noise immunity
on chip while programming. Disable clock inputs while programming.
2. Ringing/reflections on JTAG data clock signal. Altera recommends a
180 pF cap on the line, minimising the loading on the line, and
requires maximum rise/fall time.
I've seen this problem, it is very nasty (requires replacement of the
on-board device!). Once the clock was disabled for programming, there
hasn't been a single failure.
The 7K-S family (don't know about 7K-A) does *NOT* have any CRC
checking on the programming data. If an error check was in place, the
JTAG port (and other sensitive features) could be "protected".
-- Bob Elkind
Lourens Geldenhuys wrote:
>
> Hi
>
> We have a board with 8 Altera MAX7000 CPLD's in the JTAG chain. Most
> of them are MAX7128A's and MAX7064A's with one MAX7256A. The devices
> work fine and I can program them successfully using the ByteBlaster.
> However, approximately every 10'th time I reprogram the MAX7256, it
> dies. It actually programs successfully, but them fails during the
> VERIFY phase.
>
> After this the ByteBlaster software can not see the JTAG chain
> anymore. Also, the MAX7256 temperature rises within seconds so that it
> is too hot to touch.
>
> Has anybody ever came across this? Any suggestions? I've check the
> layout and power supply and decoupling, it seems fine.
>
> Regards,
> Lourens
>
> ================================================================
> Lourens Geldenhuys Tel: +27 (0)12 665 1480
> Project Engineer Fax: +27 (0)12 665 1495
> Mecalc (Pty) Ltd e-mail: lourens@mecalc.co.za
> 86 Oak Avenue, Highveld Technopark, Centurion, South Africa
> ================================================================
Article: 19534"Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> writes: > mcjy@my-deja.com wrote in message <84cs87$k4m$1@nnrp1.deja.com>... > > >For PCI core, now the market is moving > >to PCI-133. But prototyping (for testing) > >can be a big problem. Most FPGAs/CPLDs only > >support up to PCI 66. In addition, I think > >that we need to "buy" PCI specification > >document. Is it still true? > > Methinks you're confusing the PC-133 memory standard with PCI. The fastest > PCI standard is 66 MHz and a 64-bit-wide data/address bus. He might be talking about PCI-X. I've heard rumours that FPGA vendors are looking into it. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 19535
Kelly Hall wrote: > > On Wed, 29 Dec 1999 15:45:20 -0000, J.R. <j_robby@hotmail.com> wrote: > >Does anybody know where I can find an algorithm for Radix-2 online division > >(Radix-2 serial Signed Digit arithmetic) with a constant divisor. I need > >such a unit for a hardware implementation onXC4000 FPGA. I had a look at > >Ercegovac's book entitled " Digit Recurrence algorithms and implementations" > >but have not found a special algorithm for constant divisor. If someone can > >point me directly to an FPGA implementation, that would be great! :-) > > If you are dividing by a constant, can't you just multiply by the > reciprocal instead? Implementing a constant multiplier boils > down into some adder trees with various shifts of the input word. Right. It can be proven that any N-bit / N-bit -> N-bit division can be emulated exactly with a truncated/scaled multiplication by a reciprocal constant with at the most N+1 significant bits. The simplest algorithm to locate this constant is to first locate the nearest power of two which is smaller than the divisor, shift this number left by N bits and then divide by the divisor. If the remainder is greater than half the divisor, then simply increment the N-bit division result for and N-bit reciprocal. Otherwise, you need to add an extra 1 bit at the end, giving a (N+1) bit reciprocal. To use this, simply multiply by the reciprocal and shift right to correct for the initial scaling of the reciprocal. Terje -- - <Terje.Mathisen@hda.hydro.com> Using self-discipline, see http://www.eiffel.com/discipline "almost all programming can be viewed as an exercise in caching"Article: 19536
You can also go through www.pcisig.com. Also Mindshare's book "PCI System Architecture" 4th edition is very good. As I understand, PCI-X is not just a double speed PCI-66. To meet signal integrity some protocol stuff has changed. If I were doing this, I would start at 33/32, verify that state-machines and datapaths worked, and then tweak for higher speed/ wider bits. I am doing a PCI33/32 target in an Altera 10K30E and having plenty of trouble. Good luck, -steen In article <386A856B.1A3B@my-deja.com>, Joe <mcjy@my-deja.com> wrote: >Hi Andy, > >You are right to the fact that I was >confused when I wrote the message this >morning. PCI-133 is a memory bus standard. > >But there is a 133MHx PCI standard. The >one that I should have written on the >message is called PCI-X. (see the link below) >http://www.channelnet.co.uk/davidgu/news/hardware/98-8-23-2880.html >But so far not too much information >is available. > >I am interested in PCI but I found it too >difficult to find the most update information. >There are books in bookstores but they >are never update enough. And there is >also PCI-100 (which is another >memory speed specification.) > >By the way, I have found the information >about where to obtain PCI spec. doc. >PCI Special Interest Group (SIG) >P.O. Box 14070 >Portland, OR 97214 >Tel. (503) 797-4207 (International) >Fax (503) 234-6762 >(800) 433-5177 (in U.S.) > >cheers, >from >Joe > >Andy Peters wrote: >> >> mcjy@my-deja.com wrote in message <84cs87$k4m$1@nnrp1.deja.com>... >> >> >For PCI core, now the market is moving >> >to PCI-133. But prototyping (for testing) >> >can be a big problem. Most FPGAs/CPLDs only >> >support up to PCI 66. In addition, I think >> >that we need to "buy" PCI specification >> >document. Is it still true? >> >> Methinks you're confusing the PC-133 memory standard with PCI. The fastest >> PCI standard is 66 MHz and a 64-bit-wide data/address bus. >> >> -- a >> ----------------------------------------- >> Andy Peters >> Sr Electrical Engineer >> National Optical Astronomy Observatories >> 950 N Cherry Ave >> Tucson, AZ 85719 >> apeters (at) noao \dot\ edu >> >> The secret of Slurm is on a need-to-know basis.Article: 19537
I'm on the xess board subscriber list but I thought I'd just ask if anyone with experience with the xess board could help. I'm trying to figure out why when I download the gnome microcomputer code to the board why I'm getting certain results. I'm going to troubleshoot when I get home. My hex code is -12 0000 18 30 14 31 19 32 12 33 00 40 52 34 41 53 35 44 45 8f This is straight from the practical xilinx lab book. Instead of the display giving me the two nibble sum 1 7 1 7. It displays 4 0 and 8 over and over again. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19538
Hi Andy, You are right to the fact that I was confused when I wrote the message this morning. PCI-133 is a memory bus standard. But there is a 133MHx PCI standard. The one that I should have written on the message is called PCI-X. (see the link below) http://www.channelnet.co.uk/davidgu/news/hardware/98-8-23-2880.html But so far not too much information is available. I am interested in PCI but I found it too difficult to find the most update information. There are books in bookstores but they are never update enough. And there is also PCI-100 (which is another memory speed specification.) By the way, I have found the information about where to obtain PCI spec. doc. PCI Special Interest Group (SIG) P.O. Box 14070 Portland, OR 97214 Tel. (503) 797-4207 (International) Fax (503) 234-6762 (800) 433-5177 (in U.S.) cheers, from Joe Andy Peters wrote: > > mcjy@my-deja.com wrote in message <84cs87$k4m$1@nnrp1.deja.com>... > > >For PCI core, now the market is moving > >to PCI-133. But prototyping (for testing) > >can be a big problem. Most FPGAs/CPLDs only > >support up to PCI 66. In addition, I think > >that we need to "buy" PCI specification > >document. Is it still true? > > Methinks you're confusing the PC-133 memory standard with PCI. The fastest > PCI standard is 66 MHz and a 64-bit-wide data/address bus. > > -- a > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > The secret of Slurm is on a need-to-know basis.Article: 19539
Timothy The JTAG configuration interface is a bit misleading. It will say it configured just fine even though it has not gone through startup. Nicolas helped me with this one in an earlier post if you have the same problem that I had. You need to go into the design->options menu. Click on edit options next to configuration and select the startup tab. For the startup clock source select JTAG. Hope that's it. Pete -- Pete Dudley Arroyo Grande Systems Incorporated Timothy Miller <tim@techsource.com> wrote in message news:84dojt$7vp$1@nnrp1.deja.com... > In article <386A2E5F.87E72F27@dotcom.fr>, > Nicolas Matringe <nicolas@dotcom.fr> wrote: > > Timothy Miller wrote: > > > > > > I have a XCV1000 which I have been trying to program through the > JTAG > > > interface. I can scan out the device ID without a problem. When > it's > > > programmed with something as simple as a clock divider I don't get > an > > > output at all. I am currently using the constraints editor to > specify > > > IO type (lvttl). I have checked the voltages and they are fine. > Does > > > anyone have any suggestions ? Should I instantiate the io's in the > code > > > or does the p&r use the constraints file info just fine? > > > > Hi > > Does the JTAG programmer tell you that the device is configured? > > If not, you may have a problem with the startup clock (see one of my > > previous posts) > > Actually, it does tell me that the device is configured. > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 19540
Hello All
I was looking at my .pad report file for a new Virtex design and I noticed
something new.
Under the "Dedicated or Special Pin Name" section, pins called IRDY and TRDY
are each listed twice. On the TQ144 package they are on pins 53 and 56 but
then they are repeated on pins 130 and 127.
IRDY and TRDY are signal names in the PCI standard. Are these pins special
in any way on the Virtex chip? Do they have special drive strengths to meet
PCI requirements?
Any insight would be appreciated.
Pete
--
Pete Dudley
Arroyo Grande Systems Incorporated
Article: 19541Magnus Homann wrote in message ... >"Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> writes: > >> mcjy@my-deja.com wrote in message <84cs87$k4m$1@nnrp1.deja.com>... >> >> >For PCI core, now the market is moving >> >to PCI-133. But prototyping (for testing) >> >can be a big problem. Most FPGAs/CPLDs only >> >support up to PCI 66. In addition, I think >> >that we need to "buy" PCI specification >> >document. Is it still true? >> >> Methinks you're confusing the PC-133 memory standard with PCI. The fastest >> PCI standard is 66 MHz and a 64-bit-wide data/address bus. > >He might be talking about PCI-X. I've heard rumours that FPGA vendors >are looking into it. I just checked the web site Joe referred to. I stand corrected! I have the Mindshare book but I haven't had a chance to do much more than glance at it. -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu The secret of Slurm is on a need-to-know basis.Article: 19542
On Wed, 29 Dec 1999 03:00:00, steve (Steve Rencontre) wrote: > In article <3866ec0c@athene.hdm-stuttgart.de>, david_geng@yahoo.com > (David Geng) wrote: > > > Hi, there, > > > > can any one tell me what's the status(high, low or float) of the I/O > > pins > > when a EPLD or FPGA in ISP procedure? > > I'd be surprised if there are any that don't go hi-Z during ISP, but > it's not my board that'll smoke if I'm mistaken :-) I'm very new here (been reading for months), but reading the specs for the Xilinx parts this is determined by the Mbits. You can program them to be weakly pulled up or open by the way they're programmed (the 'M' pins while programing). > > Try reading the data sheet or app notes for your particular device! Well, I've read everything available, but I still have more questions than answers! I'll be back with *many* questions, but have learned a *ton* from the regulars already. ---- Keith R. Williams krw@attglobal.net P.S. When one is over one's head one must do anything to learn how to swim. ...been here before and am still breathing.Article: 19543
Dear All after I synthesis the design I found that FG and H function in FPGA are very big. They used about nearly 300 % of the resource while used CLB only 30%. How can reduce or optimize or .. suggest me? Best REgard Wannarat -- Wannarat Suntiamorntut Computer System Design Laboratory (CSDL) Computer Engineering Department Prince of Songkla University, Hatyai, Songkla 90112 Thailand Tel. 66-074-212895 ext.311 Fax. 66-074-212895Article: 19544
Thank you. But what about Altera's EPLD? David Bibico Cando <pobox303@usa.net> wrote in message news:3868FB29.C0D87313@usa.net... > For CPLDs of XC9500 series it is weak pulled up if in ISP mode (programming) > > David Geng wrote: > > > Hi, there, > > > > can any one tell me what's the status(high, low or float) of the I/O pins > > when a EPLD or FPGA in ISP procedure? > > > > Thanks a lot > > > > David >Article: 19545
I don't believe you used the PCI term 'universal' quite right, or perhaps, you weren't thinking in terms of PCI terms... There are three CARD specs, a 5V spec, a 3.3V spec and a 'universal' (plugs into either 5V or 3.3V) spec. but only two SLOT types, 5V or 3.3V. It is the card that is universal, not the slot. I don't know of any 'major' card manufacturers making 'universal' (plugs into either 5V or 3.3V system board) cards for 33MHz PCI, in fact, I don't know of any 33MHz PCI 3.3V system boards. As you said, per the PCI spec (contrary to the original posters ascertain) in a 5V signaling environment, the system board manufacturer is not required to provide 3.3V to the connectors. A 5V card will not work in a slot keyed for 3.3V, nor will a 3.3V card work in a slot keyed for 5V. A universal card will work in either, but as I said, I don't believe there are any 'main stream' cards being made to be a PCI universal card... 66MHz does require 3.3V signaling though...and does not support 5V signaling. Well, Virtex is kind of PCI 'compliant'....the fact that it doesn't use the VIO pins of the PCI bus makes it a bit weird, though they say the I/O is 5V 'tolerant'....and fully PCI compliant. The latest Virtex E series will not support 5V PCI though...so it won't be the chip to use for all the hundreds of thousands of system boards already out there, but is probably fine for a 66MHz board. By the way, you are required in the PCI spec to put a decoupling cap on the unused 3.3V pins in a 5V signaling environment to provide an A/C return path. A lot of people miss this part of the spec... As was stated, if you want to make a 33MHz PCI card, and you require 3.3V on your board, you have to provide the regulator on board and make 3.3V from the +12 or the +5... peter dudley <padudle@worldnet.att.net> wrote in article <8403hp$4qm$1@bgtnsc01.worldnet.att.net>... > You got my curiosity going on this one. > > The situation is that most computer add-in card makers design their cards to > be universal. That is their edge connectors have two notches in them so they > can plug into 5V or 3.3V slots. The problem is that 3.3V slots are required > to provide the 5V supply but 5V slots are not required to provide the 3.3V > supply. To make sure that their cards work in any slot, these card makers > only use the 5V supply and use a linear regulator to get the 3.3Volts that > they need. > > Modern FPGA's like Xilinx Virtex are compliant with the 5V and 3.3V > signalling standards even though their I/O are powered by 3.3V. > > Someone please correct me if I'm wrong on this. > > Pete > > > Peter Dudley > Arroyo Grande Systems Incorporated > > > Signal Processing in Hardware and Software > > Mahboob Ahmed <m.ahmed@ieee.org> wrote in message > news:83s975$pt2$1@nnrp1.deja.com... > > Most of the PCI slot in PCs, and SUN workstations I have checked, do not > > provide 3.3V in the PCI slot, except the new Intel boards, which do > > have 3.3V supply. Why the common PCs and workstations do not provide > > 3.3V supply in PCI slot as specified in PCI Rev? and why is it > > disabled? If a PCI card needs 3.3V in 5V 32-bit slot then what > > should be done to enable the dedicated 3.3V supply pins. > > > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > >Article: 19546
"peter dudley" <padudle@worldnet.att.net> writes: > Hello All > > I was looking at my .pad report file for a new Virtex design and I noticed > something new. > > Under the "Dedicated or Special Pin Name" section, pins called IRDY and TRDY > are each listed twice. On the TQ144 package they are on pins 53 and 56 but > then they are repeated on pins 130 and 127. > > IRDY and TRDY are signal names in the PCI standard. Are these pins special > in any way on the Virtex chip? Do they have special drive strengths to meet > PCI requirements? An educated guess would be that Virtex supports up to two PCI interfaces. Due to the timing requirment for 66 MHz PCI, they have added some special logic to take care of the hardest paths. And I guess you have to use those pins if you are going to fit a 66 MHz PCI interface in the Virtex family. I don't see how you can do two PCI interfaces in a TQ144 package, though... :-) Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 19547
Ok you are more than welcomed to join us at OpenIPCore and OpenCores projects we are now trying to define the spec you can check our sites at and join our mailing list or you can contact me directly at khatib@ieee.org http://www.openip.org/oc http://www.opencores.org Regarding the spec may be we can get the latest update from the SIG group if we tell them about our projects and their goals regrading what other details we are going to discuss them in the mailing lists Thanks Jamil Khaib wrote: > Hi > me as a memeber of the OpenIPCore project are trying to develope a USB > 2.0 core. > We need some designers to help us in this project you are welcome to > join us. > > we need also a PCI 2.2 core, and any kind of contribution you can made > is more than welcomed > > Thanks > OpenIP Organization http://www.openip.org > OpenIPCore Project http://www.openip.org/oc > OpenCores Project http://www.opencore.orgArticle: 19548
"Austin Franklin" <austin@darkroo99m.com> writes: > As you said, per the PCI spec (contrary to the original posters ascertain) > in a 5V signaling environment, the system board manufacturer is not > required to provide 3.3V to the connectors. They are required to put in 3.3V in PCI 2.2. The old PCI 2.1 didn't require the 3.3V power rail in a 5V environment, though. [...] > As was stated, if you want to make a 33MHz PCI card, and you require 3.3V > on your board, you have to provide the regulator on board and make 3.3V > from the +12 or the +5... Unless the motherboard is PCI 2.2 compliant. I think making the 3.3V optional was a big mistake. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 19549
Hi friends, I have now got CD from Actel with actel software, veribest and synplify But I can't make it working. After Actel dectop run it says: "Error reading licens file"! Have to get extra licens? (I have found nothing about this in Documentation) * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!
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