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mench@mench.com wrote in article <83889h$e0l$1@mench.mench.com>... > On 15 Dec 1999 02:39:31 GMT, in comp.lang.vhdl Austin Franklin > <austin@da88rkroom.com> wrote in article > <01bf46a5$8fb4eb50$207079c0@drt1>: > > >> when InAddrRead => > >> if nAddrStb = '1' then > >> State <= Waiting; > >> else > >> State <= InAddrRead; > >> end if; > >> > >> It's quite sad that some synthesisers clear the current state when not > > asked > >> to. > > > I believe this 'else' is required by VHDL isn't it? Does someone > > know differently? Does the VHDL language state (clearly) that is > > will maintain state if no condition in the state is met? If so, any > > reference to that? > > The "else" clause of if statements is optional; see the LRM for syntax > and semantics. BUT what does the LRM say it DOES if you don't use an if? The syntax for an if, used by it self, works fine, since you don't NEED an explicit ELSE...if just falls through to the next statement, but where in the LRM does it SAY it will maintain the last state in a state machine? I believe this is a misunderstanding of the language, though I could be wrong if someone can explicitly show a reference that says what the behavior of an if statement in a state machine will do if no condition is met. If the language description does not EXPLICITLY say (via wordage or syntax diagram of some kind), then not using an ELSE (or specifying a default condition) in a state machine is a 'mistake'. Just because 'SOME' compilers treat this 'differently' (ie, assume same state) doesn't make it correct code.Article: 19351
Austin Franklin <austin@da88rkroom.com> wrote in message
news:01bf46a4$46ff2390$207079c0@drt1...
> >
> > Anyway, some things to be careful of when you synthesis your One hot
> encoded
> > FSM's. During reset, your state register should look something like
> "00001"
> > and some FPGAs (although rarer these days) can only have a single global
> set
> > or reset which means that a '1' hot encoded state machine cannot be
> > synthesized to these type of devices.
>
> That's not true. You can use 'one hot encoding' in any device. The first
> state needs to be 'active', and you do this by making it active low.
>
Hi Austin ,
I'm aware of what you are saying above. I merely stated that I ran into a
problem before with this type of issue because the synthesis didn't invert
the initial state. See the next reply by 'Matt Billenstein' for further
clarification on a similar problem that he encountered.
How do you 'make' the state active low?, do you let synthesis deal with this
directly or do you infer it in the VHDL? Is there a name for this coding
style, e.g. 'one hot encoding'-ish :)
regards
-David
Article: 19352In article <384fc07d.193780480@news.ncl.ac.uk>, news@river-view.freeserve.co.uk wrote: > On Mon, 06 Dec 1999 08:33:58 GMT, Leon Heller > <leon_heller@hotmail.com> wrote: > > >Get the Xilinx starter kit. It comes with a JTAG programmer, a little > >CPLD evaluation board, and software that supports the CPLDs and the > >Spartan series of FPGAs, as well as the older devices. It's about $100. > > Is that the same one as: > http://www.microcall.memec.com/xilinx/promo.htm - £60 in the UK? > > I'm considering it as an FPGA starter kit- anyone had any experience > with it? Any time or feature limitations I should be aware of? I > know it doesn't have VHDL./Verilog. > > If that isn't it, do you have a UK source for the Xilinx one you > mentioned? Kanda is selling an FPGA starter kit based on Atmel's AT40K20 that has VHDL and Verilog synthesis (unfortunately no simulation) for US$150. I believe they are a UK company so surely sell there as well. I've ordred one and am waiting to receive it sso I can't yet comment on it. Bill Toner amigabill@mailexcite.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19353
Doh, forgot to give Kanda's web page... www.kanda.com Bill Toner amigabill@mailexcite.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19354
Austin Franklin wrote:
> > The "else" clause of if statements is optional; see the LRM for syntax
> > and semantics.
>
> BUT what does the LRM say it DOES if you don't use an if? The syntax for
> an if, used by it self, works fine, since you don't NEED an explicit
> ELSE...if just falls through to the next statement, but where in the LRM
> does it SAY it will maintain the last state in a state machine?
That's right, the "if" syntax is not the issue. The rule is that
signals and variables hold their values unless they are explicitly
changed.
> I believe this is a misunderstanding of the language, though I could be
> wrong
No, the language has it right. Your choices are to either babysit
your existing synthesis tools with extra assignments (which is portable)
or evaluate a new tool.
> if someone can explicitly show a reference that says what the
> behavior of an if statement in a state machine will do if no condition is
> met. If the language description does not EXPLICITLY say (via wordage or
> syntax diagram of some kind), then not using an ELSE (or specifying a
> default condition) in a state machine is a 'mistake'.
The "If" syntax is not the issue.
To VHDL a "state" is just a variable or signal value.
The issue is a synthesis tool that changes a value in
the absence of a statement ordering such a change.
> Just because 'SOME' compilers treat this 'differently' (ie, assume same
> state) doesn't make it correct code.
'SOME' compilers get it right.
Others make their own rules.
-Mike Treseler
Article: 19355> > > Anyway, some things to be careful of when you synthesis your One hot > > encoded > > > FSM's. During reset, your state register should look something like > > "00001" > > > and some FPGAs (although rarer these days) can only have a single global > > set > > > or reset which means that a '1' hot encoded state machine cannot be > > > synthesized to these type of devices. > > > > That's not true. You can use 'one hot encoding' in any device. The first > > state needs to be 'active', and you do this by making it active low. > > > > Hi Austin , > > I'm aware of what you are saying above. I merely stated that I ran into a > problem before with this type of issue because the synthesis didn't invert > the initial state. See the next reply by 'Matt Billenstein' for further > clarification on a similar problem that he encountered. > > How do you 'make' the state active low?, do you let synthesis deal with this > directly or do you infer it in the VHDL? Is there a name for this coding > style, e.g. 'one hot encoding'-ish :) > regards Hi David, It appears there are two issues here. One is will the architecture 'allow' you to do one hot state machines, and the answer to that one is yes. At least I can't name an FPGA/CPLD that can't ;-) The second issue is will your design tool allow you to. Obviously, with schematics, it is very easy to do, you just put an inverter on the output of the state flop...but with any type of synthesis, you may be limited by the tool and how it 'handles' (read possibly mangles) what it is you want to do, which is apparently the problem some people have mentioned, and it has been a problem with XABEL in the past. If you instantiate everything for the state machine, then you can do what ever you want...just like schematics. But, if you just use 'simple' syntax to create a state machine, and you tell the tools to 'one hot encode' your state machines, you may or may not get the right results, as has been observed. If the tools don't work right (either preset the first state, OR invert the first state so it's active low), then you have to instantiate everything for this SM. Another potential 'hdl tool' problem I see is supposed you only want one of your state machines encoded as 'one hot' and another one as 'highly encoded'. I don't believe you can do this with current synthesis tools (like you should be able to give the state machine name an attribute like OHE or BE...)...unless you instantiate the entire state machine...so the compiler doesn't see it as a state machine. I always recommend putting two null 'startup' states (one for clock boundary reset issues, and one for metastability to settle, which is what Xilinx claims their flops will settle in) at the beginning of a state machine to allow for the reset condition. The problem is if you have a non-synchronous reset resetting your chip, some registers may come out of reset during one clock cycle, and others on a different cycle, and if your first state(s) 'react' to some input condition....and if the flops that use those 'active' outputs haven't all been reset...you may have a problem. If you can guarantee your state machines inputs aren't going to cause an output change for your first two state machines until well after reset is gone, then the above won't matter to you. Regards, AustinArticle: 19356
Hi folks, I understand that the speed grade in XC4000 is the delay in nanoseconds across a CLB, i.e. in xc4010E-1, it takes 1ns for a signal to cross a CLB (either through the FMAPs, or the FFs). I would like to know the relationship between the speed grade among differnt series within XC4000. For instance, XC4036EX-2: Is it slower than XC4010E-1?? If I follow the above statement, it is. So, where is the speed improvement of EX family compared to E family (other than the architectural improvement)? Secondly, if you have a circuit running at a specific speed in XC4010E-3, would it be a good measure to say that it would work at 3 times this speed on XC4010E-1(roughly)? How about the speed on, say, the XC4036E-2? Cheers.Article: 19357
This is a multi-part message in MIME format. --------------BFFABDD76AA0FC2743D45EDA Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit > I'm not sure anybody does an FPGA starter kit? Mainly because the > timing of FPGA designs is much more complex than for CPLDs, and most of > the time you want/need a proper post-layout timing simulator tool. For > the same reason, the place/route tools are more complex - unless they > ignore timing constraints, in which case the design might not work! XESS has been selling an FPGA starter kit for $209 for a couple of years. Based on the Xilinx Foundation Student Edition (now with VHDL and Verilog in addition to the original ABEL and schematic entry) and the XS40-005XL Board with XC4005XL FPGA. The software includes the timing simulator, floorplanner, and constraint editor. --------------BFFABDD76AA0FC2743D45EDA Content-Type: text/x-vcard; charset=us-ascii; name="devb.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Dave Vanden Bout Content-Disposition: attachment; filename="devb.vcf" begin:vcard n:Vanden Bout;David tel;fax:(919) 387-1302 tel;work:(919) 387-0076 x-mozilla-html:FALSE url:http://www.xess.com org:XESS Corp. adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA version:2.1 email;internet:devb@xess.com title:FPGA Product Manager x-mozilla-cpt:;28560 fn:Dave Vanden Bout end:vcard --------------BFFABDD76AA0FC2743D45EDA--Article: 19358
This is a complex subject. In the very beginning, the Xilinx speed grade numbers described the max guaranteed toggle frequency ( -50, -70, -100 ) in MHz. If we had kept that method, we would be above -500 now. Obviously, there is only a tenuous relationship between this toggle frequency and a real system frequency. Then we changed to using ( roughly) the nanosecond combinatorial delay through a CLB, as -10, -7, down to -1 and -09 and -08 speed grades. Obviously, this does not give the right granularity at the fast end. -1 is not really twice as fast as -2. Also, it really boxed us in, as devices got faster and faster. Beyond that, as interconnects become more predominant in all digital ICs, the prop delay through a look-up table is not the most relevant measure. So finally, with Virtex, we decided to use an arbitrary scale, but where a higher number always describes a faster part. This sends the right message not to associate anything physical directly with the number. So don't assume that anything or everything is directly proportional. You have to look up the individual parameters. Maybe the logic gets much faster, but the interconnect less so. Or it's ( more rarely) the other way around. But you can be assured that no parameter in a better speed grade is ever slower than it was in the slower speed grade. So we guarantee monotonicity, but that's all. Don't equate a -2 in one family with a -2 in another family, although in the XC4000 series, this is pretty close. I think this reasoning holds for our competitors as well. We are all in the same boat. Peter Alfke, Xilinx Applications "J.R." wrote: > Hi folks, > > I understand that the speed grade in XC4000 is the delay in nanoseconds > across a CLB, i.e. in xc4010E-1, it takes 1ns for a signal to cross a CLB > (either through the FMAPs, or the FFs). I would like to know the > relationship between the speed grade among differnt series within XC4000. > For instance, XC4036EX-2: Is it slower than XC4010E-1?? If I follow the > above statement, it is. So, where is the speed improvement of EX family > compared to E family (other than the architectural improvement)? > Secondly, if you have a circuit running at a specific speed in XC4010E-3, > would it be a good measure to say that it would work at 3 times this speed > on XC4010E-1(roughly)? How about the speed on, say, the XC4036E-2? > > Cheers.Article: 19359
hi, "Rc1000-pp" from embedded system look actually the same board as the one in Alpha Data "ADC-RC1000", even the technical brief is idenitical. Any one know whats the different ? Is the design from Alpha Data or Embedded System? I have order one "ADC-RC000" with a xcv1000 from Alpha Data, which have not arrived yet. spyng > ---------- > From: unknown@bits.bris.ac.uk (Address not > verified)[SMTP:unknown@bits.bris.ac.uk] on behalf of Tim > Tyler[SMTP:tt@cryogen.com] > Reply To: tt@cryogen.com > Posted At: Wednesday, December 15, 1999 3:05 AM > Posted To: comp.arch.fpga > Conversation: Virtex boards > Subject: Re: Virtex boards > > Daryl Bradley <dwb105@nospam.ohm.york.ac.uk> wrote: > > [snip 3 VCC boards] > > : We have just ordered a PCI based XCV1000 board form embedded > solutions - > : have heard this is pretty good but no hands on experience yet > > Embedded Solutions' RC1000-PP board - suitable for Virtex: > http://www.embeddedsol.com/tech_info_3.htm > > Embedded Solutions' "Special Offer to universities": > http://www.embeddedsol.com/programs/academic/uni_offer.htm > > ``In partnership with the Xilinx University Program, Xilinx are > supplying a limited number of the Virtex XCV1000 parts free of > charge as a donation for suitable teaching/research projects. > > ESL is mounting these devices on the RC1000-PP reconfigurable > computing PCI board enabling this top end version of the > RC1000-PP to be offered at a very substantial discount on the > standard university discounted price.'' > -- > __________ > |im |yler The Mandala Centre http://www.mandala.co.uk/ > tt@cryogen.com > > It is a miracle whenever curiosity survives a formal education. >Article: 19360
Hi Walter, From your mail what I understand is that the simulator is unable to find the instances that you are using. Hence you must tell the simualtor where to exactly look for the instances. And since you are using Xilinx what needs to be done is to compile all the primitives under a compiled library called Simprim . The source files can be found at <Installed Directory of Xilinx>/vhdl/src/simprims Compile all the vhdl source codes into simprim library and when you try to simulate your top level design specify the path where it can find the primitives. There would be a switch that will help you to do this. Hope you find this useful. Warm Regards Sateesh Walter Soto Encinas Junior wrote: > Hi > > This is a question from a recent Synopsys user. I did a small design > to XC6200 using structural VHDL. I have the VITAL compatible library with > XC6200 primitives (AND, OR, and so on). > > I analyzed this design for simulation. The high level (behavioral) > simulation works well. But I can't backannotate the design with the timing > parameters generated by the placer/router tool, for accurate gate-level > simulation. These parameters are in SDF format, and looking into the file, > it makes sense. Look: > > (CELL > (CELLTYPE "AND2B1") > (INSTANCE COUNT_COL/COUNT_0_INI_1_C_MUX) > (DELAY > (ABSOLUTE > (PORT I0 (9.476:9.476:9.476) (8.143:8.143:8.143)) > (IOPATH I0 O (0:0:0) (0:0:0)) > (PORT I1 (3.040:3.040:3.040) (3.575:3.575:3.575)) > (IOPATH I1 O (0:0:0) (0:0:0)) > ... > > When I read the design the messages are: > > # vhdlsim -fi_all -sdf_typ -sdf_top /tb_addr/c_addr -sdf addr.sdf CFG_TB_ADDR > > **Error: vhdlsim,259: > (SDF File: addr.sdf Line: 20) instance > /TB_ADDR/C_ADDR/COUNT_COL/COUNT_0_INI_1_C_MUX not found. > > ... and a lot of messages about other instances > > Looking into the design tree, using vhdlsim, I found the path to the > cell shown above. > > # pwd > /TB_ADDR/C_ADDR/COUNT_COL/COUNT(0)/INI/C_MUX > # ls > TIMINGCHECKSON MSGON TIPD_I1 I1 > VITALBEHAVIOR > INSTANCEPATH TPD_I0_O TIPD_I0 I0 I1_IPD > XON TPD_I1_O O WIREDELAY I0_IPD > > I suppose there is a problem naming the instances. My placer/router > is the XACT6000 and there is no option to control the generation of instance > names in SDF file. Is there some config in Synopsys analyzer to make the > names of instances compatible with the names of SDF? Or this problem needs > another solution ? > > Sorry for the long posting. But it is very, very important! Thanks in > advance. > > -- > > | Walter Soto Encinas Jr | > | PhD Student | > | IFSC / USP | > | Brazil |Article: 19361
The RC1000-PP and ADC-RC1000 are identical. The board was designed by Alpha Data for Embedded Solutions to support their Handel-C compiler and is sold by both companies. Alpha Data specialise in design of hardware and produce the ADM-XRC mezzanine card which also supports Virtex from V400 to V1000 and Virtex- e. In article <0CF260C495FED111A6610000F866308D07D13C9D@mail3.ntu.edu.sg>, Oh Sheau Pyng <ASSPOh@ntu.edu.sg> wrote: > hi, > "Rc1000-pp" from embedded system look actually the same board as the > one in Alpha Data "ADC-RC1000", even the technical brief is idenitical. > > Any one know whats the different ? Is the design from Alpha Data or > Embedded System? > I have order one "ADC-RC000" with a xcv1000 from Alpha Data, which > have not arrived yet. > > spyng > > > ---------- > > From: unknown@bits.bris.ac.uk (Address not > > verified)[SMTP:unknown@bits.bris.ac.uk] on behalf of Tim > > Tyler[SMTP:tt@cryogen.com] > > Reply To: tt@cryogen.com > > Posted At: Wednesday, December 15, 1999 3:05 AM > > Posted To: comp.arch.fpga > > Conversation: Virtex boards > > Subject: Re: Virtex boards > > > > Daryl Bradley <dwb105@nospam.ohm.york.ac.uk> wrote: > > > > [snip 3 VCC boards] > > > > : We have just ordered a PCI based XCV1000 board form embedded > > solutions - > > : have heard this is pretty good but no hands on experience yet > > > > Embedded Solutions' RC1000-PP board - suitable for Virtex: > > http://www.embeddedsol.com/tech_info_3.htm > > > > Embedded Solutions' "Special Offer to universities": > > http://www.embeddedsol.com/programs/academic/uni_offer.htm > > > > ``In partnership with the Xilinx University Program, Xilinx are > > supplying a limited number of the Virtex XCV1000 parts free of > > charge as a donation for suitable teaching/research projects. > > > > ESL is mounting these devices on the RC1000-PP reconfigurable > > computing PCI board enabling this top end version of the > > RC1000-PP to be offered at a very substantial discount on the > > standard university discounted price.'' > > -- > > __________ > > |im |yler The Mandala Centre http://www.mandala.co.uk/ > > tt@cryogen.com > > > > It is a miracle whenever curiosity survives a formal education. > > > > -- ----------------------------- Alpha Data Parallel Systems Ltd. http://www.alphadata.co.uk ----------------------------- Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19362
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Hi
I'm sniffing into a Doulos course I followed some months ago and they
propose two sollutions:
The first one only works on some synth tools: use attributes to force your
synth tool to decode as you want to.
e.g.
type STATETYPE is (idle, start, stop, clear);
attribute ENUM_ENCODING of STATETYPE: type is "000" "001" 010" "100";
The other way is to use constants:
e.g.
constant idle : std_logic_vector :="000";
...
signal state: std_logic_vector (1 downto 0);
...
process
begin
wait until rising_edge (clock)
if reset ='1' then
state <= idle;
else
case
when idle => state <= start;
...
end case;
end if;
end process;
-- assing outputs e.g.
P <= state(1);
Q <= state (0);
Johan
Matt Billenstein <mbillens@one.net> schreef in berichtnieuws
IbE54.6819$g55.125519@typhoon2.kc.rr.com...
> I've always used the "Current State," "Next State" methodology when doing
> state machines in VHDL. I don't know what is more correct, but with this
> example I might write something like:
>
> <snip>
> type State is (Waiting, StartDataRead, InDataRead);
> signal CurrentState,NextState : State;
> begin
> NS : process (CurrentState,Reset,DataStb,Write)
> begin
> case CurrentState is
> when Waiting =>
> if DataStb = '0' then
> if Write = '1' then
> NextState <= StartDataRead;
> else
> NextState <= Waiting;
> end if;
> end if;
> when StartDataRead =>
> NextState <= InDataRead;
> when InDataRead =>
> if DataStb = '1' then
> NextState <= Waiting;
> else
> NextState <= InDataRead;
> end if;
> when others =>
> NextState <= Waiting;
> end case;
> end process NS;
>
> CS : process (Clock, Reset)
> begin
> if (Reset = '1') then
> CurrentState <= Waiting;
> elsif (Clock'event and Clock='1') then
> CurrentState <= NextState;
> end if;
> end process CS;
> </snip>
>
> I don't know really which is better (if either) ...
>
> Another thing I've noticed between binary and one hot encoding is a
problem
> I had on a Xilinx Spartan part (xcs30vq100-3) ... I was encoding my state
> machines one hot and in one particular state machine I wasn't explicitely
> running in a reset to set the machine to some other state, but I did have
an
> else clause in my case statement which put me in my initial state... I
was
> using the fastest encoding and the kicker is that the synthesis tools were
> synthesizing all my flops to reset ("0") which encoded one hot isn't a
valid
> state... furthermore, there was no transition out of this state
eventhough
> I provided an else clause in the case statement... my state machine would
> just stick in the invalid state after startup and do nothing... ...took
me
> awhile to figure this out (especially since I was relatively new to VHDL
at
> the time) after compiling binary once and the damn thing working... The
> solution was simple at the time and I always explicitely define a reset
> state now...
>
> l8r
>
> m
>
>
>
> Matt Billenstein
> http://w3.one.net/~mbillens/
> mbillens@one.net
>
>
> "Marc Battyani" <Marc_Battyani@csi.com> wrote in message
> news:062E9EEFDD659520.D67674846BD251B1.A017E921C8876561@lp.airnews.net...
> | I don't understand why the following state machine is ok when I use
binary
> | state encoding (with safest mode) but oscillate when I use one hot
> encoding
> | (with safest mode also).
> |
> | type State is (Waiting, StartDataRead, InDataRead);
> | signal S : State;
> | begin
> | SM : process (Clock, Reset)
> | begin
> | if (Reset = '1') then
> | State <= Waiting;
> | elsif rising_edge(Clock) then
> | case State is
> | when Waiting =>
> | if DataStb = '0' then
> | if Write = '1' then
> | State <= StartDataRead;
> | end if;
> | end if;
> | when StartDataRead =>
> | State <= EppInDataRead;
> | when InDataRead =>
> | if DataStb = '1' then
> | State <= Waiting;
> | end if;
> | when others =>
> | State <= EppWaiting;
> | end case;
> | end if;
> | end process SM;
> |
> | The compiler is VHDL express, for a Spartan xcs40.
> | Any idea ?
> |
> | Thanks
> | Marc Battyani
> |
> |
>
>
Article: 19364A few of us at Matra BAe Dynamics have used/are using a couple of Nallatech boards (www.nallatech.com) which use their DIME standard modules. They have a nice multiconfiguration tool that allows you to independently configure multiple modules on a single motherboard. The modules themselves are connected together allowing you to build your own interconnects which are fully deterministic and as fast as you can design (unlike PCI). We find this useful in work we do in video data processing. They have all the power supplies built onto the motherboards so we haven't had to add anything to the standard PC we're using. So far so good... smithers12@my-deja.com wrote in message <82r6un$1t1$1@nnrp1.deja.com>... >Hello, > >I was wondering if anyone has had any experience with the various >Virtex-based prototyping boards out on the market (e.g., Avnet, VCC, >etc.). Any recommendations would be appreciated. Thanks. > >Sincerely, > >Hugh > > >Sent via Deja.com http://www.deja.com/ >Before you buy.Article: 19365
In article <3857A3D7.4F6E@ecs.soton.ac.uk.nojunk>, Tim Forcer <tmf@ecs.soton.ac.uk.nojunk> wrote: > Nigel Orr wrote: > > > > Leon Heller wrote: > >> > >> Get the Xilinx starter kit. It comes with a JTAG programmer, > >> a little CPLD evaluation board, and software that supports > >> the CPLDs and the Spartan series of FPGAs, as well as the > >> older devices. It's about $100. > > > > Is that the same one as: > > <http://www.microcall.memec.com/xilinx/promo.htm> - £60 in the UK? > > > > I'm considering it as an FPGA starter kit- anyone had any > > experience with it? Any time or feature limitations I should > > be aware of? I know it doesn't have VHDL./Verilog. > > Note that the kit is for CPLDs (XC9500 series), not FPGAs. The kit isn't just for CPLDs, although you do get aN xc9500 eval. board. It's very easy to prototype a board for the smaller Spartan FPGAs, and configure the device with the supplied JTAG cable, and the software supports FPGA development. Leon -- Leon Heller, G1HSM Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19366
This is a multi-part message in MIME format. --------------B742F0CB3B6158B4D3BFB87A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hello All I am bringing up an new board that contains a Virtex XCV300-352 Xilinx FPGA. In addition I have some pld's that function as a VME interface and also configure the Virtex on power up from a flash memory using Select Map mode. I have a lot of test points on the board and it looks like the Select Map configuration is proceeding correctly but the Virtex does not configure. I know the part is not configuring because the DONE signal never goes true and I have some LED's that should light when the part configures. The JTAG port of the Virtex is also brought out to a connector and I have used the JTAG Programmer software and a download cable to program the Virtex. The JTAG interface seems to be working because I can read the part ID correctly but the verify command fails after programming and again the part does not configure. For JTAG configuration, my understanding is that the part only needs power so I am a little baffled. I have checked the power pins where I have 3.3V on the VCCIO pins and 2.5V on the VCCINT pins. The mode lines M[2:0] = 110 but this should not even matter for JTAG configuration. Can anyone suggest what I might be doing wrong? Like all electronic designers, I am under a bit of time pressure. Thanks for any suggestions. Pete Dudley --------------B742F0CB3B6158B4D3BFB87A Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Peter Dudley Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Peter Dudley n: Dudley;Peter org: Sandia National Labs adr: box 5800;;Mail Stop 0505;Albuquerque;NM;87185;USA email;internet: padudle@sandia.gov title: SMTS tel;work: 505.844.5565 tel;fax: 505.844.2925 note: Digital Signal Processing in Hardware and Software x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------B742F0CB3B6158B4D3BFB87A--Article: 19367
Hi there, when using the command "generate schematic from netlist" in Foundation 2.1 in a HDL-based design sometimes I get the message "error pin ... GTS not found" and no schematic is generated. I have tried all the type of net list (XNF, EDF) but both gave the same error. I also have tried to give an high impedance state (<= "Z")to all outputs with an extra "enable" input in the VHDL code but it didn't fix the problem. If someone knows how to solve this problem I would be very grateful. Thanks. Pier@cadvlsi1.df.unibo.itArticle: 19368
Peter A Dudley wrote: > > Hello All > > I am bringing up an new board that contains a Virtex XCV300-352 Xilinx > FPGA. In addition I have some pld's that function as a VME interface and > also configure the Virtex on power up from a flash memory using Select > Map mode. I have a lot of test points on the board and it looks like the > Select Map configuration is proceeding correctly but the Virtex does not > configure. I know the part is not configuring because the DONE signal > never goes true and I have some LED's that should light when the part > configures. > > The JTAG port of the Virtex is also brought out to a connector and I > have used the JTAG Programmer software and a download cable to program > the Virtex. The JTAG interface seems to be working because I can read > the part ID correctly but the verify command fails after programming and > again the part does not configure. [...] > Can anyone suggest what I might be doing wrong? Hi I had this kind of problem a few weeks ago (although I only have one Virtex on the board). You have to check, before implementing the design, that the configuration clock is JTAG's (if you program it through the JTAG). If you use the SelectMap mode, the configuration clock might need to be CCLK or User (meaning that you can't use the same bitstream for JTAG and SelectMap configuration). Hope this helps -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 19369
In article <835br9$u00$1@nnrp1.deja.com>, Leon Heller <leon_heller@hotmail.com> wrote: >In article <384fc07d.193780480@news.ncl.ac.uk>, > news@river-view.freeserve.co.uk wrote: >> On Mon, 06 Dec 1999 08:33:58 GMT, Leon Heller >> <leon_heller@hotmail.com> wrote: >> >> >Get the Xilinx starter kit. It comes with a JTAG programmer, a little >> >CPLD evaluation board, and software that supports the CPLDs and the >> >Spartan series of FPGAs, as well as the older devices. It's about >$100. >> >> Is that the same one as: >> http://www.microcall.memec.com/xilinx/promo.htm - £60 in the UK? >> >> I'm considering it as an FPGA starter kit- anyone had any experience >> with it? Any time or feature limitations I should be aware of? I >> know it doesn't have VHDL./Verilog. >> >> If that isn't it, do you have a UK source for the Xilinx one you >> mentioned? > >Yes, that's the one. I got mine from MicroCall. > >Leon One other thing you may want to check on is that the recent installs of Xilinx seem to indicated that they have switched to a time limited (1 year) version of the software so it will stop working if you don't pay more money. The work stuff and the version I have at home were purchased before they switched and are grandfathered so I don't know the details. David GessweinArticle: 19370
This is a multi-part message in MIME format. --------------9136A697539C09932212D484 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hello Nicolas You were exactly right about the startup clock. I had CCLK selected and when I changed it to the JTAG clock, I was able to configure from the JTAG port. My LED's are shining. To get the Select Map mode to work I just need to go back to CCLK and change my pld state machine to give a few more clocks. You saved me a bunch of time so if you're ever in Albuquerque, New Mexico, USA, drop me a line and I will buy you dinner or a beer. Sincerely Pete Dudley --------------9136A697539C09932212D484 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Peter Dudley Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Peter Dudley n: Dudley;Peter org: Sandia National Labs adr: box 5800;;Mail Stop 0505;Albuquerque;NM;87185;USA email;internet: padudle@sandia.gov title: SMTS tel;work: 505.844.5565 tel;fax: 505.844.2925 note: Digital Signal Processing in Hardware and Software x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------9136A697539C09932212D484--Article: 19371
Actually, the xc6200 is not supported in the Alliance release, and therefore,
there is no simprims models. The xc62000 is a discontinued product; last
supported
in the xact6000 software.
The last updates of the software exist here:
ftp://ftp.xilinx.com/pub/utilities/6200/00_index.htm
If the updates don't help, certainly a small Perl script can be written to
modify the sdf instance path match the back-annotated vhd.
Chandramohan Sateesh wrote:
>
> Hi Walter,
>
> From your mail what I understand is that the simulator is unable to find
> the instances that you are using. Hence you must tell the simualtor where
> to exactly look for the instances.
>
> And since you are using Xilinx what needs to be done is to compile all the
> primitives under a compiled library called Simprim . The source files can be
> found at
>
> <Installed Directory of Xilinx>/vhdl/src/simprims
>
> Compile all the vhdl source codes into simprim library and when you try to
> simulate your top level design specify the path where it can find the primitives.
>
> There would be a switch that will help you to do this.
>
> Hope you find this useful.
>
> Warm Regards
>
> Sateesh
>
> Walter Soto Encinas Junior wrote:
>
> > Hi
> >
> > This is a question from a recent Synopsys user. I did a small design
> > to XC6200 using structural VHDL. I have the VITAL compatible library with
> > XC6200 primitives (AND, OR, and so on).
> >
> > I analyzed this design for simulation. The high level (behavioral)
> > simulation works well. But I can't backannotate the design with the timing
> > parameters generated by the placer/router tool, for accurate gate-level
> > simulation. These parameters are in SDF format, and looking into the file,
> > it makes sense. Look:
> >
> > (CELL
> > (CELLTYPE "AND2B1")
> > (INSTANCE COUNT_COL/COUNT_0_INI_1_C_MUX)
> > (DELAY
> > (ABSOLUTE
> > (PORT I0 (9.476:9.476:9.476) (8.143:8.143:8.143))
> > (IOPATH I0 O (0:0:0) (0:0:0))
> > (PORT I1 (3.040:3.040:3.040) (3.575:3.575:3.575))
> > (IOPATH I1 O (0:0:0) (0:0:0))
> > ...
> >
> > When I read the design the messages are:
> >
> > # vhdlsim -fi_all -sdf_typ -sdf_top /tb_addr/c_addr -sdf addr.sdf CFG_TB_ADDR
> >
> > **Error: vhdlsim,259:
> > (SDF File: addr.sdf Line: 20) instance
> > /TB_ADDR/C_ADDR/COUNT_COL/COUNT_0_INI_1_C_MUX not found.
> >
> > ... and a lot of messages about other instances
> >
> > Looking into the design tree, using vhdlsim, I found the path to the
> > cell shown above.
> >
> > # pwd
> > /TB_ADDR/C_ADDR/COUNT_COL/COUNT(0)/INI/C_MUX
> > # ls
> > TIMINGCHECKSON MSGON TIPD_I1 I1
> > VITALBEHAVIOR
> > INSTANCEPATH TPD_I0_O TIPD_I0 I0 I1_IPD
> > XON TPD_I1_O O WIREDELAY I0_IPD
> >
> > I suppose there is a problem naming the instances. My placer/router
> > is the XACT6000 and there is no option to control the generation of instance
> > names in SDF file. Is there some config in Synopsys analyzer to make the
> > names of instances compatible with the names of SDF? Or this problem needs
> > another solution ?
> >
> > Sorry for the long posting. But it is very, very important! Thanks in
> > advance.
> >
> > --
> >
> > | Walter Soto Encinas Jr |
> > | PhD Student |
> > | IFSC / USP |
> > | Brazil |
--
Paulo //\\\\
| ~ ~ |
( O O )
__________________________________oOOo______( )_____oOOo_______
| . |
| / 7\'7 Paulo Dutra (paulo@xilinx.com) |
| \ \ ` Xilinx hotline@xilinx.com |
| / / 2100 Logic Drive (800) 255-7778 |
| \_\/.\ San Jose, California 95124-3450 USA |
| Oooo |
|________________________________________oooO______( )_________|
( ) ) /
\ ( (_/
\_)
Article: 19372
As Jim Granville wrote, probably your FSMs reach some illegal states. It
happens in those states where one fsm is waiting for a signal coming from
the other one.
For example, consider FSM A and FSM B
FSM A:
....
case current_state is
....
when fsm_A_state1 =>
if B_to_A ='1' then
next_state <= fsm_A_state2; --waits for signal B_to_A generated by
FSM B
else
next_state <= fsm_A_state1;
end if;
when fsm_A_state2 =>
.... -- fsm A continues
In this case I suggest you :
1) register signal B_to_A
2) states codes of fsm_A_state1 and fsm_A_state2 shall differ of only one
bit , for example fsm_A_state1=000, fsm_A_state2=010.
In this way if, when in fsm_A_state1, register output B_to_A goes
metastable
due to B_to_A register input going from '0' to '1' (in corrispondence of
a clock edge), only next_state(1) bit is affected. Two events may occur
then:
- next_state(1) is correctly registered as current_state(1)=1.That's
correct.
- next_state(1) is registered as current_state(1)=0. FSM A remains in
fsm_A_state1 but will go to fsm_A_state2 in the next clock cycle
(B_to_A
register input is now stable and ='1') .That's also correct, but
implies a latency
of one clock cycle.
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Before you buy.
Article: 19373I have quetion how to manipulate small logic changes in Quartus. Design source file is written in verilog and synthesized with FPGA compiler II. After compilation with Quartus, I need to change some logics. For example change some pins to only pull-up signals ignoring original logics. But I don't know how to do it without changing original verilog source. Can Quartus do it ? Is there anyone who know about this? Regards, Noriaki Ono --- ono@asld.ed.fujitsu.co.jpArticle: 19374
Hi I have designed a Xilinx SpartanXL project in OrCAD EXPRESS using the Xilinx Aliance 2.1i fitter. I have a microcontroller wich will handle the loading of the FPGA. My question is can someone point me in the right direction on how to include the FPGA code in the C source kode of the microcontroller SW. Regards Søren Lambæk KK-Electronic a/s Denmark E-mail: sl@kk-electronic.dk
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