Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Threads Starting Sep 2001
34646: 01/09/01: A. I. Khan: How to connect a clock to a non-clock pad ?
34651: 01/09/01: Rick Filipkiewicz: Re: How to connect a clock to a non-clock pad ?
34675: 01/09/03: Joey Oravec: Re: How to connect a clock to a non-clock pad ?
34702: 01/09/04: Vikash Rungta: Re: How to connect a clock to a non-clock pad ?
34652: 01/09/01: Harry Chung: Prom : Question on Configuration
34676: 01/09/03: =?iso-8859-1?Q?Torbj=F6rn?= Stabo: Re: Prom : Question on Configuration
34706: 01/09/04: Andy Peters: Re: Prom : Question on Configuration
34656: 01/09/02: Kris Nichols: Problems with Synthesis and Implementation in Xilinx Foundation 3.3i
34659: 01/09/02: Tim: Re: Problems with Synthesis and Implementation in Xilinx Foundation 3.3i SP8(ELITE)
34657: 01/09/02: tasi@emc: [testbench] testbench porting from Cadence to Altera
34658: 01/09/02: Sriram S: Clock Multiplication
34677: 01/09/03: Chris Mc Clements: Re: Clock Multiplication
34718: 01/09/05: Sriram S: Re: Clock Multiplication
34934: 01/09/14: Paul Hardy: Re: Clock Multiplication
34937: 01/09/14: Paul Hardy: Re: Clock Multiplication
34721: 01/09/05: Jim Granville: Re: Clock Multiplication
34925: 01/09/14: Paul Hardy: Re: Clock Multiplication
34930: 01/09/14: Tim: Re: Clock Multiplication
34662: 01/09/02: pete dudley: DSP in OTP
34663: 01/09/02: Kevin Neilson: Re: DSP in OTP
34664: 01/09/02: Uwe Bonnes: Re: DSP in OTP
34665: 01/09/02: NotMe: Re: DSP in OTP
34670: 01/09/03: Ray Andraka: Re: DSP in OTP
34679: 01/09/03: pete dudley: Re: DSP in OTP
34681: 01/09/03: Ben Franchuk: Re: DSP in OTP
34669: 01/09/03: Daniel Nilsson: using non-standard eeprom to program xilinx fpga
34705: 01/09/04: Andy Peters: Re: using non-standard eeprom to program xilinx fpga
34671: 01/09/02: Dereck: Virtex Architecture: Interconnect
34672: 01/09/03: Ray Andraka: Re: Virtex Architecture: Interconnect
34790: 01/09/07: Dereck: Re: Virtex Architecture: Interconnect
34673: 01/09/03: <khtsoi@pc90026.cse.cuhk.edu.hk>: Linux download bitstream [w/ source]
34674: 01/09/03: Russell Shaw: Segmented interconnects
34678: 01/09/03: Ray Andraka: Re: Segmented interconnects
34687: 01/09/04: Peter Ormsby: Re: Segmented interconnects
34712: 01/09/05: Russell Shaw: Re: Segmented interconnects
34717: 01/09/05: Phil Hays: Re: Segmented interconnects
34766: 01/09/06: Ray Andraka: Re: Segmented interconnects
34928: 01/09/14: Paul Hardy: Re: Segmented interconnects
34940: 01/09/14: Austin Lesea: Re: A vs. X
34941: 01/09/14: Nicolas Matringe: Re: A vs. X
34942: 01/09/14: John_H: Re: A vs. X
34943: 01/09/14: Austin Lesea: Re: A vs. X
34945: 01/09/14: Marc Battyani: Re: A vs. X
34946: 01/09/14: Austin Lesea: Re: A vs. X
34953: 01/09/15: Rick Filipkiewicz: Re: A vs. X
34955: 01/09/15: Marc Battyani: Re: A vs. X
34965: 01/09/17: Nicolas Matringe: Re: A vs. X
35005: 01/09/17: Rick Filipkiewicz: Re: A vs. X
34680: 01/09/03: Neil Stainton: How do I configure Altera Apex 20K via JTAG?
34684: 01/09/04: Peter Ormsby: Re: How do I configure Altera Apex 20K via JTAG?
34682: 01/09/03: Ozkan Dikmen: APEX20KE: Global Line for internal logic
34685: 01/09/04: Peter Ormsby: Re: APEX20KE: Global Line for internal logic
34683: 01/09/04: Rick Filipkiewicz: Multi-cycle constraints
34686: 01/09/04: Allan Herriman: Re: Multi-cycle constraints
34689: 01/09/04: Rick Filipkiewicz: Re: Multi-cycle constraints
34691: 01/09/04: Allan Herriman: Re: Multi-cycle constraints
34688: 01/09/04: Andrew Gray: Interfacing Verilog and VHDL
34700: 01/09/04: Extern: Re: Interfacing Verilog and VHDL
34728: 01/09/05: Srinivasan Venkataramanan: Re: Interfacing Verilog and VHDL
34730: 01/09/05: Sanjay Kumar Sharma: Re: Interfacing Verilog and VHDL
34782: 01/09/07: Srinivasan Venkataramanan: Re: Interfacing Verilog and VHDL
34734: 01/09/05: Andrew Gray: Re: Interfacing Verilog and VHDL
34747: 01/09/06: Srinivasan Venkataramanan: Re: Interfacing Verilog and VHDL
34692: 01/09/04: Noddy: Open collector outputs
34693: 01/09/04: Philip Freidin: Re: Open collector outputs
34694: 01/09/04: Ray Andraka: Re: Open collector outputs
34819: 01/09/10: Ben Franchuk: Re: Open collector outputs
34851: 01/09/11: Alan Nishioka: Re: Open collector outputs
34695: 01/09/04: olivier JEAN: SEARCH a model core DAC
34699: 01/09/04: Terrence Mak: ISE vs Foundation
34710: 01/09/04: Martin Maurer: Searching a few pieces of Lattice ispLSI 1016E
34714: 01/09/04: John: Give me some information!
34837: 01/09/10: Amirul Khan: Re: Give me some information!
34843: 01/09/11: Srinivasan Venkataramanan: Re: Give me some information!
34862: 01/09/11: Steven K. Knapp: Re: Give me some information!
34715: 01/09/04: Leon Qin: LPM_FIFO_DC
34720: 01/09/05: <martin.j.thompson@trw.com>: Re: LPM_FIFO_DC
34723: 01/09/05: <martin.j.thompson@trw.com>: Re: LPM_FIFO_DC
34731: 01/09/05: Leon Qin: Re: LPM_FIFO_DC
34750: 01/09/06: Martin Thompson: Re: LPM_FIFO_DC
34719: 01/09/05: Petter Gustad: Xilinx Multilinx schematics?
34724: 01/09/05: Michael Boehnel: Special counter for scheduling
34727: 01/09/05: <hamish@cloud.net.au>: Re: Special counter for scheduling
34732: 01/09/05: Michael Boehnel: Re: Special counter for scheduling
34755: 01/09/06: <hamish@cloud.net.au>: Re: Special counter for scheduling
34733: 01/09/05: Ulf Samuelsson: Re: Special counter for scheduling
34753: 01/09/06: Michael Boehnel: Re: Special counter for scheduling
34769: 01/09/07: Andy Holt: Re: Special counter for scheduling
34771: 01/09/07: Michael Boehnel: Re: Special counter for scheduling
34773: 01/09/07: Michael Boehnel: Re: Special counter for scheduling
34800: 01/09/08: Lasse Langwadt Christensen: Re: Special counter for scheduling
34729: 01/09/05: <Graham>: DLL locks with no clock present
34738: 01/09/05: Andreas Kugel: Re: DLL locks with no clock present
34736: 01/09/05: Noelia: Xilinx design flow
34756: 01/09/06: Terrence Mak: Re: Xilinx design flow
34739: 01/09/05: Andreas Kugel: Virtex-2 engineering samples
34740: 01/09/05: Austin Lesea: Re: Virtex-2 engineering samples
34745: 01/09/06: Ray Andraka: Re: Virtex-2 engineering samples
34757: 01/09/06: Austin Lesea: Re: Virtex-2 engineering samples
34741: 01/09/05: KAMRAN: HOW LONG WOULD LAST LONG
34759: 01/09/06: Austin Lesea: Re: HOW LONG WOULD LAST LONG
34749: 01/09/06: Tony Proudfoot: strange behaviour of LPM_FIFO_DC in altera 10k130e
34751: 01/09/06: Martin Thompson: Re: strange behaviour of LPM_FIFO_DC in altera 10k130e
34758: 01/09/06: Wolfgang Loewer: Re: strange behaviour of LPM_FIFO_DC in altera 10k130e
34764: 01/09/06: Mike Treseler: Re: strange behaviour of LPM_FIFO_DC in altera 10k130e
34785: 01/09/07: Russell Shaw: Re: strange behaviour of LPM_FIFO_DC in altera 10k130e
34752: 01/09/06: Noddy: Missing bits
34763: 01/09/06: Ray Andraka: Re: Missing bits
34775: 01/09/07: Noddy: Re: Missing bits
34796: 01/09/08: Ray Andraka: Re: Missing bits
34801: 01/09/08: Lasse Langwadt Christensen: Re: Missing bits
34806: 01/09/08: Ray Andraka: Re: Missing bits
34770: 01/09/07: Hal Murray: Re: Missing bits
34754: 01/09/06: amey hegde: Selection of a suitable FPGA board
34762: 01/09/06: Andreas Kugel: Re: Selection of a suitable FPGA board
34787: 01/09/07: Joey Oravec: Re: Selection of a suitable FPGA board
34772: 01/09/07: Wolfgang Loewer: Re: Selection of a suitable FPGA board
34797: 01/09/08: Ray Andraka: Re: Selection of a suitable FPGA board
34813: 01/09/09: Rick Filipkiewicz: Re: Selection of a suitable FPGA board
34816: 01/09/09: Ray Andraka: Re: Selection of a suitable FPGA board
34823: 01/09/10: Rick Filipkiewicz: Re: Selection of a suitable FPGA board
34860: 01/09/12: Rick Filipkiewicz: Re: Selection of a suitable FPGA board
34825: 01/09/10: Rick Filipkiewicz: Re: Selection of a suitable FPGA board
34760: 01/09/06: Allan Pedersen: Spartan II configuration
34761: 01/09/06: Andreas Kugel: Re: Spartan II configuration
34779: 01/09/07: Philip Freidin: Re: Spartan II configuration
34765: 01/09/06: Reinoud: MPGA (open source meta-FPGA) mailing lists, forums
34768: 01/09/07: Bill Giovino: New Website: EmbeddedSystems.org
34774: 01/09/07: Harjo Otten: cannot replace 'if' with 'case' ???
34776: 01/09/07: Thomas Stanka: Re: cannot replace 'if' with 'case' ???
34783: 01/09/07: Harjo Otten: Re: cannot replace 'if' with 'case' ???
34777: 01/09/07: olivier JEAN: To mix frequency with a FPGA
34812: 01/09/09: Ray Andraka: Re: To mix frequency with a FPGA
34834: 01/09/10: John_H: Re: To mix frequency with a FPGA
34778: 01/09/07: Andrew Gray: FPU core
34788: 01/09/07: Mirek Klaczek: Re: FPU core
34979: 01/09/17: Tom Dillon: Re: FPU core
34780: 01/09/07: Paul McCallion: Actel FPGA glitches
34793: 01/09/08: Ray Andraka: Re: Actel FPGA glitches
34820: 01/09/10: Paul McCallion: Re: Actel FPGA glitches
34829: 01/09/10: Ray Andraka: Re: Actel FPGA glitches
35015: 01/09/17: Andy Peters: Re: Actel FPGA glitches
34804: 01/09/08: Gregory C. Read: Re: Actel FPGA glitches
34822: 01/09/10: Paul McCallion: Re: Actel FPGA glitches
34781: 01/09/07: Gyunseog Yang: Clock division in Xilinx Vertex-E.
34795: 01/09/08: Ray Andraka: Re: Clock division in Xilinx Vertex-E.
34798: 01/09/08: Gyunseog Yang: Re: Clock division in Xilinx Vertex-E.
34799: 01/09/08: Ray Andraka: Re: Clock division in Xilinx Vertex-E.
34821: 01/09/10: Ulises Hernandez: Re: Clock division in Xilinx Vertex-E.
34831: 01/09/10: Gyunseog Yang: Re: Clock division in Xilinx Vertex-E.
34784: 01/09/07: David Wright: ISE 4.1
34786: 01/09/07: John Moore: Re: ISE 4.1
34866: 01/09/12: Andrew Dyer: Re: ISE 4.1
34921: 01/09/13: Kevin Brace: Re: ISE 4.1
34961: 01/09/17: Andrew Dyer: Re: ISE 4.1
34920: 01/09/13: Kevin Brace: Re: ISE 4.1
34791: 01/09/07: Dereck: Virtex: Interconnect Structure
34792: 01/09/07: Dave Colson: Spartan II use of GCK[0:3] pins as general inputs
35399: 01/10/02: Lucien Murray-Pitts: Re: Spartan II use of GCK[0:3] pins as general inputs
34802: 01/09/08: Frank Van de Sande: synplify device configuration settings
34803: 01/09/08: grad_student: SOS : A Question about synthesizng ROM
34805: 01/09/08: Ray Andraka: Re: SOS : A Question about synthesizng ROM
34907: 01/09/13: renaux: Re: SOS : A Question about synthesizng ROM
34807: 01/09/08: jfh: Powering up a multi virtex fpga board
34833: 01/09/10: Austin Lesea: Re: Powering up a multi virtex fpga board
34808: 01/09/08: Andrew Rogers: Xilinx dev. kit for Linux?
34811: 01/09/08: Ray Andraka: Re: Xilinx dev. kit for Linux?
34824: 01/09/10: Nicolas Matringe: Re: Xilinx dev. kit for Linux?
34815: 01/09/09: Duane Clark: Re: Xilinx dev. kit for Linux?
35627: 01/10/12: Erik Lins: Re: Xilinx dev. kit for Linux?
34814: 01/09/09: Andrew Rogers: Alliance: xlmap, XC3020
34817: 01/09/09: Philip Freidin: Re: Alliance: xlmap, XC3020
34818: 01/09/10: Simon Gauntlett: LVPECL : 75 Ohm Output Circuitry
34826: 01/09/10: David Feustel: ModelSim Licensing SW Installation Opens Computer to Hacking?
34830: 01/09/10: Petter Gustad: Re: ModelSim Licensing SW Installation Opens Computer to Hacking?
34832: 01/09/10: Dave Colson: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
34863: 01/09/11: Arthur: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
34879: 01/09/12: M Pedley: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
34888: 01/09/12: pete dudley: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
35013: 01/09/17: Andy Peters: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
34835: 01/09/10: Roman Rumian: DSP design kit.
34840: 01/09/11: Felix Bertram: Re: DSP design kit.
34836: 01/09/10: Steven Derrien: Data cache for fpga-cpu using Xilinx BlockRam
34839: 01/09/10: Rob Finch: Re: Data cache for fpga-cpu using Xilinx BlockRam
34848: 01/09/11: Erik Widding: Re: Data cache for fpga-cpu using Xilinx BlockRam
34867: 01/09/12: Rob Finch: Re: Data cache for fpga-cpu using Xilinx BlockRam
34838: 01/09/10: pete dudley: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
34950: 01/09/14: pete dudley: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
34954: 01/09/15: Ray Andraka: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
34975: 01/09/17: Austin Lesea: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
35026: 01/09/18: Ray Andraka: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
34841: 01/09/11: Edwin Pijpers: Spartan configuration
35097: 01/09/20: Philip Freidin: Re: Spartan configuration
34842: 01/09/10: Antonio: QPSK modulator with no multipliers
34881: 01/09/12: Nimrod Mesika: Re: QPSK modulator with no multipliers
34987: 01/09/17: Ray Andraka: Re: QPSK modulator with no multipliers
35018: 01/09/18: Antonio: Re: QPSK modulator with no multipliers
35038: 01/09/18: Ray Andraka: Re: QPSK modulator with no multipliers
35047: 01/09/19: Antonio: Re: QPSK modulator with no multipliers
34844: 01/09/11: Noddy: Timing constraints
34845: 01/09/11: Michal Rutka: Using falling and rising clock mistery.
34846: 01/09/11: Nicolas Matringe: Re: Using falling and rising clock mistery.
34873: 01/09/12: Michal Rutka: Re: Using falling and rising clock mistery.
34847: 01/09/11: Dave Moore: FPGA Evaluation Board for image processing
34869: 01/09/12: Ken: Re: FPGA Evaluation Board for image processing
34850: 01/09/11: Pete Dudley: Innoveda and ISE Alliance 4.1i ?
34857: 01/09/11: Philip Freidin: Re: Innoveda and ISE Alliance 4.1i ?
34916: 01/09/13: pete dudley: Re: Innoveda and ISE Alliance 4.1i ?
34994: 01/09/17: Bill Nowicky: Re: Innoveda and ISE Alliance 4.1i ?
34853: 01/09/11: Noddy: Missing bits Part 2!
34854: 01/09/11: John_H: Re: Missing bits Part 2!
34855: 01/09/11: Noddy: Re: Missing bits Part 2!
34864: 01/09/12: Tony Proudfoot: Re: Missing bits Part 2!
34861: 01/09/11: Tom: Question concerning Verilog scheduling
34865: 01/09/12: Parvathy Uma: Re: Question concerning Verilog scheduling
34868: 01/09/12: Paulo Valentim: LeonardoSpectrum Timing reports
34870: 01/09/12: Alan Fitch: Re: LeonardoSpectrum Timing reports
34882: 01/09/12: Mike Treseler: Re: LeonardoSpectrum Timing reports
34871: 01/09/12: Noddy: Error messages
34872: 01/09/12: M Pedley: Programming Delays in ABEL
34878: 01/09/12: M Pedley: Re: Programming Delays in ABEL
34883: 01/09/12: Rick Filipkiewicz: Re: Programming Delays in ABEL
34884: 01/09/13: Jim Granville: Re: Programming Delays in ABEL
34875: 01/09/12: Andrew Gray: Fixed or Floating point for MP3 algorithim?
34880: 01/09/12: Muzaffer Kal: Re: Fixed or Floating point for MP3 algorithim?
34885: 01/09/12: Arrigo Benedetti: Re: Fixed or Floating point for MP3 algorithim?
34898: 01/09/13: Andrew Gray: Re: Fixed or Floating point for MP3 algorithim?
34899: 01/09/13: NotMe: Re: Fixed or Floating point for MP3 algorithim?
34877: 01/09/12: Paul: Problems with Xilinx VirtexE (Newbie)
34908: 01/09/13: Falk Brunner: Re: Problems with Xilinx VirtexE (Newbie)
34989: 01/09/17: Ray Andraka: Re: Problems with Xilinx VirtexE (Newbie)
35012: 01/09/17: Andy Peters: Re: Problems with Xilinx VirtexE (Newbie)
34886: 01/09/13: Jan Pech: Block RAM initialization
34887: 01/09/13: Rick Filipkiewicz: Re: Block RAM initialization
34890: 01/09/13: Tim: Re: Block RAM initialization
34990: 01/09/17: Ray Andraka: Re: Block RAM initialization
34897: 01/09/13: Felix Bertram: Re: Block RAM initialization
34905: 01/09/13: renaux: Re: Block RAM initialization
34910: 01/09/13: Jan Pech: Re: Block RAM initialization
34935: 01/09/14: Catalin Baetoniu: Re: Block RAM initialization
34949: 01/09/15: <hamish@cloud.net.au>: Re: Block RAM initialization
34991: 01/09/17: Ray Andraka: Re: Block RAM initialization
34924: 01/09/14: Arnaud Dion: Re: Block RAM initialization
34889: 01/09/13: TonyS2: FS Data I/O 2900 Prog Fixture
34892: 01/09/13: cnspy: convert
34893: 01/09/13: Tim: Re: convert
34896: 01/09/13: Srinivasan Venkataramanan: Re: convert
34906: 01/09/13: renaux: Re: convert
34913: 01/09/13: Tim: Re: convert
34894: 01/09/13: cnspy: delay
34895: 01/09/13: NotMe: Re: delay
34900: 01/09/13: amey hegde: Using Synopsys Design Compiler to target Virtex-E FPGA
34904: 01/09/13: Ansgar Bambynek: Re: Using Synopsys Design Compiler to target Virtex-E FPGA
34939: 01/09/14: amey hegde: Re: Using Synopsys Design Compiler to target Virtex-E FPGA
34901: 01/09/13: Matthias Fuchs: configuration latency for PCI bridge in FPGA
34915: 01/09/13: Tim: Re: configuration latency for PCI bridge in FPGA
34917: 01/09/14: Jim Granville: Re: configuration latency for PCI bridge in FPGA
34936: 01/09/14: clevin1234: Re: configuration latency for PCI bridge in FPGA
34938: 01/09/14: Austin Lesea: Re: configuration latency for PCI bridge in FPGA
34958: 01/09/16: Kevin Brace: Re: configuration latency for PCI bridge in FPGA
35051: 01/09/19: pfor: Re: configuration latency for PCI bridge in FPGA
34909: 01/09/13: Thomas Schmidt: FPGA--? huh
34912: 01/09/13: Steve Shaver: Re: FPGA--? huh
34914: 01/09/13: Michael Strayer: Specifing global clocks on a Spartan II (Newbee Quest)
35003: 01/09/17: Andy Peters: Re: Specifing global clocks on a Spartan II (Newbee Quest)
35028: 01/09/18: Arnaud Dion: Re: Specifing global clocks on a Spartan II (Newbee Quest)
34918: 01/09/13: jdiaz_pr: Foundation 3.1i REINSTALLATION
34926: 01/09/14: Tim: Re: Foundation 3.1i REINSTALLATION
34931: 01/09/14: Michael Boehnel: Re: Foundation 3.1i REINSTALLATION
34932: 01/09/14: fred: Re: Foundation 3.1i REINSTALLATION
34919: 01/09/13: jdiaz_pr: Looking for knowledge on CORDIC, division, correlators, TSBs, sorting, and path-delay handling
34927: 01/09/14: Tim: Re: Looking for knowledge on CORDIC, division, correlators, TSBs, sorting, and path-delay handling
34922: 01/09/14: rAinStorms: Help!
35031: 01/09/18: Kate Thompson: Re: Help!
34923: 01/09/14: Michael Boehnel: Virtex-E1600 unsupported?
34929: 01/09/14: Tim: Re: Virtex-E1600 unsupported?
34983: 01/09/17: Michael Boehnel: Re: Virtex-E1600 unsupported?
35004: 01/09/17: Kamal Patel: Re: Virtex-E1600 unsupported?
35006: 01/09/17: Rick Filipkiewicz: Re: Virtex-E1600 unsupported?
35017: 01/09/18: Michael Boehnel: Re: Virtex-E1600 unsupported?
34944: 01/09/14: Jens-Christian Lache: using BlockRAM
34963: 01/09/16: lennart: Re: using BlockRAM
34969: 01/09/17: Jens-Christian Lache: Re: using BlockRAM
34985: 01/09/17: John_H: Re: using BlockRAM
35011: 01/09/17: Andy Peters: Re: using BlockRAM
35021: 01/09/18: Jens-Christian Lache: Re: using BlockRAM
34951: 01/09/15: Leon Heller: Altera 10K shortage
34966: 01/09/17: Martin Thompson: Re: Altera 10K shortage
34952: 01/09/15: vivek: Carry Chain: Delay
34982: 01/09/17: John_H: Re: Carry Chain: Delay
34992: 01/09/17: Ray Andraka: Re: Carry Chain: Delay
34956: 01/09/16: llandre: Problems with Xilinx App Note 223 (UART with Internal 16-Byte Buffer)
34980: 01/09/17: Erik: Re: Problems with Xilinx App Note 223 (UART with Internal 16-Byte Buffer)
34984: 01/09/17: Goran Bilski: Re: Problems with Xilinx App Note 223 (UART with Internal 16-Byte
34957: 01/09/16: Rick Filipkiewicz: Virtex-2 availability
34962: 01/09/17: Jonas Weiss: Re: Virtex-2 availability
34976: 01/09/17: Austin Lesea: Re: Virtex-2 availability
34981: 01/09/17: John_H: Re: Virtex-2 availability
34997: 01/09/17: Austin Lesea: Re: Virtex-2 availability
35092: 01/09/20: John_H: Re: Virtex-2 availability
35110: 01/09/21: Austin Lesea: Re: Virtex-2 availability
35000: 01/09/17: Bryan: Re: Virtex-2 availability
35002: 01/09/17: Austin Lesea: Re: Virtex-2 availability
34995: 01/09/17: Ray Andraka: Re: Virtex-2 availability
34998: 01/09/17: Austin Lesea: Re: Virtex-2 variable DPS availability
35025: 01/09/18: Ray Andraka: Re: Virtex-2 variable DPS availability
35007: 01/09/17: Rick Filipkiewicz: Re: Virtex-2 availability
35008: 01/09/17: Austin Lesea: Re: Virtex-2 availability
35010: 01/09/17: emanuel stiebler: Re: Virtex-2 availability
35037: 01/09/18: Rick Filipkiewicz: Re: Virtex-2 availability
34960: 01/09/17: <khtsoi@pc90026.cse.cuhk.edu.hk>: INIT attribute of SRL16E
34964: 01/09/17: <khtsoi@pc90026.cse.cuhk.edu.hk>: Re: INIT attribute of SRL16E
34970: 01/09/17: Tim: Re: INIT attribute of SRL16E
34977: 01/09/17: Austin Lesea: Re: INIT attribute of SRL16E
34988: 01/09/17: Tim: Re: INIT attribute of SRL16E
34993: 01/09/17: Ray Andraka: Re: INIT attribute of SRL16E
34999: 01/09/17: Austin Lesea: Re: INIT attribute of SRL16E
34967: 01/09/17: Jon: Altera survey
34974: 01/09/17: Nial Stewart: Re: Altera survey
34996: 01/09/17: Ray Andraka: Re: Altera survey
35016: 01/09/18: Russell Shaw: Re: Altera survey
34968: 01/09/17: Jerre: xilinx prom readback with jtag
34971: 01/09/17: Sebastian: how to simulate virtex components?
34972: 01/09/17: Jens-Christian Lache: Re: how to simulate virtex components?
34973: 01/09/17: Sebastian: Re: how to simulate virtex components?
34978: 01/09/17: Jens-Christian Lache: Re: how to simulate virtex components?
34986: 01/09/17: Tim: Re: how to simulate virtex components?
35135: 01/09/23: <hamish@cloud.net.au>: Re: how to simulate virtex components?
35140: 01/09/23: Ray Andraka: Re: how to simulate virtex components?
35225: 01/09/26: <hamish@cloud.net.au>: Re: how to simulate virtex components?
35227: 01/09/26: Ray Andraka: Re: how to simulate virtex components?
35001: 01/09/17: Catalin Baetoniu: Re: how to simulate virtex components?
35009: 01/09/17: rafael plonka: Altera Quartus II: Ouput skew ;-(
35019: 01/09/18: g. giachella: Re: Altera Quartus II: Ouput skew ;-(
35024: 01/09/18: Jean-Baptiste Monnard: Re: Altera Quartus II: Ouput skew ;-(
35289: 01/09/27: Henning Trispel: Re: Altera Quartus II: Ouput skew ;-(
35014: 01/09/17: DL: SoC embedded software issues
35020: 01/09/18: hitajian: BUGs ?
35040: 01/09/18: Mike Treseler: Re: BUGs ?
35022: 01/09/18: jas: Xilinx FPGA development boards
35023: 01/09/18: Richard Wilkinson: Synplify BUFG instantiation bug
35027: 01/09/18: Tim: Re: Synplify BUFG instantiation bug
35060: 01/09/19: Assaf Sarfati: Re: Synplify BUFG instantiation bug
35070: 01/09/20: Tim: Re: Synplify BUFG instantiation bug
35029: 01/09/18: Allan Herriman: Re: Synplify BUFG instantiation bug
35030: 01/09/18: Chih-Hsun Lin: Increase routing delay in XILINX FPGA editor
35033: 01/09/18: John_H: Re: Increase routing delay in XILINX FPGA editor
35049: 01/09/19: Chih-Hsun Lin: Re: Increase routing delay in XILINX FPGA editor
35098: 01/09/20: Philip Freidin: Re: Increase routing delay in XILINX FPGA editor
35103: 01/09/21: Chih-Hsun Lin: Re: Increase routing delay in XILINX FPGA editor
35109: 01/09/21: Ray Andraka: Re: Increase routing delay in XILINX FPGA editor
35032: 01/09/18: Russell Tessier: FPGA'2002: CFP Reminder
35035: 01/09/18: Marius Vollmer: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35044: 01/09/19: Tim: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35078: 01/09/20: Marius Vollmer: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35053: 01/09/19: Gavin Hurlbut: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35076: 01/09/20: Marius Vollmer: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35081: 01/09/20: Gavin Hurlbut: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35129: 01/09/22: Marius Vollmer: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35130: 01/09/22: Gavin Hurlbut: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35036: 01/09/18: tom curran: C designs wanted
35082: 01/09/20: renaux: Re: C designs wanted
35039: 01/09/18: Don Husby: Synplicity logic replication
35042: 01/09/18: Rick Filipkiewicz: Re: Synplicity logic replication
35043: 01/09/18: Tim: Re: Synplicity logic replication
35100: 01/09/20: Don Husby: Re: Synplicity logic replication
35108: 01/09/21: Ray Andraka: Re: Synplicity logic replication
35142: 01/09/24: Tim: Forcing a LUT logic function (was Synplicity logic replication)
35154: 01/09/24: Don Husby: Re: Forcing a LUT logic function (was Synplicity logic replication)
35327: 01/09/29: Ray Andraka: Re: Forcing a LUT logic function (was Synplicity logic replication)
35358: 01/10/01: Tim: Re: Forcing a LUT logic function (was Synplicity logic replication)
35365: 01/10/01: Ray Andraka: Re: Forcing a LUT logic function (was Synplicity logic replication)
35046: 01/09/19: Kevin Neilson: Re: Synplicity logic replication
35058: 01/09/19: Don Husby: Re: Synplicity logic replication
35054: 01/09/19: John_H: Re: Synplicity logic replication
35077: 01/09/20: Ray Andraka: Re: Synplicity logic replication
35055: 01/09/19: Ken McElvain: Re: Synplicity logic replication
35136: 01/09/23: <hamish@cloud.net.au>: Re: Synplicity logic replication
35152: 01/09/24: Don Husby: Re: Synplicity logic replication
35159: 01/09/24: Ray Andraka: Re: Synplicity logic replication
35363: 01/10/01: Jonathan Bromley: Re: Forcing a LUT logic function (was Synplicity logic replication)
35048: 01/09/19: Antonio: SquareRootRaisedCosine filter design
35056: 01/09/19: Leon Heller: Re: SquareRootRaisedCosine filter design
35050: 01/09/19: cycle: virtex II (2v3000) configuration problem
35075: 01/09/20: cycle: Re: virtex II (2v3000) configuration problem
35084: 01/09/20: Austin Lesea: Re: virtex II (2v3000) configuration problem
35052: 01/09/19: Petter Gustad: MCS overflow? promgen and xc2v6000
35059: 01/09/20: Allan Herriman: Re: MCS overflow? promgen and xc2v6000
35062: 01/09/20: Petter Gustad: Re: MCS overflow? promgen and xc2v6000
35057: 01/09/19: jas: Xilinx equivalent gate count value in the *.mrp report
35086: 01/09/20: Kamal Patel: Re: Xilinx equivalent gate count value in the *.mrp report
35061: 01/09/20: Noddy: Timing constraints...
35066: 01/09/20: Jens-Christian Lache: Re: Timing constraints...
35067: 01/09/20: Noddy: Re: Timing constraints...
35071: 01/09/20: Jens-Christian Lache: Re: Timing constraints...
35262: 01/09/27: peterc: Re: Timing constraints...
35263: 01/09/27: Ray Andraka: Re: Timing constraints...
35063: 01/09/20: Steffen Thieringer: Digital PLL for implementing in FPGA
35089: 01/09/20: Falk Brunner: Re: Digital PLL for implementing in FPGA
35064: 01/09/20: Alex Cowie: Postdoc and PhD Scholarships in Reconfigurable Computing
35065: 01/09/20: Abraham Henry Vlok: Clockin on rising AND falling edge
35068: 01/09/20: Andy Green: Re: Clockin on rising AND falling edge
35069: 01/09/20: Panu H: Re: Clockin on rising AND falling edge
35072: 01/09/20: Abraham Henry Vlok: Re: Clockin on rising AND falling edge
35079: 01/09/20: Andrew Brown: Re: Clockin on rising AND falling edge
35080: 01/09/20: lennart: Re: Clockin on rising AND falling edge
35137: 01/09/23: <hamish@cloud.net.au>: Re: Clockin on rising AND falling edge
35085: 01/09/20: Peter Alfke: Re: Clockin on rising AND falling edge
35143: 01/09/24: przemek: Re: Clockin on rising AND falling edge
35144: 01/09/24: Peter Alfke: Re: Clockin on rising AND falling edge
35146: 01/09/24: Jim Granville: Re: Clockin on rising AND falling edge
35099: 01/09/20: Philip Freidin: Re: Clockin on rising AND falling edge
35073: 01/09/20: Uwe Bonnes: Quicklogic Eclipse Pinout needed
35074: 01/09/20: Johan Ditmar: problem with location constraints in Verilog
35119: 01/09/21: Andy Peters: Re: problem with location constraints in Verilog
35120: 01/09/21: Ray Andraka: Re: problem with location constraints in Verilog
35138: 01/09/23: Austin Franklin: Re: problem with location constraints in Verilog
35139: 01/09/23: Ray Andraka: Re: problem with location constraints in Verilog
35083: 01/09/20: Samuel Richard: Asking advice on a choise of platform
35087: 01/09/20: Theron Hicks: Maximum clock rate of various Xilinx families?
35088: 01/09/20: John_H: Re: Maximum clock rate of various Xilinx families?
35090: 01/09/21: Jim Granville: Re: Maximum clock rate of various Xilinx families?
35093: 01/09/20: Theron Hicks: Re: Maximum clock rate of various Xilinx families?
35094: 01/09/20: Peter Alfke: Re: Maximum clock rate of various Xilinx families?
35095: 01/09/21: Jim Granville: Re: Maximum clock rate of various Xilinx families?
35091: 01/09/20: Charles Ross: Virtex Clock Enable and Synplify
35114: 01/09/21: Edward Moore: Re: Virtex Clock Enable and Synplify
35118: 01/09/21: Charles Ross: Re: Virtex Clock Enable and Synplify
35122: 01/09/21: John_H: Re: Virtex Clock Enable and Synplify
35125: 01/09/22: Ray Andraka: Re: Virtex Clock Enable and Synplify
35096: 01/09/21: Rick Filipkiewicz: Stopping a DLL
35111: 01/09/21: Austin Lesea: Re: Stopping a DLL
35112: 01/09/21: John_H: Re: Stopping a DLL
35113: 01/09/21: Austin Lesea: Re: Stopping a DLL
35121: 01/09/21: John_H: Re: Stopping a DLL
35123: 01/09/21: Austin Lesea: Re: Stopping a DLL
35127: 01/09/22: Rick Filipkiewicz: Re: Stopping a DLL
35116: 01/09/21: Rick Filipkiewicz: Re: Stopping a DLL
35101: 01/09/21: Dave Barry: Altera 20KE Bus Switching
35106: 01/09/21: Ahmed Shihab: Re: Altera 20KE Bus Switching
35102: 01/09/21: Klaus Falser: Hitop Warning hi434
35368: 01/10/01: Arthur: Re: Hitop Warning hi434
35369: 01/10/01: Austin Lesea: Re: Hitop Warning hi434
35104: 01/09/21: Alex: PCI design for Spartan-2
35105: 01/09/21: Bruno Gebert: Control the programming of a Xilinx 9500 CPLD from an application
35107: 01/09/21: Jeffrey Graham: comparison of performance and advantages for fpga's versus
35117: 01/09/21: Kevin Neilson: Re: comparison of performance and advantages for fpga's versus microcontroller+dsp
35328: 01/09/29: Martin Euredjian: Re: comparison of performance and advantages for fpga's versus microcontroller+dsp
35338: 01/09/29: Kevin Neilson: Re: comparison of performance and advantages for fpga's versus microcontroller+dsp
35115: 01/09/21: Jamie Sanderson: Xilinx PCI bridge reference design
35124: 01/09/22: TonyS2: FS DATA I/O 2900 Proramming Fixture
35126: 01/09/22: David: Analyse static timing for Xilinx FPGA
35128: 01/09/22: Tim: Re: Analyse static timing for Xilinx FPGA
35134: 01/09/23: David: Re: Analyse static timing for Xilinx FPGA
35141: 01/09/24: Tim: Re: Analyse static timing for Xilinx FPGA
35131: 01/09/22: Noddy: Complex mixer LUT
35132: 01/09/22: Noddy: Re: Complex mixer LUT
35133: 01/09/22: Chris Eilbeck: Re: Complex mixer LUT
35147: 01/09/24: Noddy: Re: Complex mixer LUT
35145: 01/09/24: Antonio: Coefficient scaling question
35169: 01/09/25: Kevin Neilson: Re: Coefficient scaling question
35148: 01/09/24: Ted Moreno: comp.arch.fpga : Unusual clock divider ckt
35149: 01/09/24: Peter Alfke: Re: comp.arch.fpga : Unusual clock divider ckt
35150: 01/09/24: Peter Alfke: Re: comp.arch.fpga : Unusual clock divider ckt
35151: 01/09/24: Falk Brunner: Re: comp.arch.fpga : Unusual clock divider ckt
35153: 01/09/24: NotMe: Re: comp.arch.fpga : Unusual clock divider ckt
35156: 01/09/24: Peter Alfke: Re: comp.arch.fpga : Unusual clock divider ckt
35157: 01/09/24: Ted: Re: comp.arch.fpga : Unusual clock divider ckt
35158: 01/09/24: Ray Andraka: Re: comp.arch.fpga : Unusual clock divider ckt
35161: 01/09/24: Peter Alfke: Re: comp.arch.fpga : Unusual clock divider ckt
35164: 01/09/24: Eric Smith: Re: comp.arch.fpga : Unusual clock divider ckt
35165: 01/09/24: Peter Alfke: Re: comp.arch.fpga : Unusual clock divider ckt
35170: 01/09/25: Allan Herriman: Re: comp.arch.fpga : Unusual clock divider ckt
35188: 01/09/25: Peter Alfke: Re: comp.arch.fpga : Unusual clock divider ckt
35206: 01/09/26: Allan Herriman: Re: comp.arch.fpga : Unusual clock divider ckt
35400: 01/10/03: Hal Murray: Re: comp.arch.fpga : Unusual clock divider ckt
35402: 01/10/03: Ray Andraka: Re: comp.arch.fpga : Unusual clock divider ckt
35419: 01/10/04: Allan Herriman: Re: comp.arch.fpga : Unusual clock divider ckt
35429: 01/10/04: Ray Andraka: Re: comp.arch.fpga : Unusual clock divider ckt
35443: 01/10/05: Allan Herriman: Re: comp.arch.fpga : Unusual clock divider ckt
35176: 01/09/25: Rick Filipkiewicz: Re: comp.arch.fpga : Unusual clock divider ckt
35155: 01/09/24: Luke: Please help in Cossap and VHDL ..FPGA sintesys
35160: 01/09/24: Noddy: Registered outputs...
35162: 01/09/24: Peter Alfke: Re: Registered outputs...
35166: 01/09/24: Eric Smith: WebPack ISE 4.1 is out
35167: 01/09/24: Eric Smith: Spartan-IIE?
35232: 01/09/26: Austin Lesea: Re: Spartan-IIE?
35235: 01/09/26: emanuel stiebler: Re: Spartan-IIE?
35239: 01/09/26: Austin Lesea: Re: Spartan-IIE?
35240: 01/09/26: Peter Alfke: Re: Spartan-IIE?
35245: 01/09/26: Rick Filipkiewicz: Re: Spartan-IIE?
35246: 01/09/26: Austin Lesea: Re: Spartan-IIE?
35236: 01/09/26: Tim: Re: Spartan-IIE?
35249: 01/09/26: Kevin Brace: Re: Spartan-IIE?
35295: 01/09/27: Eric Smith: Re: Spartan-IIE?
35310: 01/09/28: Austin Lesea: Re: Spartan-IIE?
35316: 01/09/28: Philip Freidin: Re: Spartan-IIE?
35322: 01/09/28: Tim: Re: Spartan-IIE?
35168: 01/09/25: Andrew Dyer: way to test foundation express version in fe_shell?
35171: 01/09/24: Ivor: How to fix the hold time violation (clock skew>data skew) in QuartusII
35174: 01/09/25: Jean-Baptiste Monnard: Re: How to fix the hold time violation (clock skew>data skew) in QuartusII
35186: 01/09/25: Noddy: Re: How to fix the hold time violation (clock skew>data skew) in QuartusII
35342: 01/09/30: A. I. Khan: Re: How to fix the hold time violation (clock skew>data skew) in
35172: 01/09/25: Oliver Diessel: RAW 2002 Call for Papers
35173: 01/09/25: Jonas Weiss: Virtex II current consumption
35220: 01/09/26: Patrick Hibbs: Re: Virtex II current consumption
35257: 01/09/27: Reinoud: Re: Virtex II current consumption
35348: 01/09/30: Phil Hays: Re: Virtex II current consumption
35403: 01/10/03: <hamish@cloud.net.au>: Re: Virtex II current consumption
35404: 01/10/03: Rick Filipkiewicz: Re: Virtex II current consumption
35427: 01/10/04: <hamish@cloud.net.au>: Re: Virtex II current consumption
35175: 01/09/25: Nicolas Matringe: Xilinx Virtex RLOC question
35177: 01/09/25: timnicolson: verification problems please help
35299: 01/09/28: Ray Andraka: Re: verification problems please help
35178: 01/09/25: renaux: ROM initialisation on Xilinx Virtex design
35179: 01/09/25: Ru-Chin Tsai: How does Altera FLEX 10k communicate with PC?
35222: 01/09/26: Armin Mueller: Re: How does Altera FLEX 10k communicate with PC?
35333: 01/09/29: Ru-Chin Tsai: Re: How does Altera FLEX 10k communicate with PC?
35341: 01/09/29: Daniel Lang: Re: How does Altera FLEX 10k communicate with PC?
35180: 01/09/25: Noddy: Logical constraints of LUT
35221: 01/09/26: Patrick Hibbs: Re: Logical constraints of LUT
35237: 01/09/26: Jamie Sanderson: Re: Logical constraints of LUT
35243: 01/09/26: Peter Alfke: Re: Logical constraints of LUT
35252: 01/09/27: Noddy: Re: Logical constraints of LUT
35272: 01/09/27: Noddy: Re: Logical constraints of LUT
35274: 01/09/27: Peter Alfke: Re: Logical constraints of LUT
35276: 01/09/27: Ray Andraka: Re: Logical constraints of LUT
35278: 01/09/27: Noddy: Re: Logical constraints of LUT
35282: 01/09/27: Ray Andraka: Re: Logical constraints of LUT
35181: 01/09/25: kuldeep: fir filter
35184: 01/09/25: RM: Re: fir filter
35211: 01/09/25: kuldeep: Re: fir filter on ASIC
35266: 01/09/27: Brad Evans: Re: fir filter on ASIC
35290: 01/09/27: Nimrod Mesika: Re: fir filter on ASIC
35189: 01/09/25: renaux: Re: fir filter
35267: 01/09/27: kuldeep: Re: fir filter
35298: 01/09/28: Ray Andraka: Re: fir filter
35334: 01/09/29: renaux: Re: fir filter
36048: 01/10/26: Tony San: Re: fir filter
36056: 01/10/27: Ray Andraka: Re: fir filter
35182: 01/09/25: Peter Lang: FPGA with embedded Memory
35183: 01/09/25: Laurent Gauch: Re: FPGA with embedded Memory
35190: 01/09/25: Peter Alfke: Re: FPGA with embedded Memory
35194: 01/09/25: Eric Smith: Re: FPGA with embedded Memory
35191: 01/09/25: Ulf Samuelsson: Re: FPGA with embedded Memory
35198: 01/09/25: Ray Andraka: Re: FPGA with embedded Memory
35192: 01/09/25: Falk Brunner: Re: FPGA with embedded Memory
35209: 01/09/26: Peter Ormsby: Re: FPGA with embedded Memory
35219: 01/09/26: Peter Ormsby: Re: FPGA with embedded Memory
35185: 01/09/25: Noddy: CLKDLL question
35193: 01/09/25: Falk Brunner: Re: CLKDLL question
35187: 01/09/25: Nicolas Matringe: Xilinx implementation problem
35275: 01/09/27: santosh shreinivasan: Re: Xilinx implementation problem
35195: 01/09/25: Tom Brooks: Xilinx 4.1 software
35201: 01/09/25: Kamal Patel: Re: Xilinx 4.1 software
35208: 01/09/25: Alan Nishioka: Re: Xilinx 4.1 software
35226: 01/09/26: Tom Brooks: Re: Xilinx 4.1 software
35234: 01/09/26: Rick Filipkiewicz: Re: Xilinx 4.1 software
35330: 01/09/29: <hamish@cloud.net.au>: Re: Xilinx 4.1 software
35352: 01/09/30: Rick Filipkiewicz: Re: Xilinx 4.1 software
35356: 01/10/01: Allan Herriman: Re: Xilinx 4.1 software
35349: 01/09/30: Phil Hays: Re: Xilinx 4.1 software
35196: 01/09/25: J.Ho: Virtex2 slice level instantiation in verilog question
35197: 01/09/25: Tim: Re: Virtex2 slice level instantiation in verilog question
35199: 01/09/25: Bryan: Re: Virtex2 slice level instantiation in verilog question
35205: 01/09/25: Ray Andraka: Re: Virtex2 slice level instantiation in verilog question
35200: 01/09/25: Ray Andraka: Re: Virtex2 slice level instantiation in verilog question
35207: 01/09/25: J.Ho: Re: Virtex2 slice level instantiation in verilog question
35229: 01/09/26: Don Husby: Re: Virtex2 slice level instantiation in verilog question
35202: 01/09/25: Russell Tessier: FPGA'2002: Paper Deadline Friday
35204: 01/09/25: BF: WANTED source code of CPLD on TI 5402 DSK
35216: 01/09/26: Martin Thompson: Re: WANTED source code of CPLD on TI 5402 DSK
35210: 01/09/25: Akshay: Handle C
35212: 01/09/26: Srinivasan Venkataramanan: Re: Handle C
35214: 01/09/26: Martin Thompson: Re: Handle C
35247: 01/09/26: Chris: Re: Handle C
35213: 01/09/26: Anand: Virtex 2 : using IOB registers
35217: 01/09/26: Jens-Christian Lache: Re: Virtex 2 : using IOB registers
35238: 01/09/26: Jamie Sanderson: Re: Virtex 2 : using IOB registers
35215: 01/09/26: Harjo Otten: Gated clocks and shortage of clock buffers
35223: 01/09/26: NotMe: Re: Gated clocks and shortage of clock buffers
35248: 01/09/27: Speedy Zero Two: Re: Gated clocks and shortage of clock buffers
35251: 01/09/27: Lasse Langwadt Christensen: Re: Gated clocks and shortage of clock buffers
35250: 01/09/27: Lasse Langwadt Christensen: Re: Gated clocks and shortage of clock buffers
35218: 01/09/26: Jens-Christian Lache: how to dublicate logic?
35228: 01/09/26: John_H: Re: how to dublicate logic?
35230: 01/09/26: Jens-Christian Lache: Re: how to dublicate logic?
35279: 01/09/27: Andy Peters: Re: how to dublicate logic?
35304: 01/09/28: Jens-Christian Lache: Re: how to dublicate logic?
35312: 01/09/28: John_H: Re: how to dublicate logic?
35314: 01/09/28: Jens-Christian Lache: Re: how to dublicate logic?
35318: 01/09/28: Ray Andraka: Re: how to dublicate logic?
35254: 01/09/27: Jens-Christian Lache: Re: how to dublicate logic?
35863: 01/10/21: Vasudeva Kamath: Re: how to dublicate logic?
35945: 01/10/24: Jens-Christian Lache: Re: how to dublicate logic?
35224: 01/09/26: Martin Thompson: Pentium 3 vs Pentium 4 benchmarks
35231: 01/09/26: Nial Stewart: Re: Pentium 3 vs Pentium 4 benchmarks
35253: 01/09/27: Martin Thompson: Re: Pentium 3 vs Pentium 4 benchmarks
35241: 01/09/26: Andreas Schmidt: Digital design/ASIC/FPGA/CAD engineer (MSEE) looking for a new position
35244: 01/09/26: Peter Alfke: Re: Digital design/ASIC/FPGA/CAD engineer (MSEE) looking for a new
35242: 01/09/26: Andreas Schmidt: Digital design/ASIC/FPGA/CAD/Hardware engineer (MSEE) looking for a new
35255: 01/09/27: Matthias Fuchs: Programming flash connected to CPLD via JTAG
35270: 01/09/27: Mike R.: Re: Programming flash connected to CPLD via JTAG
35281: 01/09/27: Ulf Samuelsson: Re: Programming flash connected to CPLD via JTAG
35285: 01/09/27: Rick Filipkiewicz: Re: Programming flash connected to CPLD via JTAG
35288: 01/09/27: Muzaffer Kal: Re: Programming flash connected to CPLD via JTAG
35293: 01/09/28: Mike R.: Re: Programming flash connected to CPLD via JTAG
35306: 01/09/28: Matthias Fuchs: Re: Programming flash connected to CPLD via JTAG
35332: 01/09/29: Dmitry Kuznetsov: Re: Programming flash connected to CPLD via JTAG
35307: 01/09/28: Wolfgang Loewer: Re: Programming flash connected to CPLD via JTAG
35345: 01/09/29: Assaf Sarfati: Re: Programming flash connected to CPLD via JTAG
35256: 01/09/27: Andrew Gray: Maxplus waveform simulations
35260: 01/09/27: Egbert Molenkamp: Re: Maxplus waveform simulations
35261: 01/09/27: C.Schlehaus: Re: Maxplus waveform simulations
35683: 01/10/13: phil: Re: Maxplus waveform simulations
35258: 01/09/27: Noddy: Block RAM instantiation
35259: 01/09/27: Noddy: Re: Block RAM instantiation
35264: 01/09/27: Allan Herriman: Xilinx UCF Syntax
35265: 01/09/27: JAK: Xilinx Xactstep 5.1/6.1
35268: 01/09/27: =?ISO-8859-1?Q?Beno=EEt?=: altera APEX 20KE
35269: 01/09/27: yaohan: sensitivity list
35273: 01/09/27: Falk Brunner: Re: sensitivity list
35291: 01/09/27: Bill McDermith: Re: sensitivity list
35277: 01/09/27: Jonathan Bromley: Re: sensitivity list
35284: 01/09/27: Falk Brunner: Re: sensitivity list
35294: 01/09/28: yaohan: Re: sensitivity list
35451: 01/10/05: Andrea Sabatini: Re: sensitivity list
35300: 01/09/28: Russell Shaw: Re: sensitivity list
35308: 01/09/28: Jonathan Bromley: Re: sensitivity list
35271: 01/09/27: Aldo Romani: Using EABs in Leonardo Spectrum with Flex10K
35301: 01/09/28: Russell Shaw: Re: Using EABs in Leonardo Spectrum with Flex10K
35317: 01/09/28: Aldo Romani: Re: Using EABs in Leonardo Spectrum with Flex10K
35329: 01/09/29: Russell Shaw: Re: Using EABs in Leonardo Spectrum with Flex10K
35337: 01/09/29: Aldo Romani: Re: Using EABs in Leonardo Spectrum with Flex10K
35343: 01/09/30: Russell Shaw: Re: Using EABs in Leonardo Spectrum with Flex10K
35280: 01/09/27: Tony Kirke: System DSP Generator on Xilinx
35286: 01/09/27: Ray Andraka: Re: System DSP Generator on Xilinx
35292: 01/09/27: M: Fastest way to become a Verilog samurai?
35297: 01/09/28: Ray Andraka: Re: Fastest way to become a Verilog samurai?
35359: 01/10/01: Sean Williams: Re: Fastest way to become a Verilog samurai?
35315: 01/09/28: Mike Treseler: Re: Meta-stability
35321: 01/09/28: Ray Andraka: Re: Meta-stability
35303: 01/09/27: Manjunathan: Meta-stability
35309: 01/09/28: Rick Filipkiewicz: Re: Meta-stability
35311: 01/09/28: Austin Lesea: Re: Meta-stability
35319: 01/09/28: Philip Freidin: Re: Meta-stability
35323: 01/09/28: Brian Philofsky: Re: Meta-stability
35324: 01/09/28: Austin Lesea: Re: Meta-stability
35331: 01/09/29: Manjunath: Re: Meta-stability
35305: 01/09/28: Noddy: Global Clock to Pad constraint
35313: 01/09/28: Atkins, Kate: Active-HDL back annotated simulation and PC memory usage
35320: 01/09/28: Ray Andraka: Re: Active-HDL back annotated simulation and PC memory usage
35325: 01/09/28: Rick Filipkiewicz: Re: Active-HDL back annotated simulation and PC memory usage
35339: 01/09/29: Kevin Neilson: Re: Active-HDL back annotated simulation and PC memory usage
35326: 01/09/28: S. Ramirez: Re: Active-HDL back annotated simulation and PC memory usage
35335: 01/09/29: Noddy: Timing on output
35336: 01/09/29: Peter Alfke: Re: Timing on output
35344: 01/09/30: Terrence Mak: about JBits
35346: 01/09/30: Patrick Muller: Xilinx Virtex-II reconfiguration
35350: 01/09/30: Peter Alfke: Re: Xilinx Virtex-II reconfiguration
35347: 01/09/30: yaohan: MAX Plus Division
35351: 01/09/30: Eric: future Xilinx products wish list ...
35354: 01/09/30: John Larkin: Re: future Xilinx products wish list ...
35377: 01/10/01: Eric: Re: future Xilinx products wish list ...
35487: 01/10/07: Rob Finch: Re: future Xilinx products wish list ...
35488: 01/10/08: Peter Alfke: Re: future Xilinx products wish list ...
35499: 01/10/08: Eric: Re: future Xilinx products wish list ...
35669: 01/10/13: Tim: Re: future Xilinx products wish list ...
35679: 01/10/13: <hamish@cloud.net.au>: Re: future Xilinx products wish list ...
35693: 01/10/13: Tim: Re: future Xilinx products wish list ...
35698: 01/10/14: <hamish@cloud.net.au>: Re: future Xilinx products wish list ...
35713: 01/10/15: Andrew Brown: Re: future Xilinx products wish list ...
35715: 01/10/15: Tim: Re: future Xilinx products wish list ...
36026: 01/10/26: Jamie Sanderson: Re: future Xilinx products wish list ...
35697: 01/10/14: Eric: Re: future Xilinx products wish list ...
35707: 01/10/15: Tim: Re: future Xilinx products wish list ...
35722: 01/10/15: Eric: Re: future Xilinx products wish list ...
35655: 01/10/12: Peter: Re: future Xilinx products wish list ...
35658: 01/10/12: Theron Hicks: Re: future Xilinx products wish list ...
35665: 01/10/12: Tom Burgess: Re: future Xilinx products wish list ...
35675: 01/10/13: Peter Alfke: Re: future Xilinx products wish list ...
35680: 01/10/13: Rick Filipkiewicz: Re: future Xilinx products wish list ...
35355: 01/09/30: Steven K. Knapp: Re: future Xilinx products wish list ...
35364: 01/10/01: Ray Andraka: Re: future Xilinx products wish list ...
35392: 01/10/02: Steven K. Knapp: Re: future Xilinx products wish list ...
35378: 01/10/02: Eric: Re: future Xilinx products wish list ...
35353: 01/09/30: Austin Franklin: Xchecker and NT???
35382: 01/10/02: peterc: Re: Xchecker and NT???
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
