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Threads Starting Nov 2006
111276: 06/11/01: MK Wong: Blog from Lattice Semiconductor
111295: 06/11/01: Logaras Evangelos: DDR_controller_EDK
111401: 06/11/02: Siva Velusamy: Re: DDR_controller_EDK
111449: 06/11/03: Guru: Re: DDR_controller_EDK
111313: 06/11/01: fp: De-serializer using Xilinx DCM
111316: 06/11/01: Peter Alfke: Re: De-serializer using Xilinx DCM
111320: 06/11/01: fp: Re: De-serializer using Xilinx DCM
111325: 06/11/01: Andy: Re: De-serializer using Xilinx DCM
111327: 06/11/01: Peter Alfke: Re: De-serializer using Xilinx DCM
111345: 06/11/01: Symon: Re: De-serializer using Xilinx DCM
111351: 06/11/01: Ray Andraka: Re: De-serializer using Xilinx DCM
111333: 06/11/01: fp: Re: De-serializer using Xilinx DCM
111341: 06/11/01: Peter Alfke: Re: De-serializer using Xilinx DCM
111347: 06/11/01: fp: Re: De-serializer using Xilinx DCM
111353: 06/11/01: Peter Alfke: Re: De-serializer using Xilinx DCM
111326: 06/11/01: MikeD: Rad-hard (neutron/SEU and space) tutorial?
111339: 06/11/01: Austin Lesea: Re: Rad-hard (neutron/SEU and space) tutorial?
111340: 06/11/01: Hans: Re: Rad-hard (neutron/SEU and space) tutorial?
111370: 06/11/02: Thomas Stanka: Re: Rad-hard (neutron/SEU and space) tutorial?
111376: 06/11/02: krishna.janumanchi@gmail.com: Re: Rad-hard (neutron/SEU and space) tutorial?
111331: 06/11/01: <rponsard@gmail.com>: can someone post or email xusbdfwu.hex (1021) from linux ISE 8.2 webpack
111337: 06/11/01: <nnn>: Need flash adc with plcc format?
111346: 06/11/01: Symon: Re: Need flash adc with plcc format?
111356: 06/11/01: Matthew Hicks: Re: Need flash adc with plcc format?
111366: 06/11/02: Symon: Re: Need flash adc with plcc format?
111378: 06/11/02: <nnn>: Re: Need flash adc with plcc format?
111388: 06/11/02: Matthew Hicks: Re: Need flash adc with plcc format?
111393: 06/11/02: <nnn>: Re: Need flash adc with plcc format?
111354: 06/11/01: JustJohn: Dual-port BlockRAM "write first" puzzler...
111365: 06/11/01: Peter Alfke: Re: Dual-port BlockRAM "write first" puzzler...
111367: 06/11/01: JustJohn: Re: Dual-port BlockRAM "write first" puzzler...
111421: 06/11/02: jbnote: Re: Dual-port BlockRAM "write first" puzzler...
111510: 06/11/04: Philip Freidin: Re: Dual-port BlockRAM "write first" puzzler...
111371: 06/11/02: Laurent Pinchart: Xilinx ISE Webpack - Any usable simulator for the Linux platform ?
111372: 06/11/02: antonio bergnoli: Re: Xilinx ISE Webpack - Any usable simulator for the Linux platform
111407: 06/11/02: Kumar Deepak: Re: Xilinx ISE Webpack - Any usable simulator for the Linux platform ?
111448: 06/11/03: Alan Myler: Re: Xilinx ISE Webpack - Any usable simulator for the Linux platform ?
111484: 06/11/03: Mike Treseler: Re: Xilinx ISE Webpack - Any usable simulator for the Linux platform
111375: 06/11/02: Nick: Tsamp for Spartan 3?
143580: 09/10/16: qamrul: Re: Tsamp for Spartan 3?
111379: 06/11/02: <joel.pigdon@gmail.com>: Quartus synthesising out signals?
111380: 06/11/02: John Adair: Re: Quartus synthesising out signals?
111381: 06/11/02: hikmetkoca: I can not simulate "pipelined divider v3.0"
111395: 06/11/02: tbrown: Re: I can not simulate "pipelined divider v3.0"
111383: 06/11/02: Brandon Jasionowski: Warning LIT:176, DCM in Virtex 4?
111384: 06/11/02: Brandon Jasionowski: Re: Warning LIT:176, DCM in Virtex 4?
111422: 06/11/02: VC: Re: Warning LIT:176, DCM in Virtex 4?
111387: 06/11/02: kilgor: Aurora v2.5 for V4FX - No "channel_up" in post-routed simulation during 200 us
111436: 06/11/02: kilgor: Re: Aurora v2.5 for V4FX - No "channel_up" in post-routed simulation during 200 us
111466: 06/11/03: kilgor: Re: Aurora v2.5 for V4FX - No "channel_up" in post-routed simulation during 200 us
111390: 06/11/02: himassk: How to avoid negative slack?
111396: 06/11/02: Symon: Re: How to avoid negative slack?
111397: 06/11/02: Austin Lesea: Re: How to avoid negative slack?
111405: 06/11/02: Symon: Re: How to avoid negative slack?
111414: 06/11/02: Austin Lesea: Re: How to avoid negative slack?
111416: 06/11/02: Symon: OT. Warning bad jokes. was :- How to avoid negative slack?
111417: 06/11/02: Austin Lesea: Re: OT. Warning bad jokes. was :- How to avoid negative slack?
111391: 06/11/03: Steve: EDK software development
111398: 06/11/02: radarman: Re: EDK software development
111408: 06/11/02: <martstev@gmail.com>: reset
111430: 06/11/03: Rob: Re: reset
111455: 06/11/03: yttrium: Re: reset
111531: 06/11/04: yttrium: Re: reset
111567: 06/11/06: KJ: Re: reset
111574: 06/11/06: Duane Clark: Re: reset
111587: 06/11/06: Martin Thompson: Re: reset
111460: 06/11/03: ALuPin@web.de: Re: reset
111493: 06/11/03: radarman: Re: reset
111582: 06/11/06: Ray Andraka: Re: reset
111597: 06/11/06: Ray Andraka: Re: reset
111590: 06/11/06: Evan Lavelle: Xilinx GSR/reset levels (was: Re: reset)
111557: 06/11/06: ALuPin@web.de: Re: reset
111577: 06/11/06: KJ: Re: reset
111586: 06/11/06: KJ: Re: reset
111410: 06/11/02: Roberto: chipscope
111518: 06/11/04: Markus Meng: Re: chipscope
111532: 06/11/04: yttrium: Re: chipscope
111541: 06/11/05: motty: Re: chipscope
111667: 06/11/07: Kevin Neilson: Re: chipscope
111423: 06/11/02: lancepickens@gmail.com: Scientific Computing on FPGA
111425: 06/11/02: Tommy Thorn: Re: Scientific Computing on FPGA
111428: 06/11/03: Symon: Re: Scientific Computing on FPGA
111447: 06/11/03: Ben Jones: Re: Scientific Computing on FPGA
111457: 06/11/03: Evan Lavelle: Re: Scientific Computing on FPGA
111500: 06/11/03: Symon: OT Re: Scientific Computing on FPGA
111519: 06/11/04: Ben Jones: Re: OT Re: Scientific Computing on FPGA
111602: 06/11/06: scott moore: Re: Scientific Computing on FPGA
111427: 06/11/02: JJ: Re: Scientific Computing on FPGA
111443: 06/11/03: <helmut.leonhardt@gmail.com>: Re: Scientific Computing on FPGA
111452: 06/11/03: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Scientific Computing on FPGA
111477: 06/11/03: Nico Coesel: Re: Scientific Computing on FPGA
111483: 06/11/03: Marc Reinig: Re: Scientific Computing on FPGA
111496: 06/11/03: Nico Coesel: Re: Scientific Computing on FPGA
111504: 06/11/04: Tim: Re: Scientific Computing on FPGA
111556: 06/11/06: eric: Re: Scientific Computing on FPGA
111575: 06/11/06: Marc Battyani: Re: Scientific Computing on FPGA
111628: 06/11/07: eric: Re: Scientific Computing on FPGA
111525: 06/11/04: scott moore: Re: Scientific Computing on FPGA
111543: 06/11/05: Marc Battyani: Re: Scientific Computing on FPGA
111459: 06/11/03: Frank Buss: Re: Scientific Computing on FPGA
111464: 06/11/03: daver2: Re: Scientific Computing on FPGA
111482: 06/11/03: JJ: Re: Scientific Computing on FPGA
111485: 06/11/03: lancepickens@gmail.com: Re: Scientific Computing on FPGA
111492: 06/11/03: JJ: Re: Scientific Computing on FPGA
111512: 06/11/04: Kryten: Re: Scientific Computing on FPGA
111535: 06/11/04: Ray Andraka: Re: Scientific Computing on FPGA
111621: 06/11/07: Marc Reinig: Re: Scientific Computing on FPGA
111646: 06/11/07: Ray Andraka: Re: Scientific Computing on FPGA
111533: 06/11/04: yttrium: Re: Scientific Computing on FPGA
111578: 06/11/06: <reiner@hartenstein.de>: Re: Scientific Computing on FPGA
111637: 06/11/07: <fpga_toys@yahoo.com>: Re: Scientific Computing on FPGA
111639: 06/11/07: <fpga_toys@yahoo.com>: Re: Scientific Computing on FPGA
111433: 06/11/02: Anonyma: digilent spartan-3 board sram timing
111461: 06/11/03: radarman: Re: digilent spartan-3 board sram timing
111513: 06/11/04: Brian Drummond: Re: digilent spartan-3 board sram timing
111505: 06/11/03: Brian Davis: Re: digilent spartan-3 board sram timing
111434: 06/11/02: ekavirsrikanth@gmail.com: regardign signal assinment statement............................
111435: 06/11/03: Mark McDougall: Re: regardign signal assinment statement............................
111445: 06/11/03: backhus: Re: regardign signal assinment statement............................
111439: 06/11/03: <kollarameshk@gmail.com>: JTAG connection for chipscope
111515: 06/11/04: Markus Meng: Re: JTAG connection for chipscope
111522: 06/11/04: John Adair: Re: JTAG connection for chipscope
111538: 06/11/05: yttrium: Re: JTAG connection for chipscope
112225: 06/11/17: Trevor Coolidge: Re: JTAG connection for chipscope
111554: 06/11/05: <kollarameshk@gmail.com>: Re: JTAG connection for chipscope
111444: 06/11/03: Davy: SystemVerilog not use Mail-box directly in VMM and AVM ?
111450: 06/11/03: NigelE: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111454: 06/11/03: Davy: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111458: 06/11/03: NigelE: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111551: 06/11/05: Davy: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111553: 06/11/05: Davy: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111738: 06/11/09: Davy: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111791: 06/11/10: AdamRose: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111446: 06/11/03: Davy: Conformal compare retiming netlist and RTL
111456: 06/11/03: axalay: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111491: 06/11/03: tullio: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111501: 06/11/04: Symon: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111503: 06/11/04: Duane Clark: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111506: 06/11/03: Ed McGettigan: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111494: 06/11/03: Duane Clark: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111529: 06/11/04: Duane Clark: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111508: 06/11/04: axalay: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111509: 06/11/04: axalay: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111462: 06/11/03: Peter Mendham: EDK 8.2i/cygwin issues
111465: 06/11/03: Peter Mendham: Re: EDK 8.2i/cygwin issues
111470: 06/11/03: Peter Mendham: Re: EDK 8.2i/cygwin issues
111473: 06/11/03: tbrown: Re: EDK 8.2i/cygwin issues
111476: 06/11/03: Peter Mendham: Re: EDK 8.2i/cygwin issues
111488: 06/11/03: Anthony M: EDK Modelsim Simulation with RS232 Hook
111507: 06/11/03: Jhlw: Cleaning generated files in Xilinx 8.2 EDK and ISE
111520: 06/11/04: Joseph Samson: Re: Cleaning generated files in Xilinx 8.2 EDK and ISE
111530: 06/11/04: Duane Clark: Re: Cleaning generated files in Xilinx 8.2 EDK and ISE
111524: 06/11/04: Jhlw: Re: Cleaning generated files in Xilinx 8.2 EDK and ISE
111549: 06/11/05: Jhlw: Re: Cleaning generated files in Xilinx 8.2 EDK and ISE
111511: 06/11/04: axalay: PCI
111516: 06/11/04: Markus Meng: Re: PCI
111517: 06/11/04: Nicolas Matringe: Re: PCI
111521: 06/11/04: John Adair: Re: PCI
111523: 06/11/04: Xesium: FSL microblaze to co-processor write problem...
111555: 06/11/06: Zara: Re: FSL microblaze to co-processor write problem...
111604: 06/11/06: Xesium: Re: FSL microblaze to co-processor write problem...
111536: 06/11/04: <drop669@gmail.com>: Using Altera Nios II Stratix II dev kit just as FPGA.
111539: 06/11/05: Amirtham: Integration of modules
111540: 06/11/05: Ralf Hildebrandt: Re: Integration of modules
111680: 06/11/07: Amirtham: Re: Integration of modules
111542: 06/11/05: ZHI: How to transform matlab value to FPGA value
111544: 06/11/05: sergey: post-synthesis simulation issues with ModelSim
111545: 06/11/05: sergey: Re: post-synthesis simulation issues with ModelSim
111558: 06/11/06: krishna.janumanchi@gmail.com: Re: post-synthesis simulation issues with ModelSim
111571: 06/11/06: sergey: Re: post-synthesis simulation issues with ModelSim
111547: 06/11/05: JG: Spartan3E kit and BPI configuration problem.
111550: 06/11/05: Davy: Formal Logic Equivalent Check (LEC)
111561: 06/11/06: Thomas Stanka: Re: Formal Logic Equivalent Check (LEC)
111572: 06/11/06: ABC: Re: Formal Logic Equivalent Check (LEC)
111560: 06/11/06: Chris: I2C Master in Verilog
111610: 06/11/06: Rotem: Re: I2C Master in Verilog
111622: 06/11/06: Paul Schreiber: Re: I2C Master in Verilog
111562: 06/11/06: Arash Partow: Schifra Reed-Solomon ECC Library
111563: 06/11/06: tsemer: choise of fpga platform
111594: 06/11/06: Jonathan Bromley: Re: choise of fpga platform
111636: 06/11/07: tsemer: Re: choise of fpga platform
111564: 06/11/06: <me_2003@walla.co.il>: To Xilinx guys out there - microblaze mapping problem
111565: 06/11/06: Göran Bilski: Re: To Xilinx guys out there - microblaze mapping problem
111631: 06/11/07: Göran Bilski: Re: To Xilinx guys out there - microblaze mapping problem
111641: 06/11/07: Göran Bilski: Re: To Xilinx guys out there - microblaze mapping problem
111591: 06/11/06: <me_2003@walla.co.il>: Re: To Xilinx guys out there - microblaze mapping problem
111640: 06/11/07: <me_2003@walla.co.il>: Re: To Xilinx guys out there - microblaze mapping problem
111650: 06/11/07: <me_2003@walla.co.il>: Re: To Xilinx guys out there - microblaze mapping problem
111570: 06/11/06: <slkjas@gmail.com>: PCIe latency
111588: 06/11/06: Andreas Ehliar: Re: PCIe latency
111630: 06/11/07: JSalk: Re: PCIe latency
111576: 06/11/06: uvbaz: Global Clocks in Xilinx Virtex-4
111585: 06/11/06: Paul: Re: Global Clocks in Xilinx Virtex-4
111592: 06/11/06: Ray Andraka: Re: Global Clocks in Xilinx Virtex-4
111612: 06/11/07: Rob: Re: Global Clocks in Xilinx Virtex-4
111614: 06/11/06: Ray Andraka: Re: Global Clocks in Xilinx Virtex-4
111617: 06/11/07: Rob: Re: Global Clocks in Xilinx Virtex-4
111619: 06/11/06: Ray Andraka: Re: Global Clocks in Xilinx Virtex-4
111620: 06/11/07: Rob: Re: Global Clocks in Xilinx Virtex-4
111615: 06/11/07: Rob: Re: Global Clocks in Xilinx Virtex-4
111596: 06/11/06: Alan Nishioka: Re: Global Clocks in Xilinx Virtex-4
111613: 06/11/06: Peter Alfke: Re: Global Clocks in Xilinx Virtex-4
111618: 06/11/06: Peter Alfke: Re: Global Clocks in Xilinx Virtex-4
111579: 06/11/06: al99999: Cypress 68013 - Xilinx FPGA
111580: 06/11/06: Will Dean: Re: Cypress 68013 - Xilinx FPGA
112502: 06/11/23: Will Dean: Re: Cypress 68013 - Xilinx FPGA
111629: 06/11/07: eric: Re: Cypress 68013 - Xilinx FPGA
111645: 06/11/07: al99999: Re: Cypress 68013 - Xilinx FPGA
112489: 06/11/23: al99999: Re: Cypress 68013 - Xilinx FPGA
111589: 06/11/06: uvbaz: surprised output of Xilinx Virtex-4
111593: 06/11/06: Jonathan Bromley: Re: surprised output of Xilinx Virtex-4
111600: 06/11/06: MM: Re: surprised output of Xilinx Virtex-4
111601: 06/11/06: Georg Acher: Re: surprised output of Xilinx Virtex-4
111607: 06/11/06: Jonathan Bromley: Re: surprised output of Xilinx Virtex-4
111598: 06/11/06: uvbaz: Re: surprised output of Xilinx Virtex-4
111599: 06/11/06: uvbaz: Re: surprised output of Xilinx Virtex-4
111633: 06/11/07: uvbaz: Re: surprised output of Xilinx Virtex-4
111603: 06/11/06: <jetmarc@hotmail.com>: ISE/EDK project on a file server?
111644: 06/11/07: Jim Wu: Re: ISE/EDK project on a file server?
111657: 06/11/07: Jon Beniston: Re: ISE/EDK project on a file server?
111605: 06/11/06: Sietse Achterop: Once synthesized BRAMs are still vanishing in WebPACK version 8.1
111609: 06/11/06: Matthew Hicks: XUP USB
111634: 06/11/07: Andreas Ehliar: Re: XUP USB
111665: 06/11/07: Matthew Hicks: Re: XUP USB
111611: 06/11/06: yy: Chip to Chip LVDS
111616: 06/11/06: Bob: Re: Chip to Chip LVDS
111675: 06/11/07: Bob: Re: Chip to Chip LVDS
111681: 06/11/08: Squirrel: Re: Chip to Chip LVDS
111638: 06/11/07: yy: Re: Chip to Chip LVDS
111687: 06/11/08: Dave Nunn: Re: Chip to Chip LVDS
111717: 06/11/08: yy: Re: Chip to Chip LVDS
111623: 06/11/07: Mark McDougall: Modelsim problem - mixed VHDL,Verilog & VHO
111662: 06/11/07: Mike Treseler: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111669: 06/11/08: Mark McDougall: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111670: 06/11/08: Mark McDougall: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111720: 06/11/09: Mark McDougall: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111723: 06/11/08: Subroto Datta: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111624: 06/11/06: avishay: Should I use an external synthesis tool?
111627: 06/11/07: backhus: Re: Should I use an external synthesis tool?
111649: 06/11/07: Mike Treseler: Re: Should I use an external synthesis tool?
111658: 06/11/07: alterauser: Re: Should I use an external synthesis tool?
111664: 06/11/07: Paul Leventis: Re: Should I use an external synthesis tool?
111625: 06/11/06: Davy: How to simulate netlist with gated clock?
111626: 06/11/07: backhus: Re: How to simulate netlist with gated clock?
111683: 06/11/08: backhus: Re: How to simulate netlist with gated clock?
111747: 06/11/09: Kim Enkovaara: Re: How to simulate netlist with gated clock?
111678: 06/11/07: Davy: Re: How to simulate netlist with gated clock?
111703: 06/11/08: <sharp@cadence.com>: Re: How to simulate netlist with gated clock?
111704: 06/11/08: daytripper: Re: How to simulate netlist with gated clock?
111730: 06/11/08: Davy: Re: How to simulate netlist with gated clock?
111731: 06/11/08: Davy: Re: How to simulate netlist with gated clock?
111768: 06/11/09: <sharp@cadence.com>: Re: How to simulate netlist with gated clock?
111642: 06/11/07: Sandip: How to generate a PROM file and then burn it on FPGA
111643: 06/11/07: <me_2003@walla.co.il>: Re: How to generate a PROM file and then burn it on FPGA
111655: 06/11/07: uvbaz: Re: How to generate a PROM file and then burn it on FPGA
111685: 06/11/08: Sandip: Re: How to generate a PROM file and then burn it on FPGA
111694: 06/11/08: <me_2003@walla.co.il>: Re: How to generate a PROM file and then burn it on FPGA
111783: 06/11/09: Sandip: Re: How to generate a PROM file and then burn it on FPGA
111648: 06/11/07: Aaron Curtin: Microblaze FPU and IEEE754 single precision number format
111652: 06/11/07: Ben Jones: Re: Microblaze FPU and IEEE754 single precision number format
111651: 06/11/07: Jialin: How to send data/program to the memory of a Spartan 3 starter kit board
111660: 06/11/07: Matthew Hicks: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111673: 06/11/08: John_H: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111721: 06/11/09: John_H: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111752: 06/11/09: John_H: Re: How to send data/program to the memory of a Spartan 3 starter
111713: 06/11/08: Jialin: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111714: 06/11/08: Jialin: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111749: 06/11/09: ScottNortman: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111762: 06/11/09: Jecel: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111653: 06/11/07: Frank van Eijkelenburg: avalon tristate slave address
111654: 06/11/07: uvbaz: confused result in Logic Analyser, being crazy...
111659: 06/11/07: Slurp: Re: confused result in Logic Analyser, being crazy...
111684: 06/11/08: backhus: Re: confused result in Logic Analyser, being crazy...
111736: 06/11/09: uvbaz: Re: confused result in Logic Analyser, being crazy...
111656: 06/11/07: Pleg: Upgrading spartan-II: possible?
111666: 06/11/07: John Adair: Re: Upgrading spartan-II: possible?
111661: 06/11/07: <karollo@o2.pl>: problems with using altera vhdl testbench in ModelSim
111668: 06/11/07: Mike Treseler: Re: problems with using altera vhdl testbench in ModelSim
111677: 06/11/07: Mike Treseler: Re: problems with using altera vhdl testbench in ModelSim
111674: 06/11/07: <karollo@o2.pl>: Re: problems with using altera vhdl testbench in ModelSim
111672: 06/11/07: ZHI: H for FPGA
111679: 06/11/07: Amirtham: problem in interfacing with SDRAM controller
111689: 06/11/08: Dre: Platform USB Cable and Windows XP Pro x64
111712: 06/11/08: Neil Glenn Jacobson: Re: Platform USB Cable and Windows XP Pro x64
112341: 06/11/20: Eric Smith: Re: Platform USB Cable and Windows XP Pro x64
111690: 06/11/08: Phil: Graphics-2-FPGA
111692: 06/11/08: Gabor: Re: Graphics-2-FPGA
111701: 06/11/08: Mike Harrison: Re: Graphics-2-FPGA
111709: 06/11/08: Arnim: Re: Graphics-2-FPGA
111716: 06/11/09: Mark McDougall: Re: Graphics-2-FPGA
111846: 06/11/11: phil: Re: Graphics-2-FPGA
111693: 06/11/08: tsemer: Field Programmable Object Array
111798: 06/11/10: Gabor: Re: Field Programmable Object Array
111966: 06/11/13: Kashmir: Re: Field Programmable Object Array
111695: 06/11/08: Dolphin: Nios2 access to EPCS device without using HAL drivers
111696: 06/11/08: Dolphin: Re: Nios2 access to EPCS device without using HAL drivers
111705: 06/11/08: Mark: Re: Nios2 access to EPCS device without using HAL drivers
111775: 06/11/10: Ben Twijnstra: Re: Nios2 access to EPCS device without using HAL drivers
111697: 06/11/08: shaz.pecobian@gmail.com: floating point arithemetic on fpga
111698: 06/11/08: Ray Andraka: Re: floating point arithemetic on fpga
111804: 06/11/10: Ray Andraka: Re: floating point arithemetic on fpga
111718: 06/11/09: Mark McDougall: Re: floating point arithemetic on fpga
111785: 06/11/09: shaz.pecobian@gmail.com: Re: floating point arithemetic on fpga
111699: 06/11/08: oopere: Non deterministic behaviour in quartus II ?
111700: 06/11/08: Will Dean: Re: Non deterministic behaviour in quartus II ?
111702: 06/11/08: oopere: Re: Non deterministic behaviour in quartus II ?
111719: 06/11/09: Mark McDougall: Re: Non deterministic behaviour in quartus II ?
111737: 06/11/09: Will Dean: Re: Non deterministic behaviour in quartus II ?
111779: 06/11/10: Mark McDougall: Re: Non deterministic behaviour in quartus II ?
111780: 06/11/10: Mark McDougall: Re: Non deterministic behaviour in quartus II ?
111724: 06/11/08: Paul Leventis: Re: Non deterministic behaviour in quartus II ?
111733: 06/11/09: oopere: Re: Non deterministic behaviour in quartus II ?
111734: 06/11/09: oopere: Re: Non deterministic behaviour in quartus II ?
111759: 06/11/09: Paul Leventis: Re: Non deterministic behaviour in quartus II ?
111764: 06/11/09: oopere: Re: Non deterministic behaviour in quartus II ?
111769: 06/11/09: Paul Leventis: Re: Non deterministic behaviour in quartus II ?
111790: 06/11/10: oopere: Re: Non deterministic behaviour in quartus II ?
111811: 06/11/10: alterauser: Re: Non deterministic behaviour in quartus II ?
111820: 06/11/10: Marc Guardiani: Re: Non deterministic behaviour in quartus II ?
111822: 06/11/10: Paul Leventis: Re: Non deterministic behaviour in quartus II ?
111707: 06/11/08: Borked Pseudo Mailed: xilinx spartan timing model
111708: 06/11/08: molecularelectronics@googlegroups.com: can you please help me VHDL coding on CSMA and DCF based project of wireless LAN
111715: 06/11/08: Kryten: Re: can you please help me VHDL coding on CSMA and DCF based project of wireless LAN
111725: 06/11/08: Andrew FPGA: Re: can you please help me VHDL coding on CSMA and DCF based project of wireless LAN
111710: 06/11/08: Brad Smallridge: Xilinx ISE ucf management
111750: 06/11/09: Paul: Re: Xilinx ISE ucf management
111938: 06/11/13: Brad Smallridge: Re: Xilinx ISE ucf management
111760: 06/11/09: Jim Wu: Re: Xilinx ISE ucf management
111960: 06/11/13: Jim Wu: Re: Xilinx ISE ucf management
111711: 06/11/08: Bhanu Chandra: pin name misspelling error!
111797: 06/11/10: Gabor: Re: pin name misspelling error!
111726: 06/11/08: Xesium: Static Power vs. Temperature
111727: 06/11/08: Andrew FPGA: Re: Static Power vs. Temperature
111740: 06/11/09: Xesium: Re: Static Power vs. Temperature
111728: 06/11/09: PLD Hacker: Where can I get a opencore of a fifo with atlantic interface?
111729: 06/11/08: <lingamaneni.naveen@gmail.com>: abel to vhdl converter
111743: 06/11/09: Jonathan Bromley: Re: abel to vhdl converter
113493: 06/12/15: Jim Granville: Re: abel to vhdl converter
111751: 06/11/09: Paul: Re: abel to vhdl converter
111753: 06/11/09: Andy: Re: abel to vhdl converter
111754: 06/11/09: Gabor: Re: abel to vhdl converter
111786: 06/11/09: John Adair: Re: abel to vhdl converter
113474: 06/12/14: <lingamaneni.naveen@gmail.com>: Re: abel to vhdl converter
113512: 06/12/15: <lingamaneni.naveen@gmail.com>: Re: abel to vhdl converter
111732: 06/11/09: Dolphin: access to EPCS pins on Altera device without using the NiosII processor
111739: 06/11/09: Julien Lochen: drive LVDS clocks with a spartan3
111766: 06/11/09: John Adair: Re: drive LVDS clocks with a spartan3
111741: 06/11/09: <rponsard@gmail.com>: PicoBlaze and (leon) grlib CAN2B core / spartan3E starter kit
111744: 06/11/09: jonas: ISE bugs or newbie error?
111745: 06/11/09: Andreas Ehliar: Re: ISE bugs or newbie error?
111746: 06/11/09: maxascent: ZBT Bus
111755: 06/11/09: Gabor: Re: ZBT Bus
111748: 06/11/09: <e8johan@gmail.com>: Microblaze + uClinux issues
111756: 06/11/09: Göran Bilski: Re: Microblaze + uClinux issues
111757: 06/11/09: Göran Bilski: Re: Microblaze + uClinux issues
111796: 06/11/10: <e8johan@gmail.com>: Re: Microblaze + uClinux issues
111758: 06/11/09: Julien Lochen: tri0 GSR = glbl.GSR;
111761: 06/11/09: Jim Wu: Re: tri0 GSR = glbl.GSR;
111854: 06/11/11: motty: Re: tri0 GSR = glbl.GSR;
111763: 06/11/09: Al: bidirectional bus
111765: 06/11/09: Mike Treseler: Re: bidirectional bus
111767: 06/11/09: Mike Treseler: Re: bidirectional bus => mux
111789: 06/11/10: Al: Re: bidirectional bus => mux
111806: 06/11/10: Mike Treseler: Re: bidirectional bus => mux
111926: 06/11/13: <helmut.leonhardt@gmail.com>: Re: bidirectional bus
111770: 06/11/09: Todd Fleming: XUP-V2Pro banking rule problem
111771: 06/11/09: Todd Fleming: Re: XUP-V2Pro banking rule problem
111772: 06/11/09: Todd Fleming: Re: XUP-V2Pro banking rule problem
111773: 06/11/09: John_H: Re: XUP-V2Pro banking rule problem
111778: 06/11/09: John_H: Re: XUP-V2Pro banking rule problem
111776: 06/11/09: Todd Fleming: Re: XUP-V2Pro banking rule problem
111777: 06/11/09: Todd Fleming: Re: XUP-V2Pro banking rule problem
111781: 06/11/09: Todd Fleming: Request to Xilinx
111784: 06/11/09: <kanglc@gmail.com>: Xilinx Partition for EDIF Flow (synthesis synplify)
111805: 06/11/10: Ray Andraka: Re: Xilinx Partition for EDIF Flow (synthesis synplify)
111839: 06/11/11: John_H: Re: Xilinx Partition for EDIF Flow (synthesis synplify)
111876: 06/11/12: Ray Andraka: Re: Xilinx Partition for EDIF Flow (synthesis synplify)
111837: 06/11/10: <kanglc@gmail.com>: Re: Xilinx Partition for EDIF Flow (synthesis synplify)
111874: 06/11/12: <kanglc@gmail.com>: Re: Xilinx Partition for EDIF Flow (synthesis synplify)
111787: 06/11/10: Matthias Alles: add-compare-select
111834: 06/11/10: Sylvain Munaut: Re: add-compare-select
154937: 13/02/23: <fabtn2012@gmail.com>: Re: add-compare-select
154938: 13/02/24: Andy Bartlett: Re: add-compare-select
154943: 13/02/25: glen herrmannsfeldt: Re: add-compare-select
154941: 13/02/25: Tim Wescott: Re: add-compare-select
154944: 13/02/25: Tim Wescott: Re: add-compare-select
111792: 06/11/10: antonio bergnoli: shaping aynchronous signal
111793: 06/11/10: <stephen.horsford@gmail.com>: Code for Verilog 8bit * 8bit pipelined multiplier
111795: 06/11/10: hikmetkoca: Re: Code for Verilog 8bit * 8bit pipelined multiplier
111825: 06/11/10: Frank Buss: Re: Code for Verilog 8bit * 8bit pipelined multiplier
111794: 06/11/10: hikmetkoca: C3188A - 1/3"Digital Output Colour Camera Module
111814: 06/11/10: Antti: Re: C3188A - 1/3"Digital Output Colour Camera Module
111824: 06/11/10: hikmetkoca: Re: C3188A - 1/3"Digital Output Colour Camera Module
111826: 06/11/10: Antti: Re: C3188A - 1/3"Digital Output Colour Camera Module
111799: 06/11/10: Anonymous: Why 64-bit PLB?
111801: 06/11/10: Ben Jones: Re: Why 64-bit PLB?
111802: 06/11/10: Anonymous: Re: Why 64-bit PLB?
111810: 06/11/10: Anonymous: Re: Why 64-bit PLB?
111821: 06/11/10: Siva Velusamy: Re: Why 64-bit PLB?
111970: 06/11/13: Jeff Cunningham: Re: Why 64-bit PLB?
112013: 06/11/14: Anonymous: Re: Why 64-bit PLB?
112223: 06/11/17: Trevor Coolidge: Re: Why 64-bit PLB?
111807: 06/11/10: Alan Nishioka: Re: Why 64-bit PLB?
111812: 06/11/10: Antti: Re: Why 64-bit PLB?
111813: 06/11/10: Alan Nishioka: Re: Why 64-bit PLB?
111800: 06/11/10: kypilop: Over power consumption of APA1000.... What's the problem??
111803: 06/11/10: Guru: opb_ddr
111965: 06/11/13: funkrhythm: Re: opb_ddr
111808: 06/11/10: Antti: Stratix-III announced
111818: 06/11/10: Thomas Entner: Re: Stratix-III announced
111827: 06/11/11: Jim Granville: Re: Stratix-III announced
111828: 06/11/10: Thomas Entner: Re: Stratix-III announced
111842: 06/11/11: Ben Twijnstra: Re: Stratix-III announced
111844: 06/11/11: Thomas Entner: Re: Stratix-III announced
111819: 06/11/10: Antti: Re: Stratix-III announced
111847: 06/11/11: unknown@aol.com: Re: Stratix-III announced
111864: 06/11/12: Jim Granville: Re: Stratix-III announced
111909: 06/11/13: <lb.edc@telenet.be>: Re: Stratix-III announced
111911: 06/11/13: Will Dean: Re: Stratix-III announced
111912: 06/11/13: Jim Granville: Re: Stratix-III announced
111913: 06/11/13: Jim Granville: Re: Stratix-III announced
111915: 06/11/13: Jim Granville: Re: Stratix-III announced
111865: 06/11/11: Antti: Re: Stratix-III announced
111910: 06/11/13: Antti: Re: Stratix-III announced
111963: 06/11/13: <rickystickyrick@hotmail.com>: Re: Stratix-III announced
111982: 06/11/14: Antti: Re: Stratix-III announced
111848: 06/11/11: Paul Leventis: Re: Stratix-III announced
112189: 06/11/17: Derek Simmons: Re: Stratix-III announced
111809: 06/11/10: Arash: I look for a wideband SERDES chip
111815: 06/11/10: John_H: Re: I look for a wideband SERDES chip
111860: 06/11/11: John_H: Re: I look for a wideband SERDES chip
111841: 06/11/10: Arash: Re: I look for a wideband SERDES chip
111863: 06/11/11: Arash: Re: I look for a wideband SERDES chip
111947: 06/11/13: <already5chosen@yahoo.com>: Re: I look for a wideband SERDES chip
111816: 06/11/10: <ian.peikon@gmail.com>: Area Constraints in Xilinx
111817: 06/11/10: Antti: Re: Area Constraints in Xilinx
111823: 06/11/10: John Adair: Re: Area Constraints in Xilinx
111830: 06/11/10: Matthew Hicks: Re: Area Constraints in Xilinx
111867: 06/11/11: Matthew Hicks: Re: Area Constraints in Xilinx
111843: 06/11/10: <ian.peikon@gmail.com>: Re: Area Constraints in Xilinx
111856: 06/11/11: RobJ: Re: Area Constraints in Xilinx
111866: 06/11/11: <ian.peikon@gmail.com>: Re: Area Constraints in Xilinx
111891: 06/11/12: Josep Duran: Re: Area Constraints in Xilinx
111829: 06/11/10: Frank Buss: using FPGAs for synthesizing?
111838: 06/11/10: Paul Leventis: Re: using FPGAs for synthesizing?
111859: 06/11/11: JJ: Re: using FPGAs for synthesizing?
111833: 06/11/10: Andy: Re: bidirectional bus => mux
111835: 06/11/10: Dennis Ruffer: Quartus download problem?
111836: 06/11/10: Davy: "|->" implicate and sequence in SVA?
111845: 06/11/11: Jonathan Bromley: Re: "|->" implicate and sequence in SVA?
111904: 06/11/12: Davy: Re: "|->" implicate and sequence in SVA?
113154: 06/12/06: Shenli: Re: "|->" implicate and sequence in SVA?
111840: 06/11/10: Alan Nishioka: Xilinx Chipscope and EDK
111862: 06/11/11: motty: Re: Xilinx Chipscope and EDK
111849: 06/11/11: Antti Lukats: MPMC2 with Virtex-5
111850: 06/11/11: vasile: replacement for Altera EPCS64
111851: 06/11/11: <jonas@mit.edu>: Virtex-5 Webpack?
111852: 06/11/11: Frank Buss: Re: Virtex-5 Webpack?
111853: 06/11/11: Slurp: Re: Virtex-5 Webpack?
111857: 06/11/11: Antti Lukats: Re: Virtex-5 Webpack?
111858: 06/11/11: <jonas@mit.edu>: Re: Virtex-5 Webpack?
111861: 06/11/11: John_H: Re: Virtex-5 Webpack?
111939: 06/11/13: Paul: Re: Virtex-5 Webpack?
113799: 06/12/22: <bkelly@altera.com>: Re: Virtex-5 Webpack?
113803: 06/12/22: Austin: Re: Virtex-5 Webpack?
113806: 06/12/23: Jim Granville: Re: Virtex-5 Webpack?
113808: 06/12/22: Austin: Re: Virtex-5 Webpack?
113809: 06/12/23: Jim Granville: Re: Virtex-5 Webpack?
113810: 06/12/22: Austin: Re: Virtex-5 Webpack?
113821: 06/12/23: Antti Lukats: Re: Virtex-5 Webpack?
113815: 06/12/22: Tommy Thorn: Re: Virtex-5 Webpack?
111855: 06/11/11: motty: EDK post 7.1 Opinions
111868: 06/11/11: fath: SDRAM of Spartan 3E
111871: 06/11/12: Frank Buss: Re: SDRAM of Spartan 3E
111869: 06/11/12: firebird: SPI module in FPGA
111872: 06/11/12: Eli Bendersky: Re: SPI module in FPGA
111890: 06/11/12: Ben Jackson: Re: SPI module in FPGA
111899: 06/11/13: Mark McDougall: Re: SPI module in FPGA
111897: 06/11/12: firebird: Re: SPI module in FPGA
111900: 06/11/12: alterauser: Re: SPI module in FPGA
111954: 06/11/13: Paul: Re: SPI module in FPGA
111870: 06/11/12: Thang Nguyen: EDK : path set
111884: 06/11/12: Thang Nguyen: Re: EDK : path set
111873: 06/11/12: Borge: Power-on reset
111875: 06/11/12: Ray Andraka: Re: Power-on reset
111886: 06/11/12: John_H: Re: Power-on reset
111898: 06/11/12: Ray Andraka: Re: Power-on reset
111905: 06/11/13: John_H: Re: Power-on reset
111887: 06/11/12: Slurp: Re: Power-on reset
112069: 06/11/15: PeteS: Re: Power-on reset
111885: 06/11/12: Borge: Re: Power-on reset
111888: 06/11/12: Borge: Re: Power-on reset
111877: 06/11/12: pete o.: Pad to Setup, Clock to Pad
111881: 06/11/12: KJ: Re: Pad to Setup, Clock to Pad
111902: 06/11/13: KJ: Re: Pad to Setup, Clock to Pad
111892: 06/11/12: Josep Duran: Re: Pad to Setup, Clock to Pad
111919: 06/11/13: Josep Duran: Re: Pad to Setup, Clock to Pad
111930: 06/11/13: <already5chosen@yahoo.com>: Re: Pad to Setup, Clock to Pad
111934: 06/11/13: <already5chosen@yahoo.com>: Re: Pad to Setup, Clock to Pad
111878: 06/11/12: pete o.: Pad to Setup, Clock to Pad
111879: 06/11/12: linnix: Xilinx XC9500 Jtag instructions?
111880: 06/11/12: Uwe Bonnes: Re: Xilinx XC9500 Jtag instructions?
111895: 06/11/12: Uwe Bonnes: Re: Xilinx XC9500 Jtag instructions?
111889: 06/11/12: linnix: Re: Xilinx XC9500 Jtag instructions?
111903: 06/11/12: linnix: Re: Xilinx XC9500 Jtag instructions?
111882: 06/11/12: <already5chosen@yahoo.com>: SOPC builder/Nios2: booting from custom NV-RAM
111883: 06/11/12: <zwsdotcom@gmail.com>: Xilinx USB cable - can't install driver
111918: 06/11/13: c d saunter: Re: Xilinx USB cable - can't install driver
111953: 06/11/13: uvbaz: Re: Xilinx USB cable - can't install driver
111956: 06/11/13: Stephan Flock: Re: Xilinx USB cable - can't install driver
111893: 06/11/12: fl: Question about Maxplus 2?
111896: 06/11/12: Ben Twijnstra: Re: Question about Maxplus 2?
111894: 06/11/12: Manny: Xilinx platform cable USB
111961: 06/11/13: Sean Durkin: Re: Xilinx platform cable USB
111994: 06/11/14: Manny: Re: Xilinx platform cable USB
112003: 06/11/14: Alan Nishioka: Re: Xilinx platform cable USB
111901: 06/11/12: fl: Question about adder structure
111906: 06/11/13: backhus: Re: Question about adder structure
111907: 06/11/13: zyan: Virtex-4 : OCM
111955: 06/11/13: Anonymous: Re: Virtex-4 : OCM
111969: 06/11/13: zyan: Re: Virtex-4 : OCM
111908: 06/11/13: zyan: MPMC2: MPMC2 with DDR2 SDRAM
111916: 06/11/13: Antti: Re: MPMC2: MPMC2 with DDR2 SDRAM
111957: 06/11/13: Siva Velusamy: Re: MPMC2: MPMC2 with DDR2 SDRAM
112012: 06/11/14: Siva Velusamy: Re: MPMC2: MPMC2 with DDR2 SDRAM
112765: 06/11/29: John Williams: Re: MPMC2: MPMC2 with DDR2 SDRAM
112772: 06/11/28: zyan: Re: MPMC2: MPMC2 with DDR2 SDRAM
112842: 06/11/30: John Williams: Re: MPMC2: MPMC2 with DDR2 SDRAM
112850: 06/11/29: Chris Case: Re: MPMC2: MPMC2 with DDR2 SDRAM
112907: 06/12/01: John Williams: Re: MPMC2: MPMC2 with DDR2 SDRAM
113400: 06/12/13: John Williams: Re: MPMC2: MPMC2 with DDR2 SDRAM
112854: 06/11/30: Antti Lukats: Re: MPMC2: MPMC2 with DDR2 SDRAM
111958: 06/11/13: Jim Wu: Re: MPMC2: MPMC2 with DDR2 SDRAM
111976: 06/11/13: Antti: Re: MPMC2: MPMC2 with DDR2 SDRAM
111979: 06/11/14: Guru: Re: MPMC2: MPMC2 with DDR2 SDRAM
112781: 06/11/29: Antti: Re: MPMC2: MPMC2 with DDR2 SDRAM
112916: 06/12/01: Antti: Re: MPMC2: MPMC2 with DDR2 SDRAM
112946: 06/12/01: Erik Widding: Re: MPMC2: MPMC2 with DDR2 SDRAM
112949: 06/12/02: Antti: Re: MPMC2: MPMC2 with DDR2 SDRAM
111917: 06/11/13: ekavirsrikanth@gmail.com: regarding changing serial data out to LVDS form
111922: 06/11/13: KJ: Re: regarding changing serial data out to LVDS form
111935: 06/11/13: Brad Smallridge: Re: regarding changing serial data out to LVDS form
111941: 06/11/13: Brad Smallridge: Re: regarding changing serial data out to LVDS form
111942: 06/11/13: Brad Smallridge: Re: regarding changing serial data out to LVDS form
111920: 06/11/13: uvbaz: How to control the running of NC-Sim and Xilinx ISE under Unix?
111921: 06/11/13: Jon Beniston: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
111924: 06/11/13: uvbaz: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
111959: 06/11/13: Jim Wu: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
111989: 06/11/14: uvbaz: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
112020: 06/11/14: <sharp@cadence.com>: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
112033: 06/11/15: uvbaz: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
111923: 06/11/13: <ruben.gue@gmail.com>: simulating two-dimensional array in vhdl
111927: 06/11/13: Mike Treseler: Re: simulating two-dimensional array in vhdl
111928: 06/11/13: <ruben.gue@gmail.com>: Re: simulating two-dimensional array in vhdl
111929: 06/11/13: Vivian Bessler: FPGA Debug Tool
111931: 06/11/13: Antti Lukats: Re: FPGA Debug Tool
111940: 06/11/13: Vivian Bessler: Re: FPGA Debug Tool
111952: 06/11/13: Vivian Bessler: Re: FPGA Debug Tool
111937: 06/11/13: AMONTEC: Re: FPGA Debug Tool
111943: 06/11/13: Vivian Bessler: Re: FPGA Debug Tool
111945: 06/11/13: <darren.redmond@gmail.com>: Re: FPGA Debug Tool
111949: 06/11/13: Will Dean: Re: FPGA Debug Tool
111946: 06/11/13: Antti: Re: FPGA Debug Tool
111932: 06/11/13: <darren.redmond@gmail.com>: Re: FPGA Debug Tool
111936: 06/11/13: Will Dean: Re: FPGA Debug Tool
111933: 06/11/13: <robquigley@gmail.com>: Re: FPGA Debug Tool
111944: 06/11/13: Brad Smallridge: Seemingly random delays on Xilinx OSERDES
112100: 06/11/16: Tom: Re: Seemingly random delays on Xilinx OSERDES
112195: 06/11/17: Brad Smallridge: Re: Seemingly random delays on Xilinx OSERDES
111948: 06/11/13: Antti: Re: FPGA Debug Tool
111950: 06/11/13: Antti: IEEE 1149.6 support in Virtex-5
111951: 06/11/13: uvbaz: Compile error by Cadence NC-Sim
111977: 06/11/14: uvbaz: Re: Compile error by Cadence NC-Sim
111985: 06/11/14: Mike Treseler: Re: Compile error by Cadence NC-Sim
112001: 06/11/14: Mike Treseler: Re: Compile error by Cadence NC-Sim
111990: 06/11/14: uvbaz: Re: Compile error by Cadence NC-Sim
112019: 06/11/14: <sharp@cadence.com>: Re: Compile error by Cadence NC-Sim
111962: 06/11/13: logjam: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
111964: 06/11/13: <rponsard@gmail.com>: Re: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
111967: 06/11/14: Mark McDougall: Re: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
111993: 06/11/14: logjam: Re: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
111971: 06/11/13: <Sudhir.Singh@email.com>: Nested Generate Statement in VHDL
111972: 06/11/14: Mark McDougall: Re: Nested Generate Statement in VHDL
111978: 06/11/14: Hans: Re: Nested Generate Statement in VHDL
111987: 06/11/14: Jim Lewis: Re: Nested Generate Statement in VHDL
111973: 06/11/13: <Sudhir.Singh@email.com>: Re: Nested Generate Statement in VHDL
111974: 06/11/13: Jhlw: Running an application from external memory in Xilinx
111975: 06/11/13: <kunals.spam.account@gmail.com>: Xilinx ML310 programming failure
111981: 06/11/14: nana: xupv2p
112021: 06/11/14: vbcity: Re: xupv2p
112024: 06/11/14: Matthew Hicks: Re: xupv2p
112027: 06/11/15: Symon: Re: xupv2p
112050: 06/11/15: Ray Andraka: Re: xupv2p
112053: 06/11/15: Symon: Re: xupv2p
112056: 06/11/15: Ray Andraka: Re: xupv2p
112051: 06/11/15: rickman: Re: xupv2p
112061: 06/11/15: rickman: Re: xupv2p
111983: 06/11/14: fl: problem about license of Modelsim in Altera quartus webpack
111984: 06/11/14: fl: Re: problem about license of Modelsim in Altera quartus webpack
111986: 06/11/14: OL: Re: problem about license of Modelsim in Altera quartus webpack
111988: 06/11/14: fl: Re: problem about license of Modelsim in Altera quartus webpack
111991: 06/11/14: Student (confused): FFT in VHDL (or Verilog) Tutorial
112222: 06/11/17: =?iso-8859-1?B?VXRrdSDWemNhbg==?=: Re: FFT in VHDL (or Verilog) Tutorial
112387: 06/11/21: Andreas Schallenberg: Re: FFT in VHDL (or Verilog) Tutorial
111992: 06/11/14: uvbaz: xilinx_device_details.xml <= which program create it?
111995: 06/11/14: fl: Why are there ModelSimAltera warning
112004: 06/11/14: Mike Treseler: Re: Why are there ModelSimAltera warning
111996: 06/11/14: rasic: sending data across a 32 bit bus
111998: 06/11/14: PeteS: Re: sending data across a 32 bit bus
112028: 06/11/14: <helmut.leonhardt@gmail.com>: Re: sending data across a 32 bit bus
111997: 06/11/14: Thomas Reinemann: Influence of temperature and manufacturing to propagation delay
111999: 06/11/14: PeteS: Re: Influence of temperature and manufacturing to propagation delay
112000: 06/11/14: John_H: Re: Influence of temperature and manufacturing to propagation delay
112005: 06/11/14: John Adair: Re: Influence of temperature and manufacturing to propagation delay
112006: 06/11/14: Austin Lesea: Re: Influence of temperature and manufacturing to propagation delay
112007: 06/11/14: PeteS: Re: Influence of temperature and manufacturing to propagation delay
112009: 06/11/14: PeteS: In defence of Austin and Xilinx
112014: 06/11/14: John_H: Re: In defence of Austin and Xilinx
112063: 06/11/15: PeteS: Re: In defence of Austin and Xilinx
112097: 06/11/16: Thomas Reinemann: Re: In defence of Austin and Xilinx
112106: 06/11/16: Austin Lesea: System Jitter calculation by hand
112120: 06/11/16: PeteS: Re: In defence of Austin and Xilinx
112010: 06/11/14: Austin Lesea: Re: Influence of temperature and manufacturing to propagation delay
112011: 06/11/14: PeteS: Re: Influence of temperature and manufacturing to propagation delay
112123: 06/11/16: PeteS: A minor addendum
112016: 06/11/15: Jeremy Stringer: Re: Influence of temperature and manufacturing to propagation delay
112022: 06/11/14: Ray Andraka: Re: Influence of temperature and manufacturing to propagation delay
112044: 06/11/15: John_H: Re: Influence of temperature and manufacturing to propagation delay
112049: 06/11/15: Austin Lesea: Re: Influence of temperature and manufacturing to propagation delay
112064: 06/11/15: PeteS: Re: Influence of temperature and manufacturing to propagation delay
112122: 06/11/16: PeteS: Re: Influence of temperature and manufacturing to propagation delay
112042: 06/11/15: Andy: Re: Influence of temperature and manufacturing to propagation delay
112078: 06/11/15: Andy: Re: Influence of temperature and manufacturing to propagation delay
112101: 06/11/16: Andy: Re: Influence of temperature and manufacturing to propagation delay
112104: 06/11/16: John McCaskill: Re: In defence of Austin and Xilinx
112232: 06/11/18: Trevor Coolidge: Re: Influence of temperature and manufacturing to propagation delay
112002: 06/11/14: MM: Aurora IP core vs. RocketIO wizard
112168: 06/11/17: kilgor: Re: Aurora IP core vs. RocketIO wizard
112008: 06/11/14: Patrick Dubois: Pipelining can reduce the slice usage
112025: 06/11/14: Daniel S.: Re: Pipelining can reduce the slice usage
112118: 06/11/16: Patrick Dubois: Re: Pipelining can reduce the slice usage
112015: 06/11/14: Anonymous: DSP Library for PPC405?
112017: 06/11/14: Thang Nguyen: EDK: command not found
112018: 06/11/14: Thang Nguyen: Software Compile : gcc command not found
112036: 06/11/15: Jon Beniston: Re: Software Compile : gcc command not found
112023: 06/11/14: awa: Programming model on FPGA
112030: 06/11/15: backhus: Re: Programming model on FPGA
112037: 06/11/15: awa: Re: Programming model on FPGA
112026: 06/11/14: Murali: Microblaze store
112029: 06/11/15: Göran Bilski: Re: Microblaze store
112058: 06/11/15: mk: Re: Microblaze store
112088: 06/11/15: Murali: Re: Microblaze store
112089: 06/11/16: mk: Re: Microblaze store
112093: 06/11/16: Göran Bilski: Re: Microblaze store
112112: 06/11/16: Muralidaran Vijayaraghavan: Re: Microblaze store
112031: 06/11/15: <jetmarc@hotmail.com>: Share BRAM for data and instruction OCM?
112032: 06/11/15: <olive_dominguez@yahoo.fr>: Impedance I/O SPARTAN3 board
112034: 06/11/15: Symon: Re: Impedance I/O SPARTAN3 board
112038: 06/11/15: PeteS: Re: Impedance I/O SPARTAN3 board
112048: 06/11/15: Symon: Re: Impedance I/O SPARTAN3 board
112067: 06/11/15: PeteS: Re: Impedance I/O SPARTAN3 board
112045: 06/11/15: <olive_dominguez@yahoo.fr>: Re: Impedance I/O SPARTAN3 board
112035: 06/11/15: gen_vlsi: How to configure Block RAMs with constant values
112039: 06/11/15: gen_vlsi: Re: How to configure Block RAMs with constant values
112043: 06/11/15: John_H: Re: How to configure Block RAMs with constant values
112046: 06/11/15: gen_vlsi: Re: How to configure Block RAMs with constant values
112040: 06/11/15: yy: Synopsys VCS for Windows
112041: 06/11/15: <tclin1998@gmail.com>: VCD (value change dump) files
112052: 06/11/15: Andreas Ehliar: Re: VCD (value change dump) files
112054: 06/11/15: <zwsdotcom@gmail.com>: Old Spartan-II, worth prototyping?
112055: 06/11/15: John_H: Re: Old Spartan-II, worth prototyping?
112074: 06/11/15: james: Re: Old Spartan-II, worth prototyping?
112105: 06/11/16: Austin Lesea: Re: Old Spartan-II, worth prototyping?
112065: 06/11/15: <zwsdotcom@gmail.com>: Re: Old Spartan-II, worth prototyping?
112095: 06/11/16: John Adair: Re: Old Spartan-II, worth prototyping?
112129: 06/11/16: Leon: Re: Old Spartan-II, worth prototyping?
112057: 06/11/15: Jhlw: Getting Xilinx DMA SG working with peripheral
112059: 06/11/15: Gabor: XCF02S + Spartan 2e JTAG config problems
112117: 06/11/16: Antti: Re: XCF02S + Spartan 2e JTAG config problems
112139: 06/11/16: Gabor: Re: XCF02S + Spartan 2e JTAG config problems
112148: 06/11/17: Antti: Re: XCF02S + Spartan 2e JTAG config problems
112060: 06/11/15: Brad Smallridge: Xilinx 2 DCMs with delay on lock
112066: 06/11/15: Ray Andraka: Re: Xilinx 2 DCMs with delay on lock
112090: 06/11/15: Brad Smallridge: Re: Xilinx 2 DCMs with delay on lock
112075: 06/11/15: VC: Re: Xilinx 2 DCMs with delay on lock
112062: 06/11/15: logjam: 8080 FSGA model in an FPGA
112068: 06/11/15: PeteS: Re: 8080 FSGA model in an FPGA
112130: 06/11/16: Jon Elson: Re: 8080 FSGA model in an FPGA
112204: 06/11/17: PeteS: Re: 8080 FSGA model in an FPGA
112340: 06/11/20: Jon Elson: Re: 8080 FSGA model in an FPGA
112345: 06/11/20: Ray Andraka: Re: 8080 FSGA model in an FPGA
112399: 06/11/21: Frank Buss: Re: 8080 FSGA model in an FPGA
112433: 06/11/22: David R Brooks: Re: 8080 FSGA model in an FPGA
112434: 06/11/22: Symon: Re: 8080 FSGA model in an FPGA
112450: 06/11/22: scott moore: Re: 8080 FSGA model in an FPGA
112452: 06/11/22: scott moore: Re: 8080 FSGA model in an FPGA
112071: 06/11/15: Jon Elson: Re: 8080 FSGA model in an FPGA
112091: 06/11/15: scott moore: Re: 8080 FSGA model in an FPGA
112131: 06/11/16: Jon Elson: Re: 8080 FSGA model in an FPGA
112076: 06/11/16: Jim Granville: Re: 8080 FSGA model in an FPGA
112086: 06/11/16: Tim: Re: 8080 FSGA model in an FPGA
112087: 06/11/16: Jim Granville: Re: 8080 FSGA model in an FPGA
112096: 06/11/16: David R Brooks: Re: 8080 FSGA model in an FPGA
112107: 06/11/16: Tim: Re: 8080 FSGA model in an FPGA
112108: 06/11/16: Gerhard Hoffmann: Re: 8080 FSGA model in an FPGA
112082: 06/11/15: logjam: Re: 8080 FSGA model in an FPGA
112083: 06/11/15: logjam: Re: 8080 FSGA model in an FPGA
112085: 06/11/15: JJ: Re: 8080 FSGA model in an FPGA
112102: 06/11/16: John Adair: Re: 8080 FSGA model in an FPGA
112103: 06/11/16: rickman: Re: 8080 FSGA model in an FPGA
112213: 06/11/17: JJ: Re: 8080 FSGA model in an FPGA
112359: 06/11/21: Grant Stockly: Re: 8080 FSGA model in an FPGA
112369: 06/11/21: rickman: Re: 8080 FSGA model in an FPGA
112397: 06/11/21: Grant Stockly: Re: 8080 FSGA model in an FPGA
112406: 06/11/21: rickman: Re: 8080 FSGA model in an FPGA
112419: 06/11/21: Grant Stockly: Re: 8080 FSGA model in an FPGA
112426: 06/11/21: rickman: Re: 8080 FSGA model in an FPGA
112461: 06/11/22: Grant Stockly: Re: 8080 FSGA model in an FPGA
112462: 06/11/22: rickman: Re: 8080 FSGA model in an FPGA
112467: 06/11/22: Grant Stockly: Re: 8080 FSGA model in an FPGA
112070: 06/11/15: Frank Buss: how to filter glitches and mutliple transitions?
112072: 06/11/15: PeteS: Re: how to filter glitches and mutliple transitions?
112073: 06/11/15: PeteS: Re: how to filter glitches and mutliple transitions?
112126: 06/11/16: PeteS: Re: how to filter glitches and mutliple transitions?
112084: 06/11/16: Frank Buss: Re: how to filter glitches and mutliple transitions?
112127: 06/11/16: Frank Buss: Re: how to filter glitches and mutliple transitions?
112128: 06/11/16: PeteS: Re: how to filter glitches and mutliple transitions?
112077: 06/11/16: Jim Granville: Re: how to filter glitches and mutliple transitions?
112081: 06/11/15: John McGrath: Re: how to filter glitches and mutliple transitions?
112140: 06/11/16: John McGrath: Re: how to filter glitches and mutliple transitions?
112079: 06/11/15: markus: Problems with Opencores' I2C "READ" function
112099: 06/11/16: Mark McDougall: Re: Problems with Opencores' I2C "READ" function
112125: 06/11/16: markus: Re: Problems with Opencores' I2C "READ" function
112080: 06/11/15: terabits: USB and AHB
112094: 06/11/16: bm: Re: USB and AHB
112110: 06/11/16: terabits: Re: USB and AHB
112115: 06/11/16: bm: Re: USB and AHB
112119: 06/11/16: terabits: Re: USB and AHB
112183: 06/11/17: terabits: Re: USB and AHB
112092: 06/11/15: andrew browning: ise 7.1
112098: 06/11/16: Peter Mendham: Compiling Linux Kernel for ML405
112133: 06/11/16: funkrhythm: Re: Compiling Linux Kernel for ML405
112155: 06/11/17: Peter Mendham: Re: Compiling Linux Kernel for ML405
112372: 06/11/21: Peter Mendham: Re: Compiling Linux Kernel for ML405
112203: 06/11/17: funkrhythm: Re: Compiling Linux Kernel for ML405
112109: 06/11/16: <florent.peyrard@gmail.com>: use boundary scan in spartan-3
112111: 06/11/16: Antti Lukats: Re: use boundary scan in spartan-3
112113: 06/11/16: <florent.peyrard@gmail.com>: Re: use boundary scan in spartan-3
112114: 06/11/16: <florent.peyrard@gmail.com>: Re: use boundary scan in spartan-3
112147: 06/11/17: colin: Re: use boundary scan in spartan-3
112156: 06/11/17: AMONTEC: Re: use boundary scan in spartan-3
112158: 06/11/17: <florent.peyrard@gmail.com>: Re: use boundary scan in spartan-3
112170: 06/11/17: colin: Re: use boundary scan in spartan-3
112116: 06/11/16: <jonas@mit.edu>: V-5 power saving ...how?
112121: 06/11/16: Austin Lesea: Re: V-5 power saving ...how?
112124: 06/11/16: <olson_ord@yahoo.it>: Synthesis size of Circuits?
112146: 06/11/17: Andreas Ehliar: Re: Synthesis size of Circuits?
112308: 06/11/20: Andreas Ehliar: Re: Synthesis size of Circuits?
112149: 06/11/17: Thomas Stanka: Re: Synthesis size of Circuits?
112214: 06/11/17: <olson_ord@yahoo.it>: Re: Synthesis size of Circuits?
112215: 06/11/17: <olson_ord@yahoo.it>: Re: Synthesis size of Circuits?
112258: 06/11/18: Thomas Stanka: Re: Synthesis size of Circuits?
112395: 06/11/21: <olson_ord@yahoo.it>: Re: Synthesis size of Circuits?
112396: 06/11/21: <olson_ord@yahoo.it>: Re: Synthesis size of Circuits?
112132: 06/11/16: terabits: Maximum Operating Frequency
112188: 06/11/17: Mike Lewis: Re: Maximum Operating Frequency
112134: 06/11/16: learnfpga: Warnings in Xilinx 8.2i
112138: 06/11/17: Jim Granville: Re: Warnings in Xilinx 8.2i
112144: 06/11/17: Antti Lukats: Re: Warnings in Xilinx 8.2i
112176: 06/11/17: learnfpga: Re: Warnings in Xilinx 8.2i
112178: 06/11/17: Antti: Re: Warnings in Xilinx 8.2i
112181: 06/11/17: rickman: Re: Warnings in Xilinx 8.2i
112186: 06/11/17: Antti: Re: Warnings in Xilinx 8.2i
112190: 06/11/17: rickman: Re: Warnings in Xilinx 8.2i
112193: 06/11/17: Antti: Re: Warnings in Xilinx 8.2i
112196: 06/11/17: rickman: Re: Warnings in Xilinx 8.2i
112198: 06/11/17: Antti: Re: Warnings in Xilinx 8.2i
112135: 06/11/16: nfirtaps: Validity of data on rising edge of clock
112136: 06/11/16: KJ: Re: Validity of data on rising edge of clock
112137: 06/11/16: Mike Treseler: Re: Validity of data on rising edge of clock
112171: 06/11/17: Symon: Re: Validity of data on rising edge of clock
112141: 06/11/16: Grant Stockly: Spartan 3/3E to Standard TTL/Low power devices
112142: 06/11/17: John_H: Re: Spartan 3/3E to Standard TTL/Low power devices
112152: 06/11/17: Grant Stockly: Re: Spartan 3/3E to Standard TTL/Low power devices
112162: 06/11/17: Uwe Bonnes: Re: Spartan 3/3E to Standard TTL/Low power devices
112143: 06/11/16: langjr15@uwgb.edu: xsa-200 building a Mp3 player
112145: 06/11/16: <vsrpkumar@rediffmail.com>: Hpw to remove combinational loops in quartus s/w
112157: 06/11/17: KJ: Re: Hpw to remove combinational loops in quartus s/w
112150: 06/11/17: uvbaz: How to use "ON NBC 12429" as clock resource of Virtex-4
112172: 06/11/17: Symon: Re: How to use "ON NBC 12429" as clock resource of Virtex-4
112151: 06/11/17: Antti: combinatorical divide by 2 in FPGA
112154: 06/11/17: Jim Granville: Re: combinatorical divide by 2 in FPGA
112160: 06/11/17: Uwe Bonnes: Re: combinatorical divide by 2 in FPGA
112159: 06/11/17: Antti: Re: combinatorical divide by 2 in FPGA
112161: 06/11/17: Antti: Re: combinatorical divide by 2 in FPGA
112163: 06/11/17: Symon: Re: combinatorical divide by 2 in FPGA
112165: 06/11/17: John_H: Re: combinatorical divide by 2 in FPGA
112207: 06/11/17: Ray Andraka: Re: combinatorical divide by 2 in FPGA
112273: 06/11/19: Antti Lukats: Re: combinatorical divide by 2 in FPGA
112166: 06/11/17: Tim: Re: combinatorical divide by 2 in FPGA
112167: 06/11/17: Antti: Re: combinatorical divide by 2 in FPGA
112169: 06/11/17: JustJohn: Re: combinatorical divide by 2 in FPGA
112174: 06/11/17: Antti: Re: combinatorical divide by 2 in FPGA
112209: 06/11/17: Antti: Re: combinatorical divide by 2 in FPGA
112210: 06/11/17: Antti: Re: combinatorical divide by 2 in FPGA
112219: 06/11/17: JustJohn: Re: combinatorical divide by 2 in FPGA
112275: 06/11/19: JustJohn: Re: combinatorical divide by 2 in FPGA
112153: 06/11/17: <olive_dominguez@yahoo.fr>: FPGA board
112164: 06/11/17: John_H: Re: FPGA board
112173: 06/11/17: Antti: memory init in Altera bitfiles, (like data2mem) is it possible?
112179: 06/11/17: jbnote: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112180: 06/11/17: Hans: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112194: 06/11/17: Antti: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112197: 06/11/17: <kempaj@yahoo.com>: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112205: 06/11/17: Thomas Entner: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112217: 06/11/18: Jim Granville: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112249: 06/11/18: Dennis Ruffer: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112284: 06/11/19: Dennis Ruffer: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112257: 06/11/19: Jim Granville: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112263: 06/11/19: Jim Granville: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112272: 06/11/19: Antti Lukats: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112274: 06/11/19: Jim Granville: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112218: 06/11/18: Thomas Entner: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112199: 06/11/17: Antti: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112208: 06/11/17: Antti: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112237: 06/11/18: Antti: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112239: 06/11/18: jbnote: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112240: 06/11/18: Antti: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112250: 06/11/18: Antti: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112252: 06/11/18: <already5chosen@yahoo.com>: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112254: 06/11/18: Antti: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112256: 06/11/18: <already5chosen@yahoo.com>: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112276: 06/11/19: jbnote: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112280: 06/11/19: jbnote: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112283: 06/11/19: jbnote: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112342: 06/11/20: radarman: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112358: 06/11/21: <already5chosen@yahoo.com>: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112373: 06/11/21: radarman: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112379: 06/11/21: <already5chosen@yahoo.com>: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112381: 06/11/21: <kempaj@yahoo.com>: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112388: 06/11/21: Antti: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112390: 06/11/21: <dkarchmer@gmail.com>: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112392: 06/11/21: Antti: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112401: 06/11/21: <dkarchmer@gmail.com>: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112175: 06/11/17: Gerd: ML405: Board support package
112177: 06/11/17: Al: pulse jitter due to clock
112182: 06/11/17: Austin Lesea: Re: pulse jitter due to clock
112185: 06/11/17: Symon: Re: pulse jitter due to clock
112192: 06/11/17: Austin Lesea: Re: pulse jitter due to clock
112224: 06/11/18: Symon: Re: pulse jitter due to clock
112242: 06/11/18: Austin Lesea: Re: pulse jitter due to clock
112267: 06/11/18: Matthew Hicks: Re: pulse jitter due to clock
112356: 06/11/21: Al: Re: pulse jitter due to clock
112378: 06/11/21: Austin Lesea: Re: pulse jitter due to clock
112383: 06/11/21: Al: Re: pulse jitter due to clock
112187: 06/11/17: nospam: Re: pulse jitter due to clock
112233: 06/11/18: Kolja Sulimma: Re: pulse jitter due to clock
112354: 06/11/21: Al: Re: pulse jitter due to clock
112386: 06/11/21: Kolja Sulimma: Re: pulse jitter due to clock
112357: 06/11/21: Al: Re: pulse jitter due to clock
112384: 06/11/21: Kolja Sulimma: Re: pulse jitter due to clock
112201: 06/11/17: PeteS: Re: pulse jitter due to clock
112234: 06/11/18: Kolja Sulimma: Re: pulse jitter due to clock
112360: 06/11/21: Al: Re: pulse jitter due to clock
112361: 06/11/21: Symon: Re: pulse jitter due to clock
112364: 06/11/21: Al: Re: pulse jitter due to clock
112365: 06/11/21: Symon: Re: pulse jitter due to clock
112367: 06/11/21: Al: Re: pulse jitter due to clock
112368: 06/11/21: Al: Re: pulse jitter due to clock
112371: 06/11/21: Symon: Re: pulse jitter due to clock
112374: 06/11/21: Al: Re: pulse jitter due to clock
112245: 06/11/18: Trevor Coolidge: Re: pulse jitter due to clock
112370: 06/11/21: John_H: Re: pulse jitter due to clock
112375: 06/11/21: Al: Re: pulse jitter due to clock
112382: 06/11/21: John_H: Re: pulse jitter due to clock
112389: 06/11/21: Al: Re: pulse jitter due to clock
112565: 06/11/24: Daniel S.: Re: pulse jitter due to clock
112184: 06/11/17: ZHI: How could the 'Serial write time out' happen
112277: 06/11/19: Andrew Holme: Re: How could the 'Serial write time out' happen
112298: 06/11/19: Andrew Holme: Re: How could the 'Serial write time out' happen
112279: 06/11/19: ZHI: Re: How could the 'Serial write time out' happen
112309: 06/11/20: ZHI: Re: How could the 'Serial write time out' happen
112191: 06/11/17: vasile: PCMCIA interface
112211: 06/11/17: PeteS: Re: PCMCIA interface
112212: 06/11/17: Duane Clark: Re: PCMCIA interface
112216: 06/11/17: John Adair: Re: PCMCIA interface
112422: 06/11/21: Daniel S.: Re: PCMCIA interface
112247: 06/11/18: vasile: Re: PCMCIA interface
112248: 06/11/18: <zwsdotcom@gmail.com>: Re: PCMCIA interface
112278: 06/11/19: John Adair: Re: PCMCIA interface
112200: 06/11/17: Frank Buss: state problems with Quartus II 6
112202: 06/11/17: Subroto Datta: Re: state problems with Quartus II 6
112206: 06/11/17: Frank Buss: Re: state problems with Quartus II 6
112220: 06/11/17: kumar: query in a design
112221: 06/11/17: kumar: Re: query in a design
112231: 06/11/18: Trevor Coolidge: IDELAY Calibration - Virtex 4
112238: 06/11/18: Antti: Re: IDELAY Calibration - Virtex 4
112243: 06/11/18: Trevor Coolidge: Re: IDELAY Calibration - Virtex 4
112301: 06/11/19: Ray Andraka: Re: IDELAY Calibration - Virtex 4
112307: 06/11/19: Antti: Re: IDELAY Calibration - Virtex 4
112236: 06/11/18: jajo: Input setup time & Output valid delay
112244: 06/11/18: Trevor Coolidge: Re: Input setup time & Output valid delay
112241: 06/11/18: jajo: Static Timing Analysis vs Dinamic Timing Analysis
112266: 06/11/18: Matthew Hicks: Re: Static Timing Analysis vs Dinamic Timing Analysis
112246: 06/11/18: Tom: IDELAY setup/hold
112251: 06/11/18: <get2venu@gmail.com>: master support for OPB device
112394: 06/11/21: <mikechin2000@gmail.com>: Re: master support for OPB device
112253: 06/11/18: Antti: EDK 8.2 Block RAM error
112259: 06/11/18: MM: Re: EDK 8.2 Block RAM error
112286: 06/11/19: MM: Re: EDK 8.2 Block RAM error
112403: 06/11/21: MM: Re: EDK 8.2 Block RAM error
112405: 06/11/21: Antti Lukats: Re: EDK 8.2 Block RAM error
112428: 06/11/21: MM: Re: EDK 8.2 Block RAM error
112473: 06/11/22: MM: Re: EDK 8.2 Block RAM error
112758: 06/11/28: MM: Re: EDK 8.2 Block RAM error
112764: 06/11/28: MM: Re: EDK 8.2 Block RAM error
112799: 06/11/29: MM: Re: EDK 8.2 Block RAM error
112897: 06/11/30: MM: Re: EDK 8.2 Block RAM error
112260: 06/11/18: Antti: Re: EDK 8.2 Block RAM error
112391: 06/11/21: Antti: Re: EDK 8.2 Block RAM error
112443: 06/11/22: Antti: Re: EDK 8.2 Block RAM error
112484: 06/11/23: Antti: Re: EDK 8.2 Block RAM error
112782: 06/11/29: Antti: Re: EDK 8.2 Block RAM error
112255: 06/11/18: John Larkin: Re: board - T562.jpg
112261: 06/11/18: PeteS: Re: board - T562.jpg
112262: 06/11/18: PeteS: Re: board - T562.jpg
112264: 06/11/18: John Larkin: Re: board - T562.jpg
112265: 06/11/19: PeteS: Re: board - T562.jpg
112268: 06/11/18: John Larkin: Re: board - T562.jpg
112287: 06/11/19: Trevor Coolidge: Re: board - T562.jpg
112289: 06/11/19: mk: Re: board - T562.jpg
112292: 06/11/20: Jim Granville: Re: board - T562.jpg
112288: 06/11/19: petrus bitbyter: Re: board - T562.jpg
112290: 06/11/19: Jim Thompson: Re: board - T562.jpg
112291: 06/11/19: Genome: Re: board - T562.jpg
112293: 06/11/19: John Larkin: Re: board - T562.jpg
112295: 06/11/19: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: board - T562.jpg
112297: 06/11/19: John Larkin: Re: board - T562.jpg
112323: 06/11/20: Joel Kolstad: Re: board - T562.jpg
112334: 06/11/20: PeteS: Re: board - T562.jpg
112294: 06/11/19: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: board - T562.jpg
112324: 06/11/20: Joel Kolstad: Re: board - T562.jpg
112325: 06/11/20: Joel Kolstad: Re: board - T562.jpg
112329: 06/11/20: John Larkin: Re: board - T562.jpg
112337: 06/11/20: PeteS: Re: board - T562.jpg
112299: 06/11/19: Ray Andraka: Re: board - T562.jpg
112300: 06/11/19: John Larkin: Re: board - T562.jpg
112336: 06/11/20: PeteS: Re: board - T562.jpg
112346: 06/11/20: Ray Andraka: Re: board - T562.jpg
112393: 06/11/21: PeteS: Re: board - T562.jpg
112407: 06/11/21: Ray Andraka: Re: board - T562.jpg
112409: 06/11/21: PeteS: Re: board - T562.jpg
112410: 06/11/21: Ray Andraka: Re: board - T562.jpg
112411: 06/11/21: PeteS: Re: board - T562.jpg
112417: 06/11/21: Ray Andraka: Re: board - T562.jpg
112425: 06/11/21: John Larkin: Re: board - T562.jpg
112431: 06/11/22: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: board - T562.jpg
112465: 06/11/22: PeteS: Re: board - T562.jpg
112470: 06/11/22: Homer J Simpson: Re: board - T562.jpg
112471: 06/11/22: John Fields: Re: board - T562.jpg
112479: 06/11/23: Homer J Simpson: Re: board - T562.jpg
112486: 06/11/23: John Fields: Re: board - T562.jpg
112505: 06/11/23: Homer J Simpson: Re: board - T562.jpg
112508: 06/11/23: John Fields: Re: board - T562.jpg
112511: 06/11/23: Homer J Simpson: Re: board - T562.jpg
112517: 06/11/23: John Fields: Re: board - T562.jpg
112520: 06/11/23: Homer J Simpson: Re: board - T562.jpg
112537: 06/11/24: John Fields: Re: board - T562.jpg
112549: 06/11/24: Homer J Simpson: Re: board - T562.jpg
112557: 06/11/24: John Fields: Re: board - T562.jpg
112562: 06/11/24: Homer J Simpson: Re: board - T562.jpg
112568: 06/11/24: John Fields: Re: board - T562.jpg
112571: 06/11/25: Homer J Simpson: Re: board - T562.jpg
112578: 06/11/25: John Fields: Re: board - T562.jpg
112589: 06/11/25: Homer J Simpson: Re: board - T562.jpg
112591: 06/11/25: John Fields: Re: board - T562.jpg
112596: 06/11/25: Homer J Simpson: Re: board - T562.jpg
112601: 06/11/25: John Fields: Re: board - T562.jpg
112602: 06/11/26: Homer J Simpson: Re: board - T562.jpg
112608: 06/11/26: John Fields: Re: board - T562.jpg
112593: 06/11/25: Jim Thompson: Re: board - T562.jpg
112597: 06/11/25: Homer J Simpson: Re: board - T562.jpg
112600: 06/11/25: Jim Thompson: Re: board - T562.jpg
112628: 06/11/26: Jim Thompson: Re: board - T562.jpg
112674: 06/11/27: Jim Thompson: Re: Was: board - T562.jpg, Now: Switched cap voltage regulator
112595: 06/11/25: Homer J Simpson: Re: board - T562.jpg
112609: 06/11/26: YD: Re: board - T562.jpg
112612: 06/11/26: Homer J Simpson: Re: board - T562.jpg
112702: 06/11/27: rickman: Re: Was: board - T562.jpg, Now: Switched cap voltage regulator
112635: 06/11/26: rickman: Was: board - T562.jpg, Now: Switched cap voltage regulator
112566: 06/11/24: John Fields: Re: board - T562.jpg
112567: 06/11/24: Homer J Simpson: Re: board - T562.jpg
112577: 06/11/25: John Fields: Re: board - T562.jpg
112587: 06/11/25: Homer J Simpson: Re: board - T562.jpg
112592: 06/11/25: John Fields: Re: board - T562.jpg
112594: 06/11/25: Homer J Simpson: Re: board - T562.jpg
112604: 06/11/26: John Fields: Re: board - T562.jpg
112611: 06/11/26: Homer J Simpson: Re: board - T562.jpg
112614: 06/11/26: John Fields: Re: board - T562.jpg
112618: 06/11/26: Homer J Simpson: Re: board - T562.jpg
112620: 06/11/26: John Larkin: Re: board - T562.jpg
112627: 06/11/27: Homer J Simpson: Re: board - T562.jpg
112629: 06/11/26: John Larkin: Re: board - T562.jpg
112630: 06/11/27: Homer J Simpson: Re: board - T562.jpg
112632: 06/11/26: John Larkin: Re: board - T562.jpg
112712: 06/11/28: Homer J Simpson: Re: board - T562.jpg
112715: 06/11/28: YD: Re: board - T562.jpg
112717: 06/11/28: Homer J Simpson: Re: board - T562.jpg
112727: 06/11/28: YD: Re: board - T562.jpg
112714: 06/11/27: YD: Re: board - T562.jpg
112641: 06/11/26: John Larkin: Re: board - T562.jpg
112619: 06/11/26: Jim Thompson: Re: board - T562.jpg
112713: 06/11/27: rickman: Re: board - T562.jpg
112634: 06/11/26: rickman: Re: board - T562.jpg
112625: 06/11/26: PeteS: Re: board - T562.jpg
112640: 06/11/27: Michael A. Terrell: Re: board - T562.jpg
112617: 06/11/26: rickman: Re: board - T562.jpg
112626: 06/11/26: PeteS: Re: board - T562.jpg
112599: 06/11/25: PeteS: Re: board - T562.jpg
112590: 06/11/25: PeteS: Re: board - T562.jpg
112542: 06/11/24: joseph2k: Re: board - T562.jpg
112421: 06/11/21: John Larkin: Re: board - T562.jpg
112429: 06/11/21: John Larkin: Re: board - T562.jpg
112455: 06/11/22: John Larkin: Re: board - T562.jpg
112343: 06/11/20: Eric Smith: Re: board - T562.jpg
112322: 06/11/20: Joel Kolstad: Re: board - T562.jpg
112413: 06/11/21: PeteS: Re: board - T562.jpg
112460: 06/11/22: rickman: Re: board - T562.jpg
112296: 06/11/19: Spehro Pefhany: Re: board - T562.jpg
112349: 06/11/21: joseph2k: Re: board - T562.jpg
112348: 06/11/21: joseph2k: Re: board - T562.jpg
112444: 06/11/22: rickman: Re: board - T562.jpg
112269: 06/11/18: <hakan.aydin@gmail.com>: spartan-3e starter kit and ethernet
112271: 06/11/18: Antti: Re: spartan-3e starter kit and ethernet
112282: 06/11/19: Antti Lukats: Re: spartan-3e starter kit and ethernet
112281: 06/11/19: u_stadler@yahoo.de: Re: spartan-3e starter kit and ethernet
112270: 06/11/18: rickman: Re: board - T562.jpg
112285: 06/11/19: Elmar Weber: Virtex-4 DDR RAM Usage (with VHDL)
112302: 06/11/19: kunil: Spartan-3E slice resources
112303: 06/11/19: Alan Nishioka: Re: Spartan-3E slice resources
112318: 06/11/20: John_H: Re: Spartan-3E slice resources
112320: 06/11/20: Eric Crabill: Re: Spartan-3E slice resources
112420: 06/11/21: kunil: Re: Spartan-3E slice resources
112304: 06/11/19: kumar: query in delay chains
112305: 06/11/19: gen_vlsi: false path
112330: 06/11/20: Hans: Re: false path
112306: 06/11/19: <bhavanireddy@gmail.com>: Q on duty cycle
112312: 06/11/20: KJ: Re: Q on duty cycle
112310: 06/11/20: jajo: Input setup time & Hold Input
112313: 06/11/20: rickman: Re: Input setup time & Hold Input
112311: 06/11/20: lecroy7200@chek.com: Simple questions on IDELAYCTRL
112335: 06/11/20: Ray Andraka: Re: Simple questions on IDELAYCTRL
113560: 06/12/16: Antti Lukats: Re: Simple questions on IDELAYCTRL vs DCM
113633: 06/12/18: Austin Lesea: Re: Simple questions on IDELAYCTRL vs DCM
113637: 06/12/18: Austin Lesea: Re: Simple questions on IDELAYCTRL vs DCM
113807: 06/12/22: Austin: Re: Simple questions on IDELAYCTRL vs DCM
113826: 06/12/23: Austin: Re: Simple questions on IDELAYCTRL vs DCM
113831: 06/12/23: Austin: Re: Simple questions on IDELAYCTRL vs DCM
112362: 06/11/21: Sean Durkin: Re: Simple questions on IDELAYCTRL
112448: 06/11/22: lecroy7200@chek.com: Re: Simple questions on IDELAYCTRL
112449: 06/11/22: lecroy7200@chek.com: Re: Simple questions on IDELAYCTRL
112457: 06/11/22: lecroy7200@chek.com: Re: Simple questions on IDELAYCTRL
113559: 06/12/16: johnp: Re: Simple questions on IDELAYCTRL vs DCM
113630: 06/12/18: johnp: Re: Simple questions on IDELAYCTRL vs DCM
113635: 06/12/18: johnp: Re: Simple questions on IDELAYCTRL vs DCM
113805: 06/12/22: lecroy7200@chek.com: Re: Simple questions on IDELAYCTRL vs DCM
113823: 06/12/23: Antti: Re: Simple questions on IDELAYCTRL vs DCM
113828: 06/12/23: lecroy7200@chek.com: Re: Simple questions on IDELAYCTRL vs DCM
113835: 06/12/23: johnp: Re: Simple questions on IDELAYCTRL vs DCM
112314: 06/11/20: Bob: Need examples/instruction: use of altpll_reconfig (Altera)
112338: 06/11/20: Subroto Datta: Re: Need examples/instruction: use of altpll_reconfig (Altera)
112339: 06/11/20: Subroto Datta: Re: Need examples/instruction: use of altpll_reconfig (Altera)
113362: 06/12/11: Bob: Re: Need examples/instruction: use of altpll_reconfig (Altera)
112315: 06/11/20: tullio: Spartan3E price update ?
112317: 06/11/20: Antti: Re: Spartan3E price update ?
112326: 06/11/20: rickman: Re: Spartan3E price update ?
112327: 06/11/20: rickman: Re: Spartan3E price update ?
112316: 06/11/20: <prathap.ap@gmail.com>: Differential to single ended convertion in FPGA
112319: 06/11/20: radarman: Parallax Stratix Smartpack accessories?
112377: 06/11/21: Antti: Re: Parallax Stratix Smartpack accessories?
112321: 06/11/20: Roger: ISE Synthesize Properties box
112328: 06/11/20: Vangelis: DDR_VDHL_models
112333: 06/11/20: MM: Re: DDR_VDHL_models
112355: 06/11/21: <helmut.leonhardt@gmail.com>: Re: DDR_VDHL_models
112436: 06/11/22: Brian Drummond: Re: DDR_VDHL_models
112331: 06/11/20: Vangelis: DDR_SDRAM_VHDL_models
112366: 06/11/21: subint: Re: DDR_SDRAM_VHDL_models
112376: 06/11/21: Patrick Dubois: Re: DDR_SDRAM_VHDL_models
112332: 06/11/20: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?=: Spartan 3 Starter Kit .mcs upload problem
112385: 06/11/21: <burn.sir@gmail.com>: Re: Spartan 3 Starter Kit .mcs upload problem
112344: 06/11/20: Vitaliy: Missing module : XFFT_V3_1 Verilog (not VHDL) module
112347: 06/11/20: fl: What's wrong with my tcl example in Quartus?
112353: 06/11/20: Alan Nishioka: Re: What's wrong with my tcl example in Quartus?
112400: 06/11/21: fl: Re: What's wrong with my tcl example in Quartus?
112350: 06/11/20: ram: timing constraints
112416: 06/11/21: <dkarchmer@gmail.com>: Re: timing constraints
112351: 06/11/20: ram: timing constraints
112352: 06/11/20: <sdave@ufl.edu>: Re: Semantics or examples for Xilinx xgpio driver under Linux?
112363: 06/11/21: =?utf-8?B?R2FMYUt0SWtVc+KEog==?=: Spartan-3E Starter Kit and programmable pre-Amplifier
112380: 06/11/21: sovan: V5 LXT PCIe Block simulation
112398: 06/11/21: sovan: Re: V5 LXT PCIe Block simulation
112402: 06/11/21: <spartanius@arcor.de>: Spartan 3E-Kit
112404: 06/11/21: Frank Buss: Re: Spartan 3E-Kit
112414: 06/11/21: Uwe Bonnes: Re: Spartan 3E-Kit
112423: 06/11/22: Frank Buss: Re: Spartan 3E-Kit
112459: 06/11/22: John_H: Re: Spartan 3E-Kit
112478: 06/11/23: Frank Buss: Re: Spartan 3E-Kit
112519: 06/11/23: Frank Buss: Re: Spartan 3E-Kit
112570: 06/11/25: John_H: Re: Spartan 3E-Kit
112573: 06/11/25: John_H: Re: Spartan 3E-Kit
112412: 06/11/21: <spartanius@arcor.de>: Re: Spartan 3E-Kit
112453: 06/11/22: <spartanius@arcor.de>: Re: Spartan 3E-Kit
112516: 06/11/23: <spartanius@arcor.de>: Re: Spartan 3E-Kit
112569: 06/11/24: <spartanius@arcor.de>: Re: Spartan 3E-Kit
112572: 06/11/24: <spartanius@arcor.de>: Re: Spartan 3E-Kit
112408: 06/11/21: markus: I2C "READ" Setup/Hold Requirement
112424: 06/11/21: Daniel S.: Re: I2C "READ" Setup/Hold Requirement
112468: 06/11/22: markus: Re: I2C "READ" Setup/Hold Requirement
112415: 06/11/21: ma: CORDIC FM Demodulation
112435: 06/11/22: Jan Panteltje: Re: CORDIC FM Demodulation
112437: 06/11/22: ma: Re: CORDIC FM Demodulation
112440: 06/11/22: Jan Panteltje: Re: CORDIC FM Demodulation
112441: 06/11/22: ma: Re: CORDIC FM Demodulation
112445: 06/11/22: Jan Panteltje: Re: CORDIC FM Demodulation
112446: 06/11/22: Jan Panteltje: Re: CORDIC FM Demodulation
112689: 06/11/27: Ray Andraka: Re: CORDIC FM Demodulation
112693: 06/11/27: Jan Panteltje: Re: CORDIC FM Demodulation
112418: 06/11/21: Jozsef: ISE 8.2 & XC9500XL family
112430: 06/11/21: Antti: Re: ISE 8.2 & XC9500XL family
112432: 06/11/21: John Adair: Re: ISE 8.2 & XC9500XL family
112464: 06/11/22: Jozsef: Re: ISE 8.2 & XC9500XL family
112427: 06/11/21: rickman: Re: board - T562.jpg
112438: 06/11/22: Sylvain Munaut <SomeOne@SomeDomain.com>: Protecting netlist for Xilinx
112456: 06/11/22: Austin Lesea: Re: Protecting netlist for Xilinx
112474: 06/11/23: Sylvain Munaut: Re: Protecting netlist for Xilinx
112476: 06/11/22: Austin Lesea: Re: Protecting netlist for Xilinx
112475: 06/11/23: Sylvain Munaut: Re: Protecting netlist for Xilinx
112466: 06/11/22: Mike Treseler: Re: Protecting netlist for Xilinx
112469: 06/11/22: PeteS: Re: Protecting netlist for Xilinx
112507: 06/11/23: <fpga_toys@yahoo.com>: Re: Protecting netlist for Xilinx
112556: 06/11/24: <jetmarc@hotmail.com>: Re: Protecting netlist for Xilinx
112439: 06/11/22: Antti: Xilinx DDR2 IP core performance
112768: 06/11/29: Finn S. Nielsen: Re: Xilinx DDR2 IP core performance
112442: 06/11/22: <guybye@hotmail.com>: Xilinx EDK - using EMC with Intel Strata Flash - assistance needed
112483: 06/11/23: <icegray@gmail.com>: Re: Xilinx EDK - using EMC with Intel Strata Flash - assistance needed
112447: 06/11/22: Koen Van Renterghem: Virtex 4 Internal Tristate (BUFT)?
112454: 06/11/22: =?utf-8?B?R2FMYUt0SWtVc+KEog==?=: Re: Virtex 4 Internal Tristate (BUFT)?
112458: 06/11/22: John_H: Re: Virtex 4 Internal Tristate (BUFT)?
112451: 06/11/22: nana: Aurora and Chipscope
112463: 06/11/22: Rune D. Jřrgensen: Cache trouble in XPS
112472: 06/11/22: <olson_ord@yahoo.it>: Division of a (rather large) Gate level Combinational Design
112477: 06/11/22: John_H: Re: Division of a (rather large) Gate level Combinational Design
112491: 06/11/23: Andreas Ehliar: Re: Division of a (rather large) Gate level Combinational Design
112487: 06/11/23: <olson_ord@yahoo.it>: Re: Division of a (rather large) Gate level Combinational Design
112494: 06/11/23: <olson_ord@yahoo.it>: Re: Division of a (rather large) Gate level Combinational Design
112480: 06/11/23: Nevo: Altera configuration with microcontroller
112481: 06/11/23: mk: Re: Altera configuration with microcontroller
112488: 06/11/23: Leon: Re: Altera configuration with microcontroller
112558: 06/11/24: unknown@aol.com: Re: Altera configuration with microcontroller
112503: 06/11/23: Will Dean: Re: Altera configuration with microcontroller
112588: 06/11/25: Nevo: Re: Altera configuration with microcontroller
112482: 06/11/22: ram: query
112485: 06/11/23: Alfmyk: C++ on uBlaze : C++ Problems...Possible Xilinx bugs ?
112506: 06/11/23: Tim Wescott: Re: C++ on uBlaze : C++ Problems...Possible Xilinx bugs ?
112533: 06/11/24: Alfmyk: Re: C++ on uBlaze : C++ Problems...Possible Xilinx bugs ?
112490: 06/11/23: Christian Schleiffer: Problems connecting MicroBlaze to custom IP
112492: 06/11/23: Antti: Re: Problems connecting MicroBlaze to custom IP
112493: 06/11/23: Christian Schleiffer: Re: Problems connecting MicroBlaze to custom IP
112515: 06/11/23: Christian Schleiffer: Re: Problems connecting MicroBlaze to custom IP
112500: 06/11/23: Zara: Re: Problems connecting MicroBlaze to custom IP
112514: 06/11/23: Christian Schleiffer: Re: Problems connecting MicroBlaze to custom IP
112495: 06/11/23: Andrew Holme: DCM Jitter
112504: 06/11/23: Austin Lesea: Re: DCM Jitter
112510: 06/11/23: John_H: Re: DCM Jitter
112518: 06/11/23: Andrew Holme: Re: DCM Jitter
112521: 06/11/24: John_H: Re: DCM Jitter
112544: 06/11/24: Austin Lesea: Re: DCM Jitter
112538: 06/11/24: Andrew Holme: Re: DCM Jitter
112540: 06/11/24: Andrew Holme: Re: DCM Jitter
112552: 06/11/24: Andrew Holme: Re: DCM Jitter
112496: 06/11/23: Andrew Holme: Voltage prorating for Spartan 3
112512: 06/11/23: John_H: Re: Voltage prorating for Spartan 3
112497: 06/11/23: Andrew Holme: Constraining timing analyser when using two DCMs
112498: 06/11/23: Symon: Re: Constraining timing analyser when using two DCMs
112509: 06/11/23: Andrew Holme: Re: Constraining timing analyser when using two DCMs
112513: 06/11/23: Andrew Holme: Re: Constraining timing analyser when using two DCMs
112499: 06/11/23: maxascent: Xilinx EDK Problem
112501: 06/11/23: Antti: Re: Xilinx EDK Problem
112522: 06/11/23: Davy: What's Nonpipelined bus mean?
112523: 06/11/23: rickman: Re: What's Nonpipelined bus mean?
112524: 06/11/23: Davy: Re: What's Nonpipelined bus mean?
112525: 06/11/23: Alex: Re: What's Nonpipelined bus mean?
112526: 06/11/23: Davy: Re: What's Nonpipelined bus mean?
112539: 06/11/24: sai: Re: What's Nonpipelined bus mean?
112603: 06/11/25: bir: Re: What's Nonpipelined bus mean?
112527: 06/11/23: Jay: Are FPGAs available with ADCs onchip ?
112528: 06/11/24: Antti Lukats: Re: Are FPGAs available with ADCs onchip ?
112545: 06/11/24: Austin Lesea: Re: Are FPGAs available with ADCs onchip ?
112529: 06/11/23: makhan: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 1
112979: 06/12/03: bijoy: Re: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 1
112982: 06/12/04: Andreas Ehliar: Re: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 1
112530: 06/11/24: ram: types of FPGA
112546: 06/11/24: Uwe Bonnes: Re: types of FPGA
112531: 06/11/24: <umeshmgowda@gmail.com>: jtag loader for picoblaze
112532: 06/11/24: Antti: Re: jtag loader for picoblaze
112534: 06/11/24: Quesito: Re: jtag loader for picoblaze
112535: 06/11/24: Quesito: Re: jtag loader for picoblaze
112536: 06/11/24: Manfred Balik: Altera MAX3000A OE and GCLR-Pins
112559: 06/11/24: Andrew Holme: Re: Altera MAX3000A OE and GCLR-Pins
112647: 06/11/27: Manfred Balik: Re: Altera MAX3000A OE and GCLR-Pins
112541: 06/11/24: <krassi@bulinfo.net>: MicroBlaze & top module?
112543: 06/11/24: Davy: Verilog problem: default case to set signal xxxx
112547: 06/11/24: Stephen Williams: Re: Verilog problem: default case to set signal xxxx
112548: 06/11/24: Jon Beniston: Re: Verilog problem: default case to set signal xxxx
112554: 06/11/24: Petter Gustad: Re: Verilog problem: default case to set signal xxxx
112598: 06/11/25: Rob Dekker: Re: Verilog problem: default case to set signal xxxx
112606: 06/11/26: Petter Gustad: Re: Verilog problem: default case to set signal xxxx
112607: 06/11/26: Petter Gustad: Re: Verilog problem: default case to set signal xxxx
112555: 06/11/24: Alex: Re: Verilog problem: default case to set signal xxxx
112561: 06/11/24: <sharp@cadence.com>: Re: Verilog problem: default case to set signal xxxx
112563: 06/11/24: Jon Beniston: Re: Verilog problem: default case to set signal xxxx
112564: 06/11/24: =?iso-8859-1?B?VXRrdSDWemNhbg==?=: Re: Verilog problem: default case to set signal xxxx
112633: 06/11/26: Davy: Re: Verilog problem: default case to set signal xxxx
112550: 06/11/24: Antti: MPMC2 DDR2 simulation
112654: 06/11/27: Antti: Re: MPMC2 DDR2 simulation
112551: 06/11/24: Al: run a counter without a clock
112560: 06/11/24: Koen Van Renterghem: Re: run a counter without a clock
112579: 06/11/25: John Adair: Re: run a counter without a clock
112582: 06/11/25: Al: Re: run a counter without a clock
112583: 06/11/25: Al: Re: run a counter without a clock
112646: 06/11/27: Jim Granville: Re: run a counter without a clock
112726: 06/11/28: Al: Re: run a counter without a clock
112753: 06/11/29: Jim Granville: Re: run a counter without a clock
112650: 06/11/27: Symon: Re: run a counter without a clock
112662: 06/11/27: Al: Re: run a counter without a clock
112651: 06/11/27: jonas: Re: run a counter without a clock
112699: 06/11/27: Jon Elson: Re: run a counter without a clock
112703: 06/11/28: Jim Granville: Re: run a counter without a clock
112724: 06/11/28: Al: Re: run a counter without a clock
112728: 06/11/28: Symon: Re: run a counter without a clock
112736: 06/11/28: Al: Re: run a counter without a clock
112740: 06/11/28: Symon: Re: run a counter without a clock
112553: 06/11/24: hypermodest: logic analyzer using FPGA
112576: 06/11/25: bm: Re: logic analyzer using FPGA
112746: 06/11/28: Jaime Andrés Aranguren Cardona: Re: logic analyzer using FPGA
112574: 06/11/24: ram: query
112575: 06/11/24: ram: query
112580: 06/11/25: dh2006: Double buffering
112778: 06/11/28: <jez-smith@hotmail.co.uk>: Re: Double buffering
112944: 06/12/01: Daniel S.: Re: Double buffering
112983: 06/12/04: Ben Jones: Re: Double buffering
112581: 06/11/25: <florent.peyrard@gmail.com>: playing test SVF files for Spartan-3 Starter Board (using iMPACT ?)
112584: 06/11/25: Roger: IE7 and ISE Help
112585: 06/11/25: jacko: Dev Kit Shipping Costs
112605: 06/11/26: John Adair: Re: Dev Kit Shipping Costs
112586: 06/11/25: Roger: Aurora 2.4 error
112686: 06/11/27: Hemanth: Re: Aurora 2.4 error
112893: 06/11/30: Roger: Re: Aurora 2.4 error
112610: 06/11/26: Antti: EDK 8.2 STUPID STUPID BUG (minor)
112613: 06/11/26: Jean Nicolle: vccaux and vccint
112615: 06/11/26: <langwadt@ieee.org>: Re: vccaux and vccint
112616: 06/11/26: rickman: Re: vccaux and vccint
112624: 06/11/27: Jean Nicolle: Re: vccaux and vccint
112642: 06/11/27: Sean Durkin: Re: vccaux and vccint
112648: 06/11/27: Symon: Re: vccaux and vccint
112664: 06/11/27: Symon: Re: vccaux and vccint
112670: 06/11/27: Sean Durkin: Re: vccaux and vccint
112687: 06/11/27: Symon: Re: vccaux and vccint
112684: 06/11/27: Bob: Re: vccaux and vccint
112718: 06/11/27: Bob: Re: more S3E DIFF_TERM quirks ( was: vccaux and vccint )
112737: 06/11/28: Bob: Re: more S3E DIFF_TERM quirks ( was: vccaux and vccint )
112623: 06/11/26: PeteS: Re: vccaux and vccint
112658: 06/11/27: rickman: Re: vccaux and vccint
112716: 06/11/27: Brian Davis: more S3E DIFF_TERM quirks ( was: vccaux and vccint )
112732: 06/11/28: Brian Davis: Re: more S3E DIFF_TERM quirks ( was: vccaux and vccint )
112745: 06/11/28: Brian Davis: Re: more S3E DIFF_TERM quirks ( was: vccaux and vccint )
112621: 06/11/26: <burn.sir@gmail.com>: Mico32, how good is it?
112622: 06/11/26: Jon Beniston: Re: Mico32, how good is it?
112720: 06/11/28: Göran Bilski: Re: Mico32, how good is it?
112766: 06/11/29: Finn S. Nielsen: Re: Mico32, how good is it?
112779: 06/11/29: Göran Bilski: Re: Mico32, how good is it?
112691: 06/11/27: <burn.sir@gmail.com>: Re: Mico32, how good is it?
112694: 06/11/27: Antti: Re: Mico32, how good is it?
112696: 06/11/27: <burn.sir@gmail.com>: Re: Mico32, how good is it?
112697: 06/11/27: Antti: Re: Mico32, how good is it?
112704: 06/11/27: Jon Beniston: Re: Mico32, how good is it?
112705: 06/11/27: Jon Beniston: Re: Mico32, how good is it?
112780: 06/11/29: Antti: Re: Mico32, how good is it?
112785: 06/11/29: <burn.sir@gmail.com>: Re: Mico32, how good is it?
112631: 06/11/26: ram: query in constraining timing
112637: 06/11/26: <dkarchmer@gmail.com>: Re: query in constraining timing
112638: 06/11/26: ram: Re: query in constraining timing
112639: 06/11/26: ram: Re: query in constraining timing
112643: 06/11/26: ram: Re: query in constraining timing
112636: 06/11/26: BODDU: QPROM in FPGA
112644: 06/11/26: pavan kumar: I2C Controller
112701: 06/11/27: tullio: Re: I2C Controller
112645: 06/11/26: pavan kumar: I2C Controller implementation
112685: 06/11/27: Tim Wescott: Re: I2C Controller implementation
112649: 06/11/27: marada: Re: Microblaze : FSL bus
112652: 06/11/27: <rponsard@gmail.com>: Re: Xilinx WebPACK 8.2.03i + Linux Problem
112653: 06/11/27: ram: tips for P&R in FPGA(quartus)
112655: 06/11/27: Frank Buss: Re: tips for P&R in FPGA(quartus)
112676: 06/11/27: Subroto Datta: Re: tips for P&R in FPGA(quartus)
112656: 06/11/27: kenm: Pullups and pulldowns in EDK?
112657: 06/11/27: Antti: Re: Pullups and pulldowns in EDK?
112710: 06/11/27: kenm: Re: Pullups and pulldowns in EDK?
112659: 06/11/27: <florent.peyrard@gmail.com>: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
112660: 06/11/27: Antti: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
112661: 06/11/27: <florent.peyrard@gmail.com>: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
112663: 06/11/27: <florent.peyrard@gmail.com>: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
112665: 06/11/27: Antti: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
112667: 06/11/27: <florent.peyrard@gmail.com>: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
112669: 06/11/27: <florent.peyrard@gmail.com>: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
112666: 06/11/27: hypermodest: Altera's USB blaster
112671: 06/11/27: Will Dean: Re: Altera's USB blaster
112692: 06/11/27: hypermodest: Re: Altera's USB blaster
112668: 06/11/27: aravind: edk evaluation
112672: 06/11/27: <icegray@gmail.com>: Microblaze Code and XMP functions
112673: 06/11/27: Antti: Re: Microblaze Code and XMP functions
112675: 06/11/27: <icegray@gmail.com>: Re: Microblaze Code and XMP functions
112719: 06/11/28: Steve: Re: Microblaze Code and XMP functions
112677: 06/11/27: Richard Klingler: nios2 toolchain sources
112678: 06/11/27: Antti: Re: nios2 toolchain sources
112679: 06/11/27: Richard Klingler: Re: nios2 toolchain sources
112682: 06/11/27: DJ Delorie: Re: nios2 toolchain sources
112707: 06/11/27: Richard Klingler: Re: nios2 toolchain sources
112690: 06/11/27: Antti: Re: nios2 toolchain sources
112695: 06/11/27: <burn.sir@gmail.com>: Re: nios2 toolchain sources
112698: 06/11/27: Derek Simmons: Re: nios2 toolchain sources
112708: 06/11/27: Richard Klingler: Re: nios2 toolchain sources
112773: 06/11/29: Richard Pennington: Re: nios2 toolchain sources
112680: 06/11/27: cathy: What's the speed grade for the XC5VLX50 on xilinx ML501 evaluation board?
112683: 06/11/27: Antti: Re: What's the speed grade for the XC5VLX50 on xilinx ML501 evaluation board?
112688: 06/11/27: cathy: Re: What's the speed grade for the XC5VLX50 on xilinx ML501 evaluation board?
112681: 06/11/27: JG: What's the status regarding MicroBlaze, Lynuxworks and uClinux 2.6?
112733: 06/11/28: Antti: Re: What's the status regarding MicroBlaze, Lynuxworks and uClinux 2.6?
112700: 06/11/27: <rodyna.zidan@gmail.com>: avnet FX12 mini module example temac design does not work in edk 8.2.02i
112706: 06/11/27: Anonymous: opb master kills linux?
112843: 06/11/30: John Williams: Re: opb master kills linux?
112879: 06/11/30: Anonymous: Re: opb master kills linux?
112709: 06/11/27: wallge: problems with verilog SDRAM models
112711: 06/11/27: <ghelbig@lycos.com>: Re: problems with verilog SDRAM models
112721: 06/11/27: Amirtham: Re: problems with verilog SDRAM models
112722: 06/11/28: <helmut.leonhardt@gmail.com>: Re: problems with verilog SDRAM models
112723: 06/11/28: <helmut.leonhardt@gmail.com>: Re: problems with verilog SDRAM models
112729: 06/11/28: Niv: Re: problems with verilog SDRAM models
112968: 06/12/03: FMF: Re: problems with verilog SDRAM models
112734: 06/11/28: Brian Drummond: Re: problems with verilog SDRAM models
112969: 06/12/03: FMF: Re: problems with verilog SDRAM models
112999: 06/12/04: Kevin Neilson: Re: problems with verilog SDRAM models
112725: 06/11/28: Antti: Re: run a counter without a clock
112730: 06/11/28: ma: Digital PLL and FM demodulation
112735: 06/11/28: John Sampson: Re: Digital PLL and FM demodulation
112739: 06/11/28: Vladimir Vassilevsky: Re: Digital PLL and FM demodulation
112756: 06/11/28: ma: Re: Digital PLL and FM demodulation
112757: 06/11/28: Vladimir Vassilevsky: Re: Digital PLL and FM demodulation
112731: 06/11/28: Antti: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
112852: 06/11/29: leevv: Re: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
112855: 06/11/30: Antti Lukats: Re: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
112888: 06/11/30: Antti Lukats: Re: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
112859: 06/11/29: Antti: Re: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
112883: 06/11/30: leevv: Re: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
112738: 06/11/28: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?=: Bus structures question (Spartan 3)
112751: 06/11/28: John_H: Re: Bus structures question (Spartan 3)
112789: 06/11/29: Andreas Ehliar: Re: Bus structures question (Spartan 3)
112752: 06/11/28: PeteS: Re: Bus structures question (Spartan 3)
112803: 06/11/29: Andy: Re: Bus structures question (Spartan 3)
112807: 06/11/29: Nico Coesel: Re: Bus structures question (Spartan 3)
112819: 06/11/29: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?=: Re: Bus structures question (Spartan 3)
112822: 06/11/29: PeteS: Re: Bus structures question (Spartan 3)
112910: 06/11/30: Daniel S.: Re: Bus structures question (Spartan 3)
112741: 06/11/28: Quesito: verilog 2 VHDL translator
112750: 06/11/28: Jon Beniston: Re: verilog 2 VHDL translator
112762: 06/11/28: <jez-smith@hotmail.co.uk>: Re: verilog 2 VHDL translator
112790: 06/11/29: Quesito: Re: verilog 2 VHDL translator
112747: 06/11/28: Steven Derrien: Xilinx ML555 availability
112749: 06/11/28: Antti: Re: Xilinx ML555 availability
112748: 06/11/28: <karollo@o2.pl>: pre-synthezis simulation in ModelSim for Actel
112755: 06/11/28: Ralf Hildebrandt: Re: pre-synthezis simulation in ModelSim for Actel
112829: 06/11/29: Ralf Hildebrandt: Re: pre-synthezis simulation in ModelSim for Actel
112767: 06/11/28: <karollo@o2.pl>: Re: pre-synthezis simulation in ModelSim for Actel
112786: 06/11/29: <burn.sir@gmail.com>: Re: pre-synthezis simulation in ModelSim for Actel
112754: 06/11/28: Daveb: Spartan3 Configuration Puzzler
112760: 06/11/28: Gabor: Re: Spartan3 Configuration Puzzler
112770: 06/11/28: davide: Re: Spartan3 Configuration Puzzler
112823: 06/11/29: John_H: Re: Spartan3 Configuration Puzzler
112830: 06/11/29: John_H: Re: Spartan3 Configuration Puzzler
112841: 06/11/29: John_H: Re: Spartan3 Configuration Puzzler
112837: 06/11/29: PeteS: Re: Spartan3 Configuration Puzzler
112763: 06/11/28: Daveb: Re: Spartan3 Configuration Puzzler
112769: 06/11/28: John_H: Re: Spartan3 Configuration Puzzler
112816: 06/11/29: Daveb: Re: Spartan3 Configuration Puzzler
112818: 06/11/29: rickman: Re: Spartan3 Configuration Puzzler
112824: 06/11/29: rickman: Re: Spartan3 Configuration Puzzler
112835: 06/11/29: rickman: Re: Spartan3 Configuration Puzzler
113041: 06/12/05: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan3 Configuration Puzzler
112759: 06/11/28: Dan K: ModelSim Xilinx edition new bug?
112775: 06/11/29: backhus: Re: ModelSim Xilinx edition new bug?
112776: 06/11/28: <helmut.leonhardt@gmail.com>: Re: ModelSim Xilinx edition new bug?
112761: 06/11/28: PeteS: So who has used Lattice FPGAs recently?
112783: 06/11/29: MK: Re: So who has used Lattice FPGAs recently?
112784: 06/11/29: <burn.sir@gmail.com>: Re: So who has used Lattice FPGAs recently?
112793: 06/11/29: Martin Thompson: Re: So who has used Lattice FPGAs recently?
112821: 06/11/29: PeteS: Re: So who has used Lattice FPGAs recently?
112900: 06/11/30: PeteS: Re: So who has used Lattice FPGAs recently?
112943: 06/12/01: PeteS: Re: So who has used Lattice FPGAs recently?
112802: 06/11/29: Andy: Re: So who has used Lattice FPGAs recently?
112805: 06/11/29: <burn.sir@gmail.com>: Re: So who has used Lattice FPGAs recently?
112876: 06/11/30: Gabor: Re: So who has used Lattice FPGAs recently?
112942: 06/12/01: Gabor: Re: So who has used Lattice FPGAs recently?
112771: 06/11/28: Brad Smallridge: Xilinx XST Incremental Design Change
112774: 06/11/28: <elf_ster@hotmail.com>: Re: Xilinx XST Incremental Design Change
112849: 06/11/29: Brad Smallridge: Re: Xilinx XST Incremental Design Change
112777: 06/11/28: jfh: Hardware in the loop simulation for Altera design
112792: 06/11/29: Andy: Re: Hardware in the loop simulation for Altera design
112856: 06/11/29: jfh: Re: Hardware in the loop simulation for Altera design
112860: 06/11/29: Thomas Stanka: Re: Hardware in the loop simulation for Altera design
112875: 06/11/30: <elf_ster@hotmail.com>: Re: Hardware in the loop simulation for Altera design
112787: 06/11/29: hansman: DVI clock generation
112791: 06/11/29: Gabor: Re: DVI clock generation
112794: 06/11/29: Martin Thompson: Re: DVI clock generation
112796: 06/11/29: Sean Durkin: Re: DVI clock generation
112800: 06/11/29: Symon: Re: DVI clock generation
112812: 06/11/29: Sean Durkin: Re: DVI clock generation
112825: 06/11/29: Austin Lesea: Re: DVI clock generation
112870: 06/11/30: Symon: Re: DVI clock generation
112885: 06/11/30: Austin Lesea: Re: DVI clock generation
112853: 06/11/29: Marlboro: Re: DVI clock generation
112788: 06/11/29: cenzatol@dei.unipd.it: Bus Lock
112795: 06/11/29: Joseph: FPGA workstation - should I wait for Window Vista?
112798: 06/11/29: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: FPGA workstation - should I wait for Window Vista?
112808: 06/11/29: Joseph: Re: FPGA workstation - should I wait for Window Vista?
112832: 06/11/29: Ralf Hildebrandt: Re: FPGA workstation - should I wait for Window Vista?
112862: 06/11/30: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: FPGA workstation - should I wait for Window Vista?
112804: 06/11/29: JJ: Re: FPGA workstation - should I wait for Window Vista?
112806: 06/11/29: mk: Re: FPGA workstation - should I wait for Window Vista?
112814: 06/11/29: Sean Durkin: Re: FPGA workstation - should I wait for Window Vista?
112817: 06/11/29: mk: Re: FPGA workstation - should I wait for Window Vista?
112809: 06/11/29: Subroto Datta: Re: FPGA workstation - should I wait for Window Vista?
112815: 06/11/29: <curtis_m_watson@yahoo.com>: Re: FPGA workstation - should I wait for Window Vista?
112872: 06/11/30: Joseph: Re: FPGA workstation - should I wait for Window Vista?
113913: 06/12/29: Alex Gibson: Re: FPGA workstation - should I wait for Window Vista?
113934: 06/12/29: Joseph Samson: Re: FPGA workstation - should I wait for Window Vista?
114719: 07/01/23: <pbFJKD@ludd.invalid>: Re: FPGA workstation - should I wait for Window Vista?
114825: 07/01/24: Joseph Samson: Re: FPGA workstation - should I wait for Window Vista?
113947: 06/12/29: David M. Palmer: Re: FPGA workstation - should I wait for Window Vista?
113948: 06/12/29: Rob Barris: Re: FPGA workstation - should I wait for Window Vista?
113949: 06/12/29: <zwsdotcom@gmail.com>: Re: FPGA workstation - should I wait for Window Vista?
114834: 07/01/24: Eric Smith: Re: FPGA workstation - should I wait for Window Vista?
112797: 06/11/29: sjb: XC3020-50 board documentation
112801: 06/11/29: John Adair: Re: XC3020-50 board documentation
112828: 06/11/29: <ghelbig@lycos.com>: Re: XC3020-50 board documentation
112871: 06/11/30: sjb: Re: XC3020-50 board documentation
113191: 06/12/07: Philip Freidin: Re: XC3020-50 board documentation
112810: 06/11/29: tenteric: FPGA application field
112811: 06/11/29: <jez-smith@hotmail.co.uk>: Re: FPGA application field
112833: 06/11/29: Ralf Hildebrandt: Re: FPGA application field
112845: 06/11/29: Austin Lesea: Re: FPGA application field
112891: 06/11/30: Austin Lesea: Re: FPGA application field
112892: 06/11/30: Ralf Hildebrandt: Re: FPGA application field
112950: 06/12/02: Ralf Hildebrandt: Re: FPGA application field
113250: 06/12/08: glen herrmannsfeldt: Re: FPGA application field
112895: 06/12/01: Jim Granville: Re: FPGA application field
113251: 06/12/08: glen herrmannsfeldt: Re: FPGA application field
112813: 06/11/29: tenteric: Re: FPGA application field
112838: 06/11/29: <jez-smith@hotmail.co.uk>: Re: FPGA application field
112844: 06/11/29: tenteric: Re: FPGA application field
112889: 06/11/30: Robin Bruce: Re: FPGA application field
112945: 06/12/01: Robin Bruce: Re: FPGA application field
112820: 06/11/29: wojtek_himself: modular design / PlanAhead
112836: 06/11/29: Salil Raje: Re: modular design / PlanAhead
112826: 06/11/29: jjlindula@hotmail.com: Stratix II GX Transceivers
112846: 06/11/30: Ben Twijnstra: Re: Stratix II GX Transceivers
112896: 06/11/30: jjlindula@hotmail.com: Re: Stratix II GX Transceivers
112905: 06/11/30: jjlindula@hotmail.com: Re: Stratix II GX Transceivers
112827: 06/11/29: <jetmarc@hotmail.com>: ISE on a cluster?
112831: 06/11/29: John_H: Re: ISE on a cluster?
112864: 06/11/30: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: ISE on a cluster?
112858: 06/11/29: <jez-smith@hotmail.co.uk>: Re: ISE on a cluster?
112874: 06/11/30: John Adair: Re: ISE on a cluster?
112834: 06/11/29: <slax0r.hax0r@gmail.com>: Spartan-3E or Generic FPGA -> PC133 interface details??
112839: 06/11/29: Matthew Hicks: Re: Spartan-3E or Generic FPGA -> PC133 interface details??
112840: 06/11/29: PeteS: Re: Spartan-3E or Generic FPGA -> PC133 interface details??
112847: 06/11/29: Bill Burris: SPI Flash on Avnet Spartan 3E Eval Kit
112848: 06/11/29: kunil: Re: SPI Flash on Avnet Spartan 3E Eval Kit
112937: 06/12/01: Bill Burris: Re: SPI Flash on Avnet Spartan 3E Eval Kit
113359: 06/12/11: Bill Burris: Re: SPI Flash on Avnet Spartan 3E Eval Kit
114594: 07/01/19: Bill Burris: Re: SPI Flash on Avnet Spartan 3E Eval Kit
114005: 07/01/02: <patrice.ulrich@evc.net>: Re: SPI Flash on Avnet Spartan 3E Eval Kit
112851: 06/11/29: Ray Andraka: Old XCell journals gone?
112857: 06/11/29: JustJohn: Re: Old XCell journals gone?
112868: 06/11/30: Michal HUSEJKO: Re: Old XCell journals gone?
112873: 06/11/30: Symon: Re: Old XCell journals gone?
112908: 06/11/30: Ray Andraka: Re: Old XCell journals gone?
112861: 06/11/30: Murali: Prefetch buffer in microblaze
112863: 06/11/30: Göran Bilski: Re: Prefetch buffer in microblaze
112865: 06/11/30: <aiiadict@gmail.com>: wanted: FPGA programmer
112881: 06/11/30: wallge: Re: wanted: FPGA programmer
112917: 06/12/01: bijoy: Re: wanted: FPGA programmer
112980: 06/12/03: BODDU Lokesh: Re: wanted: FPGA programmer
112866: 06/11/30: cippalippa: Opencores DDR SDRAM controller
112920: 06/12/01: Guru: Re: Opencores DDR SDRAM controller
112932: 06/12/01: Vangelis: Re: Opencores DDR SDRAM controller
112953: 06/12/02: cippalippa: Re: Opencores DDR SDRAM controller
112956: 06/12/02: Steven P: Re: Opencores DDR SDRAM controller
112958: 06/12/02: Frank Buss: Re: Opencores DDR SDRAM controller
113009: 06/12/05: Frank Buss: Re: Opencores DDR SDRAM controller
113361: 06/12/12: Frank Buss: Re: Opencores DDR SDRAM controller
113498: 06/12/15: Frank Buss: Re: Opencores DDR SDRAM controller
112971: 06/12/03: cippalippa: Re: Opencores DDR SDRAM controller
113002: 06/12/04: Tommy Thorn: Re: Opencores DDR SDRAM controller
113012: 06/12/04: Tommy Thorn: Re: Opencores DDR SDRAM controller
113263: 06/12/09: cippalippa: Re: Opencores DDR SDRAM controller
113275: 06/12/09: Tommy Thorn: Re: Opencores DDR SDRAM controller
113349: 06/12/11: cippalippa: Re: Opencores DDR SDRAM controller
113495: 06/12/14: cippalippa: Re: Opencores DDR SDRAM controller
112867: 06/11/30: mstrug: Question: TMED Algorithm
112869: 06/11/30: ram: help
112877: 06/11/30: fl: Can I see the detail timing parameter by Quartus II tools?
112882: 06/11/30: <dkarchmer@gmail.com>: Re: Can I see the detail timing parameter by Quartus II tools?
112884: 06/11/30: wallge: Re: Can I see the detail timing parameter by Quartus II tools?
112886: 06/11/30: fl: Re: Can I see the detail timing parameter by Quartus II tools?
112894: 06/11/30: wallge: Re: Can I see the detail timing parameter by Quartus II tools?
112901: 06/11/30: Mike Treseler: Re: Can I see the detail timing parameter by Quartus II tools?
112909: 06/11/30: Mike Treseler: Re: Can I see the detail timing parameter by Quartus II tools?
112938: 06/12/01: Mike Treseler: Re: Can I see the detail timing parameter by Quartus II tools?
113482: 06/12/14: RCIngham: Re: Can I see the detail timing parameter by Quartus II tools?
112906: 06/11/30: fl: Re: Can I see the detail timing parameter by Quartus II tools?
112923: 06/12/01: fl: Re: Can I see the detail timing parameter by Quartus II tools?
112929: 06/12/01: fpgabuilder: Re: Can I see the detail timing parameter by Quartus II tools?
112931: 06/12/01: ABC: Re: Can I see the detail timing parameter by Quartus II tools?
112878: 06/11/30: awa: Thesis
112880: 06/11/30: wallge: Re: Thesis
112914: 06/11/30: awa: Re: Thesis
112887: 06/11/30: Alan Nishioka: Anyone use Xilinx ppc405 profiling tools?
112890: 06/11/30: Guy_FPGA: Xilinx XPS - OPB - EMC software halts. Someting fishy
112898: 06/11/30: Andrew Holme: DCM jitter (again)
112899: 06/11/30: <jez-smith@hotmail.co.uk>: Re: DCM jitter (again)
112902: 06/11/30: <jez-smith@hotmail.co.uk>: Re: DCM jitter (again)
112903: 06/11/30: Austin Lesea: Re: DCM jitter (again)
112930: 06/12/01: RobJ: Re: DCM jitter (again)
112933: 06/12/01: Austin Lesea: Re: DCM jitter (again)
112915: 06/12/01: John_H: Re: DCM jitter (again)
112904: 06/11/30: onlyspam@online.ms: LVDS output pins of Altera Cyclone II
112913: 06/12/01: Rob: Re: LVDS output pins of Altera Cyclone II
112940: 06/12/01: onlyspam@online.ms: Re: LVDS output pins of Altera Cyclone II
112948: 06/12/02: Rob: Re: LVDS output pins of Altera Cyclone II
112960: 06/12/02: onlyspam@online.ms: Re: LVDS output pins of Altera Cyclone II
112963: 06/12/02: Ben Twijnstra: Re: LVDS output pins of Altera Cyclone II
113219: 06/12/08: onlyspam@online.ms: Re: LVDS output pins of Altera Cyclone II
112911: 06/11/30: Peter Alfke: Re: Old XCell journals gone?
112912: 06/11/30: Weng Tianxiang: How to save a changed *.wlf file with ModelSim
112918: 06/12/01: Hans: Re: How to save a changed *.wlf file with ModelSim
112922: 06/12/01: backhus: Re: How to save a changed *.wlf file with ModelSim
112934: 06/12/01: Weng Tianxiang: Re: How to save a changed *.wlf file with ModelSim
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