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On Oct 15, 1:10=A0pm, Andy Peters <goo...@latke.net> wrote: > On Oct 15, 8:14=A0am, rickman <gnu...@gmail.com> wrote: > > > > > On Oct 15, 12:51=A0am, GrIsH <grishkun...@gmail.com> wrote: > > > > On Oct 14, 11:35=A0am, rickman <gnu...@gmail.com> wrote: > > > > > I have never worked with SLV in the 0 to N direction. =A0To be hone= st, I > > > > don't remember the details of how assignments are made between buse= s > > > > using different directions of indexes. =A0I wouldn't expect any > > > > surprises, but then I have no experience with them. =A0Is there a r= eason > > > > that you are using 0 to N numbering instead of N downto 0 on your S= LV > > > > arrays? =A0This may not be a problem, but if you are stuck, why use= this > > > > uncommon convention? > > > > =A0 =A0 for IP2Bus_Data we are not allowed to make this convention of= N > > > downto 0 that's why i didn't use this convention. > > > Ok, it shouldn't matter really, as long as you use it correctly. =A0Can > > you explain what this bus is and why it is 0 to 31? =A0Is this a port o= n > > the uBlaze? =A0Where exactly does this restriction come from. =A0Why do > > you assign your counter result to bits 16 to 31? > > MicroBlaze is big endian. Bits 16 to 31 are the two least significant > bytes in a 32-bit word (bit 31 is the right-most bit). > > -a I wonder why they do that. I have only seen bit zero as the most significant bit in a handful of designs and I expect the first was done for fairly obscure reasons and the rest were done to be compatible. Did the uBlaze need to be compatible with something in this regard? RickArticle: 143576
rickman <gnuarm@gmail.com> wrote: (snip) > I wonder why they do that. I have only seen bit zero as the most > significant bit in a handful of designs and I expect the first was > done for fairly obscure reasons and the rest were done to be > compatible. Did the uBlaze need to be compatible with something in > this regard? I don't know about the design, but all the documentation for IBM S/360, S/370, ESA/390, and z/Architecture numbers the bits with 0 as the MSB. That complicates the description change from 32 bit (through ESA/390) to 64 bit (z/Architecture), but otherwise it is more consistent with big-endian byte order. For an architecture without bit addressing it isn't so obvious that the documentation needs to be consistent with the byte ordering, but sometimes consistency is nice. As far as uBlaze and big endian, it would seem that [8*n,8*n+7] where n is a byte number would be somewhat more convenient than the other way around. -- glenArticle: 143577
On Oct 16, 11:32=A0am, Jon Beniston <j...@beniston.com> wrote: > There are two other areas where I still see latches being used in ASIC > designs: > > =A0- In clock gating cells to ensure no glitches on the clock. > =A0- For large, regular, register files, to minimize area. > > Cheers, > Jon Hi Jon, Good point !!! But the latches in clock gating cells are different from the latch I am interested in: They are used to suppress unnecessary clock pulses to reduce power supply if flip-flops are not to change their data. What the latch we are talking about is they REPLACE flip-flops. Hope more people are invovled to get the right patent selected. I am sure the technique must be reflected in Intel one patent in details. WengArticle: 143578
On Oct 16, 4:02=A0am, colin <colin_toog...@yahoo.com> wrote: > On 15 Oct, 16:37, rickman <gnu...@gmail.com> wrote: > > > > > On Oct 13, 8:12=A0am, "colin_toog...@yahoo.com" > > > <colin_toog...@yahoo.com> wrote: > > > On 13 Oct, 11:52, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > > > colin <colin_toog...@yahoo.com> writes: > > > > > I'm trying to implement a simple CLI so that I can do some debugg= ing. > > > > > I have a microblaze license but I've just taken a look at it and > > > > > sledgehammers and nuts come to mind. I then took a look on openco= res > > > > > and nothing seems quite finished enough (and few with a C compile= r). > > > > > > Does anyone have a suggestion? > > > > > Picoblaze (but that's assembly only..) > > > > > If you can fit a sledgehammer (sorry, microblaze :) in, why not use= it? > > > > What is it you're trying to do - just wiggle some port pins, or > > > > something more complex? > > > > > If it's slow pin/signal wiggling, and alternative might be to use > > > > Chipscope's VIO block - it's not CLI, but I gather it has some tcl > > > > libraries which you could build something with... > > > > > Cheers, > > > > Martin > > > > > -- > > > > martin.j.thomp...@trw.com > > > > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyht= tp://www.conekt.net/electronics.html > > > > Martin > > > > Your right, using the VIO block answers the question I posted. I need > > > to read/write a dozen 32 bit registers. However I ultimately want a > > > processor at the outermost control loop. I will take a look at using > > > chipscope for debugging and the Picoblaze at the outer loop. Cludgy i= n > > > the short term but ultimately quite elegant. > > > > Colin > > > I have some reservations about it, but I would say you might want to > > look at the ZPU. =A0I am not a software person anymore, so I think very > > differently than those guys, but they seem to have caught on and > > recently I read that National Semi has released some sort of eval > > board that is using the ZPU in an FPGA. =A0It is supported by a C > > compiler and can get down to something well under 1000 LUTs, perhaps > > as low as 600 I think. =A0It's not so fast at that size, but should be > > plenty fast enough for a CLI (I had to google CLI to figure out what > > that meant). > > > Another option is one of the two processors from Lattice. =A0I have > > never read the license in enough detail to actually understand it (I > > am not a lawyer, thank god) but it is supposed to be open source. =A0I > > don't know if that is the same as freely usable, but I'm pretty sure > > you don't have to use it in their parts. =A0They have a Micro8 similar > > to the Picoblaze and a 32 bit CPU like the uBlaze. > > > If you are interested in using Forth (it comes with the CLI) there are > > a number of processors to choose from including my own. =A0But I have > > never completed the compiler so it is assembly only. =A0Even if that is > > very forth like, it is not a forth compiler. > > > Rick > > Rick > > The ZPU does look like one of the better projects on opencores. It is > of course at the bottom of the opencores list and I was getting fed up > looking at lots of half completed projects. > > Thanks for pointing me at it, I will google GIT later today and have a > good look at it. > Maybe I will register at lattice and take a look there as well. > > Sorry for yet another TLA :-) =A0It is a term my colleagues at several > companies have used throughout my 20 year career. > > Many thanks > > Colin Ok, that's a point for you. I had to look up TLA too! RickArticle: 143579
On Oct 16, 12:19=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > Hi, > I am really interested in the theoritic bases of how a latch circuit > can replace a flip-flop to save power The theoretical basis for how a latch *might* use less power than a flop is simple physics: - Logic gates in any technology will consume more power when switching states because any switching signal will have to charge capacitance on the chip or board that cannot be completely recovered. - CMOS logic gates consume significantly more power when they change states...it's signficantly more during switching mainly because it consumes so little while static and not switching (although leakage currents on technology's cutting edge are eroding that one) >From that one should be able to surmise that: - A free running clock consumes more power than one that doesn't free run. And then note that: - The latch enable input signal on a latch is typically not free running And conclude that if a flip flop can be replaced by a latch in a particular application, then it will consume less power than the flip flop that is clocked by a free running clock. However, if the flip flop instead is clocked with a gated clock, it won't necessarily follow that a latch will consume less power. It will depend on the implementation technology and how the flops and latches are constructed since it's conceivable that the gated clock might only be switching the same number of times that the latch enable signal would. Bottom line is that there is no basis for thinking that a latch will always consume less power than a flip flop. Whether it does or not depends on the design and the technology implementing that design. Kevin JenningsArticle: 143580
I have the same question? I am using spartan 3 where a data needs to be captured at 2 ns window. While I have aligned a DCM clock to the middle of the data window, the question is if the internal FF will meet the setup and hold time to caputre the data?(XAPP485)has some info on Tsamp. >A while ago Xilinx introduced the parameter "Tsamp" into the Virtex 4 >data sheet, described as: > "TSAMP Sampling Error at Receiver Pins > This parameter indicates the total sampling error of Virtex-4 > DDR input registers across voltage, temperature, and process. > The characterization methodology uses the DCM to capture > the DDR input registers' edges of operation. These measurements > include: > - CLK0 DCM jitter > - DCM accuracy (phase offset) > - DCM phase shift resolution > These measurements do not include package or clock tree skew." > >This is a big help to people designing high speed source synchronous >interfaces. Does anyone know if there is a similar characterisation for >Spartan 3 (or any other parts, for that matter)? It does not appear in >the data sheet, but there is a tantalising reference to it in ug2565. > >It would be great to see it characterised for all parts. >PS - I'm raising a webcase, but the process is proving a bit slow.. >Nick > > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143581
KJ <kkjennings@sbcglobal.net> wrote: (snip) > Bottom line is that there is no basis for thinking that a latch will > always consume less power than a flip flop. Whether it does or not > depends on the design and the technology implementing that design. Yes. While a latch may consume less power than an edge triggered FF, how much the rest of the circuit consumes is still important. The multi-phase clock is somewhat harder to distribute, and may use more power in its buffers. I mentioned previously the Earle latch which combines one level of logic with the latch circuit, reducing the propagation delay. A design with latches and a three phase clock requires careful balancing of the delays in different parts of the circuit. Well, FF's do, too, but maybe not quite as careful. Also, the current design tools likely won't do the analysis right for transparent latches. -- glenArticle: 143582
On Oct 15, 8:36=A0pm, Al Clark <acl...@danvillesignal.com> wrote: > SpiffyGuy <spiffyguy...@gmail.com> wrote in news:b486eb62-43f9-430b-9f62- > d4805aa74...@j39g2000yqh.googlegroups.com: > > > Hello, > > > Does anyone know of a softcore for either the Analog Devices ADSP-2191 > > or 2181 DSPs? Looks like the 2191's life is only 2 years and I need > > something that is code compatible with the 2181 DSP. > > > Thanks! > > I haven't heard that the 2191 is EOL, but it seems to me that it would be > easier to port code to another DSP that try to duplicate it with a softco= re. > > From strictly a MIPs and peripheral point of view, most of the Blackfin > product line can serve the same purpose. > > From an assembly language perspective, I think it would be easier to port > 218x or 219x code to the SHARC. The ADSP-21371 would be one possibility. = It > has all the peripherals of the 2191 and is much more powerful. It even co= sts > less. > > I learned 218x and 219x code before I learned SHARC assembly. It was a ve= ry > easy transition. > > Al Clarkwww.danvillesignal.com Thanks for the info Al. Our components group at work passed the info on to me and they always want parts that are available for around 8 years. I will double check with Analog Devices to make sure. Unfortunately, we have no budget to port the code so I'm trying to find an easy transition. Our legacy code is from the 2181 so we are now using the 2191 for that reason. A couple other projects that have had similar code migration budget issues have bought softcores (TI DSPs for example) that are cycle accurate, so figured I'd see if anyone knew of one. Appreciate the help! I will look into the Blackfin and SHARC DSPs.Article: 143583
SpiffyGuy <spiffyguy917@gmail.com> wrote: > Our components group at work passed the info on to me and > they always want parts that are available for around 8 years. Then they better buy eight years worth of parts... S.Article: 143584
On Oct 16, 6:02=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > On Oct 16, 12:19=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > Hi, > > I am really interested in the theoritic bases of how a latch circuit > > can replace a flip-flop to save power > > The theoretical basis for how a latch *might* use less power than a > flop is simple physics: > - Logic gates in any technology will consume more power when switching > states because any switching signal will have to charge capacitance on > the chip or board that cannot be completely recovered. > - CMOS logic gates consume significantly more power when they change > states...it's signficantly more during switching mainly because it > consumes so little while static and not switching (although leakage > currents on technology's cutting edge are eroding that one) > > From that one should be able to surmise that: > > - A free running clock consumes more power than one that doesn't free > run. > > And then note that: > > - The latch enable input signal on a latch is typically not free > running > > And conclude that if a flip flop can be replaced by a latch in a > particular application, then it will consume less power than the flip > flop that is clocked by a free running clock. =A0However, if the flip > flop instead is clocked with a gated clock, it won't necessarily > follow that a latch will consume less power. =A0It will depend on the > implementation technology and how the flops and latches are > constructed since it's conceivable that the gated clock might only be > switching the same number of times that the latch enable signal would. > > Bottom line is that there is no basis for thinking that a latch will > always consume less power than a flip flop. =A0Whether it does or not > depends on the design and the technology implementing that design. > > Kevin Jennings Hi Kevin, I want to know how Intel uses latches to replace its FFs. They must use less power and less time delay, and have a clever circuit, maybe a new latch circuit, and reliable calculation method and tools to transfer a FF popular design into a latch-filled design. I have searched all patents with keyword "Earle latch", but found no match. Likely Intel or a small company may have invented a new latch circuit which can be used to replace FFs to reduce power and timing delay. Those are the key points I am interested in. WengArticle: 143585
Weng Tianxiang <wtxwtx@gmail.com> wrote: (snip) > I have searched all patents with keyword "Earle latch", > but found no match. The Earle Latch was by IBM in the 1960's. It at least went into the 360/91, a pretty fast machine for the time. I believe it has a 60ns clock and does 64 bit floating point multiply in six clock cycles. The logic is pretty much what we call ECL, but built out of discrete transistor glued onto pieces of ceramic. (IBM calls it ASLT.) I don't know about patents, but it is described in many books on pipelined processors. The 360/91 was for many years the favorite of many discussions on pipelined ALUs. -- glenArticle: 143586
On Oct 16, 10:01=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > I want to know how Intel uses latches to replace its FFs. So maybe you should ask someone at Intel...a company that bigs probably has someone who trolls the FPGA newsgroups, but that's not the first place I'd consider looking for them...nor would I expect them to divulge any juicy secrets in such a forum. Perhaps you haven't noticed the name of this one is comp.arch.FPGA. The majority of folks out here are *users* of flip flops and latches, they do not *design* the flip flops and latches. Nor do these folks generally design the infrastructure that makes use of latches in FPGAs a dicey proposition, but use of flip flops the standard practice to get to a stable design and product. > They must use less power and less time delay, and have a clever > circuit, maybe a new latch circuit, and reliable calculation method > and tools to transfer a FF popular design into a latch-filled design. > They must? You assume an awful lot there. The prime mover for most companies is generally profit. > I have searched all patents with keyword "Earle latch", but found no > match. > Maybe Earle put it into the public domain without a patent. To help you out, try the link below. It seemed to produce some relevant matches to peruse...not every good idea can be found at the Patent and Trademark Office. http://lmgtfy.com/?q=3D%22Earle+latch%22 > Likely Intel or a small company may have invented a new latch circuit > which can be used to replace FFs to reduce power and timing delay. > Not necessarily. An improved latch circuit would likely also result in an improved flip flop circuit so both would benefit. Perhaps you should study up on the logic that implements flops and latches. You seem to be oblivous to the fact that not all edge triggered flip flops can functionally be replaced with latches even though it's been pointed out several times. > Those are the key points I am interested in. > I've kinda lost my interest...but good luck on what you find, gaining knowledge is almost always a good thing. KJArticle: 143587
Earlier, I wrote: > > A bug later on in the flow ( e.g. Bitgen ) could have this effect >on the hardware yet still show the terminations in the FPGA editor. > Thinking about this further, it occurred to me that what you are most likely chasing is not an obscure bug in Bitgen that broke the differential terminators, but rather a simple mistake in your IBIS simulation. The HyperLynx/Xilinx DIFF_TERM problems that I linked to earlier are fairly old; if you are doing your simulation of an LVDS_25_DT input with a version of HyperLynx >=3D v7.5, it is ALREADY MODELING the input termination of the V4. If you then added a HyperLynx "quick terminator" thinking that it was NOT modeling the on-die termination, your simulation now has an EXTRA termination where your actual board does not. So by adding one to your board, your board better matches the sim... --------------------- As I pointed in that 2006 ADS572x thread, linked to in my earlier post, the output drivers of these particular DACs are high impedance current sources, without any back termination, capable of sub-200 ps edges. It is extremely hazardous to the health of your data to connect them to a Xilinx FPGA having 10 pf Cin (single ended) without providing some sort of back termination. TI's ADS527x datasheet has a paragraph stating exactly that: http://focus.ti.com/lit/ds/symlink/ads5273.pdf [ ads5273.pdf, Rev D, Jan. 2009, page 23 ] " " The single-ended output impedance of the LVDS drivers is very " high because they are current-source driven. If there are " excessive reflections from the receiver, it might be necessary " to place a 100=E2=84=A6 termination resistor across the outputs of the " LVDS drivers to minimize the effect of reflections " --------------------- Many of TI's newer LVDS A/D's now include a selectable back termination on the LVDS outputs. The ADS6423 datasheet has a nice set of plots showing some data waveforms with/without the back termination switched in. ads6423.pdf, Rev A, June 2007, page 56, figures 79 & 80 http://focus.ti.com/lit/ds/symlink/ads6423.pdf Looking at Figure 79, is that what you meant by "RC-like Curves" ??? BrianArticle: 143588
Weng Tianxiang wrote:
> I want to know how Intel uses latches to replace its FFs.
Probably some version of of this:
http://en.wikipedia.org/wiki/File:Negative-edge_triggered_master_slave_D_flip_flop.png
The Actel 1010 did the same thing.
A latch used one logic block.
A D-flop used two.
Actel patented their implementation as well.
-- Mike Treseler
Article: 143589Is there any interest in a group buy & design of a Xilinx fpga board ? I would like a fairly large Spartan FPGA + lots of IO expansion + low cost $200 - $250 usd. The exisiting FPGA boards on the market seems either too expensive or small FPGA or too little expansion potential. The idea is to get a high capacity & low cost expandable board via a group buy to save on the PCB + assembly. Probably only for US participants.Article: 143590
On Oct 16, 3:14=A0am, Michael Schwingen <news-1235297...@discworld.dascon.de> wrote: > On 2009-10-15, rickman <gnu...@gmail.com> wrote: > > > Did you give them your email address? =A0Is this spam or you just don't > > like the fact that it is much harder for them to meet the regulations > > of dozens of countries than it is to only make the offer in the single > > country where most of their business comes from? > > On a related note: is it possible Xilinx is giving out mail addresses to > other companies? > > I use separate disposable mail addresses for each web registration, and I > just got spam from a Mentor Graphics user group, sent to the mail address > that I only used at xilinx.com. Guess I'll have to disable that account o= n > my mail server. > > cu > Michael I had that happen once or twice as well. I don't think they are literally selling the list. I think it is more of a sales channel thing. I believe the time it happened to me, I got spam from a rep firm who handled Xilinx, but also tools. I think they took some liberties with the usage of the list and sent tool advertisements to everyone on the Xilinx list. In your case, it would seem they pulled your address from their forum. I know that Xilinx will pull email addresses from anywhere, including support calls! I have a couple of email addresses that I have given only to Xilinx support that they send advertising to. RickArticle: 143591
On Oct 16, 7:29=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > rickman <gnu...@gmail.com> wrote: > > (snip) > > > I wonder why they do that. =A0I have only seen bit zero as the most > > significant bit in a handful of designs and I expect the first was > > done for fairly obscure reasons and the rest were done to be > > compatible. =A0Did the uBlaze need to be compatible with something in > > this regard? > > I don't know about the design, but all the documentation for IBM > S/360, S/370, ESA/390, and z/Architecture numbers the bits with 0 > as the MSB. =A0That complicates the description change from 32 bit > (through ESA/390) to 64 bit (z/Architecture), but otherwise it is > more consistent with big-endian byte order. > > For an architecture without bit addressing it isn't so obvious > that the documentation needs to be consistent with the byte ordering, > but sometimes consistency is nice. > > As far as uBlaze and big endian, it would seem that [8*n,8*n+7] > where n is a byte number would be somewhat more convenient than > the other way around. > > -- glen I don't follow that at all. N downto 0 numbering allows the weight of the bit to be 2**N. That is the overriding factor for me. Switching it around to "be consistent" with byte addressing when you don't have bit addressing seems pretty low on the priority list. RickArticle: 143592
rickman <gnuarm@gmail.com> wrote:
(snip of long explanation before I wrote)
>> As far as uBlaze and big endian, it would seem that [8*n,8*n+7]
>> where n is a byte number would be somewhat more convenient than
>> the other way around.
> I don't follow that at all. N downto 0 numbering allows the weight of
> the bit to be 2**N. That is the overriding factor for me. Switching
> it around to "be consistent" with byte addressing when you don't have
> bit addressing seems pretty low on the priority list.
Which seems simpler and more natural:
[8*n,8*n+7] or [31-8*n,24-8*n]
I do know that it took me longer to write the second one and
to verify that it did what I wanted it to do.
Or are you asking about the preference of big-endian for
processor design?
-- glen
Article: 143593On Oct 17, 8:21=A0am, "nwreader" <no...@home.com> wrote: > Is there any interest in a group buy & design of a Xilinx fpga board ? > I would like a fairly large Spartan FPGA + lots of IO expansion + low cos= t > $200 - $250 usd. > The exisiting FPGA boards on the market seems either too expensive or sma= ll > FPGA or too little > expansion potential. > > The idea is to get a high capacity & low cost expandable board via a grou= p > buy to save on the > PCB + assembly. Probably only for US participants. hi S3ADSP board from trenz may actually fit your requirements those modules are not yet in their online shop, but you can see high res photos of the modules in Antti-Brain august 2008 issue first units are actually sold, and the modules should be very soon be available for general buy also, the main goal for that board was low cost lots of resources, thats also the reason for low cost connectors being used - 1.27mm headers not the hirose as other modules from trenz a baseboard will also be available with breakout of the module to 4 x 2x20 100mil headers AnttiArticle: 143594
nwreader <noone@home.com> wrote: > Is there any interest in a group buy & design of a Xilinx fpga board ? > I would like a fairly large Spartan FPGA + lots of IO expansion + low cost > $200 - $250 usd. > The exisiting FPGA boards on the market seems either too > expensive or small FPGA or too little expansion potential. One that I have wondered about for a while: Can the Digilent S3E board take a larger FPGA than the one it comes with? That wouldn't require a new board design, though it does require unsoldering and soldering. -- glenArticle: 143595
On Oct 17, 11:56=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > nwreader <no...@home.com> wrote: > > Is there any interest in a group buy & design of a Xilinx fpga board ? > > I would like a fairly large Spartan FPGA + lots of IO expansion + low c= ost > > $200 - $250 usd. > > The exisiting FPGA boards on the market seems either too > > expensive or small FPGA or too little expansion potential. > > One that I have wondered about for a while: > > Can the Digilent S3E board take a larger FPGA than the one > it comes with? =A0That wouldn't require a new board design, though > it does require unsoldering and soldering. > > -- glen what board you mean? digilent s3e board was available with s3e-1600 what is the largest s3e for a while i think they stopped selling it AnttiArticle: 143596
Antti <antti.lukats@googlemail.com> wrote: > On Oct 17, 11:56?am, I wrote: >> nwreader <no...@home.com> wrote: >> > Is there any interest in a group buy & design of a Xilinx fpga board ? >> > I would like a fairly large Spartan FPGA + lots of >> > IO expansion + low cost $200 - $250 usd. >> > The exisiting FPGA boards on the market seems either too >> > expensive or small FPGA or too little expansion potential. >> One that I have wondered about for a while: >> Can the Digilent S3E board take a larger FPGA than the one >> it comes with? ?That wouldn't require a new board design, though >> it does require unsoldering and soldering. > what board you mean? > digilent s3e board was available with s3e-1600 what is the > largest s3e for a while i think they stopped selling it As far as I know, it comes only with the S3E-500. Otherwise, it would seem a fine board for the OP. -- glenArticle: 143597
On Oct 17, 2:28=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > rickman <gnu...@gmail.com> wrote: > > (snip of long explanation before I wrote) > > >> As far as uBlaze and big endian, it would seem that [8*n,8*n+7] > >> where n is a byte number would be somewhat more convenient than > >> the other way around. > > I don't follow that at all. =A0N downto 0 numbering allows the weight o= f > > the bit to be 2**N. =A0That is the overriding factor for me. =A0Switchi= ng > > it around to "be consistent" with byte addressing when you don't have > > bit addressing seems pretty low on the priority list. > > Which seems simpler and more natural: =A0 > > =A0 =A0 =A0 =A0 =A0 [8*n,8*n+7] =A0 =A0or =A0 =A0[31-8*n,24-8*n] > > I do know that it took me longer to write the second one and > to verify that it did what I wanted it to do. =A0 > > Or are you asking about the preference of big-endian for > processor design? I don't know what the above equations are for. I have never used either forms for anything that I can recall. I address bits in words all the time in VHDL. I often use notation like (foo'high-bar'high downto 0) which gives the lsbs of foo where bar is a shorter length than foo. Or conversely (foo'high downto bar'high) for the msbs in foo that are wider than bar. I have never used any notation like you have shown. RickArticle: 143598
Hi Antti, everyone, Antti wrote: > S3ADSP board from trenz may actually fit your requirements > those modules are not yet in their online shop, but you can > see high res photos of the modules in Antti-Brain august 2008 issue > first units are actually sold, and the modules should be very soon > be available for general buy also, the main goal for that board was > low cost lots of resources, thats also the reason for low cost > connectors being used - 1.27mm headers not the hirose as other > modules from trenz > > a baseboard will also be available with breakout of the module > to 4 x 2x20 100mil headers That seems to be an interesting development, and it's featured on the frontpage of their website now, but the links all still go to the 'old' series of boards they make. You can find it in their webshop, but the price is quite similar to the Xilinx S3ADSP board which also features 1Gb/s ethernet, VGA and a few other goodies. I'm interested if they'll offer any high-speed (>100Mb/s) ADCs to go on those connectors, and Gb/s ethernet would be nice too. Regards, Paul Boven.Article: 143599
rickman <gnuarm@gmail.com> wrote:
(snip, then I wrote)
>> Which seems simpler and more natural: ?
>> ? ? ? ? ? [8*n,8*n+7] ? ?or ? ?[31-8*n,24-8*n]
>> I do know that it took me longer to write the second one and
>> to verify that it did what I wanted it to do. ?
>> Or are you asking about the preference of big-endian for
>> processor design?
>
> I don't know what the above equations are for. I have never used
> either forms for anything that I can recall.
That is the verilog from. Most of the time I can read VHDL and
get the right idea, but I have never written it. (I did some
VHDL to verilog conversions that worked, never the other way.)
> I address bits in words all the time in VHDL. I often use notation
> like (foo'high-bar'high downto 0) which gives the lsbs of foo where
> bar is a shorter length than foo. Or conversely (foo'high downto
> bar'high) for the msbs in foo that are wider than bar. I have never
> used any notation like you have shown.
OK,
(8*n upto 8*n+7) or (31-8*n downto 24-8*n)
I believe in some cases verilog can do that with a variable n,
otherwise it can defintely do it with a constant n. Also, note
that the one on the right depends on knowing the width of the
word, while the one on the left does not.
-- glen
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