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A while ago Xilinx introduced the parameter "Tsamp" into the Virtex 4 data sheet, described as: "TSAMP Sampling Error at Receiver Pins This parameter indicates the total sampling error of Virtex-4 DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew." This is a big help to people designing high speed source synchronous interfaces. Does anyone know if there is a similar characterisation for Spartan 3 (or any other parts, for that matter)? It does not appear in the data sheet, but there is a tantalising reference to it in ug2565. It would be great to see it characterised for all parts. PS - I'm raising a webcase, but the process is proving a bit slow.. NickArticle: 111376
Product line of ACTEL Radiation Hardened FPGA's line : http://www.actel.com/products/aero/rtaxs.aspx RH Design considerations : http://www.actel.com/documents/Des_Tech_RH_AN.pdf About voting circuit : http://www.actel.com/documents/SynplifyRH_AN.pdf Regards, Krishna Janumanchi MikeD wrote: > Does anyone know of something more like a "how to" or real design > guidelines for designing rad-hard systems, for system/board-level (ADC, > DAC, power supplies, etc) design, as well as for FPGA and ASIC > hardware? > > I've found a lot of information around that gave specific numbers about > some chips, but I wasn't able to actually understand what the reports > were saying. I know that for an FPGA, I should either use a flash or > antifuse based chip, or otherwise use a chip with configuration CRC > checking and reloading, but how do I select parts like power supplies, > ADC/DACs, and RAMs? Even if my FPGA or ASIC design is solid, I'm > worried that I'm going to end up shooting myself in the foot on the > rest of the system. > > And for FPGAs and ASICs, what are the design considerations? How would > I implement a voting circuit for triple-redundancy in general? And how > would I avoid the possability of an error in the voting circuit? > > Also, if anyone knows of any good books, papers, > courses/classes/training, or even consultants, please let me know. > > Thanks, > MikeArticle: 111377
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:uhcxi890m.fsf@trw.com... > "KJ" <kkjennings@sbcglobal.net> writes: > >> "Martin Thompson" <martin.j.thompson@trw.com> wrote in message >> news:ulkmv8mwx.fsf@trw.com... >> > "KJ" <Kevin.Jennings@Unisys.com> writes: >> > >> > >> > More like it was an Altera-driven "standard" that Xilinx never >> > supported, so it never got to be vendor independent. >> > >> But it is a standard issued by a recognized body. But I've yet to hear >> what >> is soooo burdensome about LPM that it couldn't be supported...'specially >> since there aren't that many 'useful' functions in there to begin >> with. > > That's true - my *impression* at the time (which was around 2000) was > that Xilinx didn't want to make migration between vendors too easy. > That's just my impression mind, I don't know what actually went on. > Based on what I read around the LPM website. > >> And technically speaking I believe Xilinx 'does' support LPM, but >> from what I hear, not very well. >> > > That's interesting - any idea how? No, just from the (possibly misguided) impression that I got over the years. Googling would seem to indicate that you're correct that they don't have any support for it directly but Synplify does support LPM, so you can get LPM on X by using S (which is what I was thinking since I do have and use S). Googling a bit more and you'll see that Lattice and Actel both claim to support it. One of the hits that I got on the Xilinx site gives the following two defintions for 'LogiBLOX' and 'LPM'. The word for word match in the definitions would seem to indicate that something petty (or perceived protection of the turf) is keeping them apart. http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf LogiBLOX - Formerly called X-Blox. Library of logic modules, often with user-definable parameters, like data width. Very similar to LPM. LPM - Library of Parameterized Modules. Library of logic modules, often with userdefinable parameters, like data width. Very similar to LogiBlox. > >> We should be way beyond standardizing on things as low level as the LPM >> stuff....but we're not.... >> > > In some ways we are - I've never instantiated an LPM_COUNTER, an > incrementing variable does the job for me :-) > Yeah....in many ways I don't like holding up LPM since most of what is in there is nothing I would instantiate simply because it is (and always has been) too low level and easier to infer directly in the code. It is an example though of a standard that had the basic idea of what I'd like to see happening....just not high enough functionality and didn't get updated to add new stuff to match what is going on in the world. KJArticle: 111378
> > Is there a good reference for the types of IC packages and their effects > > on SI? > > Good, now what is SI ? is it shorthand for silicon? or is it the si units of measurements.Article: 111379
Hi all, We had some strange behaviour with our project today. We have been using Mentor Graphics HDL Maker, ModelSim and Quartus for our university project. The code simulated fine in ModelSim, everything was perfect. However when synthesised onto the Flex10k device we had everything worked fine except for one signal. We revised our code and retried various approaches all with the same result. Next we combed through the output of the synthesiser to try and find any relevant errors. We had a simple slow speed project so most of the errors were from timing violations. As a last approach, which should probably have been a first approach, we took all of the signals to output pins on the device so we could observe their state. With that simple change in HDLMaker, just adding three more output ports and wiring them up to the existing signals between modules the difficult signal started working. I assume this is something to do with optimisation in the synthesiser. But I don't think it should have done it. Has this happened to anyone else? What can I do to prevent it happening again? Is it because of bad coding style? What errors or warnings does Quartus give when it's done something like this? Try to take it easy on me, I am a university student but this is for my own knowledge not any homework question :-) Thanks JoelArticle: 111380
Joel If your signals are not used or the synthesiser thinks they are static then it might remove the signal completely or partially. Some things to check related to this are: (1) Check that your sensitivity lists are complete. Very often I have seen variance in the treatment of these lists with many synthesisers ignoring the fact they are incomplete. (2) Other things to look at are buried I/O tristates. Some synthesisers / tool combinations don't correctly implement I/O tristates if they are not at the top level of a VHDL / Verilog design. Have a look at the synthesis report for some more clues too. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development Board. http://www.enterpoint.co.uk <joel.pigdon@gmail.com> wrote in message news:1162469289.448809.163230@h54g2000cwb.googlegroups.com... > Hi all, > We had some strange behaviour with our project today. We have been > using Mentor Graphics HDL Maker, ModelSim and Quartus for our > university project. The code simulated fine in ModelSim, everything was > > perfect. However when synthesised onto the Flex10k device we had > everything worked fine except for one signal. We revised our code and > retried various approaches all with the same result. Next we combed > through the output of the synthesiser to try and find any relevant > errors. We had a simple slow speed project so most of the errors were > from timing violations. > As a last approach, which should probably have been a first approach, > we took all of the signals to output pins on the device so we could > observe their state. With that simple change in HDLMaker, just adding > three more output ports and wiring them up to the existing signals > between modules the difficult signal started working. > I assume this is something to do with optimisation in the synthesiser. > But I don't think it should have done it. > Has this happened to anyone else? > What can I do to prevent it happening again? Is it because of bad > coding style? > What errors or warnings does Quartus give when it's done something like > > this? > Try to take it easy on me, I am a university student but this is for my > > own knowledge not any homework question :-) > Thanks > Joel >Article: 111381
Hello, I can not simulate "pipelined divider v3.0" .My verilog code is below: `timescale 1ns / 1ps module divide(dividend,divisor,quot,remd,clk,rfd,ce); input [7 : 0] dividend; input [7 : 0] divisor; output [7 : 0] quot; output [7 : 0] remd; input clk; output rfd; input ce; d1 div1(dividend,divisor,quot,remd,clk,rfd,ce); endmodule when i synthesize this code xst gives no error but i cant simulate this code. when i try to simulate it, i take 2 errors ERROR:HDLParsers:3482 - Could not resolve instantiated unit SDIVIDER_V3_0 in Verilog module work/d1 in any library ERROR:Simulator:198 - Failed when handling dependencies for module test3 May someone help me about it please. How can I work it?Article: 111382
KJ wrote: > "Peter Alfke" <peter@xilinx.com> wrote in message > news:1162418895.253069.240680@f16g2000cwb.googlegroups.com... > >I remember the birth of the 22V10 (it's an AMD product, not MMI's) > > It had the gestation period of an elephant, and it almost killed the > > design engineers. Too complicated... > > Times have changed. > > Peter Alfke > > Yes, those 'V' parts were pretty versatile (hence the 'V' in 16V8, 22V10) > for those of us around at the birth of the 16R4, 16R6 and 16R8 when great > thought had to be applied to decide whether an output should be clocked or > combinatorial...and if you got it wrong you had to rewire the circuit board > to move it to the appropriate pin....well, that and having to remove and > pitch the part because it was fuse based one time programmable. > > KJ...feeling ooooooold now....where's my hot cocoa? Yes the 16R8 may seem like an incredibly simple device, but it was such an improvement over the TTL MSI devices we were otherwise using at the time. PALs seemed like a gift from the Gods. Oddly enough I am currently working on a design where I am pushing the customer to let me do it in discrete logic rather than a CPLD. The functions are pretty simple and it only takes eight or so logic chips and a couple of relay drivers. But to do it in a CPLD and have the required 40% reserve space means I have to go to a relatively huge 100 pin TQFP which just won't fit in the allotted space on the board. I could split it into two chips which would fit better, but I still am not sure I would have the required 40% reserve capacitiy and would have to add a JTAG connector to allow updates and factory programming. So discrete logic is not quite yet dead...Article: 111383
I'm receiving a strange warning in ISE for a Virtex 4. I've been seeing new warnings and infos using the new DCMs. Is it safe to ignore this warning in MAP? I couldn't find anything related in the knowledge base. This autocal appears to be generated for speed improvement? Help is much appreciated. Thanks, -Brandon <SNIP> WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol "clkgen_inst/usrclk_dcm_clk0_bufg_inst" (output signal=clkgen_inst/usrclk) has a mix of clock and non-clock loads. The non-clock loads are: Pin I0 of DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/m d/_n00001 Pin I1 of DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/m d/_n00011 </SNIP>Article: 111384
I'm also receiving this similar warning: <SNIP> WARNING:PhysDesignRules:372 - Gated clock. Clock net DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/C LKOUT is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. </SNIP> Brandon Jasionowski wrote: > I'm receiving a strange warning in ISE for a Virtex 4. I've been seeing > new warnings and infos using the new DCMs. Is it safe to ignore this > warning in MAP? I couldn't find anything related in the knowledge base. > This autocal appears to be generated for speed improvement? > > Help is much appreciated. > > Thanks, > -Brandon > > <SNIP> > WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG > symbol > "clkgen_inst/usrclk_dcm_clk0_bufg_inst" (output > signal=clkgen_inst/usrclk) > has a mix of clock and non-clock loads. The non-clock loads are: > Pin I0 of > > DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/m > d/_n00001 > Pin I1 of > > DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/m > d/_n00011 > </SNIP>Article: 111385
Hi Tim,
"Tim" <gueneysu@crypto.rub.de> wrote in message
news:1162455279.194044.12920@k70g2000cwa.googlegroups.com...
>
> Do you have a good idea how I can pass on the 33rd carry bit (or upper
> bit if sign extended) between the computations and DSP slices without
> using the fabric? It would be so easy, if the P[47]/PCIN[47] carry
> logic wouldn't be inverted...but an inverted carry is probably quite
> useless for my desire.
Nope, it's pretty easy.
Take your two 32-bit numbers. Pad one of them out to 48 bits with 0s, and
pad the other out to 48 bits with 1s. Now add them together.
(*) If there is no carry out of the 32nd stage, then the top 16 bits of the
addition will all work out as 0 + 1 = 1, so P[47] will be 1 (the inverse of
0, which is what you want).
(*) If there *is* a carry , it will propagate all the way to the 48th bit
and the output P[47] will be 0 (the inverse of 1, which is what you want).
Rinse, repeat as required.
> BTW: what is the reason for the inverted P[47] carry logic?
Symmetric rounding. It's not described very well in the V4 handbook but it's
sort of hinted at...
Cheers,
-Ben-
Article: 111386Hi, Stefan! I have similar situation, but I prefer do not download project to FPGA without comprehensive post-PAR simulation results, ;), so I stoped at no "channel_up" after 200 us post-par simulation. Behavior simulation is OK. Now try to undestand problem, but not found solution. Did you any progress in your issue? P.S. I've used newest 2.5 version. Perhaps you have to do same.Article: 111387
Hi! I built aurora core 2.5 (32 bit, 1 lane, stream) for v4fx60. Behaviorial simulation of ref desing is ok. But when I create&implement ISE8.2iSP3IP2 project with sample_aurora.ucf supplied with core I have problem with post-route simulation this core - channel_up signal is still low after enough (IMHO) time. Have anyone successful experience with post-routed sim or/and hardware test of aurora cores (v.2.4/2.5)? Thanks.Article: 111388
Thanks for the links Symo, I was hoping for some rules of thumb, but I guess I could look at a few datasheets of different packages and create my own. SI stands for signal integrity. ---Matthew Hicks <nnn> wrote in message news:4549d68c$1_3@mk-nntp-2.news.uk.tiscali.com... >> > Is there a good reference for the types of IC packages and their >> > effects >> > on SI? >> > > > Good, now what is SI ? is it shorthand for silicon? or is it the si units > of measurements. > > From laurent.pinchart@skynet.be Thu Nov 02 07:56:38 2006 Path: newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed.freenet.de!border2.nntp.ams.giganews.com!nntp.giganews.com!newsfeeder.wxs.nl!hoboe2bl2.telenet-ops.be!kramikske.telenet-ops.be!nntp.telenet.be!skynet.be!newspost001!tjb!not-for-mail Message-Id: <454a1433$0$30044$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: Xilinx ISE Webpack - Any usable simulator for the Linux platform ? Newsgroups: comp.arch.fpga Date: Thu, 02 Nov 2006 16:56:38 +0100 References: <4549b468$0$21505$ba620e4c@news.skynet.be> <4549baf0$1_1@x-privat.org> User-Agent: KNode/0.10.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 42 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 980c70f6.news.skynet.be X-Trace: 1162482739 news.skynet.be 30044 194.78.198.49:36960 X-Complaints-To: usenet-abuse@skynet.be Xref: prodigy.net comp.arch.fpga:122365 Hi Antonio, > I am very happy with ghdl, i almost use only that. Also for the post > trans/map/p&r simulations. Does it work with Xilinx cores/primitives ? Do you know of any howto that describes how to setup a Xilinx project (VHDL source files + core/primitives) for simulation with ghdl ? Laurent Pinchart > Laurent Pinchart ha scritto: >> Hi everybody, >> >> I need to simulate VHDL code using the ISE 8.2i Webpack on Linux. After >> some investigation, I found out that two simulators were available: >> >> - ModelSim, which I have some experience with, would cover all my needs, >> but the ModelSim Xilinx Starter edition only runs under Windows. >> >> - ISE Simulator, which is pretty much unusable from what I've seen so >> far. The simulation is not interactive (although I could live with that), >> but I haven't been able to watch internal signal values. It seems only >> the entity ports can be displayed, which makes debugging much more >> difficult. >> >> Is there any proper simulation solution for the Linux platform ? I know >> ModelSim has a Linux version, but that's way too expensive for personal >> projects. Is there any way to run ModelSim Xilinx Starter edition under >> Linux ? I tried running it in Wine, but it complained about not being >> able to checkout a valid license, even though the flexlm diagnosis tool >> reports no problem at all. >> >> Any help would be appreciated. Developing VHDL code without a simulator >> is near to impossible. >> >> Best regards, >> >> Laurent Pinchart >>Article: 111389
On Wed, 1 Nov 2006 10:32:30 -0000, "Ben Jones" <ben.jones@xilinx.com> wrote: >There may be a few scenarios in which register duplication really is a good >thing, but in my experience synthesis tools don't always find them. So I >tend to just leave this "feature" turned off. I think you'd normally use duplication to reduce routing congestion. On a chip I was on recently, the vendor wouldn't take a netlist that had any fanout cones with more than 2500 endpoints, and register duplication was the only practical fix. I used Teraform (deceased?) to measure the cones. Evan >(Whoops, off topic...) >Article: 111390
Hi, I am facing negative slack issue in timing analysis. The timing analysis report is as foolows: From: BufferFul2:CLK To: RCounter2[8]:D data required time 8.454 data arrival time 14.448 slack -5.994 Please suggest me for the following: 1. What are the methods to avoid negative slack? 2. How to reduce the delay caused by 'net'? 3. How to reduce the delay caused by 'cell'? 4. How to reduce the setup time of FF? 5. How to choose FF with fast CLK to Q delay? Advice me about the documents/useful notes are available in net. Thanks in advance. Regards, Himassk.Article: 111391
I'm writing a software for microblaze soft processor (Spartan 3E Starter Kit) and I have a few questions regarding the using of memory. The first question is where my code is running? The starter kit has an external 64MB DDR memory and internal local memory (Use BRAM). When I download the bit stream to the FPGA, where is the program running? It seems it is running in the local memory. Since the local memory is not big enough, for large size elf it should be running inside the DDR. I faced the error "region ilmb_cntlr_dlmb_cntlr is full" and I guess it's caused by the samll size local memory. Can anybody tell me how I can make my program run from the DDR? Do I need to develop a BSP for that? Normally the tutorial tell us the "Mark to Initialize BRAMs", that why I guess the code is downloaded to the BRAM instead of the external DDR. What's the real meanning behind this step? It seems the only method to update the code on FPGA is re-download the bit stream file. However, since the hardware has been fixed and we don't change the hardware much, is there a method that we can only update the software part without touching the whole bit file? Thanks a lot. JJArticle: 111392
"Evan Lavelle" <eml@nospam.uk> wrote in message
news:b77kk2hrrc8eks4lm668mnvi4ht9nbgp1h@4ax.com...
>
> I think you'd normally use duplication to reduce routing congestion.
> On a chip I was on recently, the vendor wouldn't take a netlist that
> had any fanout cones with more than 2500 endpoints, and register
> duplication was the only practical fix. I used Teraform (deceased?) to
> measure the cones.
Register duplication leads to more nets in the final design, not fewer, so
it's not usually going to do much for congestion. However, for these
high-fanout signals, it does make placement easier (because there are fewer
rubber-bands pulling the driving element around the die).
If I had a net with a fanout greater than a few hundred, and it wasn't a
clock or a reset, I'd probably do a bit of redesign at a higher level before
resorting to replication. :)
Cheers,
-Ben-
Article: 111393you posted in the wrong branch!!Article: 111394
On 29 Oct 2006 02:23:57 -0800, "Davy" <zhushenli@gmail.com> wrote: >Hi all, > >When studying SystemVerilog, some book said 'virtual' is used to get >the reference of the interface. But why the language not use 'ref' to >get interface reference? And what's 'virtual interface' actually mean? Don't get me started... <rant> "virtual interface" is a really stupid name; as you correctly say, "ref interface" would have been far more sensible. However, it's too late now and we're stuck with it. </rant> A "virtual interface" (or, simply, a "virtual") is just a variable that contains a reference to an existing interface instance. That reference can be moved around dynamically so that it can point to different interface instances at different times during the simulation. In practice, classes that need to talk to interfaces will usually do so via a variable of "virtual interface" type. This makes it possible for class objects (and, in particular, a test environment) to choose *at run time* how they connect to the device under test. Without virtual interfaces, all the connectivity is determined statically at elaboration time, and therefore can't be randomized or reconfigured. The VMM book has clear descriptions of how to use "virtual" to access components of an interface with the help of a clocking block in the interface, passed through a modport of that interface. It sounds complicated, but in practice it's easy to use and works well. It gives you clean isolation between a class-based testbench, running in a program block, and a device-under-test and its test harness, written in modules. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 111395
that's because there is no verilog module in the library. When you coregen, set the project to build a "structural" model--this will generate a verilog model of the divider using Xilinx primitives and you can simulate it just using a verilog simulator. Terry Brown On Thu, 02 Nov 2006 05:07:30 -0800, hikmetkoca wrote: > Hello, > > I can not simulate "pipelined divider v3.0" .My verilog code is below: > > `timescale 1ns / 1ps > > module divide(dividend,divisor,quot,remd,clk,rfd,ce); > > input [7 : 0] dividend; input [7 : 0] divisor; output [7 : 0] quot; > output [7 : 0] remd; input clk; output rfd; input ce; > > d1 div1(dividend,divisor,quot,remd,clk,rfd,ce); > > endmodule > > when i synthesize this code xst gives no error but i cant simulate this > code. when i try to simulate it, i take 2 errors > > ERROR:HDLParsers:3482 - Could not resolve instantiated unit > SDIVIDER_V3_0 in Verilog module work/d1 in any library > ERROR:Simulator:198 - Failed when handling dependencies for module > test3 > > May someone help me about it please. How can I work it?Article: 111396
"himassk" <himassk@gmail.com> wrote in message news:1162487765.096445.237730@m73g2000cwd.googlegroups.com... > Hi, > > I am facing negative slack issue in timing analysis. > > The timing analysis report is as foolows: > > From: BufferFul2:CLK > To: RCounter2[8]:D > > data required time 8.454 > data arrival time 14.448 > slack -5.994 > > Please suggest me for the following: > 1. What are the methods to avoid negative slack? > Slow down the clock. > > 2. How to reduce the delay caused by 'net'? > Make the net shorter. > > 3. How to reduce the delay caused by 'cell'? > Reduce the circuit temperature. > > 4. How to reduce the setup time of FF? > Increase the supply voltage. > > 5. How to choose FF with fast CLK to Q delay? > Very carefully. > > Advice me about the documents/useful notes are available in net. > Thanks in advance. > > Regards, > Himassk. > HTH, Syms. :-)Article: 111397
himassk, Rather than be "cute" or attempt humor, I will take you seriously: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iCountryID=1&iLanguageID=1&sTechX_ID=al_slack&BV_SessionID=@@@@1488485784.1162493159@@@@&BV_EngineID=ccccaddjefdlgfmcefeceihdffhdfkf.0 or http://tinyurl.com/yjj64v http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=&sGlobalNavPick=&sSecondaryNavPick=&multPartNum=1&sTechX_ID=kc_priorities or http://tinyurl.com/yebs4m http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=&sGlobalNavPick=&sSecondaryNavPick=&multPartNum=1&sTechX_ID=rw_tim_closure_61i or http://tinyurl.com/yej4se Austin himassk wrote: > Hi, > > I am facing negative slack issue in timing analysis. > > The timing analysis report is as foolows: > > From: BufferFul2:CLK > To: RCounter2[8]:D > > data required time 8.454 > data arrival time 14.448 > slack -5.994 > > Please suggest me for the following: > 1. What are the methods to avoid negative slack? > 2. How to reduce the delay caused by 'net'? > 3. How to reduce the delay caused by 'cell'? > 4. How to reduce the setup time of FF? > 5. How to choose FF with fast CLK to Q delay? > > Advice me about the documents/useful notes are available in net. > Thanks in advance. > > Regards, > Himassk. >Article: 111398
Steve wrote: > I'm writing a software for microblaze soft processor (Spartan 3E Starter > Kit) and I have a few questions regarding the using of memory. > > The first question is where my code is running? The starter kit has an > external 64MB DDR memory and internal local memory (Use BRAM). When I > download the bit stream to the FPGA, where is the program running? It seems > it is running in the local memory. > > Since the local memory is not big enough, for large size elf it should be > running inside the DDR. I faced the error "region ilmb_cntlr_dlmb_cntlr is > full" and I guess it's caused by the samll size local memory. Can anybody > tell me how I can make my program run from the DDR? Do I need to develop a > BSP for that? > > Normally the tutorial tell us the "Mark to Initialize BRAMs", that why I > guess the code is downloaded to the BRAM instead of the external DDR. What's > the real meanning behind this step? > > It seems the only method to update the code on FPGA is re-download the bit > stream file. However, since the hardware has been fixed and we don't change > the hardware much, is there a method that we can only update the software > part without touching the whole bit file? > > Thanks a lot. > > JJ You can update the bitstream by simply recompiling your project, and then running "Device Configuration -> Update_Bitstream" (or clicking the BRAM INIT button). This will update the contents of the BRAM's. However, if your application is so large that it won't fit in internal memory, this won't do much. Note, you can tell where your code is located by running the generate linker script on the project you are interested in. If your code is located in an external memory, you will need to use XMD to load it for debugging.Article: 111399
On 30 Oct 2006 19:21:14 -0800, "gallen" <arlencox@gmail.com> wrote: >My point to add to this is that many older engineers have difficulty >grasping new ways of operating. Convincing experienced engineers that >synthesis tools actually work can be like pulling teeth sometimes. >Just the other day, some engineers were ranting about some code that a >contractor wrote that was very very behavioral. They were complaining >about how that was killing timing and adding 10s to 100s of levels of >logic. They hadn't tried it out. I ran it through the synthesizer and >it was *faster* than the low level code. I think I should make the point, for the benfit of those of us who are long past 24, that (in my experience at least) older engineers are just as fast as younger ones at picking up new ideas. In fact, given Natural Selection, they may well be faster. My (just constructed, contentious, and probably wrong) rule-of-thumb on logic levels is: 1 - softies who write synthesisable behavioural code are likely to end up with over 50, and maybe 100, logic levels. These chips exist; I've worked on one (85 levels). 2 - experienced logic designers who can use a synthesiser can get 10 - 15 levels without thinking about it, and their chips can run at maybe 3 times the frequency of (1) above. But, of course, it takes 3 times as long to write the code. 3 - experienced logic designers who can write behavioural code can also get 10 - 15 levels without thinking too hard about it, because they understand the language and the tools. 4 - if you want to go fast, you need to do maybe 4 - 6 logic levels. This is hard work when writing RTL code, and you'll need to put in lots of fixes. There will probably be lots of places where you're effectively drawing schematics in your RTL code. 5 - there's another way to go very fast. Write your code at as high a level as you want, use a synthesiser which can do good register balancing, and give it lots of pipeline levels to work with. This works well, and is invaluable for complex algorithms. It would be interesting to know where your contractor fitted in - (1) who got lucky, (3), or (5)? Evan
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