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On 1 Nov 2006 08:10:07 -0800, "Thomas" <dtsi.india@gmail.com> wrote: >If such a code generator appears on the market will your management >wait until a bigname EDA comes out with a me too product or will they >buy it from a noname developer? I think you may be in even more trouble than me... You need to be specific about what you're generating. A human is a code generator; are you replacing humans? Are you automating something that's already done? How many people do it? How much time do they spend on it? Can you do it better than a human? Or just faster? Or just cheaper? Or is it too difficult for a human to do at all? Are you generating IP? If so, you're in trouble. People don't like buying IP, and they'll only buy it from someone they already trust. The IP itself is unimportant, anyway: what matters is how well it has been verified, and whether you can prove it. You're selling a verification plan and coverage metrics, not HDL code. Who are you targetting? Is it FPGA users? If so, you're shafted. If not, you've got no market. Google for anyone who's tried to sell IP for FPGAs; I can't believe anyone's ever made money doing this. If the users like it, the FPGA vendors will do it themselves and sell it for *zero*. Remember, the vendors are selling silicon; they need to bundle software and IP for free to get market share. If you don't understand this, think Microsoft and Netscape, WMP, etc. Finally, remember that the EDA market is tiny, and 3 mid-sized fish are desperately trying to make a living in it, primarily by eating all the smaller fish. If the FPGA vendors don't get you, then the EDA vendors will. The men's underwear market is bigger than EDA. Perhaps you should be designing a better pair of Y-fronts... :) EvanArticle: 111401
Logaras Evangelos wrote: > I want to use the MCH OPB DDR controller (mch_opb_ddr) provided in EDK, to connect a DDR memory module to a custom processor design, which does not support the OPB (On-chip Peripheral Bus). I' going to implement the design in a Virtex-II Pro device (XUP board) Are there any modifications that I have to do to the controller produced by the EDK in order to attach it to my design? Is this usage possible, or the controller can only be attached to a Microblaze processor? Apart from removing the OPB interface and writing your own custom interface, you wouldn't have to do anything. /SivaArticle: 111402
rickman wrote: > > Yes the 16R8 may seem like an incredibly simple device, but it was such > an improvement over the TTL MSI devices we were otherwise using at the > time. PALs seemed like a gift from the Gods. > > Oddly enough I am currently working on a design where I am pushing the > customer to let me do it in discrete logic rather than a CPLD. The > functions are pretty simple and it only takes eight or so logic chips > and a couple of relay drivers. But to do it in a CPLD and have the > required 40% reserve space means I have to go to a relatively huge 100 > pin TQFP which just won't fit in the allotted space on the board. What's the '40% reserve space' mean ? Sounds like some miss-directed spec, from someone that thinks PLDs are software and thus likely to need 12 revisions in the life of the product ? > I could split it into two chips which would fit better, but I still am > not sure I would have the required 40% reserve capacitiy and would have > to add a JTAG connector to allow updates and factory programming. > > So discrete logic is not quite yet dead... yes, but I'm really interested to see how you design with discrete logic, and still get 40% reserve capacity - I know, use a HEF4894, when a HEF4794 would do ! :) -jgArticle: 111403
On Thu, 2 Nov 2006 17:26:14 -0000, "Ben Jones" <ben.jones@xilinx.com> wrote: >If I had a net with a fanout greater than a few hundred, and it wasn't a >clock or a reset, I'd probably do a bit of redesign at a higher level before >resorting to replication. :) It wasn't possible in this case, unfortunately, since I didn't understand the design or have enough time. One cone actually had 10,000 endpoints. Yes, the total number of nets increased, but not by a great deal - the ideal solution would be to turn one source register into 4 registers, each driving a cone of 2,500 endpoints. EvanArticle: 111404
KJ wrote: > But you didn't answer the question....reworded to 'What is the name of that > standard IP'? lpm_fifo is the only one that I can think of that fits your > functional description. Writing the function yourself (while you may want > to do it anyway) does not qualify it as a 'standard'. You write good code > Mike, but not everything you write is ready to be called a standard ;) Ready or not, I'll call it sync_fifo. See it here: http://home.comcast.net/~mike_treseler/ From laurent.pinchart@skynet.be Thu Nov 02 11:43:54 2006 Path: newssvr29.news.prodigy.net!newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed.freenet.de!news.albasani.net!news.warperbbs.de!news.weisnix.org!newsfeed.ision.net!newsfeed2.easynews.net!ision!skynet.be!newspost001!tjb!not-for-mail Message-Id: <454a4981$0$5540$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: EDK software development Newsgroups: comp.arch.fpga Date: Thu, 02 Nov 2006 20:43:54 +0100 References: <1162488095.194664@nsserver1.polyu.edu.hk> User-Agent: KNode/0.10.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 48 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 670deeb7.news.skynet.be X-Trace: 1162496385 news.skynet.be 5540 81.242.195.60:38527 X-Complaints-To: usenet-abuse@skynet.be Xref: prodigy.net comp.arch.fpga:122381 Hi Steve, > I'm writing a software for microblaze soft processor (Spartan 3E Starter > Kit) and I have a few questions regarding the using of memory. > > The first question is where my code is running? The starter kit has an > external 64MB DDR memory and internal local memory (Use BRAM). When I > download the bit stream to the FPGA, where is the program running? It > seems it is running in the local memory. The microblaze will boot from the memory mapped at address 0x00000000 (reset vector). This is usually an internal RAM block connected to an LMB controller on the ILMB, but it could be something else. Note that the memory mapped at address 0x00000000 must be initialised before starting the processor. If you want to map the DDR at the reset vector, you will need to initialise memory externally (using XDM when debugging for instance, or dedicated logic in the FPGA). Another solution would be to write a small boot loader that will be loaded in the internal BRAM by the bitstream. The boot loader will fetch the main software from a bigger memory (this could be a serial or parallel flash), write it to DDR and jump in external RAM. The boot loader must be compiled to run from the internal BRAM, and the main software from DDR. > Since the local memory is not big enough, for large size elf it should be > running inside the DDR. I faced the error "region ilmb_cntlr_dlmb_cntlr is > full" and I guess it's caused by the samll size local memory. Can anybody > tell me how I can make my program run from the DDR? Do I need to develop a > BSP for that? > > Normally the tutorial tell us the "Mark to Initialize BRAMs", that why I > guess the code is downloaded to the BRAM instead of the external DDR. > What's the real meanning behind this step? > > It seems the only method to update the code on FPGA is re-download the bit > stream file. However, since the hardware has been fixed and we don't > change the hardware much, is there a method that we can only update the > software part without touching the whole bit file? Like radarman mentioned, you can update the bitstream without recompiling the whole FPGA, either through "Device Configuration -> Update_Bitstream" or with the "bitinit" command line software. Hope this helps. Laurent PinchartArticle: 111405
"Austin Lesea" <austin@xilinx.com> wrote in message news:eidekr$dfs1@cnn.xsj.xilinx.com... > himassk, > > Rather than be "cute" or attempt humor, I will take you seriously: > Miaow!! Anyway, why not just tell the guy to type this into Google? "negative slack" site:xilinx.com Set a man afire, and all that... Love, Symsx. :-)Article: 111406
Well, but the user has to pay for this with logic fabric resources, and I doubt that it will run at 550 MHz and have no read latency, even with read and write clocks independent. So, it's a trade-off. Peter On Nov 2, 11:40 am, Mike Treseler <mike_trese...@comcast.net> wrote: > KJ wrote: > > But you didn't answer the question....reworded to 'What is the name of that > > standard IP'? lpm_fifo is the only one that I can think of that fits your > > functional description. Writing the function yourself (while you may want > > to do it anyway) does not qualify it as a 'standard'. You write good code > > Mike, but not everything you write is ready to be called a standard ;)Ready or not, > I'll call it sync_fifo. > See it here:http://home.comcast.net/~mike_treseler/Article: 111407
Hi Laurent and Antonio, I would like to provide a bit of information on ISE Simulator that may help solve the issue you encountered while using ISE Simulator. ISE Simulator by default comes up with only the waveform of top level signals shown in the Wave Viewer. But, you can add additional signals later. Click on the tab named "Sim Hierarchy - <top level unit name>" (you will find it adjacent to the "Processes" tab ) in the ISE after you have launched ISE Simulator. You can then expand hierarchy and see internal structure and signals. Then whichever signals you desire to add to Waveform Viewer, you can select them and drag them to Wave Viewer. You will see empty Waveform for newly added signals if they are not connected to the top, else you would see a waveform for the newly added signals. Next, enter "restart" on the tcl console of ISE Simulator ( See tab "Sim Console - <top module name>" in the bottom console window) or use Tool bar (<-| ) button to restart. Then run for desired length of time (Use Run For Tool bar button, or type "run <time> <unit> e.g. run 5000 ns on Sim Console) and you would see your newly added signals in the wave viewer. Also, you can run "step" on tcl console of ISE Simulator to step through your code or can open the HDL file and set breakpoints etc. You can type "help" on the Sim Console to learn about various other commands you could use to interact with the ISE Simulator. If you have further difficulties using ISE Simulator do let know. The documentation on ISE Simulator can be found at : http://toolbox.xilinx.com/docsan/xilinx82/help/iseguide/mergedProjects/xsim/xsim.htm . Regards, Kumar Laurent Pinchart wrote: > Hi Antonio, > > > I am very happy with ghdl, i almost use only that. Also for the post > > trans/map/p&r simulations. > > Does it work with Xilinx cores/primitives ? Do you know of any howto that > describes how to setup a Xilinx project (VHDL source files + > core/primitives) > for simulation with ghdl ? > > Laurent Pinchart > > > Laurent Pinchart ha scritto: > >> Hi everybody, > >> > >> I need to simulate VHDL code using the ISE 8.2i Webpack on Linux. After > >> some investigation, I found out that two simulators were available: > >> > >> - ModelSim, which I have some experience with, would cover all my needs, > >> but the ModelSim Xilinx Starter edition only runs under Windows. > >> > >> - ISE Simulator, which is pretty much unusable from what I've seen so > >> far. The simulation is not interactive (although I could live with that), > >> but I haven't been able to watch internal signal values. It seems only > >> the entity ports can be displayed, which makes debugging much more > >> difficult. > >> > >> Is there any proper simulation solution for the Linux platform ? I know > >> ModelSim has a Linux version, but that's way too expensive for personal > >> projects. Is there any way to run ModelSim Xilinx Starter edition under > >> Linux ? I tried running it in Wine, but it complained about not being > >> able to checkout a valid license, even though the flexlm diagnosis tool > >> reports no problem at all. > >> > >> Any help would be appreciated. Developing VHDL code without a simulator > >> is near to impossible. > >> > >> Best regards, > >> > >> Laurent Pinchart > >>Article: 111408
I am using Altera Stratix II FPGA and also power supervisor circuit which generates reset which it tied to nCONFIG for configuration of the FPGA. Now, I'd like to generate RESET for the FPGA after the configuration and Initialization is complete everytime. I can't find a part that can do that..any suggetions?Article: 111409
Peter Alfke wrote:
> Well, but the user has to pay for this with logic fabric resources,
Yes ~36 ALUTs or so.
> I doubt that it will run at 550 MHz and have no read latency, even with
> read and write clocks independent.
True, but 475 MHz with default optimization is not bad.
-- Mike Treseler
Info: Selected device EP2S15F484C3 for design "sync_fifo"
Info: Fitter is performing an Auto Fit compilation, which may decrease
Fitter effort to reduce compilation time
Info: Clock "clk" has Internal fmax of 475.74 MHz between source
register "\fifo:pushed" and destination register "full_ctr[1]" (period=
2.102 ns)
Article: 111410I am trying to use Xilinx chipscope, but it is not working properly (probably mishandling by the user...). Perhaps somebody can give me some light... I used core inserter, and I have a ICON and a ILA core. I want to monitor a SPI bus in a 2VP2 device, that has 12 RAM blocks available. I defined a 1 trigger port with width 1, set with the sclk (that should be around 10MHz). And I have a 40 data width bus where I try to see many data signals. I can go to the point where I generate the programming file (bit file). Startup clock is set to JTAGclk, keep hierarchy is set to YES. I also generate (just in case) the mcs file and load my 18V04 EEPROM. I recicle power and then I click in the Analyze Design Using Chipscope. After opening the JTAG Chain (XILINX Parallel IV cable), it says that it found 1 core unit in the JTAG device Chain. But if I press the "trigger now" button, it does not give me the status of the lines. It enters a mode where it says"siting for core to be armed." and stays there forever. Am I setting the trigger in a wrong way? We are talking about versions 7.1 os ISE and chipscope pro. I would appreciate any input!Article: 111411
Davy wrote: > > When studying SystemVerilog, some book said 'virtual' is used to get > the reference of the interface. But why the language not use 'ref' to > get interface reference? I agree that it is a strange choice. However, 'ref' generally means a pass-by-reference argument. So what would you use for a virtual interface variable passed by reference, 'ref ref interface'?Article: 111412
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:454a42f8$1@clear.net.nz... > > yes, but I'm really interested to see how you design with discrete > logic, and still get 40% reserve capacity - I know, use a > HEF4894, when a HEF4794 would do ! :) And I was interested in the 'eight or so' chips which fit into the space of the TQFP-100... WillArticle: 111413
Well, how's about asynchronous arbitration of Full and Empty at 550 MHz, with non-synchronous write and read clocks? Within one clock cycle, for that's the acid test. Everything else is trivial, just two counters, each accessing one port of the RAM. Peter Alfke On Nov 2, 12:29 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > Peter Alfke wrote: > > Well, but the user has to pay for this with logic fabric resources,Yes ~36 ALUTs or so. > > > I doubt that it will run at 550 MHz and have no read latency, even with > > read and write clocks independent.True, but 475 MHz with default optimization is not bad. > > -- Mike Treseler > > Info: Selected device EP2S15F484C3 for design "sync_fifo" > Info: Fitter is performing an Auto Fit compilation, which may decrease > Fitter effort to reduce compilation time > Info: Clock "clk" has Internal fmax of 475.74 MHz between source > register "\fifo:pushed" and destination register "full_ctr[1]" (period= > 2.102 ns)Article: 111414
Symon, It reminds me of the fellow who walks into his doctor's office, and says, -"Doctor, when I do this...it hurts!" The doctor looks at him, and says, "That will be 100 euros (or dollars, your choice when you tell the joke), please." -"But you haven't told me what to do!" "I need to be paid first." -"Okay, here is your 100 euros..." "Sir, ... don't do that." The temptation was great, Austin Symon wrote: > "Austin Lesea" <austin@xilinx.com> wrote in message > news:eidekr$dfs1@cnn.xsj.xilinx.com... >> himassk, >> >> Rather than be "cute" or attempt humor, I will take you seriously: >> > Miaow!! Anyway, why not just tell the guy to type this into Google? > > "negative slack" site:xilinx.com > > Set a man afire, and all that... > > Love, Symsx. :-) > >Article: 111415
rickman wrote: > KJ wrote: >> "Peter Alfke" <peter@xilinx.com> wrote in message >> news:1162418895.253069.240680@f16g2000cwb.googlegroups.com... >>> I remember the birth of the 22V10 (it's an AMD product, not MMI's) >>> It had the gestation period of an elephant, and it almost killed the >>> design engineers. Too complicated... >>> Times have changed. >>> Peter Alfke >> Yes, those 'V' parts were pretty versatile (hence the 'V' in 16V8, 22V10) >> for those of us around at the birth of the 16R4, 16R6 and 16R8 when great >> thought had to be applied to decide whether an output should be clocked or >> combinatorial...and if you got it wrong you had to rewire the circuit board >> to move it to the appropriate pin....well, that and having to remove and >> pitch the part because it was fuse based one time programmable. >> >> KJ...feeling ooooooold now....where's my hot cocoa? > > Yes the 16R8 may seem like an incredibly simple device, but it was such > an improvement over the TTL MSI devices we were otherwise using at the > time. PALs seemed like a gift from the Gods. > > Oddly enough I am currently working on a design where I am pushing the > customer to let me do it in discrete logic rather than a CPLD. The > functions are pretty simple and it only takes eight or so logic chips > and a couple of relay drivers. But to do it in a CPLD and have the > required 40% reserve space means I have to go to a relatively huge 100 > pin TQFP which just won't fit in the allotted space on the board. I > could split it into two chips which would fit better, but I still am > not sure I would have the required 40% reserve capacitiy and would have > to add a JTAG connector to allow updates and factory programming. > > So discrete logic is not quite yet dead... > This is an area where books could be written ;) The only engineering maxim is do it right in the minimum space and minimum cost, although those two can conflict. Cheers PeteSArticle: 111416
"Austin Lesea" <austin@xilinx.com> wrote in message news:eido0i$d781@cnn.xsj.xilinx.com... > Symon, > > It reminds me of the fellow who walks into his doctor's office, and says, > > -"Doctor, when I do this...it hurts!" > > "Sir, ... don't do that." > > The temptation was great, > > Austin > :-) So, the same chap wanders in off the street and says "Doctor, doctor. I keep thinking I'm a moth!" The guy responds, "I'm terribly sorry sir, but this is a butcher's shop." The first guy says, "Yeah, I know. But your light was on." Hi Austin, there was an English comedian called Tommy Cooper who, if you've not come across him before, I think you'd like! http://users.ox.ac.uk/~peter/humour/cooper.html Sorry 4 the OT everyone, Syms.Article: 111417
Symon, I needed that. Thanks, AustinArticle: 111418
Uwe Bonnes wrote: >Jon Elson <elson@pico-systems.com> wrote: > > >>Hello, all, >> >> > > > >>Does anyone know where I can get just a few (5 - 10) Xilinx >>XCS30-3TQ144C chips? Anybody who has them wants to sell me >>a minimum of a hundred or more. I just need a few to make >>repairs on equipment in the field. I just got a board back >>from a customer who had a lightning strike, and I had to salvage >>a chip off a test module to get his unit repaired. >> >> > > > >>If anyone has a few of these chips laying around, I'd be glad to >>pay the going rate for them, too! I can probably use other speed >>ranges or temp ranges as well. I'm in the US, but that shouldn't >>make much difference, I seem to be buying my Xilinx chips from >>Australia these days! >> >> > >This is again a case for the Xilinx "online shop"... > > Maybe it presents different info to you, or you know to click something that brings up other pages. First, there is nothing on the "front" page about old Spartan devices, only for Spartan 3. Secondly, the chip links are just links to their distributors. I have already checked with ALL US franchised distributors, none have any stock of the part I need, all want large orders over US $2000. So, unless I am missing something in the online shop, it doesn't help. (If you meant Xilinx should make small quantities of obsolete products available through the online shop, then I wholeheartedly agree with that. But, it seems they may have made agreements with the distributors to not do that. I can understand why the distribs don't like that, but Maxim, TI, AD, etc. all do it anyway.) JonArticle: 111419
Jon Elson <jmelson@artsci.wustl.edu> wrote: > Uwe Bonnes wrote: ... > > > >This is again a case for the Xilinx "online shop"... > > > > > Maybe it presents different info to you, or you know to click something that > brings up other pages. First, there is nothing on the "front" page about Sorry, next time I'll tag sarcasme. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 111420
Jon Elson wrote: > > > Uwe Bonnes wrote: > >> Jon Elson <elson@pico-systems.com> wrote: >> >> >>> Hello, all, >>> >> >> >> >> >>> Does anyone know where I can get just a few (5 - 10) Xilinx >>> XCS30-3TQ144C chips? Anybody who has them wants to sell me >>> a minimum of a hundred or more. I just need a few to make >>> repairs on equipment in the field. I just got a board back >>> from a customer who had a lightning strike, and I had to salvage >>> a chip off a test module to get his unit repaired. >>> >> >> >> >> >>> If anyone has a few of these chips laying around, I'd be glad to >>> pay the going rate for them, too! I can probably use other speed >>> ranges or temp ranges as well. I'm in the US, but that shouldn't >>> make much difference, I seem to be buying my Xilinx chips from >>> Australia these days! >>> >> >> >> This is again a case for the Xilinx "online shop"... >> >> > Maybe it presents different info to you, or you know to click something > that > brings up other pages. First, there is nothing on the "front" page about > old Spartan devices, only for Spartan 3. Secondly, the chip links are just > links to their distributors. I have already checked with ALL US franchised > distributors, none have any stock of the part I need, all want large orders > over US $2000. So, unless I am missing something in the online shop, > it doesn't help. (If you meant Xilinx should make small quantities of > obsolete products available through the online shop, then I wholeheartedly > agree with that. But, it seems they may have made agreements with the > distributors > to not do that. I can understand why the distribs don't like that, but > Maxim, > TI, AD, etc. all do it anyway.) > > Jon There are other threads on this. Xilinx _used_ to offer some on-line shopping, but the level of service took a dive, as the bean-counters held sway - so it is something of a sore point.... I don't think it is Disti pressure,(but you never know...) as most Disti's don't want to know about samples / small qty Maint orders. Couple that with lead free changes, shrinking shelf lives, and larger SPQs, most Distis try to avoid carrying ANY stock at all, of a "speculative" nature. Welcome to the world of short life cycle parts... -jgArticle: 111421
Hello, > > Will the other port red the old or the new data? I am convinced that > > this is really undefined. > > You may be lucky and it works your way, but I would not bet on it. I always thought that the BRAM write-first mode was implemented as a bypass of the data store local to the bram port, and that the writes to the underlying data store were always synchronous on both ports, thus leading to a sure A result on both of these questions... Probably because this is the simplest modelling of the BRAM behaviour with synchronous logic, but I guess things are a bit more complicated in the real world... JBArticle: 111422
Brandon Jasionowski wrote: > I'm also receiving this similar warning: > > <SNIP> > WARNING:PhysDesignRules:372 - Gated clock. Clock net > > DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/C > LKOUT is sourced by a combinatorial pin. This is not good design > practice. > Use the CE pin to control the loading of data into the flip-flop. > </SNIP> > > Brandon Jasionowski wrote: > > I'm receiving a strange warning in ISE for a Virtex 4. I've been seeing > > new warnings and infos using the new DCMs. Is it safe to ignore this > > warning in MAP? I couldn't find anything related in the knowledge base. > > This autocal appears to be generated for speed improvement? > > > > Help is much appreciated. > > > > Thanks, > > -Brandon > > > > <SNIP> > > WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG > > symbol > > "clkgen_inst/usrclk_dcm_clk0_bufg_inst" (output > > signal=clkgen_inst/usrclk) > > has a mix of clock and non-clock loads. The non-clock loads are: > > Pin I0 of > > > > DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/m > > d/_n00001 > > Pin I1 of > > > > DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/m > > d/_n00011 > > </SNIP> Refer to the following - http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=21435 HTH.Article: 111423
Hi, Coming from a scientific computing standpoint (with no hardware experience). I was wondering if you can improve any dedicated tasks by designing a special purpose chips ala FPGA to run your code? Does anyone have any experience with this?Article: 111424
Jim Granville wrote: > rickman wrote: > > > > Yes the 16R8 may seem like an incredibly simple device, but it was such > > an improvement over the TTL MSI devices we were otherwise using at the > > time. PALs seemed like a gift from the Gods. > > > > Oddly enough I am currently working on a design where I am pushing the > > customer to let me do it in discrete logic rather than a CPLD. The > > functions are pretty simple and it only takes eight or so logic chips > > and a couple of relay drivers. But to do it in a CPLD and have the > > required 40% reserve space means I have to go to a relatively huge 100 > > pin TQFP which just won't fit in the allotted space on the board. > > What's the '40% reserve space' mean ? > Sounds like some miss-directed spec, from someone that thinks PLDs are > software and thus likely to need 12 revisions in the life > of the product ? Not just revisions, but changing requirements. That seems to be the big thing everyone here is concerned about, that a hardware only approach does not lend any flexibility to requirement growth. In reality, there are not many things that can change that will not require a hardware change regardless of the implementation. If you want to add signals to the mux, you will have to add those inputs to the module. If you change the number of relays, you will need to add the relays. > > I could split it into two chips which would fit better, but I still am > > not sure I would have the required 40% reserve capacitiy and would have > > to add a JTAG connector to allow updates and factory programming. > > > > So discrete logic is not quite yet dead... > > yes, but I'm really interested to see how you design with discrete > logic, and still get 40% reserve capacity - I know, use a > HEF4894, when a HEF4794 would do ! :) My point has been that it will not provide any less *useful* reconfigurability. I had the "big" presentation today and the two senior people who will have to "OK" the decision didn't even come. The guy who is our contact with the FPGA/CPLD department started kibizing at the end of the presentation saying that the discrete logic approach was not "clean". I had to call him on that BS. I am honestly looking for another job. Between dealing with the ignorance and the extreme boredom and the snail pace design work, I have decided to leave. I feel like the guy in the commercial that comes in the door after the parrot who cries, "I can't take it!" I just don't care for the commute I will have to live with. The outfit was the closest job I could get. Everything else is a lot further a way or even if it is not a lot further, it is in a lot heavier traffic. Maybe I should retire...
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