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Threads Starting May 2010

147545: 10/05/01: Andrew Pichler: Cheap FPGAs for tutorial
    147546: 10/05/01: Frank Buss: Re: Cheap FPGAs for tutorial
    147548: 10/05/01: Brian Drummond: Re: Cheap FPGAs for tutorial
    147553: 10/05/01: Patrick Maupin: Re: Cheap FPGAs for tutorial
        147555: 10/05/01: Mel: Re: Cheap FPGAs for tutorial
    147554: 10/05/01: -jg: Re: Cheap FPGAs for tutorial
    147556: 10/05/01: Gabor: Re: Cheap FPGAs for tutorial
    147557: 10/05/02: Petter Gustad: Re: Cheap FPGAs for tutorial
    147558: 10/05/03: Prevailing over Technology: Re: Cheap FPGAs for tutorial
147559: 10/05/03: Philip Pemberton: ISE 11.1 - readmemh issues
    147562: 10/05/03: Gabor: Re: ISE 11.1 - readmemh issues
        147564: 10/05/03: Gabor: Re: ISE 11.1 - readmemh issues
    147563: 10/05/03: Philip Pemberton: Re: ISE 11.1 - readmemh issues
147560: 10/05/03: Ghostboy: PCI Interrupt
    147561: 10/05/03: Nico Coesel: Re: PCI Interrupt
        147568: 10/05/04: Ghostboy: Re: PCI Interrupt
147565: 10/05/03: Vips: FIFO Depth Calculation
    147572: 10/05/04: Kolja Sulimma: Re: FIFO Depth Calculation
        147573: 10/05/04: Phil Jessop: Re: FIFO Depth Calculation
    147574: 10/05/04: Gabor: Re: FIFO Depth Calculation
    147580: 10/05/04: Muzaffer Kal: Re: FIFO Depth Calculation
        147582: 10/05/05: glen herrmannsfeldt: Re: FIFO Depth Calculation
            147583: 10/05/05: Symon: Re: FIFO Depth Calculation
                147592: 10/05/05: glen herrmannsfeldt: Re: FIFO Depth Calculation
                147593: 10/05/05: glen herrmannsfeldt: Re: FIFO Depth Calculation
                    147596: 10/05/06: Symon: Re: FIFO Depth Calculation
                        147602: 10/05/06: Symon: Re: FIFO Depth Calculation
    147597: 10/05/05: Patrick Maupin: Re: FIFO Depth Calculation
147566: 10/05/03: Vips: FIFO Depth Calculation
    147569: 10/05/04: Gabor: Re: FIFO Depth Calculation
        147577: 10/05/04: Jonathan Bromley: Re: FIFO Depth Calculation
            147586: 10/05/05: Curt Johnson: Re: FIFO Depth Calculation
        147581: 10/05/04: Muzaffer Kal: Re: FIFO Depth Calculation
    147575: 10/05/04: Vips: Re: FIFO Depth Calculation
    147576: 10/05/04: Vips: Re: FIFO Depth Calculation
    147578: 10/05/04: KJ: Re: FIFO Depth Calculation
    147579: 10/05/04: KJ: Re: FIFO Depth Calculation
    147584: 10/05/05: KJ: Re: FIFO Depth Calculation
    147585: 10/05/05: Symon: Re: FIFO Depth Calculation
147567: 10/05/04: LC: Unecessary simulation paths
    147570: 10/05/04: jt_eaton: Re: Unecessary simulation paths
    147571: 10/05/04: Muzaffer Kal: Re: Unecessary simulation paths
    147607: 10/05/06: LC: Re: Unecessary simulation paths
147587: 10/05/05: wallge: sopc builder custom component and passing parameters to VHDL package
    147616: 10/05/07: KJ: Re: sopc builder custom component and passing parameters to VHDL
147588: 10/05/05: bhaskar: Floating point unit in microblaze
    147603: 10/05/06: Martin Thompson: Re: Floating point unit in microblaze
147589: 10/05/05: mizrahi_lior: rtl simulation model for microblaze
    147594: 10/05/05: mamu: Re: rtl simulation model for microblaze
147590: 10/05/05: General Schvantzkoph: Signal name display in SignalTap
    147591: 10/05/05: General Schvantzkoph: Re: Signal name display in SignalTap
147595: 10/05/05: Sharmila: Xilinx project failed timing constraints
    147598: 10/05/05: Patrick Maupin: Re: Xilinx project failed timing constraints
        147601: 10/05/06: Fredxx: Re: Xilinx project failed timing constraints
147599: 10/05/05: Eric: FPGA Compilation Time Windows vs Linux
    147600: 10/05/05: Patrick Maupin: Re: FPGA Compilation Time Windows vs Linux
    147604: 10/05/06: General Schvantzkoph: Re: FPGA Compilation Time Windows vs Linux
        147605: 10/05/06: Nial Stewart: Re: FPGA Compilation Time Windows vs Linux
            147612: 10/05/07: whygee: Re: FPGA Compilation Time Windows vs Linux
                147615: 10/05/07: whygee: Re: FPGA Compilation Time Windows vs Linux
                147620: 10/05/08: Petter Gustad: Re: FPGA Compilation Time Windows vs Linux
                    147630: 10/05/10: David Brown: Re: FPGA Compilation Time Windows vs Linux
        147606: 10/05/06: Petter Gustad: Re: FPGA Compilation Time Windows vs Linux
            147608: 10/05/06: Jason Thibodeau: Re: FPGA Compilation Time Windows vs Linux
    147610: 10/05/06: General Schvantzkoph: Re: FPGA Compilation Time Windows vs Linux
    147613: 10/05/07: Chris Maryan: Re: FPGA Compilation Time Windows vs Linux
    147614: 10/05/07: General Schvantzkoph: Re: FPGA Compilation Time Windows vs Linux
    147632: 10/05/10: Adrian: Re: FPGA Compilation Time Windows vs Linux
147609: 10/05/06: onkars: Xilinx FFT core -- Is varying precision through the core possible?
    147611: 10/05/06: onkars: Re: Xilinx FFT core -- Is varying precision through the core possible?
147617: 10/05/07: niyander: Floating Point Division
    147618: 10/05/08: glen herrmannsfeldt: Re: Floating Point Division
    147625: 10/05/08: niyander: Re: Floating Point Division
147622: 10/05/08: Paolo Roberto Grassi: Microblaze: Boot Program from SDRAM
147626: 10/05/09: jogendersaini: repeting outputs of counter
    147629: 10/05/09: KJ: Re: repeting outputs of counter
147627: 10/05/09: jmariano: I hit the wall
147634: 10/05/10: Sharath Raju: Expecting sequential output, but RTL shows concurrent implementation.
    147637: 10/05/10: backhus: Re: Expecting sequential output, but RTL shows concurrent
        147674: 10/05/14: Martin Thompson: Re: Expecting sequential output, but RTL shows concurrent implementation.
            147679: 10/05/14: Alan Fitch: Re: Expecting sequential output, but RTL shows concurrent implementation.
                147695: 10/05/17: Martin Thompson: Re: Expecting sequential output, but RTL shows concurrent implementation.
            147696: 10/05/17: Nial Stewart: Re: Expecting sequential output, but RTL shows concurrent implementation.
                147711: 10/05/18: Martin Thompson: Re: Expecting sequential output, but RTL shows concurrent implementation.
    147638: 10/05/11: Christopher Head: Re: Expecting sequential output, but RTL shows concurrent
        147639: 10/05/11: Nial Stewart: Re: Expecting sequential output, but RTL shows concurrent implementation.
    147649: 10/05/11: backhus: Re: Expecting sequential output, but RTL shows concurrent
    147651: 10/05/12: Sharath Raju: Re: Expecting sequential output, but RTL shows concurrent
    147667: 10/05/13: rickman: Re: Expecting sequential output, but RTL shows concurrent
    147673: 10/05/13: backhus: Re: Expecting sequential output, but RTL shows concurrent
    147685: 10/05/14: Andy Peters: Re: Expecting sequential output, but RTL shows concurrent
147635: 10/05/10: Vikram: Register Now: FPGA Camp Bangalore, INDIA. May'21
147636: 10/05/11: he: Two PCIe Endpoints in one Virtex-6?
    147640: 10/05/11: maxascent: Re: Two PCIe Endpoints in one Virtex-6?
    147641: 10/05/11: Gabor: Re: Two PCIe Endpoints in one Virtex-6?
    147678: 10/05/14: Kolja Sulimma: Re: Two PCIe Endpoints in one Virtex-6?
147643: 10/05/11: smart0604: what is the fmax of the simple dual port ram in the altera fpga
    147650: 10/05/12: Nial Stewart: Re: what is the fmax of the simple dual port ram in the altera fpga
    147652: 10/05/12: John_H: Re: what is the fmax of the simple dual port ram in the altera fpga
147644: 10/05/11: m.khairy: ModelSim XE III error
147655: 10/05/13: Nial Stewart: New 'standard' compact programming header needed!
    147658: 10/05/13: Rob Gaddi: Re: New 'standard' compact programming header needed!
        147675: 10/05/14: Nial Stewart: Re: New 'standard' compact programming header needed!
            147681: 10/05/14: Rob Gaddi: Re: New 'standard' compact programming header needed!
    147659: 10/05/13: Thomas Entner: Re: New 'standard' compact programming header needed!
        147676: 10/05/14: Nial Stewart: Re: New 'standard' compact programming header needed!
            147720: 10/05/19: Nial Stewart: Re: New 'standard' compact programming header needed!
        147713: 10/05/18: -jg: Re: New 'standard' compact programming header needed!
        147731: 10/05/19: -jg: Re: New 'standard' compact programming header needed!
    147660: 10/05/13: rickman: Re: New 'standard' compact programming header needed!
    147662: 10/05/13: Jon Elson: Re: New 'standard' compact programming header needed!
        147677: 10/05/14: Nial Stewart: Re: New 'standard' compact programming header needed!
    147682: 10/05/14: whygee: Re: New 'standard' compact programming header needed!
        147691: 10/05/17: Nial Stewart: Re: New 'standard' compact programming header needed!
            147699: 10/05/17: Nial Stewart: Re: New 'standard' compact programming header needed!
                147700: 10/05/18: whygee: Re: New 'standard' compact programming header needed!
        147698: 10/05/17: Ed McGettigan: Re: New 'standard' compact programming header needed!
        147701: 10/05/17: Ed McGettigan: Re: New 'standard' compact programming header needed!
        147706: 10/05/17: rickman: Re: New 'standard' compact programming header needed!
        147708: 10/05/18: Thomas Entner: Re: New 'standard' compact programming header needed!
        147710: 10/05/18: Ed McGettigan: Re: New 'standard' compact programming header needed!
        147712: 10/05/18: rickman: Re: New 'standard' compact programming header needed!
        147715: 10/05/18: Ed McGettigan: Re: New 'standard' compact programming header needed!
147656: 10/05/13: Sharath Raju: Xilinx Synthesis Tool generates clock signals from combinatorial
    147657: 10/05/13: John McCaskill: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
        147666: 10/05/13: Rob Gaddi: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
            147717: 10/05/19: whygee: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
        147689: 10/05/16: Ralf Hildebrandt: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
            147704: 10/05/17: Muzaffer Kal: Re: Xilinx Synthesis Tool generates clock signals from combinatorial logic
            147719: 10/05/19: Nico Coesel: Re: Xilinx Synthesis Tool generates clock signals from combinatorial logic
    147661: 10/05/13: rickman: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147663: 10/05/13: John McCaskill: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147665: 10/05/13: rickman: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147668: 10/05/13: John McCaskill: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147671: 10/05/13: Sharath Raju: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147683: 10/05/14: Andy Peters: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147703: 10/05/17: Sharath Raju: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147716: 10/05/18: Andy: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147718: 10/05/18: KJ: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147725: 10/05/19: Andy: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
147664: 10/05/13: varun_agr: problem in clock input in virtexpro/spartan3a/spartan3 kit
    147669: 10/05/13: Ed McGettigan: Re: problem in clock input in virtexpro/spartan3a/spartan3 kit
    147672: 10/05/13: jt_eaton: Re: problem in clock input in virtexpro/spartan3a/spartan3 kit
    147684: 10/05/14: Andy Peters: Re: problem in clock input in virtexpro/spartan3a/spartan3 kit
147670: 10/05/13: Mike Santarini: 2 New issue of Xcell Now available
147680: 10/05/14: Mawa_fugo: Altra mega core SDI vs. Gennum devices
147686: 10/05/15: Sebastien Bourdeauducq: Spartan 6 schedule
    147687: 10/05/15: John Adair: Re: Spartan 6 schedule
    147692: 10/05/17: Uwe Bonnes: Re: Spartan 6 schedule
    147693: 10/05/17: Jon Beniston: Re: Spartan 6 schedule
    147726: 10/05/19: Uwe Bonnes: Re: Spartan 6 schedule
147688: 10/05/15: John Adair: Craignell1 FPGA DIL Module - No reserve on Ebay
147690: 10/05/16: aleksa: Spartan 2 & 3, serial config and CS pin
    147714: 10/05/18: aleksa: Re: Spartan 2 & 3, serial config and CS pin
147694: 10/05/17: roger: using ChipScope to debug external design
    147697: 10/05/17: maxascent: Re: using ChipScope to debug external design
    147702: 10/05/17: Alex Freed: Re: using ChipScope to debug external design
    147705: 10/05/17: John Adair: Re: using ChipScope to debug external design
147707: 10/05/18: binupr: Basics on Xilinx Auroroa Core
147709: 10/05/18: Eagle_mk4: MIG v3.0 inputs signal
    147759: 10/05/22: lusch: Re: MIG v3.0 inputs signal
        147800: 10/05/25: Eagle_mk4: Re: MIG v3.0 inputs signal
    147763: 10/05/22: Gabor: Re: MIG v3.0 inputs signal
        147801: 10/05/25: Eagle_mk4: Re: MIG v3.0 inputs signal
            147804: 10/05/25: RCIngham: Re: MIG v3.0 inputs signal
                147858: 10/05/27: Eagle_mk4: Re: MIG v3.0 inputs signal
                    147862: 10/05/27: Brian Drummond: Re: MIG v3.0 inputs signal
                        147893: 10/05/31: Eagle_mk4: Re: MIG v3.0 inputs signal
147721: 10/05/19: HIDDEN: sensor-FPGA-DSP image processing
    147722: 10/05/19: Petter Gustad: Re: sensor-FPGA-DSP image processing
        147724: 10/05/19: Petter Gustad: Re: sensor-FPGA-DSP image processing
    147723: 10/05/19: HIDDEN: Re: sensor-FPGA-DSP image processing
    147734: 10/05/19: David M. Palmer: Re: sensor-FPGA-DSP image processing
        147737: 10/05/20: Petter Gustad: Re: sensor-FPGA-DSP image processing
147727: 10/05/19: pes: spartan6 configuration
    147777: 10/05/23: Christopher Head: Re: spartan6 configuration
147728: 10/05/19: Philip Pemberton: Problems inferring blockram in ISE12.1
    147729: 10/05/19: John McCaskill: Re: Problems inferring blockram in ISE12.1
147730: 10/05/19: Vivek Menon: BLK_MEM_GEN_v2_8.I948.10 error when using BRAM Xilinx ISE 10.1
    147732: 10/05/20: Brian Drummond: Re: BLK_MEM_GEN_v2_8.I948.10 error when using BRAM Xilinx ISE 10.1
    147733: 10/05/19: Vivek Menon: Re: BLK_MEM_GEN_v2_8.I948.10 error when using BRAM Xilinx ISE 10.1
147735: 10/05/19: Vikram: FPGA Camp, Bangalore is tomorrow
147736: 10/05/20: jerzy.gbur@gmail.com: Availability of XC6SLX16-2CPG196C
147739: 10/05/21: Philip Pemberton: Debugging SDRAM interfaces
    147740: 10/05/21: =?UTF-8?B?R8OzcnNraSBBZGFt?=: Re: Debugging SDRAM interfaces
    147741: 10/05/21: Philip Pemberton: Re: Debugging SDRAM interfaces
        147744: 10/05/21: =?UTF-8?B?R8OzcnNraSBBZGFt?=: Re: Debugging SDRAM interfaces
    147751: 10/05/21: Brian Drummond: Re: Debugging SDRAM interfaces
    147752: 10/05/21: Philip Pemberton: Re: Debugging SDRAM interfaces
    147754: 10/05/21: Philip Pemberton: Re: Debugging SDRAM interfaces
        147757: 10/05/22: maxascent: Re: Debugging SDRAM interfaces
        147758: 10/05/22: Nico Coesel: Re: Debugging SDRAM interfaces
        147762: 10/05/22: Gabor: Re: Debugging SDRAM interfaces
            147765: 10/05/23: Nico Coesel: Re: Debugging SDRAM interfaces
            147767: 10/05/23: Brian Drummond: Re: Debugging SDRAM interfaces
                147776: 10/05/24: Brian Drummond: Re: Debugging SDRAM interfaces
    147766: 10/05/23: Philip Pemberton: Re: Debugging SDRAM interfaces
    147772: 10/05/23: Philip Pemberton: Re: Debugging SDRAM interfaces
    147785: 10/05/24: Philip Pemberton: Re: Debugging SDRAM interfaces
147742: 10/05/21: jasmile: speed grade and temperature grade aren't marked??
    147749: 10/05/21: Ed McGettigan: Re: speed grade and temperature grade aren't marked??
147743: 10/05/21: honio: Xilinx FIFO cannot be written
    147745: 10/05/21: John McCaskill: Re: Xilinx FIFO cannot be written
    147746: 10/05/21: Jan Pech: Re: Xilinx FIFO cannot be written
        147748: 10/05/21: honio: Re: Xilinx FIFO cannot be written
    147750: 10/05/21: Peter Alfke: Re: Xilinx FIFO cannot be written
147747: 10/05/21: Gladys: can I do image processing using 8bit color output FPGA board?
    147756: 10/05/21: Derek Simmons: Re: can I do image processing using 8bit color output FPGA board?
147753: 10/05/21: Thomas Jones: Any V6's available?
    147755: 10/05/21: mike_la_jolla: Re: Any V6's available?
147760: 10/05/22: John_H: Last Xilinx Webpack that was big-brother free?
    147761: 10/05/22: John_H: Re: Last Xilinx Webpack that was big-brother free?
        147768: 10/05/23: Brian Drummond: Re: Last Xilinx Webpack that was big-brother free?
            147770: 10/05/23: Brian Drummond: Re: Last Xilinx Webpack that was big-brother free?
    147769: 10/05/23: John_H: Re: Last Xilinx Webpack that was big-brother free?
    147771: 10/05/23: Uwe Bonnes: Re: Last Xilinx Webpack that was big-brother free?
    147782: 10/05/24: John_H: Re: Last Xilinx Webpack that was big-brother free?
    147816: 10/05/25: radarman: Re: Last Xilinx Webpack that was big-brother free?
    147886: 10/05/29: Muzaffer Kal: Re: Last Xilinx Webpack that was big-brother free?
    147887: 10/05/29: -jg: Re: Last Xilinx Webpack that was big-brother free?
    147889: 10/05/30: Joe Chisolm: Re: Last Xilinx Webpack that was big-brother free?
147764: 10/05/23: rombios: Xilinx Xact software for XC2018 Logic Cell Array
    147778: 10/05/23: Ed McGettigan: Re: Xilinx Xact software for XC2018 Logic Cell Array
        147781: 10/05/24: John_H: Re: Xilinx Xact software for XC2018 Logic Cell Array
        147783: 10/05/24: Paul Carpenter: Re: Xilinx Xact software for XC2018 Logic Cell Array
        147790: 10/05/24: John Adair: Re: Xilinx Xact software for XC2018 Logic Cell Array
            147814: 10/05/25: Nico Coesel: Re: Xilinx Xact software for XC2018 Logic Cell Array
    147779: 10/05/23: John Adair: Re: Xilinx Xact software for XC2018 Logic Cell Array
        147787: 10/05/24: glen herrmannsfeldt: Re: Xilinx Xact software for XC2018 Logic Cell Array
            147792: 10/05/24: glen herrmannsfeldt: Re: Xilinx Xact software for XC2018 Logic Cell Array
        147789: 10/05/24: d_s_klein: Re: Xilinx Xact software for XC2018 Logic Cell Array
        147791: 10/05/24: Gabor: Re: Xilinx Xact software for XC2018 Logic Cell Array
        147793: 10/05/24: Gabor: Re: Xilinx Xact software for XC2018 Logic Cell Array
        147796: 10/05/24: John Adair: Re: Xilinx Xact software for XC2018 Logic Cell Array
        147808: 10/05/25: d_s_klein: Re: Xilinx Xact software for XC2018 Logic Cell Array
    147780: 10/05/24: fpgahobbyist: Re: Xilinx Xact software for XC2018 Logic Cell Array
    147786: 10/05/24: Herbert Kleebauer: Re: Xilinx Xact software for XC2018 Logic Cell Array
    147788: 10/05/24: fpgahobbyist: Re: Xilinx Xact software for XC2018 Logic Cell Array
    147817: 10/05/25: Philip Pemberton: Re: Xilinx Xact software for XC2018 Logic Cell Array
    154400: 12/10/25: mark2112: RE: Xilinx Xact software for XC2018 Logic Cell Array
147773: 10/05/23: Philip Pemberton: Do Xilinx really want people to report INTERNAL_ERRORs?
    147775: 10/05/24: Philip Pemberton: Re: Do Xilinx really want people to report INTERNAL_ERRORs?
147774: 10/05/23: null: About CLB inter-slice communication in Virtex
    147784: 10/05/24: Uwe Bonnes: Re: About CLB inter-slice communication in Virtex
147794: 10/05/24: hssig: mux behavior
    147795: 10/05/24: Gabor: Re: mux behavior
        147797: 10/05/25: glen herrmannsfeldt: Re: mux behavior
            147805: 10/05/25: Symon: Re: mux behavior
                147813: 10/05/25: Brian Drummond: Re: mux behavior
            147806: 10/05/25: glen herrmannsfeldt: Re: mux behavior
                147815: 10/05/25: Brian Drummond: Re: mux behavior
    147802: 10/05/25: hssig: Re: mux behavior
    147803: 10/05/25: Gabor: Re: mux behavior
    147811: 10/05/25: Patrick Maupin: Re: mux behavior
    147812: 10/05/25: Gabor: Re: mux behavior
147798: 10/05/24: John Larkin: Re: Software bloat (Larkin was right)
    147799: 10/05/24: krw@att.bizzzzzzzzzzzz: Re: Software bloat (Larkin was right)
    147810: 10/05/25: John Larkin: Re: Software bloat (Larkin was right)
        147829: 10/05/26: Fredxx: Re: Software bloat (Larkin was right)
            147847: 10/05/26: krw@att.bizzzzzzzzzzzz: Re: Software bloat (Larkin was right)
                147854: 10/05/27: Fredxx: Re: Software bloat (Larkin was right)
                    147856: 10/05/27: Nial Stewart: Re: Software bloat (Larkin was right)
    147823: 10/05/25: krw@att.bizzzzzzzzzzzz: Re: Software bloat (Larkin was right)
147807: 10/05/25: MooseFET: Re: Software bloat (Larkin was right)
147809: 10/05/25: d_s_klein: Re: Software bloat (Larkin was right)
147818: 10/05/25: Rob Gaddi: Advice on Xilinx Spelunking
    147820: 10/05/25: glen herrmannsfeldt: Re: Advice on Xilinx Spelunking
        147824: 10/05/25: Rob Gaddi: Re: Advice on Xilinx Spelunking
    147821: 10/05/25: John_H: Re: Advice on Xilinx Spelunking
    147822: 10/05/25: Symon: Re: Advice on Xilinx Spelunking
    147826: 10/05/26: Brian Drummond: Re: Advice on Xilinx Spelunking
        147827: 10/05/25: Rob Gaddi: Re: Advice on Xilinx Spelunking
            147828: 10/05/26: Nial Stewart: Re: Advice on Xilinx Spelunking
                147838: 10/05/26: Rob Gaddi: Re: Advice on Xilinx Spelunking
                    147840: 10/05/26: Nial Stewart: Re: Advice on Xilinx Spelunking
                        147872: 10/05/28: Rob Gaddi: Re: Advice on Xilinx Spelunking
                            147879: 10/05/28: Brian Drummond: Re: Advice on Xilinx Spelunking
            147831: 10/05/26: Brian Drummond: Re: Advice on Xilinx Spelunking
        147841: 10/05/26: Darol Klawetter: Re: Advice on Xilinx Spelunking
        147859: 10/05/27: rickman: Re: Advice on Xilinx Spelunking
        147864: 10/05/28: John_H: Re: Advice on Xilinx Spelunking
        147870: 10/05/28: rickman: Re: Advice on Xilinx Spelunking
        147878: 10/05/28: rickman: Re: Advice on Xilinx Spelunking
147819: 10/05/25: Philip Pemberton: Re: Software bloat (Larkin was right)
147825: 10/05/25: shantesh: BRAM with output register using ram_style attribute
    147830: 10/05/26: John_H: Re: BRAM with output register using ram_style attribute
147832: 10/05/26: bdurr: crc16 with 16 bit inputs
    147833: 10/05/26: Stef: Re: crc16 with 16 bit inputs
        147836: 10/05/26: Stef: Re: crc16 with 16 bit inputs
        147851: 10/05/27: Petter Gustad: Re: crc16 with 16 bit inputs
        147855: 10/05/27: Stef: Re: crc16 with 16 bit inputs
    147834: 10/05/26: Jon Beniston: Re: crc16 with 16 bit inputs
    147835: 10/05/26: wojtek: Re: crc16 with 16 bit inputs
    147848: 10/05/26: Eric Smith: Re: crc16 with 16 bit inputs
    147853: 10/05/27: Florian: Re: crc16 with 16 bit inputs
    147857: 10/05/27: Fredxx: Re: crc16 with 16 bit inputs
    147863: 10/05/27: OutputLogic: Re: crc16 with 16 bit inputs
147837: 10/05/26: Leon: Using XMOS devices to replace FPGAs
    147839: 10/05/26: rickman: Re: Using XMOS devices to replace FPGAs
    147843: 10/05/26: Leon: Re: Using XMOS devices to replace FPGAs
    147845: 10/05/26: rickman: Re: Using XMOS devices to replace FPGAs
    147860: 10/05/27: rickman: Re: Using XMOS devices to replace FPGAs
147842: 10/05/26: Kazu: Help (Virtex 155 and 220 compatibility) !
    147844: 10/05/26: Gabor: Re: Help (Virtex 155 and 220 compatibility) !
147849: 10/05/26: doomsten: how to decrypt Xilinx ISE12.1 IPCORE source code
147850: 10/05/26: doomsten: Xilinx ISE12.1 IPCORE source code
147852: 10/05/27: Sean Durkin: Xilinx' partition flow in ISE12.1
    148414: 10/07/20: Kate Kelley: Re: Xilinx' partition flow in ISE12.1
147861: 10/05/27: Vivek Menon: =?windows-1252?Q?Verifying=2Fcomparing_the_FFT_output_between_Xilinx_Co?=
    147898: 10/05/31: ajjc: =?windows-1252?Q?Re=3A_Verifying=2Fcomparing_the_FFT_output_between_Xilin?=
        147951: 10/06/04: Brian Drummond: Re: Verifying/comparing the FFT output between Xilinx Coregen block and Matlabís fft function
            147961: 10/06/04: Brian Drummond: Re: Verifying/comparing the FFT output between Xilinx Coregen block and Matlabís fft function
    147946: 10/06/03: Vivek Menon: =?windows-1252?Q?Re=3A_Verifying=2Fcomparing_the_FFT_output_between_Xilin?=
    147956: 10/06/03: Vivek Menon: =?windows-1252?Q?Re=3A_Verifying=2Fcomparing_the_FFT_output_between_Xilin?=
    147963: 10/06/04: ajjc: =?windows-1252?Q?Re=3A_Verifying=2Fcomparing_the_FFT_output_between_Xilin?=
147865: 10/05/28: Sharath Raju: Block RAM unusually long setup time ?
    147866: 10/05/28: Sharath Raju: Re: Block RAM unusually long setup time ?
    147867: 10/05/28: Gabor: Re: Block RAM unusually long setup time ?
    147876: 10/05/28: Sharath Raju: Re: Block RAM unusually long setup time ?
    147899: 10/06/01: Sharath Raju: Re: Block RAM unusually long setup time ?
    147902: 10/06/01: John_H: Re: Block RAM unusually long setup time ?
    147903: 10/06/01: Ed McGettigan: Re: Block RAM unusually long setup time ?
    147935: 10/06/03: Sharath Raju: Re: Block RAM unusually long setup time ?
147868: 10/05/28: Hauke D: Re: Programming Digilent Nexys 2 from Linux
    147875: 10/05/28: Patrick Maupin: Re: Programming Digilent Nexys 2 from Linux
    147884: 10/05/29: regomodo: Re: Programming Digilent Nexys 2 from Linux
        147931: 10/06/02: jt_eaton: Re: Programming Digilent Nexys 2 from Linux
    147888: 10/05/30: =?ISO-8859-1?B?RGlu52F5IEFr5/ZyZW4=?=: Re: Programming Digilent Nexys 2 from Linux
147869: 10/05/28: rickman: Anyone else need bigger parts in small (low pin count) packages
    147871: 10/05/28: Rob Gaddi: Re: Anyone else need bigger parts in small (low pin count) packages
        147873: 10/05/28: Uwe Bonnes: Re: Anyone else need bigger parts in small (low pin count) packages
            148078: 10/06/19: Jaime Andres Aranguren C.: Re: Anyone else need bigger parts in small (low pin count) packages
        147883: 10/05/29: Nico Coesel: Re: Anyone else need bigger parts in small (low pin count) packages
    147877: 10/05/28: rickman: Re: Anyone else need bigger parts in small (low pin count) packages
    147881: 10/05/29: Symon: Re: Anyone else need bigger parts in small (low pin count) packages
        147882: 10/05/29: Michael Kellett: Re: Anyone else need bigger parts in small (low pin count) packages
            147885: 10/05/30: Symon: Re: Anyone else need bigger parts in small (low pin count) packages
                147904: 10/06/01: Rob Gaddi: Re: Anyone else need bigger parts in small (low pin count) packages
                    147906: 10/06/01: Nico Coesel: Re: Anyone else need bigger parts in small (low pin count) packages
                    147908: 10/06/01: Symon: Re: Anyone else need bigger parts in small (low pin count) packages
    147892: 10/05/31: John Adair: Re: Anyone else need bigger parts in small (low pin count) packages
    147905: 10/06/01: Marc Jet: Re: Anyone else need bigger parts in small (low pin count) packages
    147909: 10/06/01: rickman: Re: Anyone else need bigger parts in small (low pin count) packages
    147910: 10/06/01: -jg: Re: Anyone else need bigger parts in small (low pin count) packages
    147916: 10/06/02: rickman: Re: Anyone else need bigger parts in small (low pin count) packages
    147917: 10/06/02: rickman: Re: Anyone else need bigger parts in small (low pin count) packages
    147918: 10/06/02: Marc Jet: Re: Anyone else need bigger parts in small (low pin count) packages
    147919: 10/06/02: rickman: Re: Anyone else need bigger parts in small (low pin count) packages
    147923: 10/06/02: -jg: Re: Anyone else need bigger parts in small (low pin count) packages
    147924: 10/06/02: rickman: Re: Anyone else need bigger parts in small (low pin count) packages
    147929: 10/06/02: -jg: Re: Anyone else need bigger parts in small (low pin count) packages
    147936: 10/06/03: rickman: Re: Anyone else need bigger parts in small (low pin count) packages
    147948: 10/06/03: -jg: Re: Anyone else need bigger parts in small (low pin count) packages
    147949: 10/06/03: rickman: Re: Anyone else need bigger parts in small (low pin count) packages
    147954: 10/06/03: -jg: Re: Anyone else need bigger parts in small (low pin count) packages
    147957: 10/06/03: rickman: Re: Anyone else need bigger parts in small (low pin count) packages
    147958: 10/06/04: -jg: Re: Anyone else need bigger parts in small (low pin count) packages
    147959: 10/06/04: rickman: Re: Anyone else need bigger parts in small (low pin count) packages
147874: 10/05/28: onkars: Estimating resource utilization of cores (from Xilinx CoreGen)
    147880: 10/05/28: Andy Peters: Re: Estimating resource utilization of cores (from Xilinx CoreGen)
        147890: 10/05/30: onkars: Re: Estimating resource utilization of cores (from Xilinx CoreGen)
            147891: 10/05/30: Mike Treseler: Re: Estimating resource utilization of cores (from Xilinx CoreGen)
147894: 10/05/31: Marc Jet: Effect of fanout on route delay (Spartan3)
    147896: 10/05/31: Chris Maryan: Re: Effect of fanout on route delay (Spartan3)
        147897: 10/05/31: glen herrmannsfeldt: Re: Effect of fanout on route delay (Spartan3)


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