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On May 8, 9:56=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > niyander <mightycatniyan...@gmail.com> wrote: > > I am trying to implement (simulation + synthesis) for 32bit floating > > point division unit. > > To perform division basically the 23+1bit (1 hidden bit) mantissa part > > is divided with the other mantissa, and then 8bit exponents are > > subtracted and finally normalization is applied. > > So for the mantissa division part I am following Binary Division by > > Shift and Subtract method (http://courses.cs.vt.edu/~cs1104/Division/ > > ShiftSubtract/Shift.Subtract.html). > > I can use this algorithm if both the mantissa's are such that no > > remainder is left (i.e. remainder=3D0) but if mantissa's are such that = a > > remainder is left then how can i proceed with the division? if i > > proceed then quotient would be inaccurate. > > You either truncate or round. =A0Unless you are implementing an > existing architecture, it is your choice. IBM hex floating point > truncates, most of the others, including IEEE, round. =A0 > > > I have already searched google for srt division algorithm but i am not > > able to find an simple example. If some one give me srt division > > example/algorithm for a value of 22/7 i would really appreciate that. > > That will help you do it faster, but it won't change the question > about what to do with a remainder. =A0If shift and subtract, or > more likely a non-restoring algorithm, is fast enough then you > might just as well use it. =A0 > > -- glen thanksArticle: 147626
Hello, I am working on Vertex-5 and i have made a 20-bit counter. i have taken signal counter : std_logic_vector (19 downto 0) Output of the counter is monitored on scope with pre-specified pins. But surprisingly the output is first 8-bit showing proper counting and next 8-bit is similar to 1st 8-bit and last 4-bit is showing output 0. This is very strange. I dont konw common or uncommon mistake i have done. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147627
Dear all Here's my problem: I've developed an VHDL IP in ISE and integrate it into a Microblaze peripheral using the "create and import peripheral" tool. My IP uses 3 read only and one write only registers to interface with the IPIC module. The IP has one ENB input that must be set to start the operation of the FSM within, and once the IP is running, it sets the RUN output. I have connected the ENB signal to one register (the control register) and the RUN signal to another register (the status register). (I know, this is not very elegant, but I'm just trying to make the thing work) Now, the strange thing is this: when I do functional simulation in modelsim, the IP works as expected. When I do BFM Simulation in Platform Studio, the module also works, at least as far as I can tell. The problem is that when I integrate the module into my system and set the control register from the C code, the IP does not work, ie, the status register is not set. My first thought was that I made a mistake at the IPIC register interface, so I use a test version of my IP with RUN <= ENB and when I set ENB, the RUN is set inside the IP. So the problem must be on the IP. I have checked and double checked the code and I couldn't find noting obviously wrong, but since I don't have much experience in VHDL, I must be missing something or doing some stupid error. Does any one have some ideas? I really appreciate a fresh look at my code. Regards, jmariano (ISE 7.1i, XPS 7.1i, Spartan-3 Starter Kit Board)Article: 147628
On May 8, 11:26=A0pm, rickman <gnu...@gmail.com> wrote: > Everything snipped... > You're welcome > That is why I am going to take a good look at Verilog. =A0 Then go take a look > I've been > using VHDL for some 12 years and I still don't feel like I completely > understand even basic things like how signed/unsigned relate to > std_ulogic and how closely related types... well, relate! > It was in what the snipped part that you pitched out so ungloriously at the start...maybe you shouldn't be so hasty > When you convert slv to unsigned or unsigned using unsigned(), this is > not really a conversion is it? Yes, it converts a std_logic_vector to an unsigned type...if it makes you feel better think of it as applying a particular numeric interpretation to a collection of bits so that you can add them, subtract them > =A0It is not the same as using > to_integer() to convert signed to integer. =A0 Perhaps you should explain why you think that 'to_integer' is somehow different than converting between std_logic_vectors and (un)signed? Hint: They're fundamentally not...they are both converting between things of different types. > In the std_numeric library > they include conversion functions between integer and signed/ > unsigned. =A0But there are no functions to convert slv and these types. slv_sig <=3D std_logic_vector(uns_sig); un_sig1 <=3D unsigned(slv_sig); What's the trouble? > So it would seem this is not a conversion by function. =A0 It would seem you missed how to convert between the types...not that they are not type conversion functions. > So what is > it? A type conversion > > At one time I thought I understood all this, but it is so far removed > from getting work done that I typically adopt standard practices and > forget the details. =A0Then when I need to figure out something new I > have to go back to basics. =A0It just gets so time consuming. =A0I want t= o > focus on the work, not the method. > Good luck with Verilog KJArticle: 147629
On May 9, 12:04=A0pm, "jogendersaini" <jogendra.saini@n_o_s_p_a_m.gmail.com> wrote: > Hello, > > I am working on Vertex-5 and i have made a 20-bit counter. > > i have taken > > signal counter : std_logic_vector (19 downto 0) > > Output of the counter is monitored on scope with pre-specified pins. But > surprisingly the output is first 8-bit showing proper counting and next > 8-bit is similar to 1st 8-bit and last 4-bit is showing output 0. This is > very strange. I dont konw common or uncommon mistake i have done. > 1. Simulate your design until you can show that the design is functionally correct. 2. Perform timing analysis until you can show that the design has no timing errors. 3. Watch the scope show that everything is now working as you'd expect. KJArticle: 147630
On 08/05/2010 10:57, Petter Gustad wrote: > General Schvantzkoph<schvantzkoph@yahoo.com> writes: > >> that with scripts which is easier to do on Linux although the scripts can >> run on Windows if you have Cygwin installed. > > But Cygwin is slooow, especially file access, e.g using git under > Cygwin is almost impossible. > > Petter Where possible, use msys (and mingw) instead of cygwin. Cygwin goes a lot further in its posix support and simulation of a linux-style system. But that means more layers to handle the fundamental differences between Linux and Windows, and that costs in performance even if you don't need it. Msys/mingw is simpler - you don't get features that windows can't support, but what you do get runs at native speeds. I don't know if git will run with msys (and something like ActivePerl), but if it does, it will be much faster than with cygwin. Slower than under Linux, but not as bad.Article: 147631
On Apr 20, 11:39=A0am, luudee <rudolf.usselm...@gmail.com> wrote: > On Apr 12, 8:24=A0pm, luudee <rudolf.usselm...@gmail.com> wrote: > > > > > On Apr 1, 12:04=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Mar 31, 1:51=A0am, luudee <rudolf.usselm...@gmail.com> wrote: > > > > > Does anybody else, besides xilinx, make FMC boards for ml605 & sp60= 5 ? > > > > > HW-FMC-XM105-G =A0FMC XM105 DEBUG CARD > > > > HW-FMC-XM104-G =A0FMC CONNECTIVITY MEZZANINE CARD > > > > > Buying Xilinx products now means going through Avnet, which is a > > > > nightmare and HUGE lead times ... > > > > > Thanks, > > > > rudi > > > > While the XM104 is listed with a 8 week lead time on the Avnet site, = I > > > know that we have these available in inventory and they will ship > > > promptly after the order is placed. =A0The XM105 is listed with a 2 w= eek > > > lead time. > > > > There are a number of other companies releasing FMC cards, just be > > > sure that the cards support a VADJ of 2.5V and there shouldn't be a > > > problem. > > > > 4DSP recently announced a FMC familyhttp://www.przoom.com/news/66794/ > > > > Curtiss-Wright also has a number of boards.http://www.cwcembedded.com= /0/62/651.html > > > > And Xilinx has a number of other boards in pipeline to be released > > > next quarter.http://www.xilinx.com/fmc > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > Ed, > > > just an update ... > > > I ordered the above two boards through Avnet on April 1st. > > > As of today (April 12th), they are still listed as on "back order" > > with 2 & 8 week lead times. > > > Is there an alternative way to buy these boards ? We are an > > alliance partner if makes any difference ... > > > Thanks, > > rudi@i_hate_avnet.suck > > UPDATE 2 > > today I got an email that the XM105 shipped (alone). I SPECIFICALLY > checked that the boards be shipped together. The board is $159 USD, > shipping is $55 USD. > > No word when the XM104 will ship. > > Another AVnet disaster .... > > rudi UPDATE 3 Today, I finally received the final shipment from AVnet. 5 weeks and 3 days after I ordered the boards. And I had the priviledge to pay twice for shipping. Is anybody from Xilinx paying attention ? Is that the kind of experience you want to leave your customers with ? Cheers, rudiArticle: 147632
On May 6, 8:26=A0am, General Schvantzkoph <schvantzk...@yahoo.com> wrote: > Quartus 9.1 has parallel processing support on Linux, I've never used it > on Windows so I don't know if it also has parallel support on Windows. Hi, all parallel features are identical in both Windows and Linux. Cheers, Adrian Ludwin Altera CorpArticle: 147633
I thought there was a change in the latest version of vhdl that redefined std_logic_vector as a resolved subtype of std_ulogic_vector? That would make SLV and SULV as interchangeable as SL and SUL. Anyway, VHDL allows for "built-in" conversions (explicitly invoked) between "closely related" aggregate types. "CR" means that both types are aggregates of the same element type. These built-in conversions are invoked by simply using the name of the target type, so to convert SLV to unsigned, you just need "unsigned(my_slv)". BTW, I always create a subtype slv as follows: subtype slv is std_logic_vector; Now, "slv" is its own (sub)type name which can be used for declarations, and even a built-in conversion invocation: my_slv <= slv(my_unsigned); You could probably do the same thing with an alias, but I figured out the subtype trick first. AndyArticle: 147634
Hi,
I am trying to implement autocorrelation operation on an FPGA.
Autocorrelation can be written as: Phi(n) =3D Summation { x(k) * x(n-
k) }
Essentially, the signal x(k) is multiplied with a delayed version of
itself and the product is accumulated over a finite range of x(k)
samples.
I have written VHDL code, where the delay, multiply and accumulate
operations are carried out sequentially at the rising edge of the
clock.
{link to code http://sites.google.com/site/brsharath/sdmac_approach0_1.vhd?=
attredirects=3D0&d=3D1
}
In the clock process, I expect the statements within the "if block" to
execute sequentially. However, in the RTL description,
{link
http://5483477158486903344-a-1802744773732722657-s-sites.googlegroups.com/s=
ite/brsharath/sdmac_approach0_1.png?attachauth=3DANoY7cp-FCHAwKIai7JuTsVPgv=
AENU4ou15FLhplgwxKlODHsz3G3sNsTOC2xPAoaNE8IntPEYP7T9A76ACM5Ry9o6rRLdbvVtI0n=
VThp84mEtGt6bGuw2RmVcTG9sEmAQ2ULQXNYqR4xlihAZlDayHEaw7u-PsfE4HqAbgtr8fRUFm2=
2PjwSkiLrtj5rMvP5WyDwMGxA31ByVc3sdISyWa1fQClsMXTlw%3D%3D&attredirects=3D0}
it is seen that the adder and output D flip-flop of the multiplier
triggered by the same clock signal, without any delay between the two.
This causes the adder block to operate even before the multiplier
output reaches the adder input. Why is this so ? Further, in the
functional simulation, I see that the output of the DMAC unit is
updated after two clock cycles. My requirement is that the delay,
multiply and accumulate operations happen sequentially and within the
same clock cycle.
If the above description is not clear, please let me know, I may be
able to explain in a simpler manner.
Thanks,
Sharath
Article: 147635I am pleased to announce the next upcoming FPGACamp to be held on May'21, 2010. The registration for the event is completely FREE. You can RSVP by visitinghttp://events.linkedin.com/FPGA-Camp-Bangalore-India/pub/281752 orhttp://www.fpgacentral.com/fpgacamp FPGA Camp is the 1st and only open source FPGA conference, which brings engineers together and discusses FPGA, mainly NextGen FPGA technology, application, methodology, best practices and challenges. Also provide a location to meet other local FPGA designers to share their stories. Agenda (visit http://www.fpgacentral.com/fpgacamp for details) 09:00 Registration & Booths 09:30 Welcome & Introductions 09:45 KeyNote 10:30 Mastering FPGA Design through Debug : Adrian Hernandez, Senior Manager, Xilinx USA 11:15 Tea break 11:30 Latest High Speed Transceiver Technology provides answer to the Bandwidth Bottleneck in the Telecommunication Industry - John Wei, Altera , Hong Kong 12:15 Upgrading to SystemVerilog for FPGA Designs - Srinivasan Venkataramanan, CVC 12:45 Lunch & Booths 02:00 Memories; interfaces and controllers - Sandeep Kulkarni, Lattice 02:45 Panel Discussion State of FPGA technology & its adoption in India 03:30 Tea break 03:15 Customer Presentation 04:15 Vendor Presentation (small presentations from various vendors about their product - 5 to 10 mins) 05:00 Booths Continues Sponsors: Platinum Sponsor Altera Gold Sponsors Xilinx, Lattice Silver Sponsor ARM Registration: FREE! Feel free to bring a friend. Just RSVP here or fill the form at http://www.fpgacentral.com/fpgacamp Contact us if you would like to: - Volunteer with us - Speak or Refer a speaker If you are a vendor: - Would like to put a booth - Free -Demo/Talk about a product: Free (Tell us what and why) Look forward to see you all at the event. Registration is first come first serve, recommend to register before all the seats are filled. Cheers, VikramArticle: 147636
Hello, I had a look into the V6 Datasheets, but couldn't find a direct clue. Would it be possible to implemement two PCIe Endpoints in one Virtex-6 FPGA? Most of the V6-Devices offer two hard PCIe blocks and the PCIe root device should initiate link training on all lanes. If I understand this correctly, it should be possible, to build a card with for example a x8 finger, 4 lanes to one PCIe hard block, 4 to the other, which would identify to the host system as two independent x4 systems but plugged into one x8 slot. Am I missing something? Comments are greatly appreciated. Cheers, HEArticle: 147637
On 11 Mai, 06:32, Sharath Raju <brshar...@gmail.com> wrote:
> Hi,
>
> I am trying to implement autocorrelation operation on an FPGA.
> Autocorrelation can be written as: Phi(n) =3D Summation { x(k) * x(n-
> k) }
> Essentially, the signal x(k) is multiplied with a delayed version of
> itself and the product is accumulated over a finite range of x(k)
> samples.
>
> I have written VHDL code, where the delay, multiply and accumulate
> operations are carried out sequentially at the rising edge of the
> clock.
>
> {link to codehttp://sites.google.com/site/brsharath/sdmac_approach0_1.vhd=
?attredir...
>
> }
>
> In the clock process, I expect the statements within the "if block" to
> execute sequentially. However, in the RTL description,
>
> {linkhttp://5483477158486903344-a-1802744773732722657-s-sites.googlegroup=
s...}
> =A0it is seen that the adder and output D flip-flop of the multiplier
> triggered by the same clock signal, without any delay between the two.
> This causes the adder block to operate even before the multiplier
> output reaches the adder input. =A0Why is this so ? Further, in the
> functional simulation, I see that the output of the DMAC unit is
> updated after two clock cycles. My requirement is that the delay,
> multiply and accumulate operations happen sequentially and within the
> same clock cycle.
>
> If the above description is not clear, please let me know, I may be
> able to explain in a simpler manner.
>
> Thanks,
> Sharath
Hi Sharath,
I wonder that your code synthesizes at all.
Normally a process with two different clock triggers (rising edge and
falling edge) would cause an error,
Maybe you got luck, because your signal del_2_x doesn't appear in the
other clock region.
Anyway, this half clock delay is unnecessary. Make it a full cycle or
leave it away.
Also you have no reset scheme, just default assignments in the
declarations.
Xilinx ISE can handle that, but other tools ignore it.
Now to your implementation, do you know about pipelining?
This is what's happening in your code. It's nothing bad, just
something to be considered.
Remember the driver/reader concept of VHDL signals?
So when you are assigning to some signal ,the value is writen to the
signals driver, but other assignments that use this signal in the same
process take the old value from the signals reader.
Every assignment in a clocked process creates a register, so you have
to take care that your datapath has proper delays for all signals, to
put the right data at the right time at the inputs of yor arithmetic
operators.
Did you make a time schedule plan for your data? There you can see
which signals need extra delay
Have a nice simulation
Eilert
Article: 147638On Mon, 10 May 2010 23:31:23 -0700 (PDT) backhus <goouse99@googlemail.com> wrote: [snip] > Also you have no reset scheme, just default assignments in the > declarations. > Xilinx ISE can handle that, but other tools ignore it. [snip] Sorry for hijacking the thread, but... do you mean that if I write this code: signal foo : std_ulogic_vector(3 downto 0) := "1010"; I would *not* normally expect the FPGA to power up with "1010" in the signal!? I've only ever worked with Xilinx FPGAs using ISE, so I assumed it worked everywhere; is this not the case? (kind of nice to know in case I do some day end up using a different make of FPGA...) ChrisArticle: 147639
> Sorry for hijacking the thread, but... do you mean that if I write this > code: > signal foo : std_ulogic_vector(3 downto 0) := "1010"; > I would *not* normally expect the FPGA to power up with "1010" in the > signal!? I've only ever worked with Xilinx FPGAs using ISE, so I > assumed it worked everywhere; is this not the case? (kind of nice to > know in case I do some day end up using a different make of FPGA...) You shouldn't rely in this if you want your designs to be 'portable'. You should also think about active reset logic for your design so that you know everything will definitely power up to a known state. What happens if you have a portion of your design you want to hold in reset until something else is configured properly? I have done this to allow a quick simulation of a module and know that Quartus throws up a warning (although I'm not sure if it does actually implement the reset value). Bottom line is you need a reset mechanism in to set these values. Nial.Article: 147640
I would of thought if the PCIe spec says that you can do this then it would be possible to do it. If the Virtex 6 hardblocks operate independently from each other then it comes down to what the PCIe spec says. Regards Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147641
On May 11, 6:55=A0am, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > I would of thought if the PCIe spec says that you can do this then it wou= ld > be possible to do it. If the Virtex 6 hardblocks operate independently fr= om > each other then it comes down to what the PCIe spec says. > > Regards > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I don't think the PCIe specification requires a system to connect to multiple endpoints in a multi-lane slot. In fact I would bet that if you tried this in a typical PC you would at best get a single 4-lane endpoint detected and at worst a "broken" 8-lane endpoint, due to the hardware connections to the second 4 lanes. It's also possible that some systems would allow this sort of connection, but if you look at typical PCIe switches, it would mean they would need to allocate more switch resources to the slot to handle what is probably an unusual case. In my experience with PC motherboards, economics are always the deciding factor in what gets supported. Corner cases are often thrown out the window when they incur any extra cost.Article: 147642
On May 8, 8:26=A0pm, rickman <gnu...@gmail.com> wrote: > Everything snipped... > > That is why I am going to take a good look at Verilog. =A0I've been > using VHDL for some 12 years and I still don't feel like I completely > understand even basic things like how signed/unsigned relate to > std_ulogic and how closely related types... well, relate! Well, since Verilog knows nothing about types, there are no conversions. But you do a lot of DSP, and proper numeric representation is obviously important. You'll go absolutely batshit crazy trying to sort out numeric operations in Verilog. (And don't buy into that line about how "C and Verilog are highly similar.") FWIW, I tend to always use VHDL's unsigned() and signed() (as needed) types in preference to std_logic_vectors when the arrays of bits represent actual numbers. I also use unsigned() and signed() types on port lists. For things like counters, I use ranged naturals, unless of course the count can be negative. -aArticle: 147643
I used the simple dual port ram in quartus with the altera fpga,but when i simulate it in 100Mhz, the read data isn't what i haved writen in. but the classic timing analyzer shows the fmax is about 200Mhz.could anybody help me. I am so bothered with it. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147644
Hi all i'm suing ISE 11.4 and ModelSim XE III when i do the behavioral simulation it works well but when i do the post place & route simulation the ModelSim report this errors "# ** Error: netgen/par/fpu_double_timesim.vhd(45842): (vcom-1141) Identifier "x_dsp48a1" does not identify a component declaration." how can i fix this error?! thanks in advance --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147645
On May 11, 12:23=A0pm, Andy Peters <goo...@latke.net> wrote: > But you do a lot of DSP, and proper numeric representation is > obviously important. You'll go absolutely batshit crazy trying to sort > out numeric operations in Verilog. (And don't buy into that line about > how "C and Verilog are highly similar.") Verilog and DSP is not very difficult. And C is quite similar in some ways, although it does have nice features like structures that are not available in (non-System) Verilog. But, if you're happy coding with C, you can easily code most of your testbench in C with verilog. Regards, PatArticle: 147646
"rickman" <gnuarm@gmail.com> wrote in message news:f7fe2df7-3398-4f24-8146-71192784abf7@t17g2000vbk.googlegroups.com... >I think I have about had it with VHDL. I've been using the > numeric_std library and eventually learned how to get around the > issues created by strong typing although it can be very arcane at > times. I have read about a few suggestions people are making to help > with some aspects of the language, like a selection operator like > Verilog has. But it just seems like I am always fighting some aspect > of the VHDL language. > > I guess part of my frustration is that I have yet to see where strong > typing has made a real difference in my work... at least an > improvement. My customer uses Verilog and has mentioned several times > how he had tried using VHDL and found it too arcane to bother with. > He works on a much more practical level than I often do and it seems > to work well for him. > > One of my goals over the summer is to teach myself Verilog so that I > can use it as well as I currently use VHDL. Then I can make a fully > informed decision about which I will continue to use. I'd appreciate > pointers on good references, web or printed. > > Without starting a major argument, anyone care to share their feelings > on the differences in the two languages? > > Rick The last time I searched the general-purpose jobs newsgroup for jobs available for either, there were about twice as many jobs available for VHDL as for Verilog. Looks to me like a good reason to learn both, and then stay current enough on both to be able to use either, as the job prefers. Robert Miles a Verilog user, retired early due to health reasons previously a LASAR 6 user and a Logic 5 userArticle: 147647
On May 11, 10:45=A0pm, "Robert Miles" <mile...@usenet-news.net> wrote: > "rickman" <gnu...@gmail.com> wrote in message > > news:f7fe2df7-3398-4f24-8146-71192784abf7@t17g2000vbk.googlegroups.com... > > > > >I think I have about had it with VHDL. =A0I've been using the > > numeric_std library and eventually learned how to get around the > > issues created by strong typing although it can be very arcane at > > times. =A0I have read about a few suggestions people are making to help > > with some aspects of the language, like a selection operator like > > Verilog has. =A0But it just seems like I am always fighting some aspect > > of the VHDL language. > > > I guess part of my frustration is that I have yet to see where strong > > typing has made a real difference in my work... at least an > > improvement. =A0My customer uses Verilog and has mentioned several time= s > > how he had tried using VHDL and found it too arcane to bother with. > > He works on a much more practical level than I often do and it seems > > to work well for him. > > > One of my goals over the summer is to teach myself Verilog so that I > > can use it as well as I currently use VHDL. =A0Then I can make a fully > > informed decision about which I will continue to use. =A0I'd appreciate > > pointers on good references, web or printed. > > > Without starting a major argument, anyone care to share their feelings > > on the differences in the two languages? > > > Rick > > The last time I searched the general-purpose jobs newsgroup for jobs > available for either, there were about twice as many jobs available for > VHDL as for Verilog. =A0Looks to me like a good reason to learn both, > and then stay current enough on both to be able to use either, as the > job prefers. Yes, I guess jobs is important to many, but I work for myself and my main customer uses Verilog. He hasn't had a problem with me using VHDL, but every time I express any exasperation with some aspect of VHDL I am reminded of how Verilog doesn't have that problem. I know of a few instances of when strong typing found bugs for me before they turned into lab bug searches... which is one of the main reasons for using such features. The earlier in the process bugs are found, the easier they are found and the smaller the impact. Still, there is a cost and the question is whether the cost is justified... RickArticle: 147648
"rickman" <gnuarm@gmail.com> wrote in message news:95699341-d174-4ce0-89de-c169c903d86e@d39g2000yqa.googlegroups.com... On May 11, 10:45 pm, "Robert Miles" <mile...@usenet-news.net> wrote: > "rickman" <gnu...@gmail.com> wrote in message > > news:f7fe2df7-3398-4f24-8146-71192784abf7@t17g2000vbk.googlegroups.com... > > > > >I think I have about had it with VHDL. I've been using the > > numeric_std library and eventually learned how to get around the > > issues created by strong typing although it can be very arcane at > > times. I have read about a few suggestions people are making to help > > with some aspects of the language, like a selection operator like > > Verilog has. But it just seems like I am always fighting some aspect > > of the VHDL language. > > > I guess part of my frustration is that I have yet to see where strong > > typing has made a real difference in my work... at least an > > improvement. My customer uses Verilog and has mentioned several times > > how he had tried using VHDL and found it too arcane to bother with. > > He works on a much more practical level than I often do and it seems > > to work well for him. > > > One of my goals over the summer is to teach myself Verilog so that I > > can use it as well as I currently use VHDL. Then I can make a fully > > informed decision about which I will continue to use. I'd appreciate > > pointers on good references, web or printed. > > > Without starting a major argument, anyone care to share their feelings > > on the differences in the two languages? > > > Rick > > The last time I searched the general-purpose jobs newsgroup for jobs > available for either, there were about twice as many jobs available for > VHDL as for Verilog. Looks to me like a good reason to learn both, > and then stay current enough on both to be able to use either, as the > job prefers. Yes, I guess jobs is important to many, but I work for myself and my main customer uses Verilog. He hasn't had a problem with me using VHDL, but every time I express any exasperation with some aspect of VHDL I am reminded of how Verilog doesn't have that problem. I know of a few instances of when strong typing found bugs for me before they turned into lab bug searches... which is one of the main reasons for using such features. The earlier in the process bugs are found, the easier they are found and the smaller the impact. Still, there is a cost and the question is whether the cost is justified... Rick --- Looks like you've had better luck than I did at finding new jobs without moving to another state to be near the job location. But then my last job ended back in 2002, so things could easily have changed since then. Robert MilesArticle: 147649
On 11 Mai, 09:11, Christopher Head <ch...@cs.ubc.ca> wrote: > On Mon, 10 May 2010 23:31:23 -0700 (PDT) > > backhus <goous...@googlemail.com> wrote: > > [snip]> Also you have no reset scheme, just default assignments in the > > declarations. > > Xilinx ISE can handle that, but other tools ignore it. > > [snip] > > Sorry for hijacking the thread, but... do you mean that if I write this > code: > > signal foo : std_ulogic_vector(3 downto 0) := "1010"; > > I would *not* normally expect the FPGA to power up with "1010" in the > signal!? I've only ever worked with Xilinx FPGAs using ISE, so I > assumed it worked everywhere; is this not the case? (kind of nice to > know in case I do some day end up using a different make of FPGA...) > > Chris Hi Chris, That's right. The synthesis standard for VHDL treats assignments at declaration time as "ignored". They work and are intended to use for simulation (e.g. in testbenches). That XST uses these values is due to the fact that they can be held in the programming bitstream, and thus be present at power up for an SRAM based FPGA. Think of ASICs (or antifuse FPGAs) and this is no more true, so, as Neal mentioned, your code isn't portable anymore. Same is if you use a tool that strictly complies with the VHDL simulation standard. I didn't mention how to solve the problem, because that's a tricky question. It depends on many things whether you should do it, and how to do it. e.g. Registers in datapaths don't necessarily need a reset. The values are continuously overwritten. BUT: If you have a feedback path your simulation can stuck with 'X'es. One possible solution is to create Registers with an asynchronous reset, that will be used by ths testbench, and tied to the inactive state for synthesis. So the net will be optimized away and there are no 'X'es in a real chip. :-) For Counters/FSMs and such you have to decide. e.g.: A loadable counter doesn't need a reset, if the first thing that happens is a load operation. Also you should think about asynchronous and synchronous resets. A nice paper about this topic can be found on the Xilinx website. Have a nice synthesis Eilert
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