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hamilton <hamilton@nothere.com> writes: > So, do you have a design for the VGA output from your FPGA ?? Well, he did just ask about VGA timings and posted code too a few days ago, so that's probably a yes...Article: 148201
hamilton <hamilton@nothere.com> wrote in news:i06hvk$6p4$1 @news.eternal-september.org: > So, do you have a design for the VGA output from your FPGA ?? > Yes I do.Article: 148202
On Jun 27, 11:42=A0am, Giorgos Tzampanakis <g...@hw.ac.uk> wrote: > hamilton <hamil...@nothere.com> wrote in news:i06hvk$6p4$1 > @news.eternal-september.org: > > > So, do you have a design for the VGA output from your FPGA ?? > > Yes I do. Giorgios, At "http://opencores.org/project,yavga" you can find a simple VGA core. Maybe you can customize that project for your needs. There are also some (linux) shell script to easly customize the char- set. Regards SandroArticle: 148203
Hi, I am a verilog designer and I'd like to try OVL on an Actel design. I can't figure out how to use the OVL library. I downloaded it, but in the Actel Libero tool I can't find any way to add a path to the library. So if on my verilog code I put a OVL assertion, it will be flagged as an error by the Actel "Check HDL file" feature. Any advice ?Article: 148204
I wanted to know if anyone has used the Altera Stratix4GX PCIe card as a root port. I have used it as endpoint but have not used as a root- port. As an endpoint all I have to do is plug in the card to a motherboard. But as a root-port, it needs to send out the requests to end point.Article: 148205
On Jun 28, 5:20=A0am, tullio <tullio.gra...@gmail.com> wrote: > Hi, > > =A0I am a verilog designer and I'd like to try OVL on an Actel design. > I can't figure out how to use the OVL library. > I downloaded it, but in the Actel Libero tool I can't find any way to > add a path to the library. > So if on my verilog code I put a OVL assertion, it will be flagged as > an error by the Actel "Check HDL file" feature. > Any advice ? What makes you think that the Actel synthesizer is going to be able to deal with the Open Verification Library? AKAIK, there are few to no synthesizable parts of that library. RKArticle: 148206
Hi all, I would like to incorporate into my design a VGA controller . For this purpose, I am planning to use the Xilinx XPS TFT controller IP which has the VGA signals included in it. However, the issue is this IP has 6 bit width for each of the three colour components . However, the normal VGA port uses only one bit for this. I would like to know if it is possible to interface this IP to the normal VGA port using only one bit of the color components.? Or any good places where I could search for a VGA controller IP for this board? Thanks and RegardsArticle: 148207
The color signals for VGA are analog, not digital. Ordinarily you would run each six-bit color components into a six-bit DAC and amplifier to drive the VGA color signal. If you only want eight colors (including black and white), then you can use just one bit of each color; that's what some low-cost FPGA eval boards do. Finding a different VGA controller IP block isn't going to solve this problem.Article: 148208
Manmohan <mmmmec@gmail.com> wrote: > I would like to incorporate into my design a VGA controller . For this > purpose, I am planning to use the Xilinx XPS TFT controller IP which > has the VGA signals included in it. However, the issue is this IP has > 6 bit width for each of the three colour components . However, the > normal VGA port uses only one bit for this. > I would like to know if it is possible to interface this IP to the > normal VGA port using only one bit of the color components.? The usual VGA video signal is analog, so saying one bit isn't quite right. However, many FPGA based development boards only supply one bit. As the VGA monitor amplifiers have a finite (and ever increasing) bandwidth you could dither the output to get a few more colors. That might work better for CRT than for LCD though. Can you do a frequency multiplier with a DLL? If you get to 200MHz or so, and the video amplifier rolls off at 25MHz then you can get nine different values for each of R, G, and B. -- glenArticle: 148209
Hi, I am working on the creation of MicroBlaze. I am able to generate single BRAM of 64 KB. I would like to have many BRAM (say 4) each of size 8KB connected to the LMB Bus of the MicroBlaze. Can anyone explain how to do this. Thanks Vivek --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148210
Hello, I am not sure if this post is in the right place - I hope to get some help I am looking for a PCI/e based FPGA solution - The board should be able to support LVDS with 2 RJ45 i/o ports which connect to CAT5 cables. I plan to implement SPI signal on the FPGA and send the generated signal over LVDS. I am looking for a hardware solution for this. Can you please point to me viable options, and where I can find these? I am looking for solutions with PCI/e drivers and API which reduce my implementation time. thanks, Sharath --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148211
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'mult_ipif_0/mult_ipif_0/USER_LOGIC_I'
with
type 'user_logic' could not be resolved. A pin name misspelling can
cause
this, a missing edif or ngc file, or the misspelling of a type name.
Symbol
'user_logic' is not supported in target 'spartan3e'.
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock
driver
debug_module/debug_module/BUFG_DRCK1 drives no clock pins
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 1
Number of warnings: 1
One or more errors were found during NGDBUILD. No NGD file will be
written.
Writing NGDBUILD log file "system.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow
execution...
make: *** [__xps/system_routed] Error 1
Done!
can any one help ? i am learning this tool for EDk
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 148212On Jun 29, 2:38=A0pm, "sharath20284" <sharath20284@n_o_s_p_a_m.yahoo.com> wrote: > Hello, > > I am not sure if this post is in the right place - I hope to get some hel= p > > I am looking for a PCI/e based FPGA solution - The board should be able t= o > support LVDS with 2 RJ45 i/o ports which connect to CAT5 cables. I plan t= o > implement SPI signal on the FPGA and send the generated signal over LVDS. > > I am looking for a hardware solution for this. Can you please point to me > viable options, and where I can find these? I am looking for solutions wi= th > PCI/e drivers and API which reduce my implementation time. > > thanks, > Sharath > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Because SPI is amazingly slow (compared to LVDS-capable speeds) I'd suggest buying a generic PCI/e development board that would otherwise fit the bill then wire up your own RJ45s. There's no majic to having an "amazing" connection with SPI since it's such a lethargic communication method. Good luck.Article: 148213
We are struggling to get the ML605 board running on our Dell PowerEdge SC430 in slot 4 (x8 slot). Out of the box the unit did not recognize the card but I could view the system PCI architecture using PCITree. After building a PCIe x8 gen 1 core using ISE 12.1 (with the patch per AR#35422) per xtp0044.pdf, the unit now complains of an error when initializing PCI Exptress slot 4. I have tried all three settings of jumper J42. There are no other expansion slots being used. Has anyone struggled in a similar way bringing up their ML605 using the PCIe? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148214
Am 30.06.2010 02:45, schrieb steveb: > We are struggling to get the ML605 board running on our Dell PowerEdge > SC430 in slot 4 (x8 slot). Out of the box the unit did not recognize the > card but I could view the system PCI architecture using PCITree. After > building a PCIe x8 gen 1 core using ISE 12.1 (with the patch per AR#35422) > per xtp0044.pdf, the unit now complains of an error when initializing PCI > Exptress slot 4. I have tried all three settings of jumper J42. There are > no other expansion slots being used. > > Has anyone struggled in a similar way bringing up their ML605 using the > PCIe? > > > > --------------------------------------- > Posted through http://www.FPGARelated.com Did you try using 11.4 as suggested by the xtp044? I ran into some problems, too, using 12.1 + patch (without further investigation) but it all worked fine with 11.4 hthArticle: 148215
On Jun 29, 8:38=A0pm, "vivek1609" <vivek1609@n_o_s_p_a_m.rediffmail.com> wrote: > Hi, > > I am working on the creation of MicroBlaze. I am able to generate single > BRAM of 64 KB. I would like to have many BRAM (say 4) each of size 8KB > connected to the LMB Bus of the MicroBlaze. Can anyone explain how to do > this. > > Thanks > Vivek > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Hi, You can add as many LMB_BRAM controllers on the LMB Bus as you like. G=F6ranArticle: 148216
On 30 Juni, 09:44, Goran_Bilski <goran.bil...@xilinx.com> wrote: > On Jun 29, 8:38=A0pm, "vivek1609" <vivek1609@n_o_s_p_a_m.rediffmail.com> > wrote: > > > Hi, > > > I am working on the creation of MicroBlaze. I am able to generate singl= e > > BRAM of 64 KB. I would like to have many BRAM (say 4) each of size 8KB > > connected to the LMB Bus of the MicroBlaze. Can anyone explain how to d= o > > this. > > > Thanks > > Vivek > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > Hi, > > You can add as many LMB_BRAM controllers on the LMB Bus as you like. > > G=F6ran I did exactly that and it worked fine from a XPS point of view, but the SW guys working in EDK claimed that here was some kind of problem to use the extra RAM. I was a bit surprised since it was a simple task to make it appear in the address map as a continuation of the original RAM, maybe you G=F6ran can explain to me what could be the problem? The guy is on vacation right now and I never had time to get the full story. Thanks! /LarsArticle: 148217
I am not sure if such a program exists, but I would like to be able to test a fairly large design by not having to write lots of testbenches. Idealy I would like a program were I could connect my DUT and give some constraints and then test vectors would be produced to test all cases within the constraints. Has anyone had any experience of such a program? Thanks Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148218
On Jun 30, 12:58=A0pm, Lars <noreply.lar...@gmail.com> wrote: > On 30 Juni, 09:44, Goran_Bilski <goran.bil...@xilinx.com> wrote: > > > > > > > On Jun 29, 8:38=A0pm, "vivek1609" <vivek1609@n_o_s_p_a_m.rediffmail.com= > > > wrote: > > > > Hi, > > > > I am working on the creation of MicroBlaze. I am able to generate sin= gle > > > BRAM of 64 KB. I would like to have many BRAM (say 4) each of size 8K= B > > > connected to the LMB Bus of the MicroBlaze. Can anyone explain how to= do > > > this. > > > > Thanks > > > Vivek > > > > --------------------------------------- =A0 =A0 =A0 =A0 > > > Posted throughhttp://www.FPGARelated.com > > > Hi, > > > You can add as many LMB_BRAM controllers on the LMB Bus as you like. > > > G=F6ran > > I did exactly that and it worked fine from a XPS point of view, but > the SW guys working in EDK claimed that here was some kind of problem > to use the extra RAM. I was a bit surprised since it was a simple task > to make it appear in the address map as a continuation of the original > RAM, maybe you G=F6ran can explain to me what could be the problem? The > guy is on vacation right now and I never had time to get the full > story. > > Thanks! > /Lars- Hide quoted text - > > - Show quoted text - Hi Lars, I'm not aware of any SW issues on the extra RAM. The only thing I can think of is the linker script, they just have to make sure that the new RAM is included in the linker script. G=F6ranArticle: 148219
"maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote in message news:ceydnR30ct0U3bbRnZ2dnUVZ_jWdnZ2d@giganews.com... >I am not sure if such a program exists, but I would like to be able to test > a fairly large design by not having to write lots of testbenches. Idealy I > would like a program were I could connect my DUT and give some constraints > and then test vectors would be produced to test all cases within the > constraints. Has anyone had any experience of such a program? No experience myself but have a look at inFact: http://www.mentor.com/products/fv/infact/ Hans www.ht-lab.comArticle: 148220
On Jun 29, 8:30=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > On Jun 29, 2:38=A0pm, "sharath20284" > > > > <sharath20284@n_o_s_p_a_m.yahoo.com> wrote: > > Hello, > > > I am not sure if this post is in the right place - I hope to get some h= elp > > > I am looking for a PCI/e based FPGA solution - The board should be able= to > > support LVDS with 2 RJ45 i/o ports which connect to CAT5 cables. I plan= to > > implement SPI signal on the FPGA and send the generated signal over LVD= S. > > > I am looking for a hardware solution for this. Can you please point to = me > > viable options, and where I can find these? I am looking for solutions = with > > PCI/e drivers and API which reduce my implementation time. > > > thanks, > > Sharath > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > Because SPI is amazingly slow (compared to LVDS-capable speeds) I'd > suggest buying a generic PCI/e development board that would otherwise > fit the bill then wire up your own RJ45s. =A0There's no majic to having > an "amazing" connection with SPI since it's such a lethargic > communication method. That's probably not a bad idea, but don't consider SPI to be trivial to implement just because the data rate is not high. SPI has no spec and is often implemented at up to 10 MHz data rates. You need to be aware of edge effects, especially on the clock line. LVDS is not a bad idea, but it requires special attention to matching delays in order for the edges to arrive at the same time to avoid glitches. RickArticle: 148221
Hi,
I have a very simple design using a latch. I know latches should not
be used but it is a necessary evil in this case for speed reason. If
someone can find as fast of a way to do this with synchronous logic, I
would love to hear it.
My question is that ISE 12.1 is inserting a BUFG in between the input
ms3_n and the latch input during synthesis. I do not understand why.
I do not have any constraint on this code at all.
If anybody has a good explanation, I would really appreciate it
because I am at a loss. Thanks,
Amish
[CODE]
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity dspInterfaceTest is
port(
ms3_n : in STD_LOGIC;
ack : out STD_LOGIC;
s_done : in std_logic
);
end dspInterfaceTest;
architecture dspInterfaceTest of dspInterfaceTest is
signal s_doneLatch : std_logic;
begin
p_doneLatch : process(s_done, ms3_n)
begin
if(s_done = '1') then
s_doneLatch <= '1';
elsif(ms3_n = '1') then
s_doneLatch <= '0';
end if;
end process p_doneLatch;
ack <= 'Z' when ms3_n = '1' else s_doneLatch;
end dspInterfaceTest;
[/CODE]
Article: 148222On Jun 30, 6:03=A0am, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > I am not sure if such a program exists, but I would like to be able to te= st > a fairly large design by not having to write lots of testbenches. Idealy = I > would like a program were I could connect my DUT and give some constraint= s > and then test vectors would be produced to test all cases within the > constraints. Has anyone had any experience of such a program? > > Thanks > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I auditioned Mentor's version of such a program. I assert that all programs of this type have the same failing: They are good at verifying that a design does what it does, they are not good at verifying that a design does what it is supposed to do. For a test, I created a module that intentionally got the Ethernet CRC wrong. The generated test bench passed the module with no comments at all. <RANT> There is a reason that good verification engineers charge good money for their talent. There is a reason that companies that delegate verification to junior engineers have such a hard time with verification. </RANT> RKArticle: 148223
On 6/30/2010 7:37 AM, Amish Rughoonundon wrote: > Hi, > I have a very simple design using a latch. I know latches should not > be used but it is a necessary evil in this case for speed reason. If > someone can find as fast of a way to do this with synchronous logic, I > would love to hear it. > > My question is that ISE 12.1 is inserting a BUFG in between the input > ms3_n and the latch input during synthesis. I do not understand why. > I do not have any constraint on this code at all. > > If anybody has a good explanation, I would really appreciate it > because I am at a loss. Thanks, > Amish > > [CODE] > library IEEE; > use IEEE.STD_LOGIC_1164.all; > > entity dspInterfaceTest is > port( > ms3_n : in STD_LOGIC; > ack : out STD_LOGIC; > s_done : in std_logic > ); > end dspInterfaceTest; > > architecture dspInterfaceTest of dspInterfaceTest is > > signal s_doneLatch : std_logic; > begin > > p_doneLatch : process(s_done, ms3_n) > begin > if(s_done = '1') then > s_doneLatch<= '1'; > > elsif(ms3_n = '1') then > s_doneLatch<= '0'; > end if; > > end process p_doneLatch; > > ack<= 'Z' when ms3_n = '1' else s_doneLatch; > > end dspInterfaceTest; > [/CODE] No idea offhand, but your ack signal is going directly to a top-level pin, not internal logic, right? -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148224
On 23 juin, 19:50, Sergio <chec...@gmail.com> wrote:
> On Jun 23, 7:54=A0am, Gladys <yuhu...@gmail.com> wrote:
>
> > I found that Xilinx provide an IP core called RAM-based Shift
> > Register, the maximum depth is 1088, however, my image could have a
> > high resolution of 3664 x 2748, which means I need a depth of 2748, is
> > there any other methode to implement this? Thank you
>
> There's a white paper from Xilinx titled "Implementing and Testing
> Efficient Video Line Stores". It explains how to use Block RAMs as a
> huge shift register of an arbitrary length. I've used the provided
> examples with success in the past. You can find it here:http://www.xilinx=
.com/products/boards/s3estarter/reference_designs.htm
>
> Regards,
> Sergio
On 23 juin, 19:50, Sergio <chec...@gmail.com> wrote:
> On Jun 23, 7:54 am, Gladys <yuhu...@gmail.com> wrote:
>
> > I found that Xilinx provide an IP core called RAM-based Shift
> > Register, the maximum depth is 1088, however, my image could have a
> > high resolution of 3664 x 2748, which means I need a depth of 2748, is
> > there any other methode to implement this? Thank you
>
> There's a white paper from Xilinx titled "Implementing and Testing
> Efficient Video Line Stores". It explains how to use Block RAMs as a
> huge shift register of an arbitrary length. I've used the provided
> examples with success in the past. You can find it here:http://www.xilinx=
.com/products/boards/s3estarter/reference_designs.htm
>
> Regards,
> Sergio
Thank you so much for help, I've successfully implemented the line
buffer of about 3000 delay of data 12bits for my image processing.
Now I have another question: the pixels are in bayer pattern, such as:
R1
B G B
R2 G R G R3
B G B
R4
I want to correct the defective pixel 5x5 pixel surrounding, then
replace it by the average value of the nearest same color neighbor
pixels.
For example, the R in the middle is a dead pixel, then R=3D(R1+R2+R3+R4)/
4
In vertical, I've built 4 line buffer, but in horizontal, I still need
to have 5 pixels available at the same time, do I need to use shift
registers again to
delay the data for 4, 3, 2, 1clock cycle?
I find it's memory consuming and I'm not sure if my solution is
correct. Could you please help me? Thanks again.
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