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Hello, I'm working on an embedded project (EDK 11.2) and am using the TEMAC IP core (xps_ll_temac) and the TEMAC fifo (xps_ll_fifo). From what I can tell, the size of the Tx fifo is only 2Kb; this causes a bit of an issue for me: I am using my embedded project to stream 20 byte words over Ethernet. Right now, each packet contains a full IP and UDP header, and 10 of these 20-byte words. This fills the FIFO in its entirety. The problem is that I recieve a new word every ~20 microseconds. Given the size of the fifo, I'm firing off a packet every 200 microseconds. This corresponds to a rate of about 5000 packets / second. The FPGA can keep up with this data rate without issue, but it is too many packets for the listening computer's software to handle, and the entire system boggs down and crashes. I am wondering if it is possible to increase the size of the FIFO somehow, so that I could (say) include 100 20-byte words per packet (ie, have a fifo that is ~16 Kb in size). Does anyone know if what I want to do is possible? Are there any other suggestions? Thanks! Sean GriffinArticle: 148051
On Jun 16, 10:19=A0am, Griffin <captain.grif...@gmail.com> wrote: > I'm working on an embedded project (EDK 11.2) and am using the TEMAC > IP core (xps_ll_temac) and the TEMAC fifo (xps_ll_fifo). > > I am wondering if it is possible to increase the size of the FIFO > somehow, so that I could (say) include 100 20-byte words per packet > (ie, have a fifo that is ~16 Kb in size). We use xps_ll_temac and xps_ll_fifo when building +1GbE ethernet stacks in hw. To support jumbo frames we replaced the hardwired 2kB blockram FIFO with a VHDL version that supports parameterized depth and width. The VHDL for the fifo is described at www.codetronix.com/index.php?option=3Dcom_content&id=3D121 /PerArticle: 148052
On Jun 15, 10:55=A0pm, Vips <thevipulsi...@gmail.com> wrote: > Hi All > > I am designing a module and I am having some issues .. Let me explain > what =A0I am doing. > > I am getting =A0data as 64 bytes in each clock cycle . What are your actual Data, and Max FPGA clock speeds ? > Once we have detected a sync and the start of frame pattern then we > have to make sure it is not mistakingly taking the patter in the > payload as the start of the frma e again . Most sync protocols avoid this by design. What sync protocol are you using on the transmit ? -jgArticle: 148053
On Jun 16, 9:31=A0am, Symon <symon_bre...@hotmail.com> wrote: > On 6/15/2010 12:57 PM, LC wrote: > > > Symon wrote: > >> On 6/14/2010 1:45 PM, LC wrote: > > >>> Should I expect that this would be the right up limit I could do it ? > >>> Is there any clever design of this frontend to allow higher speed ? > > >> Does XAPP265 give you any architectural hints that you can use in your > >> Altera part? > >> HTH., Syms. > > > Tks, Symon, > > Indeed there are some variations induced by this reading that I'll try. > > Thanks. > > > Luis C. > > Hi Luis, > You might want to pay particular attention to the DDR registers in the > IOBs. I expect your Altera part has the same features, but I dunno for > sure. The registers mean that your internal logic can run at half the > speed of the external signals. Which is nice. > HTH, Syms. That's what I would suggest. By using the DDR registers, the data stream can be split into odd/even words with parallel paths. Then each stream would only need to run at half the rate on the I/O pins. Since you already have the 500 MHz clock you can just divide that by two to generate two enables, one for the odd and one for the even data streams. I've never used the DDR registers. You probably want to look closely at the example code that Altera provides. RickArticle: 148054
On Jun 16, 12:03=A0pm, backhus <goous...@googlemail.com> wrote: > On 15 Jun., 12:55, Vips <thevipulsi...@gmail.com> wrote: > > > > > Hi All > > > I am designing a module and I am having some issues .. Let me explain > > what =A0I am doing. > > > I am getting =A0data as 64 bytes in each clock cycle . In these 64 byte= s > > I look for sync bits which is "01" and then a fixed pattern of "1111" > > for the start of the frame . The next byte tells us the length of the > > payload . Now the minimum payload could be of 4 byes so there is a > > chance that in the current 64 bytes we can have multiple short frames > > of 4 bytes and henceforth we can have many start and stop bytes . > > > Once we have detected a sync and the start of frame pattern then we > > have to make sure it is not mistakingly taking the patter in the > > payload as the start of the frma e again . > > > I have made a loop that goes 63 downto 0 and looks for each byte for > > sync and start bit pattern > > > if it finds the sync and the start fame pattern then i am using a flag > > to make sure it is not mistakingly taking the pattern in the payload > > as the another start frame once it has detected the start of the frame > > and sync successfully. > > > Solution : I have made a counter that runs inside the loop (63 down to > > 0) and it is 13 bits wide ( as there could be 8192 max payload) > > > so once the count length is equal to payload length I am disabling the > > flag to allow it to go into detection of sync and start of the frame. > > > Problem: The problem is that whe i am using a 13 bit counter inside a > > loop that goes 64 iterations makes a very large HW during syntheis . > > > Can you provide a solution to this problem as i would be able to > > detect smallest payload ( 4 bytes in this case) as well as max payload > > bytes in an efficient way. > > > I will really appreciate you help in this regard. > > > Regards > > > Vips > > Hi Vips, > did I get that right, that your sync word consists of 2+4=3D 6 Bits? > Like Sandro said, things would be a lot easier if you could expand > this to 8 bits, so you would be able to work on whole bytes only. > Of course, to handle the data frames you need to do it at a higher > clock rate than the data rate of your 64-Byte interface. > > How about this: > Make your 64-Byte buffer a barrel shifter capable of moving the data > by 1/4/8-Bit width. (This needs a 5-input LUT in front of each FF, > actual FPGAs have 6-input LUTs and can do this at maximum clock speed) > So you make a detection FSM at the end, that searches for =A0'01'. If > that is detected, a 4 bit comparator can tell you wether the following > four bits are "1111" or not. > If Not, you continue searching, if Yes you shift by 4 once to get rid > of the "1111" nibble. > Then you take the next byte to load your payload counter. (How can you > have payloads between 4 and 8192 bytes with an 8 bit information? is > it nonlinear?) > Now you are moving the data by 8 bits at a time and forward it to the > following stages until the end of the frame. > You don't need a special flag, since everything is controlled by your > FSM and the Frame Counter. > After reading the last byte your FSM starts alll over again and > searches for the next sync signal. > > The bad thing is that you have to search for a 2+4 bit pattern that > can be anywhere in the 64 bit . > This serial approach is nice, but needs high overclocking (in the > worst case 512 times, but with some moderate use of combinatorical > preprocessing, this may be reduced to 64 times). > > The problem is in the frame format, which doesn't fit into whole > bytes. > Do the 64 Bytes come from some deserializer? > Why is the syncing not done on that level? It's low effort for a small > FSM, so it could run on high frequencies. > In that case you would just have a Frame Length byte at the beginning > of your 64 byte buffer and need only 8 times overclocking and a > bytewise-only barrel shifter, which is simple. > All the junk data and sync bits have already been thrown out. > > I hope there have been some helpful suggestions for your problem. > Have a nice synthesis > =A0 Eilert Hi Eilert /Sandro Thanks for the suggestion. I would like to slightly modify the spec here , may be i did not made clear. I have made a record and date is separate with includes the frame pattern "1111" other 4+ 8 is the length. The sync bit is separately moved in record so i just try to see the sync bits "01" in the recored. I am getting the frame in the form of record that has (4+ 8) array of 64 values. I am working with PCI E 3.0 I have no choice as i am getting the record type as input so i have to process it the way i am getting it. Again if i do sequential search then i will have to use a loop to detect the sync and the frame start pattern thanks vipulArticle: 148055
On Jun 17, 2:07=A0am, Vips <thevipulsi...@gmail.com> wrote: > On Jun 16, 12:03=A0pm, backhus <goous...@googlemail.com> wrote: > > > > > On 15 Jun., 12:55, Vips <thevipulsi...@gmail.com> wrote: > > > > Hi All > > > > I am designing a module and I am having some issues .. Let me explain > > > what =A0I am doing. > > > > I am getting =A0data as 64 bytes in each clock cycle . In these 64 by= tes > > > I look for sync bits which is "01" and then a fixed pattern of "1111" > > > for the start of the frame . The next byte tells us the length of the > > > payload . Now the minimum payload could be of 4 byes so there is a > > > chance that in the current 64 bytes we can have multiple short frames > > > of 4 bytes and henceforth we can have many start and stop bytes . > > > > Once we have detected a sync and the start of frame pattern then we > > > have to make sure it is not mistakingly taking the patter in the > > > payload as the start of the frma e again . > > > > I have made a loop that goes 63 downto 0 and looks for each byte for > > > sync and start bit pattern > > > > if it finds the sync and the start fame pattern then i am using a fla= g > > > to make sure it is not mistakingly taking the pattern in the payload > > > as the another start frame once it has detected the start of the fram= e > > > and sync successfully. > > > > Solution : I have made a counter that runs inside the loop (63 down t= o > > > 0) and it is 13 bits wide ( as there could be 8192 max payload) > > > > so once the count length is equal to payload length I am disabling th= e > > > flag to allow it to go into detection of sync and start of the frame. > > > > Problem: The problem is that whe i am using a 13 bit counter inside a > > > loop that goes 64 iterations makes a very large HW during syntheis . > > > > Can you provide a solution to this problem as i would be able to > > > detect smallest payload ( 4 bytes in this case) as well as max payloa= d > > > bytes in an efficient way. > > > > I will really appreciate you help in this regard. > > > > Regards > > > > Vips > > > Hi Vips, > > did I get that right, that your sync word consists of 2+4=3D 6 Bits? > > Like Sandro said, things would be a lot easier if you could expand > > this to 8 bits, so you would be able to work on whole bytes only. > > Of course, to handle the data frames you need to do it at a higher > > clock rate than the data rate of your 64-Byte interface. > > > How about this: > > Make your 64-Byte buffer a barrel shifter capable of moving the data > > by 1/4/8-Bit width. (This needs a 5-input LUT in front of each FF, > > actual FPGAs have 6-input LUTs and can do this at maximum clock speed) > > So you make a detection FSM at the end, that searches for =A0'01'. If > > that is detected, a 4 bit comparator can tell you wether the following > > four bits are "1111" or not. > > If Not, you continue searching, if Yes you shift by 4 once to get rid > > of the "1111" nibble. > > Then you take the next byte to load your payload counter. (How can you > > have payloads between 4 and 8192 bytes with an 8 bit information? is > > it nonlinear?) > > Now you are moving the data by 8 bits at a time and forward it to the > > following stages until the end of the frame. > > You don't need a special flag, since everything is controlled by your > > FSM and the Frame Counter. > > After reading the last byte your FSM starts alll over again and > > searches for the next sync signal. > > > The bad thing is that you have to search for a 2+4 bit pattern that > > can be anywhere in the 64 bit . > > This serial approach is nice, but needs high overclocking (in the > > worst case 512 times, but with some moderate use of combinatorical > > preprocessing, this may be reduced to 64 times). > > > The problem is in the frame format, which doesn't fit into whole > > bytes. > > Do the 64 Bytes come from some deserializer? > > Why is the syncing not done on that level? It's low effort for a small > > FSM, so it could run on high frequencies. > > In that case you would just have a Frame Length byte at the beginning > > of your 64 byte buffer and need only 8 times overclocking and a > > bytewise-only barrel shifter, which is simple. > > All the junk data and sync bits have already been thrown out. > > > I hope there have been some helpful suggestions for your problem. > > Have a nice synthesis > > =A0 Eilert > > Hi =A0 Eilert /Sandro > > Thanks for the suggestion. I would like to slightly modify the spec > here , may be i did not made clear. =A0I have made a record and date is > separate with includes the frame pattern "1111" other 4+ 8 is the > length. The sync bit is separately moved in record so i just try to > see the sync bits "01" in the recored. > > I am getting the frame in the form of record that has (4+ 8) array of > 64 values. I am working with PCI E 3.0 > > I have no choice as i am getting the record type as input so i have to > process it the way i am getting it. > > Again if i do sequential search then i will have to use a loop to > detect the sync and the frame start pattern > > thanks > > vipul This explanation is less clear to me than your original problem statement. What does "(4+ 8) array" mean? I think I understand that your 64 bytes (if you are receiving 64 bytes in each clock cycle, which I am not sure of) can hold multiple frames of data. I have no understanding of what a frame is at this point. Does the frame start with "1111"? Does it start with "01" and the "1111" is a marker for the end of header and start of data? How do you find the byte count? I will say that your design WILL have to use a lot of logic. I'm not clear if your frames are byte aligned or not. If they are, then you will have 64 copies of the logic required to detect a frame, including the counter logic that must be decoded or possibly combinatorially counted down (depending on your how your code is written), which is very messy. If your frames are not byte aligned this logic must be repeated for each bit, 512 times! If you want this to be efficient, start drawing some block diagrams of how you expect the logic to be implemented and see just how complex it is. Right now you seem to be writing software which is translated into hardware. When you do this you have little control over the resulting hardware. If you figure out what hardware you want, then you can use your Hardware DESCRIPTION Language to actually describe the hardware you want rather than letting the tools give you the hardware it wants. If you can make your problem clear, perhaps we can help you with the details of how to structure your hardware. RickArticle: 148056
Why is Google too dense to fix their SPAM problem? There are so many ways they could address the problem and as far as I can tell, they treat it as a PR concern and have tried to give us a control that does nothing! You can flag posts as being spam very easily now. Each post has a link at the bottom that lets you report spam. There are times when I flag every post that come into the groups I read. I see nothing happen with that SPAM. The existing SPAM posts are not deleted. The same SPAM posts are not prevented. In other words, it is a control that is not wired into anything. Once I switched from a newsreader to Google I decided I liked it and don't want to return. But I am getting tired of dealing with all the SPAM. There are some days with some groups that the SPAM outnumbers the real posts by 10 to 1. It makes the groups nearly useless. I believe there is a similar page at embeddedrelated.com. Does that work any better? RickArticle: 148057
Hi, I recently got the Actel Smartfusion eval kit. Since I use Linux, I am running the windows Libero IDE under wine. While the application runs fine under wine, I am not able to program the device with the Flashpro software. Seems like it is not able to talk to the programmer. I know this is as much a wine issue, but i wanted to know if there is a native software for linux which can be used to just program the device and which supports smartfusion fpgas. And which can work on the free gold license. Thanks Manish --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148058
>Dear Friends,
>
>i am using Altium Designer for fpga and embedded project on digilent
>spartan3E-500 board.
>I have created an FPGA project in Altium using open bus document
containing
>three device:
>1. TSK3000A
>2. WB_PRTIO_1 (for leds)
>3. WB_UART_V2_1
>Added a top level schematic sheet. Added constraint file to the project
>containing correct fpga pin designators. Configured the TSK3000 memory
size
>as 16K. The fpga project gets synthesized and bit stream is generated
>without any problem.
>Next i created an embedded project and made it child of the TSK3000 cpu.
>Configured Aplication Memory as 0-8K as ROM and 8k-16K as ram.
>Adjusted the Stack size to 512. Heap size " " (nothing not even 0).
>Created main.c and software platform document. My software platform
>document contains:
>hardware rappers:
>1. WB_PRTIO_1
>2. WB_UART_V2_1
>and driver files:
>1. DRV_PRTIO_1
>2. DRV_UART_V2_1
>
>following is my main.c:
>-------------------------------------------------
>#include <stdio.h>
>#include <stdint.h>
>#include <drv_uart8.h>
>#include <drv_ioport.h>
>#include "hardware.h"
>#include "devices.h"
>
>uart8_t* uart;
>ioport_t* ioport;
>
>void main(void)
>{
>int value=0;
>uart = uart8_open(DRV_UART8_1); //uart8_t* uart8_open(int id);
>uart8_set_baudrate(uart,19200);
>ioport = ioport_open(DRV_IOPORT_1); //ioport_t* ioport_open(const int
id);
>
>value = uart8_write(uart,"helloworld\n", 20);
>ioport_set_value(ioport, WB_PRTIO_1, 0xaa);
>ioport_set_value(ioport, WB_PRTIO_1, 0x55);
>
>while (1)
>{
>//int uart8_putchar(uart8_t *restrict drv, int val);
>//uart8_putchar(uart, uart8_getchar(uart)); //int uart8_getchar(uart8_t
>*restrict drv);
>uart8_putchar(uart, 'U');
>
>}
>
>}
>---------------------------------
>I have attached pc com port with my boards serial port and running hyper
>terminal on the other end of the serial cable.
>Now the problem is:
>I can write to leds without any problem but i never see prints from
>uart8_write(); function.
>
>I have following questions which I hope someone will come up with
answers:
>
>1. How to compute value of stack requirement?
>2. How to compute value for heap?
>3. What might be wrong with my design that i don't see message on the
>serial port?
>4. How can i configure my embedded design to re-direct printf output to
>UART?
>
>Regards.
>
>
>
>---------------------------------------
>Posted through http://www.FPGARelated.com
>
First of all your check if are opening the correct uart -
>and driver files:
>1. DRV_PRTIO_1
>2. DRV_UART_V2_1 <<<<<<<
>
>uart = uart8_open(DRV_UART8_1); //uart8_t* uart8_open(int id);
they are different.
To redirect your printf to UART, go to software platform file.
GO to Serial IO options - there is option to select your stdout and stdin
device - set to your uart device name.
the printf will be redirected to the uart now.
For your stack requirement - the .map file gives you a preliminary stack
analysis
Regards
Manish
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 148059On Jun 17, 4:29=A0am, rickman <gnu...@gmail.com> wrote: > Why is Google too dense to fix their SPAM problem? =A0There are so many > ways they could address the problem and as far as I can tell, they > treat it as a PR concern and have tried to give us a control that does > nothing! =A0You can flag posts as being spam very easily now. =A0Each pos= t > has a link at the bottom that lets you report spam. =A0There are times > when I flag every post that come into the groups I read. =A0I see > nothing happen with that SPAM. =A0The existing SPAM posts are not > deleted. =A0The same SPAM posts are not prevented. =A0In other words, it > is a control that is not wired into anything. > > Once I switched from a newsreader to Google I decided I liked it and > don't want to return. =A0But I am getting tired of dealing with all the > SPAM. =A0There are some days with some groups that the SPAM outnumbers > the real posts by 10 to 1. =A0It makes the groups nearly useless. =A0I > believe there is a similar page at embeddedrelated.com. =A0Does that > work any better? > > Rick I read the group through Google groups as well and have the same experience with non-action with reporting spam. I also rate each of the posts with the lowest 1-star. If they at least gave an option to not display 1-start posts that would be a big benefit.Article: 148060
On Jun 17, 4:29=A0am, rickman <gnu...@gmail.com> wrote: > Why is Google too dense to fix their SPAM problem? It's not their spam problem, it's your (our) spam problem. For all we know, they get to charge advertisers extra because we're spending more time in the forum reporting spam. RKArticle: 148061
On Thu, 17 Jun 2010 04:29:51 -0700 (PDT), rickman wrote: >Why is Google too dense to fix their SPAM problem? It's "the tragedy of the commons" - they are culturally committed to the open Internet with all the evils and joys that brings. On the other hand, as others have pointed out, there's a perfectly serviceable free solution out there: I use the old free version of Forte Agent (still available on their website if you look hard enough) and have signed up with the admirable eternal-september news server. All free, no spam, and only the very occasional dropped post (presumably mis-classified as spam). The only really big drawback is that eternal-september only keeps posts for about three months before expiring them, so I tend to archive for myself any gems I stumble across. Forte Free Agent is a bit stupid about cross-posts too, but that's so rarely a problem that I just live with it. I still find Usenet a more agreeable environment than almost any Web-based forum mechanism, and I'll go on using it as long as there are any even vaguely interesting discussions going on. Please don't go away, Rick :-) -- Jonathan BromleyArticle: 148062
On Jun 17, 2:29=A0pm, Jonathan Bromley <s...@oxfordbromley.plus.com> wrote: > On Thu, 17 Jun 2010 04:29:51 -0700 (PDT), rickman wrote: > >Why is Google too dense to fix their SPAM problem? > > It's "the tragedy of the commons" - they are > culturally committed to the open Internet with > all the evils and joys that brings. > > On the other hand, as others have pointed out, there's > a perfectly serviceable free solution out there: I use > the old free version of Forte Agent (still available > on their website if you look hard enough) and > have signed up with the admirable eternal-september > news server. =A0All free, no spam, and only the very > occasional dropped post (presumably mis-classified > as spam). =A0The only really big drawback is that > eternal-september only keeps posts for about > three months before expiring them, so I tend to > archive for myself any gems I stumble across. > Forte Free Agent is a bit stupid about cross-posts > too, but that's so rarely a problem that I just > live with it. > > I still find Usenet a more agreeable environment > than almost any Web-based forum mechanism, and > I'll go on using it as long as there are any > even vaguely interesting discussions going on. > Please don't go away, Rick :-) > -- > Jonathan Bromley Google is still the best portal to the UseNet for those of us who are unable or unwilling to install newsreaders or who just don't want the added hassle. In addition to the spam filtering problem, Google Groups seems to have a spam sourcing problem as well. Many regular UseNet users will filter out all posts originated by Google Groups (including this one) in order to avoid the spam coming from the groups. For example the recent threads "Simple hack to get $<random number> to your home", show up as posted through Google Groups: X-Trace: posting.google.com 1276801463 16334 127.0.0.1 (17 Jun 2010 19:04:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 17 Jun 2010 19:04:23 +0000 (UTC) Complaints-To: groups-abuse@google.com I'm not sure if sending complaints to groups-abuse@google.com has any effect. As to other moderated forums, I've seen that a large portion of traffic that once showed up on c.a.f has now moved to Xilinx Forums. This could represent the amount that used to be posted to c.a.f via the Xilinx forum site, but I doubt it. There is something to be said for a well-moderated site that allows attachments, etc. UseNet is pretty much in the dark ages in that respect. The real downside to the moderated sites is the over-use of categories (remember when we were trying to decide if there should be c.a.f.X?) Most of us decided it's best to keep the forum as general as practical. I don't think there's any free ride... Regards, GaborArticle: 148063
shoonya <manish.paradkar@n_o_s_p_a_m.gmail.com> wrote: > Hi, > I recently got the Actel Smartfusion eval kit. Since I use Linux, I am > running the windows Libero IDE under wine. > While the application runs fine under wine, I am not able to program the > device with the Flashpro software. Seems like it is not able to talk to the > programmer. > I know this is as much a wine issue, but i wanted to know if there is a > native software for linux which can be used to just program the device and > which supports smartfusion fpgas. > And which can work on the free gold license. How is the hardware connected (serial/parallel/USB). -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 148064
Hi, thanks for the quick response! I'll take a look as soon as I can (working on another experiment at the moment) and get back to you, but at face value it seems to be what it is I'm looking for. -Sean. > We use xps_ll_temac and xps_ll_fifo when building +1GbE ethernet > stacks in hw. To support jumbo frames we replaced the hardwired 2kB > blockram FIFO with a VHDL version that supports parameterized depth > and width. The VHDL for the fifo is described atwww.codetronix.com/index.php?option=com_content&id=121 > > /PerArticle: 148065
>shoonya <manish.paradkar@n_o_s_p_a_m.gmail.com> wrote: >> Hi, > >> I recently got the Actel Smartfusion eval kit. Since I use Linux, I am >> running the windows Libero IDE under wine. > >> While the application runs fine under wine, I am not able to program the >> device with the Flashpro software. Seems like it is not able to talk to the >> programmer. > >> I know this is as much a wine issue, but i wanted to know if there is a >> native software for linux which can be used to just program the device and >> which supports smartfusion fpgas. > >> And which can work on the free gold license. > >How is the hardware connected (serial/parallel/USB). >-- >Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > >Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >--------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > Hi, Here's the kit http://www.actel.com/products/hardware/devkits_boards/smartfusion_eval.aspx It has to usb connections. One for power and uart - it uses the cp210x chip from Silicon Labs. The other usb is for programming which has actel flaspro3 programmer. I got a response from actel saying that flaspro is not supported in Linux even though they have a linux version of Libero. Beats me. Regards Manish --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148066
On 17 Jun., 15:11, "shoonya" <manish.paradkar@n_o_s_p_a_m.gmail.com> wrote: [..] > I recently got the Actel Smartfusion eval kit. Since I use Linux, I am > running the windows Libero IDE under wine. > > While the application runs fine under wine, I am not able to program the > device with the Flashpro software. Seems like it is not able to talk to the > programmer. > > I know this is as much a wine issue, but i wanted to know if there is a > native software for linux which can be used to just program the device and > which supports smartfusion fpgas. . First there is also a linux version of most tools in Libero. But it has drawbacks in performance against windows. It might be that wine +windows version shows better performance than linux native version of the tools. For programming there is only the windows version of the FlashPro. I guess this is due to the fact that the programmer needs direct control of the interface. At least the older versions of FlashPro required admin rights for programming over parallel port. I have no experience with wine, but expect that wine won't allow that direct access to the hardware that FlashPro seems to require. bye ThomasArticle: 148067
>On 17 Jun., 15:11, "shoonya" <manish.paradkar@n_o_s_p_a_m.gmail.com> >wrote: >[..] >> I recently got the Actel Smartfusion eval kit. Since I use Linux, I am >> running the windows Libero IDE under wine. >> >> While the application runs fine under wine, I am not able to program the >> device with the Flashpro software. Seems like it is not able to talk to the >> programmer. >> >> I know this is as much a wine issue, but i wanted to know if there is a >> native software for linux which can be used to just program the device and >> which supports smartfusion fpgas. >. >First there is also a linux version of most tools in Libero. But it >has drawbacks in performance against windows. It might be that wine >+windows version shows better performance than linux native version of >the tools. > >For programming there is only the windows version of the FlashPro. I >guess this is due to the fact that the programmer needs direct control >of the interface. At least the older versions of FlashPro required >admin rights for programming over parallel port. I have no experience >with wine, but expect that wine won't allow that direct access to the >hardware that FlashPro seems to require. > >bye Thomas > Hi Thomas, >For programming there is only the windows version of the FlashPro. That is it. There is no native Linux version of Flashpro. :( Wine will only allow direct access to the hardware if that hardware has a native linux driver loaded. Regards Manish --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148068
Hi,
I am trying to use this FIFO design in a Spartan6:
http://www.asic-world.com/examples/verilog/asyn_fifo.html
Doing so makes Xst emit a shrill warning (Xst:3002) because a latch
construct does not play well with the Spartan6 architecture, as it has
both an asynchronous set and reset. And as the warning says, the
circuit is still built but results in poor timing.
The construct in question is:
always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous
Clear & Preset.
if (Rst_Status | Clear_in)
Status =3D 0; //Going 'Empty'.
else if (Set_Status)
Status =3D 1; //Going 'Full'.
To fix the warning and improve timing, I have replaced it with:
wire Clear_Status =3D Rst_Status | Clear_in;
always @(posedge Clear_Status, posedge Set_Status)
if (Clear_Status)
Status <=3D 1'b0;
else
Status <=3D 1'b1;
Would this design still work without metastability problems?
I guess the answer to this question is probably in the article
"Asynchronous FIFO in Virtex-II FPGAs" by Peter Alfke, but I cannot
find it anywhere for download.
Thanks,
S=E9bastien
PS. I do not want to use CORE Generator FIFOs.
Article: 148069On Jun 18, 10:43=A0am, Sebastien Bourdeauducq <sebastien.bourdeaud...@gmail.com> wrote: > Hi, > > I am trying to use this FIFO design in a Spartan6:http://www.asic-world.c= om/examples/verilog/asyn_fifo.html > > Doing so makes Xst emit a shrill warning (Xst:3002) because a latch > construct does not play well with the Spartan6 architecture, as it has > both an asynchronous set and reset. And as the warning says, the > circuit is still built but results in poor timing. > > The construct in question is: > always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous > Clear & Preset. > =A0 if (Rst_Status | Clear_in) > =A0 =A0 Status =3D 0; =A0//Going 'Empty'. > =A0 else if (Set_Status) > =A0 =A0 Status =3D 1; =A0//Going 'Full'. > > To fix the warning and improve timing, I have replaced it with: > wire Clear_Status =3D Rst_Status | Clear_in; > always @(posedge Clear_Status, posedge Set_Status) > =A0 if (Clear_Status) > =A0 =A0 Status <=3D 1'b0; > =A0 else > =A0 =A0 Status <=3D 1'b1; > > Would this design still work without metastability problems? > > I guess the answer to this question is probably in the article > "Asynchronous FIFO in Virtex-II FPGAs" by Peter Alfke, but I cannot > find it anywhere for download. > > Thanks, > S=E9bastien > PS. I do not want to use CORE Generator FIFOs. The new version of the code does not do the same thing as the original. The difference is in what happens if both clear and set are active and you release the clear input. In that case the original code would set the output high, the new version would stay low, since it requires a rising edge of the set. If that particular case never happens, then you should be able to use the new code. Regards, GaborArticle: 148070
Sebastien Bourdeauducq <sebastien.bourdeauducq@gmail.com> wrote: > Hi, > I am trying to use this FIFO design in a Spartan6: > http://www.asic-world.com/examples/verilog/asyn_fifo.html > Doing so makes Xst emit a shrill warning (Xst:3002) because a latch > construct does not play well with the Spartan6 architecture, as it has > both an asynchronous set and reset. And as the warning says, the > circuit is still built but results in poor timing. ... > I guess the answer to this question is probably in the article > "Asynchronous FIFO in Virtex-II FPGAs" by Peter Alfke, but I cannot > find it anywhere for download. I use the "generic_fifo" from opencores. The "generic ram" needed by the module I replaced with straight XST synthesizable RAM code. generic_fifo also supplies an indication of the filling degree, so throttling when transfering blocks of data gest simple. I use the fifo to transfer blocks of data with about 16 MByte/sec via an FT2232H. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 148071
I'm no luck figuring out how to implement the timing constraints for something that, to my mind, ought to be pretty simple. I'm connected to an external synchronous logic chip. For now let's call it a regular 74HC74 flip flop, but the details are unimportant. My FPGA outputs D and CLK to the 74HC74, and reads back Q. The FPGA has a single global clock net, call it SysClk. I've got a state machine running on SysClk generating both data and clock for this widget; the clock is running at a sufficiently low rate that it's being generated by a simple, rising-edge only, divide-by-N from my master clock. My logic defines both D and CLK in a way that they're registered outputs and Q as a registered input with no logic; such that all of them should be able to be pushed into the IOBs. The 74HC74 datasheet tells me that I've got setup time (Ts), hold time (Th), and clock-to-output delay (Tcko). How do I go about communicating these requirements to the Xilinx toolchain? Clearly it's some combination of OFFSET constraints, but what are the magic words? UG612 discusses the use of the REFERENCE_PIN qualifier to indicate that the output data is referred to the output clock, but the example doesn't give any advice that would connect those OFFSET constraints to only define the relationship between D and CLK, not the entire world and CLK. And I can't seem to find any information whatsoever that would let me define the relationship between CLK and Q. I've gone through the Constraints Guide. I've gone through UG612. I've gone through Austin's 5 part series over on the Xilinx forums. And I'm still lost. Anyone have any revelations for me? -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148072
Hello. I am working at an SoC startup developing EDA software for FPGA-like structures. Currently we have a half-finished software covering from technology mapping to placement and routing for FPGA. I am looking for opportunities to put the software into practice. Originally the software was expected to evaluate FPGA structures (known or unknown) for various application domains. So it is not designated to any specific logic cell or interconnect. Instead, given structure descriptions, this software can perform technology mapping, packing, placement and routing on a wide variety of structures. Actually, there does exist limitations like entities in logic cell must be organized in tree structure, interconnection must build on switches and the overall structure must be repetitive. Even though, the software is flexible enough to be customized to different FPGA structures. The frustration I am facing to is that there is few chance to practice since the top priority task for a startup is to make money and survive. So after talking with my boss, now I am seeking opportunities outside. Main features of the software: 1. Flexible logic cell structure. We have developed algorithm performing technology mapping and packing in the same time. The logic cell don't need to be look-up table only. You can add in other special purpose entities like mux. The software can automatically map and pack netlist into expected logic cells given a proper specification. 2. Flexible interconnection. Similiar to VPR, the placement and routing algorithms work on abstract interconnection model. 3. Heterogeneous placement. What VPR cannot do is placement for blocks of different size, which is an unavoidable case for real-world FPGA designs. For example, adders are usually synthesized to a bank of logic cells which requires to be placed along dedicated carry chains. Our algorithm deals with such cases by a partition-and-place approach. 4. Unified design representation. All algorithms read design from and store to the same database. So there is no need for data transformation as using discrete tools like ABCmap and VPR. 5. Complete Pythonization (ongoing). The database and core algorithms are written in C++. But we are porting the database to Python so that one can operate on designs directly from Python. The core algorithms will also be exposed to Python. By enjoying the elegancy and extensibility of Python, design flows are built up quite easily. Then I have to mention some shortages of the software. 1. No GUI/IDE. We are used to scripting and is unfamiliar with GUI development. But I think with Python it is easy to design cross-platform GUI and IDE. 2. No RTL design entry. Currently we are using icarus to parse RTL Verilog to gate level. We are thinking of build an RTL HDL parser but haven't have time to kick it off. 3. No synthesis optimization. Since we haven't reach RTL level, there is no synthesis and logic optimization algorithms yet. 4. Not timing-driven. Existing algorithms are bound to resource constraints. We haven't put timing constraints into consideration yet. I am wondering whether there is any FPGA startup or other design house that works on embedded reconfigurable fabric will need such kind of software. If not any, it will be locked up in the basement until 2012 or someday due to the company strategy. As a main developer, I will be very sad if so. That is why I post here. I am looking for an opportunity to practice and to push forward the software. Personally I think open-source is one of the possible way out and it is the most interesting way. It will be cool if we can build up an open source design automation flow to lower the software barrel for FPGA/reconfigurable market. But there is a long way to go. Besides, since the software is still my company's proprietary, though the company is open to open source, I have to find a profitable reason for open-source. Should you have any suggestions, advices, critism or willings, please fill free to let me know. I will appreciate very much for your feed back. And thank you for reading this far. Yujie Wen Celestial Semiconductor. Shanghai Office. yujie.wen REPLACE_WITH_AT celestialsemi.cn --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148073
On Thu, 17 Jun 2010 15:04:02 -0700 (PDT), Gabor wrote: >Google is still the best portal to the UseNet for those of >us who are unable or unwilling to install newsreaders Maybe so, but it really doesn't work for me: the threading model is a mess, the editing is a mess, and the spam sucks. I use it when I have to, if for any reason I don't have access to my usual Usenet setup. >who just don't want the added hassle. What hassle? It took me ten minutes to set up and install my newsreader, five minutes to subscribe at eternal-september. And now I have a sane Usenet environment. >For example the recent threads >"Simple hack to get $<random number> to your home" which I simply didn't see at all. But I *do* see the overwhelming majority of meaningful posts that came via Google Groups. I'm happy to let other experts do the spam-filtering for me - my eyeballs can easily handle the occasional escapees. >As to other moderated forums, I've seen that a large portion >of traffic that once showed up on c.a.f has now moved to >Xilinx Forums. This could represent the amount that used to >be posted to c.a.f via the Xilinx forum site, but I doubt it. >There is something to be said for a well-moderated site that >allows attachments, etc. That's fair enough. On the other hand, there are enough side-channels available these days that the attachments problem is really no problem at all. It's certainly true that no-one seems to be setting up any new Usenet groups these days, at least not in our line of work. For example, all the new SystemVerilog verification methodologies (UVM, VMM, OVM) have their own forum sites that work pretty well. I don't mind using them, again on the condition that someone else does the sysadmin effort. The modern forum engines seem to work reasonably well provided there is only modest traffic; all their window-dressing tends to get in the way when there is a lot of material. >I don't think there's any free ride... No, for sure. But I'm on a ride that's cheap enough for me, and going in roughly the right direction too. -- Jonathan BromleyArticle: 148074
On Jun 18, 1:27=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > I'm no luck figuring out how to implement the timing constraints for > something that, to my mind, ought to be pretty simple. =A0I'm connected t= o > an external synchronous logic chip. =A0For now let's call it a regular > 74HC74 flip flop, but the details are unimportant. =A0My FPGA outputs D > and CLK to the 74HC74, and reads back Q. > > The FPGA has a single global clock net, call it SysClk. =A0I've got a > state machine running on SysClk generating both data and clock for this > widget; the clock is running at a sufficiently low rate that it's being > generated by a simple, rising-edge only, divide-by-N from my master > clock. =A0My logic defines both D and CLK in a way that they're registere= d > outputs and Q as a registered input with no logic; such that all of them > should be able to be pushed into the IOBs. > > The 74HC74 datasheet tells me that I've got setup time (Ts), hold time > (Th), and clock-to-output delay (Tcko). =A0How do I go about communicatin= g > these requirements to the Xilinx toolchain? =A0Clearly it's some > combination of OFFSET constraints, but what are the magic words? > > UG612 discusses the use of the REFERENCE_PIN qualifier to indicate that > the output data is referred to the output clock, but the example doesn't > give any advice that would connect those OFFSET constraints to only > define the relationship between D and CLK, not the entire world and CLK. > =A0 And I can't seem to find any information whatsoever that would let me > define the relationship between CLK and Q. > > I've gone through the Constraints Guide. =A0I've gone through UG612. =A0I= 've > gone through Austin's 5 part series over on the Xilinx forums. =A0And I'm > still lost. =A0Anyone have any revelations for me? > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order Basically, you are using a source synchronous output clock to your flip-flop. There is no constraint to my knowledge that would do the job you're looking for which is to define the relative timing on two outputs. This should be correct by design. i.e. if you push both CLK and Q outputs into IOB flops, using DDR flops if necessary for the clock, you should have essentially zero timing difference between CLK and Q if they are switching on the same edge of the same global clock. Make your Tsu and Th based on the relative timing to the IOB flops, for example making CLK go high on the falling edge of the internal clock and changing Q on the next rising edge to get 1/2 cycle of hold time. HTH, Gabor
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