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Hi,
I have write simple lockup table:
#################### [CODE] ####################
din : in std_logic_vector (3 downto 0);
dout : out std_logic_vector (1 downto 0)
begin
process(din)
begin
case(din) is
when "000" => dout <= conv_std_logic_vector(2, 2);
when "001" => dout <= conv_std_logic_vector(0, 2);
when "010" => dout <= conv_std_logic_vector(1, 2);
when "011" => dout <= conv_std_logic_vector(1, 2);
when "100" => dout <= conv_std_logic_vector(2, 2);
when "101" => dout <= conv_std_logic_vector(3, 2);
when "110" => dout <= conv_std_logic_vector(3, 2);
when "111" => dout <= conv_std_logic_vector(0, 2);
when others => null;
end case;
end process;
#################### [/CODE] ####################
But I want to write values in HEX format example:
#################### [CODE] ####################
din : in std_logic_vector (3 downto 0);
dout : out std_logic_vector (1 downto 0)
begin
process(din)
begin
case(din) is
when x"0" => dout <= x"2";
when x"1" => dout <= x"0";
when x"2" => dout <= x"1";
when x"3" => dout <= x"1";
when x"4" => dout <= x"2";
when x"5" => dout <= x"3";
when x"6" => dout <= x"3";
when x"7" => dout <= x"0";
when others => null;
end case;
end process;
#################### [/CODE] ####################
But with this format i obtain an error ...
"String literal "0000" is of size 4 but is expected to be of size 3."
VHDl x"--" generate bit_vector, but how limit number of bit ?
Thanks.
secureasm
Article: 146976> I basically want a binary image I can program into the Flash chip. In that case, you can just convert the ELF to a binary using lm32-elf- objcopy. JonArticle: 146977
On Apr 7, 9:56=A0am, Kappa <secure...@gmail.com> wrote: > > #################### [/CODE] #################### > > But with this format i obtain an error ... > > "String literal "0000" is of size 4 but is expected to be of size 3." > > VHDl x"--" generate bit_vector, but how limit number of bit ? > > Thanks. > > secureasm Two choices from my perspective: use Octal instead of heX (O"6") introduced in VHDL-1993 or extend the case value din to 4 bits with concatenation. The one url I grabbed for the VHDL-1993 reference (http:// www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/) mentions: "One limitation in VHDL-1993 is that hexadecimal bit-string literals always contain a multiple of 4 bits, and octal ones a multiple of 3 bits. You can=92t have a 10-bit hexadecimal bit-string literal, or one containing values other than 0, 1 or _, for example."Article: 146978
On Apr 7, 10:55=A0am, John_H <newsgr...@johnhandwork.com> wrote: > On Apr 7, 9:56=A0am, Kappa <secure...@gmail.com> wrote: > > > > > #################### [/CODE] #################### > > > But with this format i obtain an error ... > > > "String literal "0000" is of size 4 but is expected to be of size 3." > > > VHDl x"--" generate bit_vector, but how limit number of bit ? > > > Thanks. > > > secureasm > > Two choices from my perspective: use Octal instead of heX (O"6") > introduced in VHDL-1993 or extend the case value din to 4 bits with > concatenation. > > The one url I grabbed for the VHDL-1993 reference (http://www.doulos.com/= knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/) > mentions: > > "One limitation in VHDL-1993 is that hexadecimal bit-string literals > always contain a multiple of 4 bits, and octal ones a multiple of 3 > bits. You can=92t have a 10-bit hexadecimal bit-string literal, or one > containing values other than 0, 1 or _, for example." The error message strangely does not match the declared size of din as (3 downto 0). I would have expected the original code to have an error message...Article: 146979
Hi > Two choices from my perspective: use Octal instead of heX (O"6") > introduced in VHDL-1993 or extend the case value din to 4 bits with > concatenation. OK for 3 bits I use O"6" instead of X, but with 5 bits ? > "One limitation in VHDL-1993 is that hexadecimal bit-string literals > always contain a multiple of 4 bits, and octal ones a multiple of 3 > bits. You can=92t have a 10-bit hexadecimal bit-string literal, or one > containing values other than 0, 1 or _, for example." If I can't have 10 bits then not even 5 bits ? Thanks. secureasmArticle: 146980
On Apr 7, 11:57=A0am, Kappa <secure...@gmail.com> wrote: > Hi > > > Two choices from my perspective: use Octal instead of heX (O"6") > > introduced in VHDL-1993 or extend the case value din to 4 bits with > > concatenation. > > OK for 3 bits I use O"6" =A0instead of X, but with 5 bits ? > > > "One limitation in VHDL-1993 is that hexadecimal bit-string literals > > always contain a multiple of 4 bits, and octal ones a multiple of 3 > > bits. You can=92t have a 10-bit hexadecimal bit-string literal, or one > > containing values other than 0, 1 or _, for example." > > If I can't have 10 bits then not even 5 bits ? > > Thanks. > > secureasm Maybe you'd do better with VHDL-2008? Perhaps you could take the suggestion of concatenating your case variable to get a multiple of 4 bits so it evens out with the compare.Article: 146981
On Wed, 7 Apr 2010 06:56:35 -0700 (PDT), Kappa wrote:
>#################### [CODE] ####################
>
>din : in std_logic_vector (3 downto 0);
>dout : out std_logic_vector (1 downto 0)
>
>begin
>
> process(din)
> begin
> case(din) is
> when "000" => dout <= conv_std_logic_vector(2, 2);
> when "001" => dout <= conv_std_logic_vector(0, 2);
[...]
> when others => null;
> end case;
> end process;
>
>#################### [/CODE] ####################
YUCK.
You're fighting against VHDL's strict rules, instead of getting
them to work for you.
Do you like this version better?
constant input_bit_width: positive := din'length;
constant output_bit_width: positive := dout'length;
subtype T_input_code is integer range 0 to (2**input_bit_width-1);
subtype T_output_code is integer range 0 to (2**output_bit_width-1);
type T_code_map is array(T_input_code) of T_output_code;
----------------- HERE IS THE LOOKUP TABLE ---------
constant code_map: T_code_map := (
0 => 2,
1 => 0,
2 => 1,
3 => 1,
4 => 2,
5 => 3,
6 => 3,
7 => 0);
------------------------------------------------------
-- You will get errors if you don't provide the full set
-- of map values, but you can use OTHERS if you wish.
...
process (din)
variable code_in: T_input_code;
variable code_out: T_output_code;
begin
code_in := to_integer(unsigned(din));
code_out := code_map(code_in);
dout <= std_logic_vector(to_unsigned(code_out, output_bit_width));
end process;
There are lots of other possibilities; the precise way you choose to
parameterize this design, and set up the constants, depends on how it
fits into the rest of your design and how it will be used. If you
are careful and lucky, you can probably avoid the type conversions
in this part of the code, because you are using appropriate numeric
data types in the body of your design. But that's another discussion.
If you absolutely insist on hex representation, you can easily
rewrite the map table:
constant code_map: T_code_map := (
16#0# => 16#2#,
...
16#7# => 16#0#);
Oh, and I've used numeric_std instead of std_logic_horrible
for the numeric conversions.
Named types, subtypes and constants are your friend, especially
when revisiting the code later, if you choose the names wisely.
I'll leave it to someone else to open a discussion about
the incomplete case statement.
--
Jonathan Bromley
Article: 146982On Mar 31, 10:04=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Mar 31, 1:51=A0am, luudee <rudolf.usselm...@gmail.com> wrote: > > > Does anybody else, besides xilinx, make FMC boards for ml605 & sp605 ? > > > HW-FMC-XM105-G =A0FMC XM105 DEBUG CARD > > HW-FMC-XM104-G =A0FMC CONNECTIVITY MEZZANINE CARD > > > Buying Xilinx products now means going through Avnet, which is a > > nightmare and HUGE lead times ... > > > Thanks, > > rudi > > While the XM104 is listed with a 8 week lead time on the Avnet site, I > know that we have these available in inventory and they will ship > promptly after the order is placed. =A0The XM105 is listed with a 2 week > lead time. > > There are a number of other companies releasing FMC cards, just be > sure that the cards support a VADJ of 2.5V and there shouldn't be a > problem. > > 4DSP recently announced a FMC familyhttp://www.przoom.com/news/66794/ > > Curtiss-Wright also has a number of boards.http://www.cwcembedded.com/0/6= 2/651.html > > And Xilinx has a number of other boards in pipeline to be released > next quarter.http://www.xilinx.com/fmc > > Ed McGettigan > -- > Xilinx Inc. Ed, I just board a ML605 kit and is shopping FMC daughter board. I understand that Xilinx worked with Analog Device on a multi-mode radio demo platform. Analog Devices provided a RF board called Mixed Signal Digital Pre-Distortion (MSDPD) board. I wonder if that board is available for purchase. I got the information from: http://www.xilinx.com/publications/prod_mktg/Radio-TDP-SellSheet.pdf YanArticle: 146983
HI, I want to use sll operator(shift operator)specified in VHDL93. I am using xilinx ISE simulator.The compilation of code fails giving error HDLParsers:808- sll can not have such operands in this context. I think that i should activate VHDL93 in the simulator.MODELSIM has the facility to activate it through compiler settings. HOw to activate it in XILINX? Plz tell me.It's very very urgent. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146984
>On Dec 23, 11:15 am, Gabor <ga...@alacron.com> wrote: >> On Dec 23, 1:50 am, "Andrew W. Hill" <aquaregi...@gmail.com> wrote: >> > I'm using EDK 10.1, specced for the ML501. When I reach the mapping >> > phase, I get the following error (several times): >> >> > ERROR:PhysDesignRules:1492 - Incompatible programming for comp >> > mb_plb_M_ABus<1>. >> > The pair of luts SLICEL_A5LUT and SLICEL_A6LUT must have a >> > compatible >> > equation, lower bits must be programmed the same. The SLICEL_A5LUT >> > hex >> > equation is <O5=0x08080808> and the SLICEL_A6LUT hex equation is >> > <O6=0x607AA67800008888>. >> >> > I found the following Xilinx note on the error, which notes that this >> > error was erroneously thrown in EDK versions <8 :http://www.xilinx.com/support/answers/23645.htm >> >> > My system is fairly standard. I used BSB and added a few things >> > (LEDs,switches), but nothing particularly exotic. Is there something >> > obvious that I might have missed, or is this likely to be an error >> > with DRC? >> >> The obvious question, given the note from Xilinx, is did you ever >> build >> any part of this system under an older revision of EDK? Xilinx >> software >> is famous for failing to clean up old bits of object... > >I previously built under EDK 9, but I did a clean from within EDK and >also did a quick walkthrough of the remaining files. I've never built >it in EDK <8. >Cheers >Andrew > I got the same error message. "Incompatible programming for comp mb_plb_M_Abus<29>". After installing the service pack 3 for ISE, this problem went away. -Doug W --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146985
Hi, > You're fighting against VHDL's strict rules, instead of getting > them to work for you. I ask those who know more than me ... > Do you like this version better? > > =A0 constant =A0input_bit_width: positive :=3D din'length; > =A0 constant output_bit_width: positive :=3D dout'length; > =A0 subtype T_input_code is integer range 0 to (2**input_bit_width-1); > =A0 subtype T_output_code is integer range 0 to (2**output_bit_width-1); > =A0 type T_code_map is array(T_input_code) of T_output_code; > > =A0 ----------------- HERE IS THE LOOKUP TABLE --------- > =A0 constant code_map: T_code_map :=3D ( > =A0 =A0 0 =3D> 2, > =A0 =A0 1 =3D> 0, > =A0 =A0 2 =3D> 1, > =A0 =A0 3 =3D> 1, > =A0 =A0 4 =3D> 2, > =A0 =A0 5 =3D> 3, > =A0 =A0 6 =3D> 3, > =A0 =A0 7 =3D> 0); How use HEX value ... my request came from them do not want to return to decimal format ... :-| ... > =A0 ------------------------------------------------------ > =A0 -- You will get errors if you don't provide the full set > =A0 -- of map values, but you can use OTHERS if you wish. > =A0 ... > =A0 process (din) > =A0 =A0 variable code_in: T_input_code; > =A0 =A0 variable code_out: T_output_code; > =A0 begin > =A0 =A0 code_in :=3D to_integer(unsigned(din)); > =A0 =A0 code_out :=3D code_map(code_in); > =A0 =A0 dout <=3D std_logic_vector(to_unsigned(code_out, output_bit_width= )); > =A0 end process; Is somewhat more complicated for me but certainly more professional ... > There are lots of other possibilities; the precise way you choose to > parameterize this design, and set up the constants, depends on how it > fits into the rest of your design and how it will be used. =A0If you > are careful and lucky, you can probably avoid the type conversions > in this part of the code, because you are using appropriate numeric > data types in the body of your design. =A0But that's another discussion. This is our main problem, avoid conversion of format, I'm translating a simple C code in VHDL using HEX, I wanted to keep reading two code. > If you absolutely insist on hex representation, you can easily > rewrite the map table: > > =A0 constant code_map: T_code_map :=3D ( > =A0 =A0 16#0# =3D> 16#2#, > =A0 =A0 ... > =A0 =A0 16#7# =3D> 16#0#); Is perfect ... > Oh, and I've used numeric_std instead of std_logic_horrible > for the numeric conversions. > > Named types, subtypes and constants are your friend, especially > when revisiting the code later, if you choose the names wisely. You are quite right, especially if you often revises the code. > I'll leave it to someone else to open a discussion about > the incomplete case statement. Thanks. secureasmArticle: 146986
Hi, again me ... :-) ... I have one problem with SUM of 3 signal. ############# [CODE]############# signal E : std_logic_vector (3 downto 0); signal Z : std_logic_vector (3 downto 0); signal r : std_logic; signal total : std_logic_vector(4 downto 0); total <= Zi + Ei + r; ############# [/CODE]############# If I generate the block schematic (Xilinx ISE) the "adder" have 2 input of 4 bits and CI, and so far are perfectly okay, but the output is 4 bits without CO ... why ? Where he finished 5th bit of total signal ? Where is that wrong ? I'm confused ... secureasmArticle: 146987
Add a notes, infact I receiving a warning from tools: "Width mismatch. <total> has a width of 5 bits but assigned expression is 4-bit wide." I have used alse this template (for adder with carry out) but without resul : <temp_value> <= <input1> + <input2>; <output_sum> <= <temp_value>((<adder_width>-1) downto 0); <carry_out> <= <temp_value>(<adder_width>); How generate adder with carry out ? secureasmArticle: 146988
Kappa wrote:
> Add a notes, infact I receiving a warning from tools:
>
> "Width mismatch. <total> has a width of 5 bits but assigned expression
> is 4-bit wide."
>
> I have used alse this template (for adder with carry out) but without
> resul :
>
> <temp_value> <= <input1> + <input2>;
> <output_sum> <= <temp_value>((<adder_width>-1) downto 0);
> <carry_out> <= <temp_value>(<adder_width>);
>
> How generate adder with carry out ?
>
> secureasm
one way I have used : implement a "normal" adder,
with 1 more MSB and one more LSB, so you have
tmp : std_logic_vector(width+1 downto 0);
then : you construct your 2 operands so that
- the LSB is the carry in, it goes on one input,
the other input is stuck to '1' => carry in propagates
to the next LSB.
- The MSB is the carry out.
- the other bits are the normal wide operands.
I did this on http://yasep.org/VHDL/ASU_ROP2_16.vhd
and the result code is :
-- add/sub :
sumAux := unsigned('0' & ActualAr & '1') + unsigned('0' & ActualBr & Addsubr);
-- if (Addsub = '0') then + else -
modulo some variable renaming, of course, and
the temporary result sumAux here is a unsigned,
it is cast later as a std_logic_vector :
-- trim the LSB (carry-in)
Sum(Sum'left downto 0) <= std_ulogic_vector(sumAux(sumAux'left downto 1));
It should work everywhere and the unnecessary bits
must be optimised out.
HTH
yg
--
http://ygdes.com / http://yasep.org
Article: 146989
You can use the "explicit" shift:
process( clk )
begin
i f rst = '1' then
A <= ( others => '0' );
elsif rising_edge( clk ) then
A( N-2 downto 0 ) <= A( N-1 downto 1 );
A( N-1 ) <= '0';
end if;
end process;
Obviously this code should be adapted to your specific case.
Regards,
mt
Article: 146990On Apr 8, 4:30=A0am, Kappa <secure...@gmail.com> wrote: > Hi, again me ... :-) ... > > I have one problem with SUM of 3 signal. > > ############# [CODE]############# > > signal E : std_logic_vector (3 downto 0); > signal Z : std_logic_vector (3 downto 0); > signal r =A0: std_logic; > signal total : std_logic_vector(4 downto 0); > > total <=3D Zi + Ei + r; > > ############# [/CODE]############# > > If I generate the block schematic (Xilinx ISE) the "adder" have 2 > input of 4 bits and CI, and so far are perfectly okay, but the output > is 4 bits without CO ... why ? > Does total(4) get used anywhere? If not, then it will get optimized away since it is not needed. > Where he finished 5th bit of total signal ? > You tell us, the use of total(4) would be in your code. Any signal that does cause an output pin to change either directly, or indirectly, will get optimized away. > Where is that wrong ? > Your expectations are likely what is wrong. > I'm confused ... > Try bringing total(4) to an output pin. KJArticle: 146991
Hello, I'm a graduate student and I have a project on the ML402 (Virtex-4) board under EDK 11.2, and I am unable to download a specific ELF I have created to the board. Other software applications (both EDK generated and programmed by myself) can be successfully downloaded and run as part of this EDK project, but not the one I am currently work on. The following is the output I receive: ==== XMD% dow udp_temac_test/executable.elf System Reset .... DONE Downloading Program -- udp_temac_test/executable.elf section, .vectors.reset: 0x00000000-0x00000003 section, .vectors.sw_exception: 0x00000008-0x0000000b section, .vectors.interrupt: 0x00000010-0x00000013 section, .vectors.hw_exception: 0x00000020-0x00000023 section, .text: 0x00000050-0x00012c3b section, .init: 0x00012c3c-0c00012c63 section.fini: 0x00012c64-0x00012c83 ERROR: Failed to download ELF file. I-Side Memory Access Check Failed Section, 0x00000050-0x00012c3b Not Accessible from Processor I-Side Interface ==== Had anyone had this issue before? Anyone have any idea what might be causing it / how to solve it? Thanks in advance, Sean.Article: 146992
This doesn't answer your question per se, but is worth reading. http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf You are using ieee.numeric_std.all ? You should be! HTH., Syms.Article: 146993
I have included my .mhs file: # ###########################################################################= ### # Created by Base System Builder Wizard for Xilinx EDK 11.2 Build EDK_LS2.6 # Mon Mar 8 17:09:28 2010 # Target Board: Xilinx Virtex 4 ML402 Evaluation Platform Rev 1 # Family: virtex4 # Device: xc4vsx35 # Package: ff668 # Speed Grade: -10 # Processor number: 1 # Processor 1: microblaze_0 # System clock frequency: 100.0 # Debug Interface: On-Chip HW Debug Module # ###########################################################################= ### PARAMETER VERSION =3D 2.1.0 PORT fpga_0_DDR_SDRAM_DDR_Clk_pin =3D fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR =3D O PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin =3D fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR =3D O PORT fpga_0_DDR_SDRAM_DDR_CE_pin =3D fpga_0_DDR_SDRAM_DDR_CE_pin, DIR =3D O PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin =3D fpga_0_DDR_SDRAM_DDR_CS_n_pin, DIR =3D O PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin =3D fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR =3D O PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin =3D fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR =3D O PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin =3D fpga_0_DDR_SDRAM_DDR_WE_n_pin, DIR =3D O PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =3D fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR =3D O, VEC =3D [1:0] PORT fpga_0_DDR_SDRAM_DDR_Addr_pin =3D fpga_0_DDR_SDRAM_DDR_Addr_pin, DIR =3D O, VEC =3D [12:0] PORT fpga_0_DDR_SDRAM_DDR_DQ_pin =3D fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR =3D IO, VEC =3D [31:0] PORT fpga_0_DDR_SDRAM_DDR_DM_pin =3D fpga_0_DDR_SDRAM_DDR_DM_pin, DIR =3D O, VEC =3D [3:0] PORT fpga_0_DDR_SDRAM_DDR_DQS_pin =3D fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR =3D IO, VEC =3D [3:0] PORT fpga_0_IIC_EEPROM_Sda_pin =3D fpga_0_IIC_EEPROM_Sda_pin, DIR =3D IO PORT fpga_0_IIC_EEPROM_Scl_pin =3D fpga_0_IIC_EEPROM_Scl_pin, DIR =3D IO PORT fpga_0_LEDs_4Bit_GPIO_IO_pin =3D fpga_0_LEDs_4Bit_GPIO_IO_pin, DIR =3D IO, VEC =3D [0:3] PORT fpga_0_LEDs_Positions_GPIO_IO_pin =3D fpga_0_LEDs_Positions_GPIO_IO_pin, DIR =3D IO, VEC =3D [0:4] PORT fpga_0_RS232_Uart_RX_pin =3D fpga_0_RS232_Uart_RX_pin, DIR =3D I PORT fpga_0_RS232_Uart_TX_pin =3D fpga_0_RS232_Uart_TX_pin, DIR =3D O PORT fpga_0_SRAM_Mem_A_pin =3D fpga_0_SRAM_Mem_A_pin_vslice_7_29_concat, DIR =3D O, VEC =3D [7:29] PORT fpga_0_SRAM_Mem_CEN_pin =3D fpga_0_SRAM_Mem_CEN_pin, DIR =3D O PORT fpga_0_SRAM_Mem_OEN_pin =3D fpga_0_SRAM_Mem_OEN_pin, DIR =3D O PORT fpga_0_SRAM_Mem_WEN_pin =3D fpga_0_SRAM_Mem_WEN_pin, DIR =3D O PORT fpga_0_SRAM_Mem_BEN_pin =3D fpga_0_SRAM_Mem_BEN_pin, DIR =3D O, VEC =3D [0:3] PORT fpga_0_SRAM_Mem_ADV_LDN_pin =3D fpga_0_SRAM_Mem_ADV_LDN_pin, DIR =3D O PORT fpga_0_SRAM_Mem_DQ_pin =3D fpga_0_SRAM_Mem_DQ_pin, DIR =3D IO, VEC = =3D [0:31] PORT fpga_0_SRAM_ZBT_CLK_OUT_pin =3D clk_100_0000MHzDCM0, DIR =3D O PORT fpga_0_Soft_TEMAC_TemacPhy_RST_n_pin =3D fpga_0_Soft_TEMAC_TemacPhy_RST_n_pin, DIR =3D O PORT fpga_0_Soft_TEMAC_MII_TX_CLK_0_pin =3D fpga_0_Soft_TEMAC_MII_TX_CLK_0_pin, DIR =3D I PORT fpga_0_Soft_TEMAC_GMII_TXD_0_pin =3D fpga_0_Soft_TEMAC_GMII_TXD_0_pin, DIR =3D O, VEC =3D [7:0] PORT fpga_0_Soft_TEMAC_GMII_TX_EN_0_pin =3D fpga_0_Soft_TEMAC_GMII_TX_EN_0_pin, DIR =3D O PORT fpga_0_Soft_TEMAC_GMII_TX_ER_0_pin =3D fpga_0_Soft_TEMAC_GMII_TX_ER_0_pin, DIR =3D O PORT fpga_0_Soft_TEMAC_GMII_TX_CLK_0_pin =3D fpga_0_Soft_TEMAC_GMII_TX_CLK_0_pin, DIR =3D O PORT fpga_0_Soft_TEMAC_GMII_RXD_0_pin =3D fpga_0_Soft_TEMAC_GMII_RXD_0_pin, DIR =3D I, VEC =3D [7:0] PORT fpga_0_Soft_TEMAC_GMII_RX_DV_0_pin =3D fpga_0_Soft_TEMAC_GMII_RX_DV_0_pin, DIR =3D I PORT fpga_0_Soft_TEMAC_GMII_RX_ER_0_pin =3D fpga_0_Soft_TEMAC_GMII_RX_ER_0_pin, DIR =3D I PORT fpga_0_Soft_TEMAC_GMII_RX_CLK_0_pin =3D fpga_0_Soft_TEMAC_GMII_RX_CLK_0_pin, DIR =3D I PORT fpga_0_Soft_TEMAC_MDC_0_pin =3D fpga_0_Soft_TEMAC_MDC_0_pin, DIR =3D O PORT fpga_0_Soft_TEMAC_MDIO_0_pin =3D fpga_0_Soft_TEMAC_MDIO_0_pin, DIR =3D IO PORT fpga_0_Soft_TEMAC_PHY_INTR_pin =3D fpga_0_Soft_TEMAC_PHY_INTR_pin, DIR =3D I, SIGIS =3D INTERRUPT, SENSITIVITY =3D LEVEL_LOW, INTERRUPT_PRIORITY =3D MEDIUM PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR =3D O, VEC =3D [6:0] PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =3D fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR =3D I PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =3D fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR =3D I PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =3D fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR =3D O PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =3D fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR =3D O PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =3D fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR =3D O PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =3D fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR =3D IO, VEC =3D [15:0] PORT fpga_0_clk_1_sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ =3D 100000000 PORT fpga_0_rst_1_sys_rst_pin =3D sys_rst_s, DIR =3D I, SIGIS =3D RST, RST_POLARITY =3D 0 PORT event_getter_0_pixels_in_pin =3D event_getter_0_pixels_in, DIR =3D I, VEC =3D [0:6] PORT event_getter_0_pixels_out_pin =3D event_getter_0_pixels_out, DIR =3D O, VEC =3D [0:6] PORT sv_timer_0_timer_expired_watch_pin =3D sv_timer_0_timer_expired_watch, DIR =3D O PORT sv_timer_0_hard_reset_pin =3D sv_timer_0_hard_reset, DIR =3D I PORT si_timer_0_hard_reset_pin =3D si_timer_0_hard_reset, DIR =3D I PORT si_timer_0_timer_expired_watch_pin =3D si_timer_0_timer_expired_watch, DIR =3D O BEGIN xps_intc PARAMETER INSTANCE =3D xps_intc_0 PARAMETER HW_VER =3D 2.00.a PARAMETER C_BASEADDR =3D 0x81800000 PARAMETER C_HIGHADDR =3D 0x8180ffff BUS_INTERFACE SPLB =3D mb_plb PORT Intr =3D Soft_TEMAC_fifo_IP2INTC_Irpt&si_timer_irc PORT Irq =3D microblaze_0_Interrupt END BEGIN si_timer PARAMETER INSTANCE =3D si_timer_0 PARAMETER HW_VER =3D 1.00.a PARAMETER C_BASEADDR =3D 0xca020000 PARAMETER C_HIGHADDR =3D 0xca02ffff BUS_INTERFACE SPLB =3D mb_plb PORT IP2INTC_Irpt =3D si_timer_irc PORT hard_reset =3D si_timer_0_hard_reset PORT timer_expired_watch =3D si_timer_0_timer_expired_watch END BEGIN proc_sys_reset PARAMETER INSTANCE =3D proc_sys_reset_0 PARAMETER C_EXT_RESET_HIGH =3D 0 PARAMETER HW_VER =3D 2.00.a PORT Slowest_sync_clk =3D clk_100_0000MHzDCM0 PORT Ext_Reset_In =3D sys_rst_s PORT MB_Debug_Sys_Rst =3D Debug_SYS_Rst PORT Dcm_locked =3D Dcm_all_locked PORT MB_Reset =3D mb_reset PORT Bus_Struct_Reset =3D sys_bus_reset PORT Peripheral_Reset =3D sys_periph_reset END BEGIN microblaze PARAMETER INSTANCE =3D microblaze_0 PARAMETER C_FAMILY =3D virtex4 PARAMETER C_INTERCONNECT =3D 1 PARAMETER C_DEBUG_ENABLED =3D 1 PARAMETER C_ICACHE_BASEADDR =3D 0x88300000 PARAMETER C_ICACHE_HIGHADDR =3D 0x883fffff PARAMETER C_CACHE_BYTE_SIZE =3D 65536 PARAMETER C_ICACHE_ALWAYS_USED =3D 1 PARAMETER C_DCACHE_BASEADDR =3D 0x88300000 PARAMETER C_DCACHE_HIGHADDR =3D 0x883fffff PARAMETER C_DCACHE_BYTE_SIZE =3D 65536 PARAMETER C_DCACHE_ALWAYS_USED =3D 1 PARAMETER HW_VER =3D 7.20.b PARAMETER C_USE_ICACHE =3D 1 PARAMETER C_USE_DCACHE =3D 1 BUS_INTERFACE DLMB =3D dlmb BUS_INTERFACE ILMB =3D ilmb BUS_INTERFACE DPLB =3D mb_plb BUS_INTERFACE IPLB =3D mb_plb BUS_INTERFACE DXCL =3D microblaze_0_DXCL BUS_INTERFACE IXCL =3D microblaze_0_IXCL BUS_INTERFACE DEBUG =3D microblaze_0_mdm_bus PORT MB_RESET =3D mb_reset PORT INTERRUPT =3D microblaze_0_Interrupt END BEGIN mdm PARAMETER INSTANCE =3D mdm_0 PARAMETER C_MB_DBG_PORTS =3D 1 PARAMETER C_USE_UART =3D 1 PARAMETER C_UART_WIDTH =3D 8 PARAMETER HW_VER =3D 1.00.f PARAMETER C_BASEADDR =3D 0x84400000 PARAMETER C_HIGHADDR =3D 0x8440ffff BUS_INTERFACE SPLB =3D mb_plb BUS_INTERFACE MBDEBUG_0 =3D microblaze_0_mdm_bus PORT Debug_SYS_Rst =3D Debug_SYS_Rst END BEGIN plb_v46 PARAMETER INSTANCE =3D mb_plb PARAMETER C_FAMILY =3D virtex4 PARAMETER HW_VER =3D 1.04.a PORT PLB_Clk =3D clk_100_0000MHzDCM0 PORT SYS_Rst =3D sys_bus_reset END BEGIN bram_block PARAMETER INSTANCE =3D lmb_bram PARAMETER C_FAMILY =3D virtex4 PARAMETER HW_VER =3D 1.00.a BUS_INTERFACE PORTA =3D ilmb_port BUS_INTERFACE PORTB =3D dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE =3D ilmb_cntlr PARAMETER HW_VER =3D 2.10.b PARAMETER C_BASEADDR =3D 0x00000000 PARAMETER C_HIGHADDR =3D 0x0000ffff BUS_INTERFACE SLMB =3D ilmb BUS_INTERFACE BRAM_PORT =3D ilmb_port END BEGIN lmb_v10 PARAMETER INSTANCE =3D ilmb PARAMETER HW_VER =3D 1.00.a PORT LMB_Clk =3D clk_100_0000MHzDCM0 PORT SYS_Rst =3D sys_bus_reset END # PORT pixels_in =3D event_getter_0_pixels_in # PORT pixels_out =3D event_getter_0_pixels_out BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE =3D dlmb_cntlr PARAMETER HW_VER =3D 2.10.b PARAMETER C_BASEADDR =3D 0x00000000 PARAMETER C_HIGHADDR =3D 0x0000ffff BUS_INTERFACE SLMB =3D dlmb BUS_INTERFACE BRAM_PORT =3D dlmb_port END BEGIN lmb_v10 PARAMETER INSTANCE =3D dlmb PARAMETER HW_VER =3D 1.00.a PORT LMB_Clk =3D clk_100_0000MHzDCM0 PORT SYS_Rst =3D sys_bus_reset END BEGIN clock_generator PARAMETER INSTANCE =3D clock_generator_0 PARAMETER C_CLKIN_FREQ =3D 100000000 PARAMETER C_CLKOUT0_FREQ =3D 100000000 PARAMETER C_CLKOUT0_PHASE =3D 90 PARAMETER C_CLKOUT0_GROUP =3D DCM0 PARAMETER C_CLKOUT0_BUF =3D TRUE PARAMETER C_CLKOUT1_FREQ =3D 100000000 PARAMETER C_CLKOUT1_PHASE =3D 0 PARAMETER C_CLKOUT1_GROUP =3D DCM0 PARAMETER C_CLKOUT1_BUF =3D TRUE PARAMETER C_CLKOUT2_FREQ =3D 125000000 PARAMETER C_CLKOUT2_PHASE =3D 0 PARAMETER C_CLKOUT2_GROUP =3D NONE PARAMETER C_CLKOUT2_BUF =3D TRUE PARAMETER C_CLKOUT3_FREQ =3D 200000000 PARAMETER C_CLKOUT3_PHASE =3D 0 PARAMETER C_CLKOUT3_GROUP =3D NONE PARAMETER C_CLKOUT3_BUF =3D TRUE PARAMETER HW_VER =3D 3.01.a PORT CLKIN =3D dcm_clk_s PORT CLKOUT0 =3D clk_100_0000MHz90DCM0 PORT CLKOUT1 =3D clk_100_0000MHzDCM0 PORT CLKOUT2 =3D clk_125_0000MHz PORT CLKOUT3 =3D clk_200_0000MHz PORT RST =3D net_gnd PORT LOCKED =3D Dcm_all_locked END BEGIN xps_sysace PARAMETER INSTANCE =3D SysACE_CompactFlash PARAMETER C_MEM_WIDTH =3D 16 PARAMETER C_FAMILY =3D virtex4 PARAMETER HW_VER =3D 1.01.a PARAMETER C_BASEADDR =3D 0x83600000 PARAMETER C_HIGHADDR =3D 0x8360ffff BUS_INTERFACE SPLB =3D mb_plb PORT SysACE_MPA =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_pin PORT SysACE_CLK =3D fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PORT SysACE_MPIRQ =3D fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin PORT SysACE_CEN =3D fpga_0_SysACE_CompactFlash_SysACE_CEN_pin PORT SysACE_OEN =3D fpga_0_SysACE_CompactFlash_SysACE_OEN_pin PORT SysACE_WEN =3D fpga_0_SysACE_CompactFlash_SysACE_WEN_pin PORT SysACE_MPD =3D fpga_0_SysACE_CompactFlash_SysACE_MPD_pin END BEGIN xps_ll_fifo PARAMETER INSTANCE =3D Soft_TEMAC_fifo PARAMETER HW_VER =3D 1.02.a PARAMETER C_BASEADDR =3D 0x81a00000 PARAMETER C_HIGHADDR =3D 0x81a0ffff BUS_INTERFACE SPLB =3D mb_plb BUS_INTERFACE LLINK =3D Soft_TEMAC_llink0 PORT IP2INTC_Irpt =3D Soft_TEMAC_fifo_IP2INTC_Irpt END BEGIN xps_ll_temac PARAMETER INSTANCE =3D Soft_TEMAC PARAMETER C_NUM_IDELAYCTRL =3D 3 PARAMETER C_IDELAYCTRL_LOC =3D IDELAYCTRL_X1Y4-IDELAYCTRL_X2Y4- IDELAYCTRL_X2Y5 PARAMETER C_FAMILY =3D virtex4 PARAMETER C_PHY_TYPE =3D 1 PARAMETER C_TEMAC1_ENABLED =3D 0 PARAMETER C_BUS2CORE_CLK_RATIO =3D 1 PARAMETER C_TEMAC_TYPE =3D 2 PARAMETER C_TEMAC0_PHYADDR =3D 0b00001 PARAMETER HW_VER =3D 2.02.a PARAMETER C_BASEADDR =3D 0x81c00000 PARAMETER C_HIGHADDR =3D 0x81c0ffff BUS_INTERFACE SPLB =3D mb_plb BUS_INTERFACE LLINK0 =3D Soft_TEMAC_llink0 PORT TemacPhy_RST_n =3D fpga_0_Soft_TEMAC_TemacPhy_RST_n_pin PORT GTX_CLK_0 =3D clk_125_0000MHz PORT REFCLK =3D clk_200_0000MHz PORT LlinkTemac0_CLK =3D clk_100_0000MHzDCM0 PORT MII_TX_CLK_0 =3D fpga_0_Soft_TEMAC_MII_TX_CLK_0_pin PORT GMII_TXD_0 =3D fpga_0_Soft_TEMAC_GMII_TXD_0_pin PORT GMII_TX_EN_0 =3D fpga_0_Soft_TEMAC_GMII_TX_EN_0_pin PORT GMII_TX_ER_0 =3D fpga_0_Soft_TEMAC_GMII_TX_ER_0_pin PORT GMII_TX_CLK_0 =3D fpga_0_Soft_TEMAC_GMII_TX_CLK_0_pin PORT GMII_RXD_0 =3D fpga_0_Soft_TEMAC_GMII_RXD_0_pin PORT GMII_RX_DV_0 =3D fpga_0_Soft_TEMAC_GMII_RX_DV_0_pin PORT GMII_RX_ER_0 =3D fpga_0_Soft_TEMAC_GMII_RX_ER_0_pin PORT GMII_RX_CLK_0 =3D fpga_0_Soft_TEMAC_GMII_RX_CLK_0_pin PORT MDC_0 =3D fpga_0_Soft_TEMAC_MDC_0_pin PORT MDIO_0 =3D fpga_0_Soft_TEMAC_MDIO_0_pin END BEGIN xps_mch_emc PARAMETER INSTANCE =3D SRAM PARAMETER C_FAMILY =3D virtex4 PARAMETER C_NUM_BANKS_MEM =3D 1 PARAMETER C_NUM_CHANNELS =3D 2 PARAMETER C_INCLUDE_NEGEDGE_IOREGS =3D 1 PARAMETER C_MEM0_WIDTH =3D 32 PARAMETER C_MAX_MEM_WIDTH =3D 32 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 =3D 0 PARAMETER C_SYNCH_MEM_0 =3D 1 PARAMETER C_TCEDV_PS_MEM_0 =3D 0 PARAMETER C_TAVDV_PS_MEM_0 =3D 0 PARAMETER C_THZCE_PS_MEM_0 =3D 0 PARAMETER C_TWC_PS_MEM_0 =3D 0 PARAMETER C_TWP_PS_MEM_0 =3D 0 PARAMETER C_TLZWE_PS_MEM_0 =3D 0 PARAMETER HW_VER =3D 3.00.a PARAMETER C_MEM0_BASEADDR =3D 0x88300000 PARAMETER C_MEM0_HIGHADDR =3D 0x883fffff BUS_INTERFACE SPLB =3D mb_plb BUS_INTERFACE MCH0 =3D microblaze_0_IXCL BUS_INTERFACE MCH1 =3D microblaze_0_DXCL PORT RdClk =3D clk_100_0000MHzDCM0 PORT Mem_A =3D 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_29_concat & 0b00 PORT Mem_CEN =3D fpga_0_SRAM_Mem_CEN_pin PORT Mem_OEN =3D fpga_0_SRAM_Mem_OEN_pin PORT Mem_WEN =3D fpga_0_SRAM_Mem_WEN_pin PORT Mem_BEN =3D fpga_0_SRAM_Mem_BEN_pin PORT Mem_ADV_LDN =3D fpga_0_SRAM_Mem_ADV_LDN_pin PORT Mem_DQ =3D fpga_0_SRAM_Mem_DQ_pin END BEGIN xps_uartlite PARAMETER INSTANCE =3D RS232_Uart PARAMETER C_FAMILY =3D virtex4 PARAMETER C_BAUDRATE =3D 9600 PARAMETER C_DATA_BITS =3D 8 PARAMETER C_USE_PARITY =3D 0 PARAMETER C_ODD_PARITY =3D 0 PARAMETER HW_VER =3D 1.01.a PARAMETER C_BASEADDR =3D 0x84000000 PARAMETER C_HIGHADDR =3D 0x8400ffff BUS_INTERFACE SPLB =3D mb_plb PORT RX =3D fpga_0_RS232_Uart_RX_pin PORT TX =3D fpga_0_RS232_Uart_TX_pin END BEGIN xps_gpio PARAMETER INSTANCE =3D LEDs_Positions PARAMETER C_FAMILY =3D virtex4 PARAMETER C_ALL_INPUTS =3D 0 PARAMETER C_GPIO_WIDTH =3D 5 PARAMETER C_INTERRUPT_PRESENT =3D 0 PARAMETER C_IS_DUAL =3D 0 PARAMETER HW_VER =3D 2.00.a PARAMETER C_BASEADDR =3D 0x81400000 PARAMETER C_HIGHADDR =3D 0x8140ffff BUS_INTERFACE SPLB =3D mb_plb PORT GPIO_IO =3D fpga_0_LEDs_Positions_GPIO_IO_pin END BEGIN xps_gpio PARAMETER INSTANCE =3D LEDs_4Bit PARAMETER C_FAMILY =3D virtex4 PARAMETER C_ALL_INPUTS =3D 0 PARAMETER C_GPIO_WIDTH =3D 4 PARAMETER C_INTERRUPT_PRESENT =3D 0 PARAMETER C_IS_DUAL =3D 0 PARAMETER HW_VER =3D 2.00.a PARAMETER C_BASEADDR =3D 0x81420000 PARAMETER C_HIGHADDR =3D 0x8142ffff BUS_INTERFACE SPLB =3D mb_plb PORT GPIO_IO =3D fpga_0_LEDs_4Bit_GPIO_IO_pin END BEGIN xps_iic PARAMETER INSTANCE =3D IIC_EEPROM PARAMETER C_IIC_FREQ =3D 100000 PARAMETER C_TEN_BIT_ADR =3D 0 PARAMETER C_FAMILY =3D virtex4 PARAMETER HW_VER =3D 2.01.a PARAMETER C_BASEADDR =3D 0x81600000 PARAMETER C_HIGHADDR =3D 0x8160ffff BUS_INTERFACE SPLB =3D mb_plb PORT Sda =3D fpga_0_IIC_EEPROM_Sda_pin PORT Scl =3D fpga_0_IIC_EEPROM_Scl_pin END BEGIN mpmc PARAMETER INSTANCE =3D DDR_SDRAM PARAMETER C_FAMILY =3D virtex4 PARAMETER C_NUM_PORTS =3D 1 PARAMETER C_NUM_IDELAYCTRL =3D 2 PARAMETER C_IDELAYCTRL_LOC =3D IDELAYCTRL_X0Y4-IDELAYCTRL_X0Y5 PARAMETER C_MEM_TYPE =3D DDR PARAMETER C_MEM_PARTNO =3D HYB25D256160BT-7 PARAMETER C_MEM_DATA_WIDTH =3D 32 PARAMETER C_MEM_DM_WIDTH =3D 4 PARAMETER C_MEM_DQS_WIDTH =3D 4 PARAMETER C_PIM0_BASETYPE =3D 2 PARAMETER HW_VER =3D 5.02.a PARAMETER C_MPMC_BASEADDR =3D 0x8c000000 PARAMETER C_MPMC_HIGHADDR =3D 0x8fffffff BUS_INTERFACE SPLB0 =3D mb_plb PORT MPMC_Clk0 =3D clk_100_0000MHzDCM0 PORT MPMC_Clk90 =3D clk_100_0000MHz90DCM0 PORT MPMC_Clk_200MHz =3D clk_200_0000MHz PORT MPMC_Rst =3D sys_periph_reset PORT DDR_Clk =3D fpga_0_DDR_SDRAM_DDR_Clk_pin PORT DDR_Clk_n =3D fpga_0_DDR_SDRAM_DDR_Clk_n_pin PORT DDR_CE =3D fpga_0_DDR_SDRAM_DDR_CE_pin PORT DDR_CS_n =3D fpga_0_DDR_SDRAM_DDR_CS_n_pin PORT DDR_RAS_n =3D fpga_0_DDR_SDRAM_DDR_RAS_n_pin PORT DDR_CAS_n =3D fpga_0_DDR_SDRAM_DDR_CAS_n_pin PORT DDR_WE_n =3D fpga_0_DDR_SDRAM_DDR_WE_n_pin PORT DDR_BankAddr =3D fpga_0_DDR_SDRAM_DDR_BankAddr_pin PORT DDR_Addr =3D fpga_0_DDR_SDRAM_DDR_Addr_pin PORT DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ_pin PORT DDR_DM =3D fpga_0_DDR_SDRAM_DDR_DM_pin PORT DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS_pin END BEGIN event_getter PARAMETER INSTANCE =3D event_getter_0 PARAMETER HW_VER =3D 1.03.a PARAMETER C_BASEADDR =3D 0xcf400000 PARAMETER C_HIGHADDR =3D 0xcf40ffff BUS_INTERFACE SPLB =3D mb_plb PORT pixels_in =3D event_getter_0_pixels_in PORT pixels_out =3D event_getter_0_pixels_out END BEGIN sv_timer PARAMETER INSTANCE =3D sv_timer_0 PARAMETER HW_VER =3D 2.04.a PARAMETER C_BASEADDR =3D 0xca000000 PARAMETER C_HIGHADDR =3D 0xca00ffff BUS_INTERFACE SPLB =3D mb_plb PORT timer_expired_watch =3D sv_timer_0_timer_expired_watch PORT hard_reset =3D sv_timer_0_hard_reset END On Apr 8, 9:51=A0am, Griffin <captain.grif...@gmail.com> wrote: > Hello, > > I'm a graduate student and I have a project on the ML402 (Virtex-4) > board under EDK 11.2, and I am unable to download a specific ELF I > have created to the board. Other software applications (both EDK > generated and programmed by myself) can be successfully downloaded and > run as part of this EDK project, but not the one I am currently work > on. > > The following is the output I receive: > =3D=3D=3D=3D > XMD% dow udp_temac_test/executable.elf > System Reset .... DONE > Downloading Program -- udp_temac_test/executable.elf > section, .vectors.reset: 0x00000000-0x00000003 > section, .vectors.sw_exception: 0x00000008-0x0000000b > section, .vectors.interrupt: 0x00000010-0x00000013 > section, .vectors.hw_exception: 0x00000020-0x00000023 > section, .text: 0x00000050-0x00012c3b > section, .init: 0x00012c3c-0c00012c63 > section.fini: 0x00012c64-0x00012c83 > ERROR: Failed to download ELF file. > > I-Side Memory Access Check Failed > Section, 0x00000050-0x00012c3b Not Accessible from Processor I-Side > Interface > > =3D=3D=3D=3D > > Had anyone had this issue before? Anyone have any idea what might be > causing it / how to solve it? > > Thanks in advance, > > Sean.Article: 146994
> Does total(4) get used anywhere? =A0If not, then it will get optimized > away since it is not needed. Yes, I use all 5 bits of "total" signal. > You tell us, the use of total(4) would be in your code. =A0Any signal > that does cause an output pin to change either directly, or > indirectly, will get optimized away. OK, but I use all signal ... secureasmArticle: 146995
Hi, I have resolved my problem. This code not work : ############# [CODE]############# signal E : std_logic_vector (3 downto 0); signal Z : std_logic_vector (3 downto 0); signal r : std_logic; signal total : std_logic_vector(4 downto 0); total <= Zi + Ei + r; ############# [/CODE]############# This code work very well : ############# [CODE]############# signal E : std_logic_vector (3 downto 0); signal Z : std_logic_vector (3 downto 0); signal r : std_logic; signal total : integer; signal total_signal : std_logic_vector(4 downto 0); total <= conv_integer(Zi) + conv_integer(Ei) + conv_integer(r); total_signal <= conv_std_logic_vector(total, 5); ############# [/CODE]############# This create adder with carry out signal ... Thanks. secureasmArticle: 146996
On Apr 8, 9:51=A0am, Griffin <captain.grif...@gmail.com> wrote: > Hello, > > I'm a graduate student and I have a project on the ML402 (Virtex-4) > board under EDK 11.2, and I am unable to download a specific ELF I > have created to the board. Other software applications (both EDK > generated and programmed by myself) can be successfully downloaded and > run as part of this EDK project, but not the one I am currently work > on. > > The following is the output I receive: > =3D=3D=3D=3D > XMD% dow udp_temac_test/executable.elf > System Reset .... DONE > Downloading Program -- udp_temac_test/executable.elf > section, .vectors.reset: 0x00000000-0x00000003 > section, .vectors.sw_exception: 0x00000008-0x0000000b > section, .vectors.interrupt: 0x00000010-0x00000013 > section, .vectors.hw_exception: 0x00000020-0x00000023 > section, .text: 0x00000050-0x00012c3b > section, .init: 0x00012c3c-0c00012c63 > section.fini: 0x00012c64-0x00012c83 > ERROR: Failed to download ELF file. > > I-Side Memory Access Check Failed > Section, 0x00000050-0x00012c3b Not Accessible from Processor I-Side > Interface > > =3D=3D=3D=3D > > Had anyone had this issue before? Anyone have any idea what might be > causing it / how to solve it? > > Thanks in advance, > > Sean. Just a guess, but are you sure your .elf file isn't too big to fit in memory? I see: > Section, 0x00000050-0x00012c3b Not Accessible from Processor I-Side and: BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE =3D dlmb_cntlr PARAMETER HW_VER =3D 2.10.b PARAMETER C_BASEADDR =3D 0x00000000 PARAMETER C_HIGHADDR =3D 0x0000ffff BUS_INTERFACE SLMB =3D dlmb BUS_INTERFACE BRAM_PORT =3D dlmb_port END Which seems to imply that you have 64K of BRAM and a somewhat larger .elf file. Are you trying to load this into internal block RAM or do you have an external SDRAM memory? Regards, GaborArticle: 146997
On 4/8/2010 5:04 PM, Kappa wrote: > Hi, I have resolved my problem. > This code work very well : > secureasm It work very well until next time. Stop, in the name of your sanity, using std_logic_arith. Read, as a matter of some urgency, http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf You should never mix your arithmetic libraries!* numeric_std is all you need. Cheers, Syms. * http://www.youtube.com/watch?v=Qg77BCUi0pMArticle: 146998
Dear All, We are planning to design a board with four FPGAs to emulate X86 CPU. The FPGA=92s JTAG ports are serially chained together. My problem is that whether the Xilinx=92s ChipScope can support debugging multiple FPGAs via a single JTAG chain at the same time? So we can set different trigger conditions to different FPGA chips at the same time and watch the sampled data from ChipScope. Thanks in advance, Speed.Article: 146999
I am not sure about ChipScope (Pro) but Dialite from Temento can do this and can also handle mixed vendors. http://www.temento.com/index.php?rubrique=15 Do you really need 4 FPGAs? Hans www.ht-lab.com "Speed" <speedboy1211@gmail.com> wrote in message news:faa559c2-2ef8-440c-b9bc-3ccd212528fd@u31g2000yqb.googlegroups.com... Dear All, We are planning to design a board with four FPGAs to emulate X86 CPU. The FPGA’s JTAG ports are serially chained together. My problem is that whether the Xilinx’s ChipScope can support debugging multiple FPGAs via a single JTAG chain at the same time? So we can set different trigger conditions to different FPGA chips at the same time and watch the sampled data from ChipScope. Thanks in advance, Speed.
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