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Threads Starting Jul 2002
44782: 02/07/01: Alan McKitterick: re..filter design for fpga
44784: 02/07/01: Kai Eckert: Altera Archive
44785: 02/07/01: Holger Englert: Reconfiguring .SOF file
44845: 02/07/03: Ben Twijnstra: Re: Reconfiguring .SOF file
44786: 02/07/01: Minlin Fan: combine the Verilog code
44791: 02/07/01: John_H: Re: combine the Verilog code
44798: 02/07/01: Rick Filipkiewicz: Re: combine the Verilog code
44788: 02/07/01: steve synakowski: Can Coolrunner's be daisy chained?
44792: 02/07/01: Falk Brunner: Re: Can Coolrunner's be daisy chained?
44796: 02/07/01: steve synakowski: Re: Can Coolrunner's be daisy chained?
44800: 02/07/01: steve synakowski: Re: Can Coolrunner's be daisy chained?
44793: 02/07/01: rickman: Re: Can Coolrunner's be daisy chained?
44801: 02/07/01: Ray Andraka: Re: Can Coolrunner's be daisy chained?
44802: 02/07/01: Dan Kuechle: dammage to Virtex-E???
44803: 02/07/01: Austin Lesea: Re: No damage to Virtex-E from 2.5V vs 3.3 V IOB standard
44806: 02/07/01: Doug Wilson: Xilinx XAPP622: Info on ROUTE constraint?
44824: 02/07/02: Philip Freidin: Re: Xilinx XAPP622: Info on ROUTE constraint?
44808: 02/07/01: Search for knowledge: Converting Altera Block Ram to Xilinx Block Ram
44809: 02/07/02: Peter Alfke: Re: Converting Altera Block Ram to Xilinx Block Ram
44810: 02/07/02: Spam Hater: Re: Converting Altera Block Ram to Xilinx Block Ram
44811: 02/07/02: Ray Andraka: Re: Converting Altera Block Ram to Xilinx Block Ram
45054: 02/07/11: Guy Schlacter: Re: Converting Altera Block Ram to Xilinx Block Ram
44812: 02/07/02: eko_mies: VHDL (IP) to PC/LPT ?
44813: 02/07/02: Sandeep Unni: VHDL Compliation Problem in Synario
44832: 02/07/02: VhdlCohen: Re: VHDL Compliation Problem in Synario
44849: 02/07/02: Jay: Re: VHDL Compliation Problem in Synario
44817: 02/07/02: Arash Salarian: Power consumtion simulation for FPGA?
44819: 02/07/02: Arash Salarian: Re: Power consumtion simulation for FPGA?
44823: 02/07/02: Martin: Re: Power consumtion simulation for FPGA?
44826: 02/07/02: Ray Andraka: Re: Power consumtion simulation for FPGA?
44841: 02/07/02: Rick Filipkiewicz: Re: Power consumtion simulation for FPGA?
44842: 02/07/02: Ray Andraka: Re: Power consumtion simulation for FPGA?
44870: 02/07/03: Arash Salarian: Re: Power consumtion simulation for FPGA?
44872: 02/07/03: Austin Lesea: Re: Power consumtion simulation for FPGA?
44879: 02/07/03: Ray Andraka: Re: Power consumtion simulation for FPGA?
44820: 02/07/02: Thomas: Communication between FPGA and PC
44830: 02/07/02: Falk Brunner: Re: Communication between FPGA and PC
44866: 02/07/03: Thomas: Re: Communication between FPGA and PC
44953: 02/07/08: Anton Erasmus: Re: Communication between FPGA and PC
44956: 02/07/08: Rick Filipkiewicz: Re: Communication between FPGA and PC
45107: 02/07/12: Anton Erasmus: Re: Communication between FPGA and PC
45114: 02/07/12: Rick Filipkiewicz: Re: Communication between FPGA and PC
45202: 02/07/15: Steve Casselman: Re: Communication between FPGA and PC
44821: 02/07/02: Krzysztof Szczepanski: Configuring VIRTEX with init states of FF
44822: 02/07/02: Steve Joures: DC to DC converter at 1.5V
44851: 02/07/02: Tom Seim: Re: DC to DC converter at 1.5V
44943: 02/07/07: jakab tanko: Re: DC to DC converter at 1.5V
44825: 02/07/02: Rob Finch: Converting to Altera Quartus
44836: 02/07/02: Kevin Brace: Re: Converting to Altera Quartus
44844: 02/07/03: Ben Twijnstra: Re: Converting to Altera Quartus
44848: 02/07/02: Peter Alfke: Re: Converting to Altera Quartus
44856: 02/07/03: Kevin Brace: Re: Converting to Altera Quartus
44857: 02/07/03: Jim Granville: Re: Converting to Altera Quartus
44864: 02/07/03: Jim Granville: Re: Converting to Altera Quartus
44862: 02/07/03: Kevin Brace: Re: Converting to Altera Quartus
44850: 02/07/02: Jay: Re: Converting to Altera Quartus
44859: 02/07/03: Kevin Brace: Re: Converting to Altera Quartus
44867: 02/07/03: Ray Andraka: Re: Converting to Altera Quartus
44883: 02/07/03: Peter Alfke: Re: Converting to Altera Quartus
44927: 02/07/06: Kevin Brace: Re: Converting to Altera Quartus
44929: 02/07/06: Ray Andraka: Re: Converting to Altera Quartus
44930: 02/07/06: rickman: Re: Converting to Altera Quartus
44932: 02/07/06: Ray Andraka: Re: Converting to Altera Quartus
44937: 02/07/06: Kevin Brace: Re: Converting to Altera Quartus
44939: 02/07/07: Jim Granville: Re: Converting to Altera Quartus
44936: 02/07/06: Kevin Brace: Re: Converting to Altera Quartus
44938: 02/07/07: Ray Andraka: Re: Converting to Altera Quartus
44827: 02/07/02: oleg afanasjev: synthesis using FPGA Express from Aldec 4.2 fails
44828: 02/07/02: Zhijian Hu: Partners wanted for MP3 ASIC core
44829: 02/07/02: Bill: Virtex II - Assigning Pins before routing?
44831: 02/07/02: John_H: Re: Virtex II - Assigning Pins before routing?
44834: 02/07/02: Ray Andraka: Re: Virtex II - Assigning Pins before routing?
44835: 02/07/02: Peter Alfke: Re: Virtex II - Assigning Pins before routing?
44838: 02/07/02: Davis Moore: Re: Virtex II - Assigning Pins before routing?
44839: 02/07/02: Davis Moore: Re: Virtex II - Assigning Pins before routing?
44840: 02/07/02: Peter Alfke: Re: Virtex II - Assigning Pins before routing?
44833: 02/07/02: Weifeng Xu: Bitstream Verification (JBITS)
44846: 02/07/03: Neil Franklin: Re: Bitstream Verification (JBITS)
44871: 02/07/03: Weifeng Xu: Re: Bitstream Verification (JBITS)
44873: 02/07/03: Nicholas Weaver: Re: Bitstream Verification (JBITS)
44878: 02/07/03: Weifeng Xu: Re: Bitstream Verification (JBITS)
44881: 02/07/03: Nicholas Weaver: Re: Bitstream Verification (JBITS)
44880: 02/07/03: Neil Franklin: Re: Bitstream Verification (JBITS)
44843: 02/07/02: Salman Sheikh: altera 10K30A synthesis
44854: 02/07/02: Kevin Brace: Re: altera 10K30A synthesis
44847: 02/07/02: Arrigo Benedetti: Chameleon Systems
44852: 02/07/03: Nathan Baulch: Could someone please simplify Synplify for me...
44905: 02/07/05: Arash Salarian: Re: Could someone please simplify Synplify for me...
44860: 02/07/03: Jonathan Bromley: Re: DC to DC converter at 1.5V
44861: 02/07/03: Jonathan Bromley: Re: VHDL Compliation Problem in Synario
44863: 02/07/03: Ken Mac: Anyone use the full Aldec 5.1 flow?
44865: 02/07/03: Paul Baxter: Re: Anyone use the full Aldec 5.1 flow?
44907: 02/07/05: Kate Atkins: Re: Anyone use the full Aldec 5.1 flow?
44869: 02/07/03: Jonathan Bromley: Re: DC to DC converter at 1.5V
44874: 02/07/03: Josan Moreno: Modelsim 5.6a for Linux execution problem
44885: 02/07/04: Kai Harrekilde-Petersen: Re: Modelsim 5.6a for Linux execution problem
44876: 02/07/03: Radoslaw Mitura: Jtag extest
44968: 02/07/08: John Eaton: Re: Jtag extest
44877: 02/07/03: Uwe Bonnes: Xilinix Webpack ChipViewer very slow
44882: 02/07/03: Tang King: Who are making BGA and gasket ?
44884: 02/07/04: Bill: Virtex II - IO TILE, IOB PAD #4
44889: 02/07/04: Philip Freidin: Re: Virtex II - IO TILE, IOB PAD #4
44896: 02/07/04: Marc Randolph: Re: Virtex II - IO TILE, IOB PAD #4
44886: 02/07/04: jas: glitches in back annotation
44887: 02/07/04: John Williams: Fixed point arithmetic
44895: 02/07/05: Addie Tang: Re: Fixed point arithmetic
44888: 02/07/04: Heiko Kalte: Maximum frequency in Virtex and Virtex-E Devices
44892: 02/07/04: enterpoint: Re: Maximum frequency in Virtex and Virtex-E Devices
44893: 02/07/04: Ray Andraka: Re: Maximum frequency in Virtex and Virtex-E Devices
44915: 02/07/05: <hamish@cloud.net.au>: Re: Maximum frequency in Virtex and Virtex-E Devices
44917: 02/07/05: Ray Andraka: Re: Maximum frequency in Virtex and Virtex-E Devices
44890: 02/07/04: Steve Joures: Routing Virtex-II 256 pin BGA on 4 layers
44916: 02/07/05: Manfred Kraus: Re: Routing Virtex-II 256 pin BGA on 4 layers
44999: 02/07/09: emanuel stiebler: Re: Routing Virtex-II 256 pin BGA on 4 layers
44891: 02/07/04: =?iso-8859-1?Q?Pawe=B3?= J. Rajda: Spartan II configuration ...
44894: 02/07/04: Guerre: 3.3 volt tolerance in Virtex-II Pro?
44931: 02/07/06: Philip S.W.C Toms: Re: 3.3 volt tolerance in Virtex-II Pro?
44957: 02/07/08: Greg Deuerling: Re: 3.3 volt tolerance in Virtex-II Pro?
44958: 02/07/08: rickman: Re: 3.3 volt tolerance in Virtex-II Pro?
44964: 02/07/08: Stephan Neuhold: Re: 3.3 volt tolerance in Virtex-II Pro?
44899: 02/07/04: ben cohen: Lessons Learned -- Need your inputs
44928: 02/07/06: Clyde R. Shappee: Re: Lessons Learned -- Need your inputs
44934: 02/07/06: VhdlCohen: Re: Lessons Learned -- Need your inputs
44900: 02/07/04: <ted_jmt@zapta.com>: How to improve this VHDL code ?
44906: 02/07/05: Martin Thompson: Re: How to improve this VHDL code ?
44909: 02/07/05: Laurent Gauch: Re: How to improve this VHDL code ?
44901: 02/07/04: <ted_jmt@zapta.com>: Please ignore my previous postings
44902: 02/07/05: Ray Andraka: Re: Type conversion - adding integer to logic_vector
44904: 02/07/05: Martin Thompson: Re: Type conversion - adding integer to logic_vector
44914: 02/07/05: Ray Andraka: Re: Type conversion - adding integer to logic_vector
44948: 02/07/08: Martin Thompson: Re: Type conversion - adding integer to logic_vector
44903: 02/07/05: Allan Herriman: Re: Macro/Function in VHDL testbench ?
44908: 02/07/05: Laurent Gauch: Triscend: SDK CD-ROM : where ?
44924: 02/07/06: Janusz Raniszewski: Re: Triscend: SDK CD-ROM : where ?
44910: 02/07/05: Ryan: VHDL Simili INOUT Problem
44911: 02/07/05: lktan: choosing RC100 over RC1000?
44912: 02/07/05: Jonathan Bromley: Re: Fixed point arithmetic
44942: 02/07/07: Philippe: Re: Fixed point arithmetic
44945: 02/07/08: John Williams: Re: Fixed point arithmetic
44913: 02/07/05: JP Nicholls: Xilinx Spartan-E LVDS at 622Mbps?
44919: 02/07/05: Uwe Bonnes: Setting individual slewrate on Xilinx Coolrunner II
44922: 02/07/05: Mark Ng: Re: Setting individual slewrate on Xilinx Coolrunner II
44923: 02/07/05: cfk: N-bit, 2-input adder
44933: 02/07/06: Ken McElvain: Re: N-bit, 2-input adder
44925: 02/07/06: Philip Leong: VHDL/FPGA research position at CUHK
44926: 02/07/06: Terrence Mak: Problems on using JBits
44935: 02/07/06: Nicholas Weaver: Virtex manhattan distance delay model...
44940: 02/07/06: John Hovell: Newbie FPGA recommedation
44941: 02/07/07: Ray Andraka: Re: Newbie FPGA recommedation
44946: 02/07/08: Tony Burch: Re: Newbie FPGA recommedation
44947: 02/07/08: Thorsten Trenz: Re: Newbie FPGA recommedation
44962: 02/07/08: Manfred Kraus: Re: Newbie FPGA recommedation
44969: 02/07/08: Kevin Brace: Re: Newbie FPGA recommedation
44944: 02/07/07: Derrick Cheng: ModelSim License problem
44949: 02/07/08: Holger Veit: Re: ModelSim License problem
44960: 02/07/08: Benjamin Todd: Re: ModelSim License problem
44963: 02/07/08: Holger Kleinegraeber: Re: ModelSim License problem
45043: 02/07/10: Rob Finch: Re: ModelSim License problem
45080: 02/07/11: newman: Re: ModelSim License problem
44950: 02/07/08: Jonathan Bromley: Re: Fixed point arithmetic
44951: 02/07/08: Stefan Schulte: Xilinix or Altera - which dev-board?
44973: 02/07/08: Anna Acevedo: Re: Xilinix or Altera - which dev-board?
45003: 02/07/09: Al Williams: Re: Xilinix or Altera - which dev-board?
45012: 02/07/10: Ben Twijnstra: Re: Xilinix or Altera - which dev-board?
45030: 02/07/10: Stefan Schulte: Re: Xilinix or Altera - which dev-board?
45060: 02/07/11: Kevin Brace: Re: Xilinix or Altera - which dev-board?
44952: 02/07/08: Heiko Kalte: High Performance (partial) FPGA (Re-)Configuration
44954: 02/07/08: Laurent Gauch: Camera Link to Virtex-II ?
44955: 02/07/08: Kumar: problem while generating clk1x,clk2x,clk180 clocks from CLKDLL
44959: 02/07/08: Benjamin Todd: Re: problem while generating clk1x,clk2x,clk180 clocks from CLKDLL
44961: 02/07/08: Holger Kleinegraeber: Virtex reset signal internaly hold?
44984: 02/07/09: Ray Andraka: Re: Virtex reset signal internaly hold?
44965: 02/07/08: TED: Are these design guideline safe ?
44966: 02/07/08: John_H: Re: Are these design guideline safe ?
44974: 02/07/08: TED: Re: Are these design guideline safe ?
44977: 02/07/09: Jim Granville: Re: Are these design guideline safe ?
44989: 02/07/09: Rick Filipkiewicz: Re: Are these design guideline safe ?
44971: 02/07/08: Peter Alfke: Re: Are these design guideline safe ?
44970: 02/07/08: Helmut Sennewald: SpartanXL,2E: How many flipflops on one clock-net?
44978: 02/07/08: Peter Alfke: Re: SpartanXL,2E: How many flipflops on one clock-net?
44979: 02/07/09: Helmut Sennewald: Re: SpartanXL,2E: How many flipflops on one clock-net?
45256: 02/07/17: Helmut Sennewald: Re: SpartanXL,2E: How many flipflops on one clock-net?
44972: 02/07/08: Bruno Bohrer Cozer: Altera SOPC Connectors
44975: 02/07/08: Jim Raynor: loading Spartan 2E configuration
44976: 02/07/08: Philip Pemberton: Getting started with FPGAs
44982: 02/07/08: Mark: Re: Getting started with FPGAs
45020: 02/07/10: Philip Pemberton: Re: Getting started with FPGAs
45096: 02/07/12: Paul: Re: Getting started with FPGAs
45002: 02/07/09: Al Williams: Re: Getting started with FPGAs
45007: 02/07/09: Lorenzo Lutti: Re: Getting started with FPGAs
45017: 02/07/09: Al Williams: Re: Getting started with FPGAs
44980: 02/07/08: Jeremy Whatley: ISE 4.2i : Clock Buffer Disable
44981: 02/07/08: Duane Clark: Re: ISE 4.2i : Clock Buffer Disable
44985: 02/07/08: Kevin Brace: Re: ISE 4.2i : Clock Buffer Disable
44983: 02/07/08: <dano1@attglobal.net>: Virtex-II PRO Channel alignment not working?
45032: 02/07/10: Winnie Hsu: Re: [FUD msg] Virtex-II PRO Channel alignment not working?
44988: 02/07/08: John_H: Xilinx adder RLOCs
44990: 02/07/09: Russell: Re: Xilinx adder RLOCs
45011: 02/07/09: John_H: Re: Xilinx adder RLOCs
45014: 02/07/10: John_H: Re: Xilinx adder RLOCs
45047: 02/07/10: g_ping: Re: Xilinx adder RLOCs
44991: 02/07/09: =?iso-8859-1?Q?St=E9phane?= Guyetant: how to keep info. in RAM during reconfiguration?
45005: 02/07/09: rickman: Re: how to keep info. in RAM during reconfiguration?
45023: 02/07/10: Allan Herriman: Re: how to keep info. in RAM during reconfiguration?
45013: 02/07/09: Jeff Mock: Re: how to keep info. in RAM during reconfiguration?
45035: 02/07/10: Rick Filipkiewicz: Re: how to keep info. in RAM during reconfiguration?
45046: 02/07/10: Jeff Mock: Re: how to keep info. in RAM during reconfiguration?
44996: 02/07/09: Hakon Lislebo: DCM - LOCKED output stays high when it shouldn't?
44997: 02/07/09: Stephan Neuhold: Re: DCM - LOCKED output stays high when it shouldn't?
45001: 02/07/09: Austin Lesea: Re: DCM - LOCKED output stays high when it shouldn't?
45024: 02/07/10: Hakon Lislebo: Re: DCM - LOCKED output stays high when it shouldn't?
45033: 02/07/10: Austin Lesea: Re: DCM - LOCKED output stays high when it shouldn't?
44998: 02/07/09: Benoit: test sign
45000: 02/07/09: Mike Rosing: Advice on tools and question on Virtex2
45185: 02/07/15: Mike Rosing: Re: Advice on tools and question on Virtex2
45302: 02/07/18: Manfred Kraus: Re: Advice on tools and question on Virtex2
45004: 02/07/09: Antony: LUT and Xilinx Distributed SelectRam
45006: 02/07/09: John_H: Re: LUT and Xilinx Distributed SelectRam
45034: 02/07/10: Antony: Re: LUT and Xilinx Distributed SelectRam
45040: 02/07/10: John_H: Re: LUT and Xilinx Distributed SelectRam
45041: 02/07/10: Peter Alfke: Re: LUT and Xilinx Distributed SelectRam
45008: 02/07/09: M Schreiber: Bi-Directional Bus problem in Xilinx FPGA
45009: 02/07/09: Hari Devanath: Re: Bi-Directional Bus problem in Xilinx FPGA
45031: 02/07/10: Laurent Gauch: Re: Bi-Directional Bus problem in Xilinx FPGA
45025: 02/07/10: Laurent Gauch: Re: Bi-Directional Bus problem in Xilinx FPGA
45048: 02/07/10: M Schreiber: Re: Bi-Directional Bus problem in Xilinx FPGA
45059: 02/07/11: Kevin Brace: Re: Bi-Directional Bus problem in Xilinx FPGA
45010: 02/07/09: Kevin Brace: Re: EDIF and JHDL information
45015: 02/07/10: Guy Schlacter: anyone get email about www.cradle.com ???
45016: 02/07/10: John Williams: Re: anyone get email about www.cradle.com ???
45055: 02/07/11: Guy Schlacter: Re: anyone get email about www.cradle.com ???
45061: 02/07/11: Kevin Brace: Re: anyone get email about www.cradle.com ???
45414: 02/07/22: Guy: Re: anyone get email about www.cradle.com ???
45018: 02/07/10: Reala: 32 bit multiplier (1 cycle)
45019: 02/07/10: Peter Alfke: Re: 32 bit multiplier (1 cycle)
45021: 02/07/10: Reala: Re: 32 bit multiplier (1 cycle)
45026: 02/07/10: Ray Andraka: Re: 32 bit multiplier (1 cycle)
45045: 02/07/11: Reala: Re: 32 bit multiplier (1 cycle)
45022: 02/07/10: Anthony Ellis: XST and Bidirectional I/O ports
45037: 02/07/10: Kevin Brace: Re: XST and Bidirectional I/O ports
45178: 02/07/15: Anthony Ellis: Re: XST and Bidirectional I/O ports
45027: 02/07/10: BROTO Laurent: LogiCore and PLX
45100: 02/07/12: Laurent Gauch: Re: LogiCore and PLX
45162: 02/07/14: Assaf Sarfati: Re: LogiCore and PLX
45028: 02/07/10: Mike Rosing: Re: Security features
45102: 02/07/12: Austin Lesea: Re: Security features
45126: 02/07/13: Mike Rosing: Re: Security features
45029: 02/07/10: ssy: How to locate the combinational loop in RTL source
45051: 02/07/10: Jeff Mock: Re: How to locate the combinational loop in RTL source
45062: 02/07/11: ssy: Re: How to locate the combinational loop in RTL source
45052: 02/07/10: John_H: Re: How to locate the combinational loop in RTL source
45036: 02/07/10: Frank Zhifeng Yuan: DPLL
45039: 02/07/10: Ray Andraka: Re: DPLL
45042: 02/07/10: John_H: Re: DPLL
45038: 02/07/10: Daniel: FPGA/CPLD Decision help?
45044: 02/07/11: Jim Raynor: Re: FPGA/CPLD Decision help?
45050: 02/07/10: ZhengLin: Re: FPGA/CPLD Decision help?
45063: 02/07/11: ssy: Re: FPGA/CPLD Decision help?
45064: 02/07/11: Neil Stainton: Re: FPGA/CPLD Decision help?
45056: 02/07/11: John Williams: Re: anyone get email about www.cradle.com ???
45057: 02/07/10: Nagaraj: Read Delay
45058: 02/07/11: John Williams: Re: Read Delay
45065: 02/07/11: nitin: Dynamic Addition Subtraction
45067: 02/07/11: Ray Andraka: Re: Dynamic Addition Subtraction
45066: 02/07/11: Adel: What open core MAC to choose?
45068: 02/07/11: Jianyong Niu: Need a non-pipelined signed integer divider
45079: 02/07/11: Ray Andraka: Re: Need a non-pipelined signed integer divider
45076: 02/07/11: John_H: Re: Using DLL's for 90 Degree Phase Shift
45074: 02/07/11: n1089240: Using DLL's for 90 Degree Phase Shift
45075: 02/07/11: Tom D: Using an FPGA as an embedded system timing master
45077: 02/07/11: D Brown: Deterministic Output?
45078: 02/07/11: Alan Nishioka: Re: Deterministic Output?
45087: 02/07/12: Allan Herriman: Re: Deterministic Output?
45090: 02/07/12: Petter Gustad: Re: Deterministic Output?
45161: 02/07/14: Allan Herriman: Re: Deterministic Output?
45088: 02/07/12: Nicholas Weaver: Re: Deterministic Output?
45095: 02/07/12: Ray Andraka: Re: Deterministic Output?
45081: 02/07/11: Bill: Virtex II - What to do with unused banks?
45082: 02/07/11: Peter Alfke: Re: Virtex II - What to do with unused banks?
45083: 02/07/12: John_H: Xilinx RPMs before Virtex-II
45084: 02/07/12: res19j1c: FPGA CPU?
45085: 02/07/12: John Williams: Re: FPGA CPU?
45086: 02/07/12: Rob Finch: Re: FPGA CPU?
45093: 02/07/12: res19j1c: Re: FPGA CPU?
45105: 02/07/12: Muzaffer Kal: Re: FPGA CPU?
45104: 02/07/12: Goran Bilski: Re: FPGA CPU?
45106: 02/07/12: Nicholas Weaver: Re: FPGA CPU?
45108: 02/07/12: Helmut Sennewald: Re: FPGA CPU?
45109: 02/07/12: Nicholas Weaver: Re: FPGA CPU?
45115: 02/07/12: Rick Filipkiewicz: Re: FPGA CPU?
45117: 02/07/12: Goran Bilski: Re: FPGA CPU?
45129: 02/07/13: Javier =?iso-8859-1?Q?Fern=E1ndez?= Baldomero: Re: FPGA CPU?
45136: 02/07/13: ssy: Re: FPGA CPU?
45175: 02/07/15: Goran Bilski: Re: FPGA CPU?
45141: 02/07/13: Sebastian Gruber: Re: FPGA CPU?
45145: 02/07/13: res19j1c: Re: FPGA CPU?
45089: 02/07/12: Reala: How to develop a MCU?
45091: 02/07/12: Thomas Heller: Replacing a XC4006E
45092: 02/07/12: mike: HDL generate from handel-C can be accepted by synthesis tools?
45314: 02/07/18: Noel Klonsky: Re: HDL generate from handel-C can be accepted by synthesis tools?
45094: 02/07/12: yi don: some questions from a fpga newer
45330: 02/07/19: chris rutten: Re: some questions from a fpga newer
45097: 02/07/12: Paul: Security features
45101: 02/07/12: Austin Lesea: Re: Security features
45252: 02/07/17: Jay: Re: Security features
45098: 02/07/12: Hristo Stevic: 6 parallel inputs to Mux? How?
45181: 02/07/14: Jay: Re: 6 parallel inputs to Mux? How?
45240: 02/07/17: hristo: Re: 6 parallel inputs to Mux? How?
45242: 02/07/17: Ray Andraka: Re: 6 parallel inputs to Mux? How?
45099: 02/07/12: Bob W: Question: Xilinx schematic entry, constants, bit swapping
45103: 02/07/12: Dan Kuechle: Re: Question: Xilinx schematic entry, constants, bit swapping
45885: 02/08/09: =?ISO-8859-1?Q?Narc=EDs_Nadal?=: Re: Question: Xilinx schematic entry, constants, bit swapping
45110: 02/07/12: Randall Holman: PCMCIA host
45111: 02/07/12: Frank Zhifeng Yuan: Actel 3.3v to 5v
45112: 02/07/12: Peter Alfke: Re: Actel 3.3v to 5v
45113: 02/07/12: Johann Glaser: Accurate Oscillator
45116: 02/07/12: Peter Alfke: Re: Accurate Oscillator
45127: 02/07/13: Johann Glaser: Re: Accurate Oscillator
45118: 02/07/12: Ray Andraka: Re: Accurate Oscillator
45128: 02/07/13: Johann Glaser: Re: Accurate Oscillator
45131: 02/07/13: Ray Andraka: Re: Accurate Oscillator
45134: 02/07/13: Johann Glaser: Re: Accurate Oscillator
45137: 02/07/13: Helmut Sennewald: Re: Accurate Oscillator
45138: 02/07/13: Johann Glaser: Re: Accurate Oscillator
45139: 02/07/13: Paul Baxter: Re: Accurate Oscillator
45143: 02/07/13: Johann Glaser: Re: Accurate Oscillator
45160: 02/07/13: Daniel Lang: Re: Accurate Oscillator
45164: 02/07/14: Johann Glaser: Re: Accurate Oscillator
45130: 02/07/13: Noddy: Re: Accurate Oscillator
45149: 02/07/13: John_H: Re: Accurate Oscillator
45150: 02/07/13: Ray Andraka: Re: Accurate Oscillator
45151: 02/07/13: Johann Glaser: Re: Accurate Oscillator
45153: 02/07/13: Paul Baxter: Re: Accurate Oscillator
45163: 02/07/14: Johann Glaser: Re: Accurate Oscillator
45133: 02/07/13: Rene Tschaggelar: Re: Accurate Oscillator
45135: 02/07/13: Johann Glaser: Re: Accurate Oscillator
45119: 02/07/12: Mark Barr: Foundation 2.1i --- does it support vertexII?
45132: 02/07/13: S. Ramirez: Re: Foundation 2.1i --- does it support vertexII?
45140: 02/07/13: Ray Andraka: Re: Foundation 2.1i --- does it support vertexII?
45159: 02/07/14: S. Ramirez: Re: Foundation 2.1i --- does it support vertexII?
45173: 02/07/15: Ray Andraka: Re: Foundation 2.1i --- does it support vertexII?
45182: 02/07/15: Rick Filipkiewicz: Re: Foundation 2.1i --- does it support vertexII?
45189: 02/07/15: Ray Andraka: Re: Foundation 2.1i --- does it support vertexII?
45120: 02/07/12: Arrigo Benedetti: Webpack under Linux ?
45154: 02/07/13: Uwe Bonnes: Re: Webpack under Linux ?
45166: 02/07/14: Duane Clark: Re: Webpack under Linux ?
45171: 02/07/14: Uwe Bonnes: Re: Webpack under Linux ?
45211: 02/07/16: Troy Schultz: Re: Webpack under Linux ?
45121: 02/07/13: Loi Tran: 5V input to CLOCK on Xilinx Spartan 2
45122: 02/07/12: Peter Alfke: Re: 5V input to CLOCK on Xilinx Spartan 2
45123: 02/07/12: Peter Alfke: Re: 5V input to CLOCK on Xilinx Spartan 2
45124: 02/07/13: Loi Tran: Re: 5V input to CLOCK on Xilinx Spartan 2
45125: 02/07/13: Loi Tran: Re: 5V input to CLOCK on Xilinx Spartan 2
45142: 02/07/13: Steve T Shannon: serial configuration in parallel? Xilinx Spartan-II
45144: 02/07/13: Hal Murray: Re: serial configuration in parallel? Xilinx Spartan-II
45157: 02/07/14: Peter Alfke: Re: serial configuration in parallel? Xilinx Spartan-II
45146: 02/07/13: Steve Charlwood: What proportion of an FPGA's configuration data is used for routing?
45147: 02/07/13: Nicholas Weaver: Re: What proportion of an FPGA's configuration data is used for routing?
45152: 02/07/13: Steve Charlwood: Re: What proportion of an FPGA's configuration data is used for routing?
45155: 02/07/14: Peter Alfke: Re: What proportion of an FPGA's configuration data is used for routing?
45165: 02/07/14: Steve Charlwood: Re: What proportion of an FPGA's configuration data is used for routing?
45167: 02/07/14: Peter Alfke: Re: What proportion of an FPGA's configuration data is used for routing?
45174: 02/07/15: Ray Andraka: Re: What proportion of an FPGA's configuration data is used for routing?
45158: 02/07/14: John_H: Re: What proportion of an FPGA's configuration data is used for routing?
45148: 02/07/13: Mike Rosing: Re: How to add BUFG to an internal signal?
45168: 02/07/14: Mike Rosing: Re: How to add BUFG to an internal signal?
45184: 02/07/15: Mike Rosing: Re: How to add BUFG to an internal signal?
45264: 02/07/17: Duane Clark: Re: How to add BUFG to an internal signal?
45254: 02/07/17: Duane Clark: Re: How to add BUFG to an internal signal?
45169: 02/07/14: MICHAEL ALEX: EDIF netlist from XST
45170: 02/07/14: Uwe Bonnes: Re: EDIF netlist from XST
45176: 02/07/14: Kevin Brace: Re: EDIF netlist from XST
45925: 02/08/11: Juergen Otterbach: Re: EDIF netlist from XST
45931: 02/08/11: Hans-Jürgen Dorn: Re: EDIF netlist from XST
46056: 02/08/15: tom curran: Re: EDIF netlist from XST
45172: 02/07/14: Joe Lawrence: Sensitivity list (VHDL) & FPGA pin assignment
45177: 02/07/15: Muzaffer Kal: Re: Sensitivity list (VHDL) & FPGA pin assignment
45205: 02/07/15: Yury: Re: Sensitivity list (VHDL) & FPGA pin assignment
45180: 02/07/14: Jay: Re: Sensitivity list (VHDL) & FPGA pin assignment
45236: 02/07/17: Thomas Stanka: Re: Sensitivity list (VHDL) & FPGA pin assignment
45179: 02/07/15: Anthony Ellis: How to add BUFG to an internal signal?
45188: 02/07/15: Ray Andraka: Re: How to add BUFG to an internal signal?
45192: 02/07/15: Anthony Ellis: Re: How to add BUFG to an internal signal?
45207: 02/07/16: Kevin Brace: Re: How to add BUFG to an internal signal?
45183: 02/07/15: Rick Filipkiewicz: Virtex-2 configuration: Device check ?
45194: 02/07/15: Austin Lesea: Re: Virtex-2 configuration: Device check ?
45186: 02/07/15: Jon Nicoll: Xilinx (spartan 2) programming 'lore' (CLK timing etc) sought
45196: 02/07/15: Austin Lesea: Re: Xilinx (spartan 2) - SI even applies to the config pins
45255: 02/07/17: Jay: Re: Xilinx (spartan 2) - SI even applies to the config pins
45390: 02/07/22: jakab tanko: Re: Xilinx (spartan 2) - SI even applies to the config pins
45187: 02/07/15: paul hill: dsp v fpga
45257: 02/07/17: Jay: Re: dsp v fpga
45327: 02/07/19: Tina Falkenberg: Re: dsp v fpga
45351: 02/07/19: Ray Andraka: Re: dsp v fpga
45190: 02/07/15: Tom D: Spartan clock mirroring
45195: 02/07/15: Austin Lesea: Re: Spartan clock mirroring
45191: 02/07/15: =?iso-8859-1?q?St=E9phane_Mancini?=: SOPC builder
45193: 02/07/15: Wolfgang Loewer: Re: SOPC builder
45197: 02/07/15: Marcel: Which is best method for register with settable and clearable bits
45198: 02/07/15: Benjamin Todd: Re: Which is best method for register with settable and clearable bits
45201: 02/07/15: Peter Alfke: Re: Which is best method for register with settable and clearable bits
45199: 02/07/15: Jim Kearney: Re: Which is best method for register with settable and clearable bits
45200: 02/07/15: Bill: Virtex 2 (XC2V500) Engineering Sample Errata Sheet
45203: 02/07/15: rshaley: FS: XILINX xcs20xl-5pq208c 1550 pcs NEW
45204: 02/07/15: Joey Nelson: Design Techniques for Memory Mapped Registers.
45309: 02/07/18: John Ledford: Re: Design Techniques for Memory Mapped Registers.
45586: 02/07/27: Hal Murray: Re: Design Techniques for Memory Mapped Registers.
45206: 02/07/15: jetmarc: AT40K / FPSLIC - Place & Route tools (3rd party)?
45215: 02/07/16: Arash Salarian: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45217: 02/07/16: Ken McElvain: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45231: 02/07/17: Ray Andraka: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45228: 02/07/16: jetmarc: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45234: 02/07/17: Arash Salarian: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45243: 02/07/17: Ray Andraka: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45262: 02/07/17: Ken McElvain: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45266: 02/07/17: John_H: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45268: 02/07/17: John_H: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45275: 02/07/17: Ken McElvain: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45284: 02/07/18: Ray Andraka: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45303: 02/07/18: Ken McElvain: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45307: 02/07/18: Ray Andraka: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45379: 02/07/21: Ulf Samuelsson: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45392: 02/07/22: jetmarc: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45208: 02/07/16: Laurent Gauch: uCLinux on microblaze
45209: 02/07/16: Alexander Weiss: JTAG Analyzer with HP16510
45269: 02/07/17: u1061771156: Re: JTAG Analyzer with HP16510
45319: 02/07/18: Alan Gosselin: Re: JTAG Analyzer with HP16510
45210: 02/07/16: Jens Hildebrandt: Re: I want to buy 4 Xilinx FPGA
45220: 02/07/16: Erik: Re: I want to buy 4 Xilinx FPGA
45224: 02/07/16: Kevin Brace: Re: I want to buy 4 Xilinx FPGA
45260: 02/07/17: Erik: Re: I want to buy 4 Xilinx FPGA
45263: 02/07/17: Kevin Brace: Re: I want to buy 4 Xilinx FPGA
45288: 02/07/18: Deli Geng (David): Re: I want to buy 4 Xilinx FPGA
45294: 02/07/19: Bevan Weiss: Re: I want to buy 4 Xilinx FPGA
45299: 02/07/18: Keith R. Williams: Re: I want to buy 4 Xilinx FPGA
45320: 02/07/18: Erik: Re: I want to buy 4 Xilinx FPGA
45318: 02/07/18: Erik: Re: I want to buy 4 Xilinx FPGA
45348: 02/07/19: Kevin Brace: Re: I want to buy 4 Xilinx FPGA
45377: 02/07/21: Erik: Re: I want to buy 4 Xilinx FPGA
45471: 02/07/24: Kevin Brace: Re: I want to buy 4 Xilinx FPGA
45703: 02/08/01: Erik: Re: I want to bay 4 Xilinx FPGA
45861: 02/08/07: Kevin Brace: Re: I want to bay 4 Xilinx FPGA
46296: 02/08/24: <vikinger@uni.de>: Re: I want to bay 4 Xilinx FPGA
45570: 02/07/27: Hal Murray: Re: I want to buy 4 Xilinx FPGA
45585: 02/07/27: Erik: Re: I want to buy 4 Xilinx FPGA
45235: 02/07/16: Thomas Stanka: Re: I want to buy 4 Xilinx FPGA
45212: 02/07/16: Utku Ozcan: Re: Spartan PROMs...
45213: 02/07/16: Arash Salarian: problem porting sync write, async read RAM to Xilinx...
45214: 02/07/16: Arash Salarian: Re: problem porting sync write, async read RAM to Xilinx...
45216: 02/07/16: Benjamin Todd: Re: problem porting sync write, async read RAM to Xilinx...
45218: 02/07/16: Peter Alfke: Re: problem porting sync write, async read RAM to Xilinx...
45233: 02/07/17: Arash Salarian: Re: problem porting sync write, async read RAM to Xilinx...
45244: 02/07/17: Ray Andraka: Re: problem porting sync write, async read RAM to Xilinx...
45251: 02/07/17: Jay: Re: problem porting sync write, async read RAM to Xilinx...
45272: 02/07/17: Rick Filipkiewicz: Re: problem porting sync write, async read RAM to Xilinx...
45277: 02/07/17: Ken McElvain: Re: problem porting sync write, async read RAM to Xilinx...
45279: 02/07/17: John_H: Re: problem porting sync write, async read RAM to Xilinx...
45219: 02/07/16: Jay: Re: I want to buy 4 Xilinx FPGA
45261: 02/07/17: Erik: Re: I want to buy 4 Xilinx FPGA
45221: 02/07/16: Randal Kuramoto: Re: Spartan PROMs...
45222: 02/07/16: Pootle (AT DOT DOT): LVDS interface cable recommendation sought
45223: 02/07/16: Uwe Bonnes: Re: LVDS interface cable recommendation sought
45227: 02/07/17: Bill Sloman: Re: LVDS interface cable recommendation sought
45229: 02/07/17: Bob: Re: LVDS interface cable recommendation sought
45232: 02/07/16: John Larkin: Re: LVDS interface cable recommendation sought
45278: 02/07/17: Joey Nelson: Re: LVDS interface cable recommendation sought
45246: 02/07/17: JP Nicholls: Re: LVDS interface cable recommendation sought
45248: 02/07/17: John_H: Re: LVDS interface cable recommendation sought
45292: 02/07/18: Bill Sloman: Re: LVDS interface cable recommendation sought
45517: 02/07/25: JP Nicholls: Re: LVDS interface cable recommendation sought
45522: 02/07/25: JP Nicholls: Re: LVDS interface cable recommendation sought
45529: 02/07/25: John_H: Re: LVDS interface cable recommendation sought
45540: 02/07/25: Bill Sloman: Re: LVDS interface cable recommendation sought
45225: 02/07/16: weniyaa: Active HDL 4.2SE library update
45226: 02/07/16: Dick Ginther: XC2V1500 & XC2V2000 availabilty
45329: 02/07/19: chris rutten: Re: XC2V1500 & XC2V2000 availabilty
45230: 02/07/17: Reala: I would like to know how to develop a MCU.
45241: 02/07/17: Laurent Gauch: Re: I would like to know how to develop a MCU.
45282: 02/07/18: Reala: Re: I would like to know how to develop a MCU.
45247: 02/07/17: emanuel stiebler: Re: I would like to know how to develop a MCU.
45281: 02/07/18: Reala: Re: I would like to know how to develop a MCU.
45387: 02/07/22: Benjamin Todd: Re: I would like to know how to develop a MCU.
45237: 02/07/17: John Hovell: Simulating Xilinx Block RAM with ModelSim
45271: 02/07/17: John Hovell: Re: Simulating Xilinx Block RAM with ModelSim
45274: 02/07/17: Jeff Cunningham: Re: Simulating Xilinx Block RAM with ModelSim
45238: 02/07/17: Jonathan Bromley: Re: Which is best method for register with settable and clearable bits
45239: 02/07/17: Jonathan Bromley: Re: Design Techniques for Memory Mapped Registers.
45258: 02/07/17: Joey Nelson: Re: Design Techniques for Memory Mapped Registers.
45249: 02/07/17: Jonathan Bromley: Re: LVDS interface cable recommendation sought
45267: 02/07/17: Bill Sloman: Re: LVDS interface cable recommendation sought
45250: 02/07/17: venkat: Commercial FPGA Architectures
45253: 02/07/17: Steve Charlwood: Re: Commercial FPGA Architectures
45276: 02/07/17: Jeff Cunningham: Re: Commercial FPGA Architectures
45280: 02/07/17: Peter Alfke: Re: Commercial FPGA Architectures
45259: 02/07/17: craig mcclure: ALTERA PLMG5192 programming adapter
45265: 02/07/17: Theron Hicks: problem with configuration of spartan2e
45270: 02/07/17: Peter Alfke: Re: problem with configuration of spartan2e
45273: 02/07/17: Theron Hicks: Re: problem with configuration of spartan2e
45283: 02/07/18: Russell: Anyone tried altera floorplanner yet?
45285: 02/07/18: BROTO Laurent: Problem with OpenCore PCI IP Core
45287: 02/07/18: Nicolas Matringe: Re: Problem with OpenCore PCI IP Core
45289: 02/07/18: BROTO Laurent: Re: Problem with OpenCore PCI IP Core
45301: 02/07/18: Srinivasan Venkataramanan: Re: Problem with OpenCore PCI IP Core
45313: 02/07/18: Kevin Brace: Re: Problem with OpenCore PCI IP Core
45363: 02/07/20: cfk: Re: Problem with OpenCore PCI IP Core
45369: 02/07/20: rickman: Re: Problem with OpenCore PCI IP Core
45424: 02/07/23: BROTO Laurent: Re: Problem with OpenCore PCI IP Core
45286: 02/07/18: Noddy: Good VHDL Book...
45297: 02/07/18: Srinivasan Venkataramanan: Re: Good VHDL Book...
45291: 02/07/18: Shareef Jalloq: Xillinx functional netlist simulation
45293: 02/07/18: Ray Andraka: Re: Xilinx XC9500/XC9500XL versus XC5200 Questions
45295: 02/07/18: lktan: Mapping error
45296: 02/07/18: Lasse Langwadt Christensen: trick to using bufgce?
45298: 02/07/18: =?iso-8859-1?q?St=E9phane_Mancini?=: NIOS programming related to ISR
45300: 02/07/18: Wolfgang Loewer: Re: NIOS programming related to ISR
45304: 02/07/18: Børge Strand: Getting started with WebPACK and Verilog
45311: 02/07/18: Kevin Brace: Re: Getting started with WebPACK and Verilog
45326: 02/07/19: Noddy: Re: Getting started with WebPACK and Verilog
45334: 02/07/19: Al Williams: Re: Getting started with WebPACK and Verilog
45305: 02/07/18: Klaus Vestergaard Kragelund: Xilinx XC9500/XC9500XL versus XC5200 Questions
45306: 02/07/18: Shareef Jalloq: Re: AMBA specyfication
45308: 02/07/18: Yanick: Virtex-II variable vs fixed DCM phase-shift ?
45312: 02/07/18: Bryan: Re: Virtex-II variable vs fixed DCM phase-shift ?
45315: 02/07/18: Austin Lesea: Re: Virtex-II variable vs fixed DCM phase-shift ?
45324: 02/07/18: Yanick: Re: Virtex-II variable vs fixed DCM phase-shift ?
45338: 02/07/19: Rod Barman: Re: Virtex-II variable vs fixed DCM phase-shift ?
45350: 02/07/19: Austin Lesea: Re: Virtex-II variable vs fixed DCM phase-shift ?
45354: 02/07/20: Bill: Re: Virtex-II variable vs fixed DCM phase-shift ?
45310: 02/07/18: Kevin Neilson: V2 Pipelined Embedded Mulitplier PAR issues
46406: 02/08/28: Jason Phillips: Re: V2 Pipelined Embedded Mulitplier PAR issues
46578: 02/09/04: Ray Andraka: Re: V2 Pipelined Embedded Mulitplier PAR issues
45321: 02/07/18: SneeR: AMBA specyfication
45322: 02/07/18: Martin Guibert: How's the FPGA design job market near you??
45323: 02/07/19: bbdjsk: Re: How's the FPGA design job market near you??
45325: 02/07/19: Spam Hater: Re: How's the FPGA design job market near you??
45331: 02/07/19: Martin Guibert: Re: How's the FPGA design job market near you??
45356: 02/07/20: Spam Hater: Re: How's the FPGA design job market near you??
45359: 02/07/20: Kang Liat Chuan: Re: How's the FPGA design job market near you??
45448: 02/07/24: B__ S_______: Re: How's the FPGA design job market near you??
45464: 02/07/24: Ray Andraka: Re: How's the FPGA design job market near you??
45328: 02/07/19: Johan Ditmar: black box components with parameters in Synplify
45341: 02/07/19: Ray Andraka: Re: black box components with parameters in Synplify
45386: 02/07/22: Johan Ditmar: Re: black box components with parameters in Synplify
45397: 02/07/22: Ken McElvain: Re: black box components with parameters in Synplify
45412: 02/07/23: Ken McElvain: Re: black box components with parameters in Synplify
45413: 02/07/23: Ray Andraka: Re: black box components with parameters in Synplify
45415: 02/07/23: Ken McElvain: Re: black box components with parameters in Synplify
45332: 02/07/19: Dan: Theft protection of FPGA configuration data
45336: 02/07/19: Nicholas Weaver: Re: Theft protection of FPGA configuration data
45342: 02/07/19: Ray Andraka: Re: Theft protection of FPGA configuration data
45343: 02/07/19: Kevin Brace: Re: Theft protection of FPGA configuration data
45346: 02/07/19: Timothy R. Sloper: Re: Theft protection of FPGA configuration data
45347: 02/07/19: Kevin Brace: Re: Theft protection of FPGA configuration data
45349: 02/07/19: Ray Andraka: Re: Theft protection of FPGA configuration data
45333: 02/07/19: Juha Pajunen: Making my own software
45344: 02/07/19: Kevin Brace: Re: Making my own software
45385: 02/07/22: Wolfgang Loewer: Re: Making my own software
45575: 02/07/27: Martin Schoeberl: Re: Making my own software
45335: 02/07/19: Tom Seim: Counter Metrics
45337: 02/07/19: Peter Alfke: Re: Counter Metrics
45339: 02/07/19: Ken Mac: what FIR filter coefficient bit widths do you use?
45391: 02/07/22: Ken Mac: Re: what FIR filter coefficient bit widths do you use?
45340: 02/07/19: Jason White: fpga or cpld?
45345: 02/07/19: Thomas Heller: PCI FPGA prototype board with lots of SDRAM?
45352: 02/07/19: Quiet Desperation: FPGA Compiler II, Windows Version 3.7.1
45353: 02/07/19: ben cohen: spiral / waterfall /watersluice : Which are your methods?
45357: 02/07/19: John Larkin: Re: spiral / waterfall /watersluice : Which are your methods?
45361: 02/07/20: Martin Guibert: Re: spiral / waterfall /watersluice : Which are your methods?
45439: 02/07/23: Ray Andraka: Re: spiral / waterfall /watersluice : Which are your methods?
45365: 02/07/20: ben cohen: Re: spiral / waterfall /watersluice : Which are your methods?
45372: 02/07/20: John Larkin: Re: spiral / waterfall /watersluice : Which are your methods?
45364: 02/07/20: Phil Hays: Re: spiral / waterfall /watersluice : Which are your methods?
45366: 02/07/20: John Larkin: Re: spiral / waterfall /watersluice : Which are your methods?
45367: 02/07/20: rickman: Re: spiral / waterfall /watersluice : Which are your methods?
45371: 02/07/20: John Larkin: Re: spiral / waterfall /watersluice : Which are your methods?
45375: 02/07/20: Nicholas Weaver: Re: spiral / waterfall /watersluice : Which are your methods?
45378: 02/07/21: rickman: Re: spiral / waterfall /watersluice : Which are your methods?
45380: 02/07/21: Nicholas Weaver: Re: spiral / waterfall /watersluice : Which are your methods?
45368: 02/07/20: Stefan Doll: Re: spiral / waterfall /watersluice : Which are your methods?
45410: 02/07/22: Domagoj: Re: spiral / waterfall /watersluice : Which are your methods?
45428: 02/07/23: Abernathey Family: Re: spiral / waterfall /watersluice : Which are your methods?
45441: 02/07/23: Domagoj: Re: spiral / waterfall /watersluice : Which are your methods?
45716: 02/08/02: Stan: Re: spiral / waterfall /watersluice : Which are your methods?
45729: 02/08/02: ehml: Re: spiral / waterfall /watersluice : Which are your methods?
45744: 02/08/03: Domagoj Babic: Re: spiral / waterfall /watersluice : Which are your methods?
45442: 02/07/23: ben cohen: Re: spiral / waterfall /watersluice : Which are your methods?
45355: 02/07/20: todd: WTB: Old xilinx development system or dongle (circa 1993-7)
45358: 02/07/19: Mike Rosing: Re: cpld programming
45360: 02/07/20: Deli Geng (David): Spartan II JTAG connection with other devices
45373: 02/07/20: Walter Dvorak: Re: Spartan II JTAG connection with other devices
45381: 02/07/21: Ray Andraka: Re: Spartan II JTAG connection with other devices
45389: 02/07/22: Petter Gustad: Re: Spartan II JTAG connection with other devices
45362: 02/07/20: HUA QIAN: How could I generated an efficient 16*16 multiplier in Vertex-II?
45376: 02/07/21: Niv: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
45395: 02/07/22: Jakka Bhasker Reddy: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
45403: 02/07/22: Jay: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
45418: 02/07/23: Kevin Neilson: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
45429: 02/07/23: Ray Andraka: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
45430: 02/07/23: Ray Andraka: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
45370: 02/07/20: hull: CoreGen question of the new FFT core
45489: 02/07/24: Kevin Brace: Re: CoreGen question of the new FFT core
45374: 02/07/20: <=?ISO-8859-1?Q?Antonio_Mart=EDnez_=C1lvarez?=>: Do you know a parallel algorithym for 2D convolution
45400: 02/07/22: Niall Battson: Re: Do you know a parallel algorithym for 2D convolution
45443: 02/07/24: John Williams: Re: Do you know a parallel algorithym for 2D convolution
45382: 02/07/22: Jim Granville: Re: TMS 1000
45383: 02/07/21: Jim McGinnis: Re: TMS 1000
45401: 02/07/22: Spehro Pefhany: Re: TMS 1000
45547: 02/07/25: Eric Smith: Re: TMS 1000
45402: 02/07/22: Everett M. Greene: Re: TMS 1000
45569: 02/07/27: Hal Murray: Re: TMS 1000
45384: 02/07/22: Jason Crawford: Clock-gating in Virtex-E parts
45394: 02/07/22: Ken McElvain: Re: Clock-gating in Virtex-E parts
45404: 02/07/22: Kevin Neilson: Re: Clock-gating in Virtex-E parts
45421: 02/07/23: Lasse Langwadt Christensen: Re: Clock-gating in Virtex-E parts
45436: 02/07/23: John Adair: Re: Clock-gating in Virtex-E parts
45463: 02/07/24: Edward Moore: Re: Clock-gating in Virtex-E parts
45484: 02/07/24: Lasse Langwadt Christensen: Re: Clock-gating in Virtex-E parts
45388: 02/07/22: Børge Strand: Verilog newbie question
45405: 02/07/22: Jay: Re: Verilog newbie question
45393: 02/07/22: jetmarc: Delays in Leonardo
45396: 02/07/22: Laurent Gauch: Re: Delays in Leonardo
45406: 02/07/22: Ken Schmidt: Xilinx ISE 4.2i Is A Step Backwards! Beware!!!
45435: 02/07/23: <hamish@cloud.net.au>: Re: Xilinx ISE 4.2i Is A Step Backwards! Beware!!!
45545: 02/07/25: Jeff Cunningham: Re: Xilinx ISE 4.2i Is A Step Backwards! Beware!!!
45549: 02/07/25: Kevin Brace: Re: Xilinx ISE 4.2i Is A Step Backwards! Beware!!!
45407: 02/07/22: D Brown: Xilinx NGDBuild -sd option in Project Navigator?
45466: 02/07/24: D Brown: Re: Xilinx NGDBuild -sd option in Project Navigator?
45408: 02/07/22: Buddy Smith: Re: VHDL xor address decode implementation in Altera
45409: 02/07/22: Autofuzz: Cheap licenses..
45411: 02/07/22: Ray Andraka: Re: Cheap licenses..
45416: 02/07/23: Reala: Translate the design from FPGA to Custom IC
45417: 02/07/23: Spam Hater: Re: Translate the design from FPGA to Custom IC
45423: 02/07/23: Reala: Re: Translate the design from FPGA to Custom IC
45432: 02/07/23: Ray Andraka: Re: Translate the design from FPGA to Custom IC
45434: 02/07/23: Børge Strand: Re: Translate the design from FPGA to Custom IC
45450: 02/07/24: B__ S_______: Re: Translate the design from FPGA to Custom IC
45455: 02/07/24: Reala: Re: Translate the design from FPGA to Custom IC
45510: 02/07/25: no_one: Re: Translate the design from FPGA to Custom IC
45515: 02/07/25: Reala: Re: Translate the design from FPGA to Custom IC
45591: 02/07/28: dudu: Re: Translate the design from FPGA to Custom IC
45717: 02/08/02: Stan: Re: Translate the design from FPGA to Custom IC
45793: 02/08/06: KVLKCL: Re: Translate the design from FPGA to Custom IC
45482: 02/07/24: Kevin Brace: Re: Translate the design from FPGA to Custom IC
45505: 02/07/25: Reala: Re: Translate the design from FPGA to Custom IC
45419: 02/07/23: Reala: 16 X 16 multplier
45431: 02/07/23: Ray Andraka: Re: 16 X 16 multplier
45420: 02/07/22: suchitra: cpld programming
45426: 02/07/23: Uwe Bonnes: Re: xilinx v ti
45437: 02/07/23: John_H: Re: xilinx v ti
45438: 02/07/23: Jerry Avins: Re: xilinx v ti
45427: 02/07/23: Ray Andraka: Re: xilinx v ti
45433: 02/07/23: Børge Strand: Editing constraints in WebPack
45461: 02/07/24: Walter Dvorak: Re: Editing constraints in WebPack
45485: 02/07/24: Kevin Brace: Re: Editing constraints in WebPack
45440: 02/07/23: Ray Andraka: RLOC Origin problems in ISE4.2sp3?
45459: 02/07/24: Stephan Neuhold: Re: RLOC Origin problems in ISE4.2sp3?
45465: 02/07/24: Ray Andraka: Re: RLOC Origin problems in ISE4.2sp3?
45535: 02/07/25: Bret Wade: Re: RLOC Origin problems in ISE4.2sp3?
45543: 02/07/26: Ray Andraka: Re: RLOC Origin problems in ISE4.2sp3?
45564: 02/07/26: Bret Wade: Re: RLOC Origin problems in ISE4.2sp3?
45444: 02/07/23: Doug Wilson: Xilinx DCMs, RST, and phase coherence
45562: 02/07/26: Marc Randolph: Re: Xilinx DCMs, RST, and phase coherence
45445: 02/07/24: Kevin Neilson: Re: delay pipes in verilog for spartan IIe?
45446: 02/07/24: John_H: Re: delay pipes in verilog for spartan IIe?
45451: 02/07/24: Kevin Neilson: Re: delay pipes in verilog for spartan IIe?
45467: 02/07/24: John_H: Re: delay pipes in verilog for spartan IIe?
45473: 02/07/24: Kevin Neilson: Re: delay pipes in verilog for spartan IIe?
45453: 02/07/23: John Hovell: Re: delay pipes in verilog for spartan IIe?
45468: 02/07/24: John_H: Re: delay pipes in verilog for spartan IIe?
45472: 02/07/24: Ray Andraka: Re: delay pipes in verilog for spartan IIe?
45502: 02/07/24: rickman: Re: delay pipes in verilog for spartan IIe?
45521: 02/07/25: Ray Andraka: Re: delay pipes in verilog for spartan IIe?
45447: 02/07/23: Sniper Daryl: How to implement efficient wide word comparator?
45452: 02/07/23: John_H: Re: How to implement efficient wide word comparator?
45528: 02/07/25: John_H: More: How to implement efficient wide word comparator?
45597: 02/07/29: Daryl: Re: How to implement efficient wide word comparator?
45454: 02/07/24: Giuseppe³: Re: How to implement efficient wide word comparator?
45516: 02/07/25: Børge Strand: Re: How to implement efficient wide word comparator?
45520: 02/07/25: Ray Andraka: Re: How to implement efficient wide word comparator?
45449: 02/07/24: Jeff Reeve: 32-bit PCI Target core
45458: 02/07/24: BROTO Laurent: Re: 32-bit PCI Target core
45474: 02/07/24: Kevin Brace: Re: 32-bit PCI Target core
45581: 02/07/27: cfk: Re: 32-bit PCI Target core
48507: 02/10/18: huijun xie: Re: 32-bit PCI Target core
48509: 02/10/18: huijun xie: Re: 32-bit PCI Target core
48552: 02/10/20: Spam Hater: Re: 32-bit PCI Target core
48554: 02/10/20: Kevin Brace: Re: 32-bit PCI Target core
48623: 02/10/22: Spam Hater: Re: 32-bit PCI Target core
45456: 02/07/24: Michael Cozza: Field Programmable SoC's
45460: 02/07/24: Uwe Bonnes: Re: Field Programmable SoC's
45462: 02/07/24: Jim Granville: Re: Field Programmable SoC's
45457: 02/07/23: jaideep: Field Programmable SoC's
45469: 02/07/24: Prashant: FPGA prototyping boards
45476: 02/07/24: Kevin Brace: Re: FPGA prototyping boards
45470: 02/07/24: Kaplan: Wind River Diab Xilinx Edition
45500: 02/07/24: Winnie Hsu: Re: Wind River Diab Xilinx Edition
45538: 02/07/25: Kaplan: Re: Wind River Diab Xilinx Edition
45539: 02/07/25: Austin Lesea: Re: Wind River Diab Xilinx Edition
45475: 02/07/24: D Brown: Gatelevel Simulation of Xilinx Block RAM
45477: 02/07/24: Uwe Bonnes: Re: 8bit Magnitude Comparator
45507: 02/07/25: Jim Granville: Re: 8bit Magnitude Comparator
45509: 02/07/24: Klaus Vestergaard Kragelund: Re: 8bit Magnitude Comparator
45478: 02/07/24: John_H: Re: 8bit Magnitude Comparator
45493: 02/07/24: Uwe Bonnes: Re: 8bit Magnitude Comparator
45497: 02/07/24: Uwe Bonnes: Re: 8bit Magnitude Comparator
45503: 02/07/24: rickman: Re: 8bit Magnitude Comparator
45494: 02/07/24: John_H: Re: 8bit Magnitude Comparator
45511: 02/07/25: Klaus Vestergaard Kragelund: Re: 8bit Magnitude Comparator
45508: 02/07/24: Klaus Vestergaard Kragelund: Re: 8bit Magnitude Comparator
45488: 02/07/24: Pascal Delouche: Re: Power-Up sequencing problem with Altera Apex20KE
45490: 02/07/24: Jim Raynor: vhdl dll question....help please
45492: 02/07/24: Duane Clark: Re: vhdl dll question....help please
45499: 02/07/24: Jim Raynor: XST vs FPGA Express???
45514: 02/07/25: Martin: Re: XST vs FPGA Express???
45501: 02/07/25: Peter Boot: FPGA expert needed
45567: 02/07/27: Ray Andraka: Re: FPGA expert needed
45504: 02/07/24: Klaus Vestergaard Kragelund: 8bit Magnitude Comparator
45506: 02/07/25: POK: Where can get the CISC core(8-bit) for Verilog??
45512: 02/07/25: Colin Marquardt: Re: Another way to simulate
45513: 02/07/25: Jim Granville: Re: Another way to simulate
45518: 02/07/25: Bruderer: LVDS on virtex-II with leonardo
45519: 02/07/25: Anjan: hold time
45527: 02/07/25: John_H: Re: hold time
45530: 02/07/25: Ray Andraka: Re: hold time
45534: 02/07/25: John_H: Re: hold time
45548: 02/07/25: Kevin Brace: Re: hold time
45571: 02/07/26: Anjan: Re: hold time
45523: 02/07/25: Børge Strand: Is the WebPack Constraints Editor evil?
45524: 02/07/25: Børge Strand: Re: Is the WebPack Constraints Editor evil?
45525: 02/07/25: Troy Schultz: Re: Is the WebPack Constraints Editor evil?
45531: 02/07/25: Børge Strand: Re: Is the WebPack Constraints Editor evil?
45537: 02/07/25: Speedy Zero Two: Re: Is the WebPack Constraints Editor evil?
45663: 02/07/31: Børge Strand: Re: Is the WebPack Constraints Editor evil?
45526: 02/07/25: Ryan: Specifying memory during synthesis
45532: 02/07/25: BROTO Laurent: Problem with mapping
45551: 02/07/25: Anjan: Re: Problem with mapping
45552: 02/07/26: Kevin Brace: Re: Problem with mapping
45553: 02/07/26: Kevin Brace: Re: Problem with mapping
45554: 02/07/26: BROTO Laurent: Re: Problem with mapping
45566: 02/07/26: Kevin Brace: Re: Problem with mapping
45582: 02/07/27: cfk: Re: Problem with mapping
45555: 02/07/26: Benjamin Todd: Re: Problem with mapping
45533: 02/07/25: Dmitri Katchalov: ALU in VHDL and a bunch of questions
45536: 02/07/25: Goran Bilski: Re: ALU in VHDL and a bunch of questions
45565: 02/07/26: Ray Andraka: Re: ALU in VHDL and a bunch of questions
45556: 02/07/26: Renaud Pacalet: Re: ALU in VHDL and a bunch of questions
45557: 02/07/26: Adrian Bica: Re: ALU in VHDL and a bunch of questions
45577: 02/07/27: MikeJ: Re: ALU in VHDL and a bunch of questions
45578: 02/07/27: Dmitri Katchalov: Re: ALU in VHDL and a bunch of questions
45579: 02/07/27: rickman: Re: ALU in VHDL and a bunch of questions
45583: 02/07/27: Ray Andraka: Re: ALU in VHDL and a bunch of questions
45588: 02/07/27: Eric Smith: Re: ALU in VHDL and a bunch of questions
45593: 02/07/28: Ray Andraka: Re: ALU in VHDL and a bunch of questions
45599: 02/07/29: Dmitri Katchalov: Re: ALU in VHDL and a bunch of questions
45609: 02/07/29: Ray Andraka: Re: ALU in VHDL and a bunch of questions
45622: 02/07/29: MikeJ: Re: ALU in VHDL and a bunch of questions
45626: 02/07/30: Ray Andraka: Re: ALU in VHDL and a bunch of questions
45541: 02/07/25: Prashant: logic elements v/s logic cells
45542: 02/07/25: Austin Lesea: Re: logic elements v/s logic cells
45544: 02/07/26: Ray Andraka: Re: logic elements v/s logic cells
45561: 02/07/26: Prashant: Re: logic elements v/s logic cells
45546: 02/07/25: Kevin Brace: Re: logic elements v/s logic cells
45559: 02/07/26: John_H: Re: logic elements v/s logic cells
45560: 02/07/26: rickman: Re: logic elements v/s logic cells
45563: 02/07/26: John_H: Re: logic elements v/s logic cells
45576: 02/07/27: rickman: Re: logic elements v/s logic cells
45584: 02/07/27: John_H: Re: logic elements v/s logic cells
45623: 02/07/29: MikeJ: Re: logic elements v/s logic cells
45627: 02/07/30: Ray Andraka: Re: logic elements v/s logic cells
45629: 02/07/30: Nicholas C. Weaver: Re: logic elements v/s logic cells
45550: 02/07/25: Leon Qin: Can Synplify7.1 run well on RedHat 7.2?
45558: 02/07/26: Dan Fabrizio: Announce: TimingAnalyzer Program Update
45572: 02/07/26: suchitra: can 555 be used as clock input to cplds
45573: 02/07/27: Falk Brunner: Re: can 555 be used as clock input to cplds
45580: 02/07/27: Leon Heller: Re: can 555 be used as clock input to cplds
45574: 02/07/27: Martin Schoeberl: Re: can 555 be used as clock input to cplds
45587: 02/07/28: Jim Granville: Re: can 555 be used as clock input to cplds
45664: 02/07/31: Børge Strand: Re: can 555 be used as clock input to cplds
45589: 02/07/27: ndesi: Programming FLASH with Xilinx Parallel Cable III
45604: 02/07/29: Daryl: Re: Programming FLASH with Xilinx Parallel Cable III
45611: 02/07/29: Manfred Kraus: Re: Programming FLASH with Xilinx Parallel Cable III
45613: 02/07/29: Steve Casselman: Re: Programming FLASH with Xilinx Parallel Cable III
45590: 02/07/28: <_nospam_nshimizu_at_bosei_cc_@bosei.cc.u-tokai.ac.jp>: SFL2VL now output compatible verilog with Exemplar
45596: 02/07/28: hristo: Bit serial arithmetic Vs Digit serial Arithmetic
45608: 02/07/29: Ray Andraka: Re: Bit serial arithmetic Vs Digit serial Arithmetic
45621: 02/07/29: hristo: Re: Bit serial arithmetic Vs Digit serial Arithmetic
45635: 02/07/30: Thomas Reinemann: Re: Bit serial arithmetic Vs Digit serial Arithmetic
46555: 02/09/03: Lars Wanhammar: Re: Bit serial arithmetic Vs Digit serial Arithmetic
45598: 02/07/29: Thomas Wollinger: secure FPGA
45605: 02/07/29: Daryl: Re: secure FPGA
45610: 02/07/29: S. Ramirez: Re: secure FPGA
45614: 02/07/29: Timothy R. Sloper: Re: secure FPGA
45616: 02/07/29: Nicholas C. Weaver: Re: secure FPGA
45617: 02/07/29: Timothy R. Sloper: Re: secure FPGA
45619: 02/07/29: Ray Andraka: Re: secure FPGA
45625: 02/07/29: Kevin Neilson: Re: secure FPGA
45628: 02/07/30: Ray Andraka: Re: secure FPGA
45620: 02/07/29: Nicholas C. Weaver: Re: secure FPGA
46008: 02/08/14: rk: Re: secure FPGA
45631: 02/07/30: Hal Murray: Re: secure FPGA
45646: 02/07/30: Timothy R. Sloper: Re: secure FPGA
45612: 02/07/29: Manfred Kraus: Re: secure FPGA
45640: 02/07/30: Pete Ormsby: Re: secure FPGA
45632: 02/07/30: Gazza: Re: secure FPGA
45634: 02/07/30: Thomas Wollinger: Re: physical attacks (& secure FPGA) - some more questions
45639: 02/07/30: Ray Andraka: Re: physical attacks (& secure FPGA) - some more questions
45600: 02/07/29: William Lenihan: timing got worse?
45603: 02/07/29: Allan Herriman: Re: timing got worse?
45689: 02/08/01: <hamish@cloud.net.au>: Re: timing got worse?
45601: 02/07/29: Mitchell Crago: Wishbone <-> CoreConnect
45602: 02/07/29: David R Brooks: VHDL configurations with Xilinx ISE 4.1i
45618: 02/07/29: Mike Treseler: Re: VHDL configurations with Xilinx ISE 4.1i
45606: 02/07/29: Noddy: Complex FIR low pass filters
45607: 02/07/29: Ray Andraka: Re: Complex FIR low pass filters
45615: 02/07/29: emanuel stiebler: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45624: 02/07/29: M. Randelzhofer: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45677: 02/07/31: emanuel stiebler: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45699: 02/08/01: M. Randelzhofer: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45633: 02/07/30: <mrmikehicks@earthlink.net>: Dual Port Block RAM
45637: 02/07/30: Michael Rhotert: Re: Dual Port Block RAM
45660: 02/07/31: <mrmikehicks@earthlink.net>: Re: Dual Port Block RAM
45642: 02/07/30: Brian Davis: Re: Dual Port Block RAM
45680: 02/08/01: <mrmikehicks@earthlink.net>: Re: Dual Port Block RAM
45636: 02/07/30: Jesper Kristensen: How to generate correct Express Mode configuration bit stream for Spartan-XL...?
45638: 02/07/30: Laurent Gauch: VIRTEX-II pro -> LVTTL 3.3
45780: 02/08/05: Ken Ryan: Re: VIRTEX-II pro -> LVTTL 3.3
45810: 02/08/06: Richard Schwarz: Re: VIRTEX-II pro -> LVTTL 3.3
45641: 02/07/30: Ersin: ntelist problem
45662: 02/07/31: William Lenihan: Re: ntelist problem
45665: 02/07/31: Ersin: Re: ntelist problem
45667: 02/07/31: Ersin: Re: ntelist problem
45643: 02/07/30: mok: Looking for a Virtex-II based video board...
45644: 02/07/30: Ken Mac: Maximum FIR coefficient widths on FPGA
45650: 02/07/30: Ray Andraka: Re: Maximum FIR coefficient widths on FPGA
45654: 02/07/30: Ken Mac: Re: Maximum FIR coefficient widths on FPGA
45647: 02/07/30: Jerry: VirtexE : OrCAD capture part symbol
45674: 02/07/31: Walt: Re: VirtexE : OrCAD capture part symbol
45681: 02/08/01: Austin Franklin: Re: VirtexE : OrCAD capture part symbol
45687: 02/08/01: Greg Deuerling: Re: VirtexE : OrCAD capture part symbol
45649: 02/07/30: Daniel: Impedance Measureing
45655: 02/07/30: John_H: Re: Impedance Measureing
45657: 02/07/30: Daniel: Re: Impedance Measureing
45659: 02/07/30: James Horn: Re: Impedance Measureing
45704: 02/08/01: cfk: Re: Impedance Measureing
45651: 02/07/30: Lasse Langwadt Christensen: anyone with a few xc2v3000-fg676-5 ??
45652: 02/07/30: Ben Howe: Pipelined Multiplier Implemented in Slices in Virtex II
45653: 02/07/30: Ray Andraka: Re: Pipelined Multiplier Implemented in Slices in Virtex II
45684: 02/08/01: Edward Moore: Re: Pipelined Multiplier Implemented in Slices in Virtex II
45686: 02/08/01: Ray Andraka: Re: Pipelined Multiplier Implemented in Slices in Virtex II
45745: 02/08/03: Rick Filipkiewicz: Re: Pipelined Multiplier Implemented in Slices in Virtex II
45800: 02/08/06: Ray Andraka: Re: Pipelined Multiplier Implemented in Slices in Virtex II
45688: 02/08/01: Wolfgang Loewer: Re: Pipelined Multiplier Implemented in Slices in Virtex II
45700: 02/08/01: Ben Howe: Re: Pipelined Multiplier Implemented in Slices in Virtex II
45656: 02/07/30: John Larkin: lots of shift registers
45658: 02/07/30: John Eaton: Re: lots of shift registers
45671: 02/07/31: Falk Brunner: Re: lots of shift registers
45728: 02/08/02: Manfred Kraus: Re: lots of shift registers
45803: 02/08/06: Ray Andraka: Re: lots of shift registers
45858: 02/08/07: John: Re: lots of shift registers
45661: 02/07/31: Scott L. Baker: looking for : Intel .hex to Xilinx .coe conversion
45668: 02/07/31: Rudolf Usselmann: 2.75V IOs @ Virtex/Spartan2E
45746: 02/08/03: Stuart Brorson: Re: 2.75V IOs @ Virtex/Spartan2E
45669: 02/07/31: Børge Strand: Name of reset net
45679: 02/08/01: Spam Hater: Re: Name of reset net
45670: 02/07/31: Autofuzz: FPGA performance matrix..
45675: 02/07/31: Ray Andraka: Re: FPGA performance matrix..
45673: 02/07/31: Jonathan Bromley: Re: tone detection...
45678: 02/07/31: jetmarc: Re: tone detection...
45676: 02/07/31: jf hasson: logicore pci macro in virtex problem
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