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how do you mean available? no sign of anyway to download....or is it me? Dave "Rob Finch" <robfinch@sympatico.ca> wrote in message news:rtJs9.1762$Kf.256319@news20.bellglobal.com... > Hi, > > A 6502 compatible core is available at > http://www.birdcomputer.ca/Cores/bc_6502.html > Small and Fast. > > Rob > > > > >Article: 48601
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:aosep8$p4rpu$1@ID-84877.news.dfncis.de... > "Will" <wv9557@yahoo.com> schrieb im Newsbeitrag > news:4a885870.0210190910.e66333c@posting.google.com... > > My experience with large XILINX distributors is not very good. It seems > > like they are not really interested in selling inexpensive evaluation > kits. > > Hmm, I guess the large Xilinx distibutors are focused on the big business. > But there are enough 3rd partys, wich also welcome small hobbyists. > I ordered some stuff from nuhorizons, no probs. > Burched I dont know, but I guess his main focus is very much the hobbyists, > isnt it? We don't exclude anyone:) Our aim is to make the boards affordable for students, hobbyists, and all development labs. And because we have the modular B5 system, users can either purchase the B5 mainboard by itself, and then self build the rest of the system, or add B5 plug-on module interfaces and resources as needed, or as budget allows (most often important for students and hobbyists). It's easy to get to know us;) The B5-X300 mainboard's webpage is at http://www.burched.biz/b5x300.html The B5-X300 with the XC2S300E device and the programming cable included, is US$179. The XC2S300E device is supported by the free Xilinx Webpack design tools. > ;-) > > -- > MfG > Falk > Best regards Tony Burch http://www.BurchED.biz FPGA boards for System-On-Chip prototyping and educationArticle: 48602
Someone know where to buy fpga (Xilinx,Altera) in quantities of 1 to 5 Thanks in advanceArticle: 48603
I would guess available as in "for license" as in for commercial payment. Does this newsgroup allow commercial advertisements? So... No it is not you, I read the posting and the newsgroup the same way as you did. BTW, a couple of years ago Green Mountain Computing offered a synthesizable 68HC11 core that was downloadable for free. I used this core for a class project for a grad couse in HW-SW codesign. I suppose that posting could have been considered as advertisement for Green Mountain but at least the core was free (even if it targeted their software for simulation, etc.) Just my opinion, Theron Hicks "Speedy Zero Two" <david@manorsway.NOSPAMPLEASE.freeserve.co.uk> wrote in message news:ap1ml8$vim$1@news7.svr.pol.co.uk... > how do you mean available? > no sign of anyway to download....or is it me? > > Dave > > "Rob Finch" <robfinch@sympatico.ca> wrote in message > news:rtJs9.1762$Kf.256319@news20.bellglobal.com... > > Hi, > > > > A 6502 compatible core is available at > > http://www.birdcomputer.ca/Cores/bc_6502.html > > Small and Fast. > > > > Rob > > > > > > > > > > > >Article: 48604
Addressing item 1 only, sythesizers will better understand how to efficiently
implement a single arithmetic chain rather than working backwars from a mux of
two arithmetic values. Try
assign {carry_out,sum,x} = {a,carry_in} + ( fn ? -{ b,1'b1 }: { b,1'b1 });
though the synth might still be confused by the 2's complement. To go "whole
hog" to the minimum solution, you may have to explicitly perform the negative:
assign {carry_out,sum,x} = {a,carry_in} + ( fn ? {~b,1'b1 }: { b,1'b1 });
( -n == ~n + 1 . . . -{n,1} == ~{n,1} + 1 == {~n,0} + 1 == {~n,1} )
It's all much smaller now!
Article: 48605"Javier Garcia" <minosss@yahoo.com> wrote in message news:a92a77a9.0210211239.77b73234@posting.google.com... > Someone know where to buy fpga (Xilinx,Altera) in quantities of 1 to 5 > Thanks in advance Farnell stocks several Xilinx FPGAs. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 48606
try digikey at www.digikey.com "Javier Garcia" <minosss@yahoo.com> wrote in message news:a92a77a9.0210211239.77b73234@posting.google.com... > Someone know where to buy fpga (Xilinx,Altera) in quantities of 1 to 5 > Thanks in advanceArticle: 48607
Calvin Klein wrote: > > Hi, > > I am using an FPGA to access a Compact Flash card. How can I find out > the files and directory structures of the files in CF card? I wrote in some > binary > files with a Win-XP compatible card reader. What kind of knowledge do I > need to read? Thanks. Hi, ummm, Calvin... CompactFlash is basically PCMCIA (which of course stands for People Can't Memorise Computer Industry Acronyms) with a smaller connector. Unless you are prepared to cough up big bucks for documentation from the CompactFlash association, you must go and learn everything you can about PCMCIA (it's been around long enough that there are a few books available). Then you need to map the PCMCIA into CF. Then once you think you know how to do it, you might consider beginning a design. Or, you can buy a PCMCIA/CF chipset from a semiconductor vendor, and get started that way. This is not a project you'll do in a week or maybe even a month... That's the electrical side. You seem more intereseted in the data side, which as I understand it is almost identical to PCMCIA. 3 levels - raw memory mode, IO mode and IDE mode (ie like a hard drive). All cards must support the memory mapped mode, then you can optionally implement the IO or IDE interfaces. The Card Information Structure (CIS) is where all this sort of info is stored. Get a PCMCIA book, it'll probably be the best place to start if you are doing this on the cheap. Regards, JohnArticle: 48608
Answers:
1) Not sure what yours did. If you are not using the same tool it may not have
recognized the structure. IIRC, Jan is using synplicity. You can code right
down to the LUT level by instantiating the LUTs. We do tht in some of our stuff
rather in order to put floorplanning in the source. It also avoids the pushing
on a rope syndrome which occurs all too often when going from version to version
of a tool or between vendors. You can get a decent feel for the way stuff got
coneected with the floorplanner. I don't think the free beer tools have the
FPGA editor, so you won't get the detail.
2) The tools don't do floorplanning, they only do placement. The placement
they do is pretty much random, which means if you have knowledge of your design
and a little bit of talent, you can substantially outperform the automatic
placement. Of course, if your target clock is not pushing the part,then perhaps
it is not necessary to do it. Floorplanning give you the benefits of a faster
and denser design, which in turn will tend to reduce power, since a good
percentage of the power is dissipated in the routeing pips. As with many
things, you need to evaluate a cost/benefit to determine if it is worthwhile for
you.
3) Jan published his stuff in circuit cellar. I've seen others out there, but
none as well documented as Jan's. Have you tried google?
Ralph Mason wrote:
> I have been trying to learn verilog with the aim of designing a cpu I have
> an idea of. I have been using the Very good document by Jan Gray on his
> system on chip design.
>
> I have a couple of queries, an odd mix of them.
>
> 1. As a learning process I have copped his adder, he says that it turns
> into 17 LUT's although mine ends up at 52 - Is there some optimizations I am
> missing here? are there any pragmas you can use in these situations to say
> what you want? Can you get right down to the actual LUT level and connect
> them up yourself? Using the free Xilinx tools can you actually see the way
> it has connected the actual LUTs?
>
> module addsub(clk, fn, carry_in,carry_out,x,a,b,sum);
> input clk, fn,carry_in;
> input [15:0] a,b;
> output [15:0] sum;
> output x,carry_out ;
>
> assign {carry_out,sum,x} = fn ? {a,carry_in} - { b,1'b1 }
> :{a,carry_in} + { b,1'b1 } ;
>
> endmodule
>
> 2. Floorplaning - Is there any info on this, it seems that you don't need
> to do it because the tools do it automatically, I am guessing sometimes you
> can do it better yourself to give a faster device? It looks like a
> laborious process - is it?
>
> 3. General - The CPU I want to design is a RISC / CISC design where a pre
> processor reads CISC instructions from ram and places RISC instructions (or
> jumps to RISC subs) to do the same them in an internal pipeline for a RISC
> internal cpu ( or perhaps many instances of the same RISC cpu and a single
> pre processor to provide a kind of hardware multithreading) - Is there any
> notes on existing designs like this that one could read.
>
> Thanks for any help / suggestions / ideas
> Ralph
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48609Javier Garcia <minosss@yahoo.com> wrote: : Someone know where to buy fpga (Xilinx,Altera) in quantities of 1 to 5 : Thanks in advance It depends on family and package and when you expect availability. E.g. Virtex is available at RS-Components ( for a premium price), Spartan and Spartan II at Schukat here in Germany. www.nuhorizons.com list a lot more devices, but most are not immediate available. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 48610
Ralph Mason wrote > 1. As a learning process I have copped his adder, he says that it turns > into 17 LUT's although mine ends up at 52 - Is there some optimizations I am > missing here? are there any pragmas you can use in these situations to say > what you want? Can you get right down to the actual LUT level and connect > them up yourself? Using the free Xilinx tools can you actually see the way > it has connected the actual LUTs? First, congratulations on going to the trouble of actually looking under the hood and *inspecting* what came out of your tools. That is a very good practice. Welcome to "pushing on a rope". (fpgacpu.org/usenet/rope_pushing.html: "You know exactly what you want -- a particular optimal, hand-mapped, hand-placed layout for your datapath -- but the tools get in the way, and you spend hours trying to discover an incantation that persuades the tools to emit the desired result.") Here the goal was to generate a+b or a-b with cin and cout at a cost of one LUT per bit. The hardware is willing, but you will need to perform a bit of experimentation to discover an expression that the synthesis tool will repeatably synthesize into the desired hardware idiom. The construction you 'copped' did work for one version of some synthesis tool once. Of course that does not mean it works reliably across all tools and all versions of all tools! I like John_H's suggestion -- it may succeed more often than the mux(+,-) that I used. BTW IIRC in this specific instance it was also necessary to move the single assignment into its own module -- the synthesis tool created the inefficient mux(+, -) form if the assignment was inline in the parent module. > 2. Floorplaning - Is there any info on this, it seems that you don't need > to do it because the tools do it automatically, I am guessing sometimes you > can do it better yourself to give a faster device? It looks like a > laborious process - is it? It need not be laborious, but you have to learn the ropes. It think we old timers are fortunate because we grew up doing hierarchical schematics, and so writing the same hierarchical structural HDL is familiar and natural. It is long past time I investigated how to do this with XST Verilog and wrote it up for my site... > 3. General - The CPU I want to design is a RISC / CISC design where a pre > processor reads CISC instructions from ram and places RISC instructions (or > jumps to RISC subs) to do the same them in an internal pipeline for a RISC > internal cpu ( or perhaps many instances of the same RISC cpu and a single > pre processor to provide a kind of hardware multithreading) - Is there any > notes on existing designs like this that one could read. Interesting. If the "preprocessor" is hardware, this was done in e.g. Intel P6, in the AMD K6, in some VAX implementations, and so forth. If the "preprocessor" is software, this was done in e.g. SoftWindows, Digital's FX!32 and Transmeta. There's lots in the library (see e.g. IEEE Micro) and in Google! (Also time to update my resources/book section of my site.) Jan Gray, Gray Research LLCArticle: 48611
www.free-ip.com still has a 6502 core to download. Not tried it however. b.t.w I have verified the latest version of the t80 (z80) core at www.opencores.org to be absolutely cycle accurate - at least for all the code I have run on it so far - may have missed some though ;-) MikeJ "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:ap1o65$2kff$1@msunews.cl.msu.edu... > I would guess available as in "for license" as in for commercial payment. > Does this newsgroup allow commercial advertisements? So... No it is not > you, I read the posting and the newsgroup the same way as you did. BTW, a > couple of years ago Green Mountain Computing offered a synthesizable 68HC11 > core that was downloadable for free. I used this core for a class project > for a grad couse in HW-SW codesign. I suppose that posting could have been > considered as advertisement for Green Mountain but at least the core was > free (even if it targeted their software for simulation, etc.) > Just my opinion, > Theron Hicks > > > "Speedy Zero Two" <david@manorsway.NOSPAMPLEASE.freeserve.co.uk> wrote in > message news:ap1ml8$vim$1@news7.svr.pol.co.uk... > > how do you mean available? > > no sign of anyway to download....or is it me? > > > > Dave > > > > "Rob Finch" <robfinch@sympatico.ca> wrote in message > > news:rtJs9.1762$Kf.256319@news20.bellglobal.com... > > > Hi, > > > > > > A 6502 compatible core is available at > > > http://www.birdcomputer.ca/Cores/bc_6502.html > > > Small and Fast. > > > > > > Rob > > > > > > > > > > > > > > > > > > > > >Article: 48612
John Williams wrote > CompactFlash is basically PCMCIA (which of course stands for People > Can't Memorise Computer Industry Acronyms) with a smaller connector. > Unless you are prepared to cough up big bucks for documentation from the > CompactFlash association, you must go and learn everything you can about > PCMCIA (it's been around long enough that there are a few books > available). AFAIK, the CF spec is freely available from the CF association, or some similar setup. Try www.compactflash.org or Google. > That's the electrical side. You seem more intereseted in the data side, > which as I understand it is almost identical to PCMCIA. 3 levels - raw > memory mode, IO mode and IDE mode (ie like a hard drive). All cards > must support the memory mapped mode, then you can optionally implement > the IO or IDE interfaces. The Card Information Structure (CIS) is where > all this sort of info is stored. Get a PCMCIA book, it'll probably be > the best place to start if you are doing this on the cheap. Try the IBM site for their tiny hard disks with a CF interface. They have as good a set of docs as anyone. For the logical layout, the Linux kernel is a good source :-)Article: 48613
Jan, Ralph,
Long time ago we got tired of pushing on the rope for every design we did, so we
went ahead and created a library of parameterized structurally instantiated
things like d registers, various flavors of adders/subtractors, delay queues,
etc. Easy to do in VHDL with the generate statement, a real PITA in verilog
without the v2000 extensions. Because of some of the things like the generate,
I have become something of a VHDL bigot so you'll have to excuse that. Usually
I could get the tools to behave with inferred stuff if I structured the
inference to look like the hardware, something like this:
neg_b<= b when sub='1' else not b;
cin<= 1 when sub='1' else 0;
sum_d<= a + neg_b+cin;
The results vary by synth and version, but this structure seems to get there
most of the time.
Jan Gray wrote:
> Ralph Mason wrote
>
> > 1. As a learning process I have copped his adder, he says that it turns
> > into 17 LUT's although mine ends up at 52 - Is there some optimizations I
> am
> > missing here? are there any pragmas you can use in these situations to say
> > what you want? Can you get right down to the actual LUT level and connect
> > them up yourself? Using the free Xilinx tools can you actually see the way
> > it has connected the actual LUTs?
>
> First, congratulations on going to the trouble of actually looking under the
> hood and *inspecting* what came out of your tools. That is a very good
> practice.
>
> Welcome to "pushing on a rope". (fpgacpu.org/usenet/rope_pushing.html: "You
> know exactly what you want -- a particular optimal, hand-mapped, hand-placed
> layout for your datapath -- but the tools get in the way, and you spend
> hours trying to discover an incantation that persuades the tools to emit the
> desired result.")
>
> Here the goal was to generate a+b or a-b with cin and cout at a cost of one
> LUT per bit. The hardware is willing, but you will need to perform a bit of
> experimentation to discover an expression that the synthesis tool will
> repeatably synthesize into the desired hardware idiom.
>
> The construction you 'copped' did work for one version of some synthesis
> tool once. Of course that does not mean it works reliably across all tools
> and all versions of all tools!
>
> I like John_H's suggestion -- it may succeed more often than the mux(+,-)
> that I used.
>
> BTW IIRC in this specific instance it was also necessary to move the single
> assignment into its own module -- the synthesis tool created the inefficient
> mux(+, -) form if the assignment was inline in the parent module.
>
> > 2. Floorplaning - Is there any info on this, it seems that you don't need
> > to do it because the tools do it automatically, I am guessing sometimes
> you
> > can do it better yourself to give a faster device? It looks like a
> > laborious process - is it?
>
> It need not be laborious, but you have to learn the ropes. It think we old
> timers are fortunate because we grew up doing hierarchical schematics, and
> so writing the same hierarchical structural HDL is familiar and natural.
>
> It is long past time I investigated how to do this with XST Verilog and
> wrote it up for my site...
>
> > 3. General - The CPU I want to design is a RISC / CISC design where a pre
> > processor reads CISC instructions from ram and places RISC instructions
> (or
> > jumps to RISC subs) to do the same them in an internal pipeline for a
> RISC
> > internal cpu ( or perhaps many instances of the same RISC cpu and a single
> > pre processor to provide a kind of hardware multithreading) - Is there any
> > notes on existing designs like this that one could read.
>
> Interesting. If the "preprocessor" is hardware, this was done in e.g. Intel
> P6, in the AMD K6, in some VAX implementations, and so forth. If the
> "preprocessor" is software, this was done in e.g. SoftWindows, Digital's
> FX!32 and Transmeta. There's lots in the library (see e.g. IEEE Micro) and
> in Google! (Also time to update my resources/book section of my site.)
>
> Jan Gray, Gray Research LLC
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48614"Jan Gray" <jsgray@acm.org> wrote in message news:ap21sj$qs3$1@slb5.atl.mindspring.net... > Welcome to "pushing on a rope". (fpgacpu.org/usenet/rope_pushing.html: "You > know exactly what you want -- a particular optimal, hand-mapped, hand-placed > layout for your datapath -- but the tools get in the way, and you spend > hours trying to discover an incantation that persuades the tools to emit the > desired result.") Comming from a mostly SW background it sounds like the same as trying to get the compiler to produce just that perfect assembly for you - about 50% of the time you just give up and write it your self > > 3. General - The CPU I want to design is a RISC / CISC design where a pre > > processor reads CISC instructions from ram and places RISC instructions > (or > > jumps to RISC subs) to do the same them in an internal pipeline for a > RISC > > internal cpu ( or perhaps many instances of the same RISC cpu and a single > > pre processor to provide a kind of hardware multithreading) - Is there any > > notes on existing designs like this that one could read. > > Interesting. If the "preprocessor" is hardware, this was done in e.g. Intel > P6, in the AMD K6, in some VAX implementations, and so forth. If the > "preprocessor" is software, this was done in e.g. SoftWindows, Digital's > FX!32 and Transmeta. There's lots in the library (see e.g. IEEE Micro) and > in Google! (Also time to update my resources/book section of my site.) I haven't decided if the pre processor will be SW loaded microcode (prefered) or hard coded yet or not, I just want to minimise external bus activity, and also be able to fed lots of internal processors ( kinda a cross between the Transmeta, with the and these multip threading pentiums), the multiple internal processors could also share some of the bigger units (say a multiplier) I am going to play with a software emulation first to see how it turns out, what boosts performace the most, what works and what doesn't Thanks RalphArticle: 48615
Allan Herriman wrote: > On Sat, 19 Oct 2002 16:15:01 GMT, Ken McElvain <ken@synplicity.com> > wrote: > > >>Thanks! Actually there are several of the hotline folks that read the >>newsgroup, but we limit the number of posters. >> > > Ah, good. I'd like to know what you are doing about the SRL16 > inference rule change between 7.0 and 7.1. We have a number of > designs here that break in 7.1 and 7.2 because Synplify Pro is > inappropriately changing FF into SRL16E. > > Problem 1 (fixed in 7.2 beta) Some FF with 350MHz clock get converted > to SRL16E. SRL16E don't work at 350MHz (in Virtex2). > > Problem 2 (still outstanding) Some FF with async reset get converted > to SRL16E. SRL16E don't have an async reset input, so this is a > functional change. > (It's that old problem of Synplify trying to be too clever about the > meaning of GSR when the startup block is present. If an FPGA has an > external reset input (connected to the startup block) then it is *not* > correct to assume that GSR is only active during configuration.) Sorry, this was a bug in the 7.2 beta1 . I understand that it has already been fixed in the current 7.2 beta2. We usually go through 2 rounds of beta before production release. > > Problem 3 (still outstanding) Some FF that were in IOBs get converted > to SRL16E. This breaks the I/O timing on the part. We would love a small test case (or any test case). Our test cases appear to work properly. We are not supposed to be sucking in flip flops connected to I/Os. > > > Problem 3 is actually the worst one for us, since most of the designs > infer I/O FF. > > I rather liked the 6.x rule that only allowed an RTL FF to be > converted to SRL16E when the FF was coded without an async reset or > set. > > Regards, > Allan. >Article: 48616
Hi, I need to configure an old FPGA XC4005E, but in the WebPack is not
present (i've tried 4.2 and 3.3 version).
Any one know witch is the program that i have to use and where i can find
it?
Thanks
Mauro
--
Mauro Pintus
www.geocities.com/triac11
--
Article: 48617Hi Tim, Tim wrote: > > AFAIK, the CF spec is freely available from the CF association, or > some similar setup. Try www.compactflash.org or Google. Yes, the specification is available at the CF website, however it is exactly that, a specification (electrical, mechanical, timing etc). Unless you are already familiar with the *meaning* of the various signals, the interface bus and so, it doesn't really get you any closer to understanding what is actually required to design a CF card or host. This is particularly the case when it comes to the data side - the CIS and so on. > Try the IBM site for their tiny hard disks with a CF interface. They > have as good a set of docs as anyone. Interesting - so do IBM publish the specs necessary for a host to talk to their CF hard disks? Or do they just say "This is a standard CF IDE/ATAPI-style device"? I started down this path a few months back, trying to determine if it was feasible for a mere mortal to design and build and FPGA-based CF card interface. I started with the CF spec, quickly gave up on that, then basically proceeded to learn as much as I could about PCMCIA. After getting to grips with that I was going to revisit the spec. The project is shelved for now. I also glimpsed briefly at the other portable / handheld interface "standards", SmartMedia, SecureDigital et al - and got pretty frustrated by the barriers in place preventing mortals (and small companies) getting in on the act. Unless you will pay expensive membership fees, and exorbitant prices for standards and specs etc, you don't really have a chance. At least PCMCIA has been around long enough for a few people to write reasonable technical books about it. Rgds, JohnArticle: 48618
b.t.w I have verified the latest version of the t80 (z80) core at > www.opencores.org to be absolutely cycle accurate - at least for all the > code I have run on it so far - may have missed some though ;-) > Let's start a z80 vs 6502 war :) > > I would guess available as in "for license" as in for commercial payment. The core is available for free for individual use or evaluation purposes. Only commercial use requires a license. http://www.birdcomputer.ca/Projects/Prj6502/bc6502_page.html I assumed that people would be able to find this link, but maybe I need to organize my website a little better... > > Does this newsgroup allow commercial advertisements? So... No it is not Where do you find the rules of the newsgroup or any newsgroup ? Obviously, I should have put more detail in my original post. RobArticle: 48619
I have read the CompactFlash specs already but find not so useful. By the way, what's the link between IDE and ATA? I am pretty confused that they are quoted inter-changeably. -- Xu Qijun ---------------------------------------------------- Oki Techno Centre (Singapore) Pte Ltd 20 Science Park Road #02-06/10, Teletech Park, Singapore Science Park II, 117674 Singapore. Tel: +65-6779-1621 Fax: +65-6779-2382 DID: +65-6770-7081 E-mail: qijun677@oki.com URL: www.okitechno.com ---------------------------------------------------- Friends may come and go, but enemies accumulate. "John Williams" <j2.williams@qut.edu.au> wrote in message news:3DB4A6C1.EF1CA95C@qut.edu.au... > Hi Tim, > > Tim wrote: > > > > AFAIK, the CF spec is freely available from the CF association, or > > some similar setup. Try www.compactflash.org or Google. > > Yes, the specification is available at the CF website, however it is > exactly that, a specification (electrical, mechanical, timing etc). > Unless you are already familiar with the *meaning* of the various > signals, the interface bus and so, it doesn't really get you any closer > to understanding what is actually required to design a CF card or host. > > This is particularly the case when it comes to the data side - the CIS > and so on. > > > Try the IBM site for their tiny hard disks with a CF interface. They > > have as good a set of docs as anyone. > > Interesting - so do IBM publish the specs necessary for a host to talk > to their CF hard disks? Or do they just say "This is a standard CF > IDE/ATAPI-style device"? > > I started down this path a few months back, trying to determine if it > was feasible for a mere mortal to design and build and FPGA-based CF > card interface. I started with the CF spec, quickly gave up on that, > then basically proceeded to learn as much as I could about PCMCIA. > After getting to grips with that I was going to revisit the spec. The > project is shelved for now. > > I also glimpsed briefly at the other portable / handheld interface > "standards", SmartMedia, SecureDigital et al - and got pretty frustrated > by the barriers in place preventing mortals (and small companies) > getting in on the act. Unless you will pay expensive membership fees, > and exorbitant prices for standards and specs etc, you don't really have > a chance. At least PCMCIA has been around long enough for a few people > to write reasonable technical books about it. > > Rgds, > > JohnArticle: 48620
This is a general question. Does PCMCIA contain a functionality of auto-boot like a CD_ROM? I am thinking about whether I can copy the Win-XP OS into an IBM MicroDrive, and get rid of the CDROM on my notebooks. Friends may come and go, but enemies accumulate. "John Williams" <j2.williams@qut.edu.au> wrote in message news:3DB47954.44B87902@qut.edu.au... > > > Calvin Klein wrote: > > > > Hi, > > > > I am using an FPGA to access a Compact Flash card. How can I find out > > the files and directory structures of the files in CF card? I wrote in some > > binary > > files with a Win-XP compatible card reader. What kind of knowledge do I > > need to read? Thanks. > > Hi, ummm, Calvin... > > CompactFlash is basically PCMCIA (which of course stands for People > Can't Memorise Computer Industry Acronyms) with a smaller connector. > Unless you are prepared to cough up big bucks for documentation from the > CompactFlash association, you must go and learn everything you can about > PCMCIA (it's been around long enough that there are a few books > available). Then you need to map the PCMCIA into CF. Then once you > think you know how to do it, you might consider beginning a design. > > Or, you can buy a PCMCIA/CF chipset from a semiconductor vendor, and get > started that way. This is not a project you'll do in a week or maybe > even a month... > > That's the electrical side. You seem more intereseted in the data side, > which as I understand it is almost identical to PCMCIA. 3 levels - raw > memory mode, IO mode and IDE mode (ie like a hard drive). All cards > must support the memory mapped mode, then you can optionally implement > the IO or IDE interfaces. The Card Information Structure (CIS) is where > all this sort of info is stored. Get a PCMCIA book, it'll probably be > the best place to start if you are doing this on the cheap. > > Regards, > > JohnArticle: 48621
Erwin Rol <Erwin.Rol_nospam_@Q-Soft-Engineering.com> wrote in message news:<ap10n4$a9h$05$1@news.t-online.com>... > Murali K Warier wrote: > > Hi All, > > > > I tried to download the free Webpack software from Xilinx website. > > Whatever I did, I could not download the single file (170 MB) beyond > > 26%. I tried two download managers, GetRight and Gozilla, to no avail. > > The server is always busy with something else. Is there a way around? > > I do have a fast connection to the net. Thanks for any suggestions. > > I had the same problem, i could not download it with mozilla or galeon. > With wget it worked, but i could see that it needed 3 or 4 retries to > get the whole file. So give wget a try , that should work. > > - Erwin > > > > > Thanks and regards, > > Murali. Thank you Erwin, for the suggestion. I downloaded it with wget, after a couple of retries. Murali.Article: 48622
Please help
I write a simple verilog programe to calculate a 4 * 4 matrix
multiplication. C = A * B, A is pre-defined.
I write a task calc_line to calculate one line, like follows:
module matrix_multi
...
for(j = 0; j < 16; j = i + 4)
calc_line(in[j], in[j + 1], in[j + 2], in[j + 3], out[j], out[j +
1], out[j + 2], out[j + 3]);
...
task calc_line;
input a, b, c, d;
output dout0, dout1, dout2, dout3;
....
//multiply here
....
endtask
endmodule
After the synthesis/implementation, it seems that 4 physic calc_line
"blocks"(maybe not accurate, I don't know the term)
are prodused to run, it use too much resource, I only need one block and
re-use it in the loop.
Hopes you can understand what I say, I don't know how to describe it in
special terms.
How can I do it?
I use Active HDL 5.1 , Xilinx ISE 4.1, FPGA is Xilinx VIRTEX2
Thanks for any advance
Article: 48623Thanks for reminding me about the Xilinx web site. You know, I can't remember the person's name. IIRC, and I probably don't, he was in northern Europe somewhere. He pulled it down about 2 years ago. A groups.google.com search in comp.lang.verilog (VHDL?) might turn it up. Basically, some people started complaining that it wasn't -complete-, and he got tired of hearing about it. SH7 On Sun, 20 Oct 2002 13:59:53 -0500, Kevin Brace <kev3inbrac5eusen7et@ho9tmail.c1om> wrote: > > Anyhow, just for curiosity, who used to distribute the PCI IP >core you are talking about, and when was it taken down? >Article: 48624
Hi, Basically, Foundation uses Synopsys for synthesis, and ISE uses Xilinx's own 'XST' for synthesis. (IIRC, Foundation used Aldec for simulation, while ISE uses ModelSim.) Xilinx pulled the plug on Foundation in May of this year. XST seems to work "just fine" for SpartanII, and IIE. Install ISE, and the FPGA Express package, and you can use either synthesiser. SH7 On Mon, 21 Oct 2002 22:09:18 +0200, "Noddy" <g9731642@campus.ru.ac.za> wrote: >Hi, > >Probably should have worded question a bit better. > >Thanks for the reply, but I am still a bit confused. I have a 4.2 upgrade >pack which consists of a set of CDs for installing Foundation 4.2, and >another set for installing ISE 4.2. How is ISE different to Foundation?? I >want to design for a Spartan IIE, so which should I install? I checked the >datasource CD to check which device families are supported, and it said ISE >Foundation supports Spartan IIE. Perhaps ISE is used in a different context >here? > >Adrian > > >> Adrian, >> >> ISE refers generally to the Design Tool. There are four configurations of >this tool that you may use, and Foundation is one of them. The other >configurations include Alliance, BaseX, and WebPACK. >> >> You can check here for more info: >> http://support.xilinx.com/ise/devsys_feature_guide.pdf >> >> I hope this helps. >> >> Regards, >> Kamal >
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