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Why is the price of 48$ that hard to find ? Rene James Wang wrote: > Hi, > > We are making Download ByteBlasterMV for Altera FPGA and EPLD > configuration/programming. It's reliable, affordale and suitable for > PLD development and somebody who want's to learn PLD. Details please > check at: http://www.minford.ca.Article: 48676
"John Williams" <j2.williams@qut.edu.au> ha scritto nel messaggio news:3DB47954.44B87902@qut.edu.au... > CompactFlash is basically PCMCIA Actually, most CompactFlash support directly the ATA-IDE standard (after all, PCMCIA is basically an improved IDE bus). It's quite easy to interface a CF in this way to a micro or FPGA, you do almost everything with four registers. You can find an IDE-CF adapter (it's simply a connector adapter) here: http://www.sandisk.com/tech/oem_design/cf/Cf_ide.pdf On Sandisk site you can also find useful tecnhical references for development. -- LorenzoArticle: 48677
"Leon de Boer" <ldeboer@attglobal.net> ha scritto nel messaggio news:3db567c7_3@news1.prserv.net... > SOLUTIONS I CANT DO THAT WOULD WORK > 1.) Put a schmidt trigger on the signal (requires board > change) > 2.) Slow the state machine down to go over the state > machine I had a very similar problem (a state machine fed by some optocoupled inputs). I solved it by putting a flip-flop on each state machine input, clocked by the state machine clock (maybe inverted, I don't remember). Another, "harder" way could be reducing the value of pull-up or pull-down resistor wired to the optocoupler output. This typically reduces rising and falling times. -- LorenzoArticle: 48678
Ralph, If you click on the vbw file in the "sources in project", the processes for current view" should get four simulation options. If you do not see these I suggest you reinstall Sorry best I can do Dave "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:8w9t9.161$8o1.18230@news.xtra.co.nz... > I have been trying to simulate a design using the test bench waveform, but I > didn't have modelsim installed. So I have downloaded and installed it. > > However, after installing modelsim, selecting the .tbw file only gives me > the option of viewing the file (before I installed modelsim I had options to > run the simulation) > > Does anyone have any idea what is going on here and how I get those options > back? > > Thanks > Ralph > >Article: 48679
Xilinx now offers XC4000 implementation support through a free download package separate from WebPACK. This is part of the ISE Classics now available at http://www.xilinx.com/ise_classics/index.htm, which also offers older versions of WebPACK. Mauro Pintus wrote: > Hi, I need to configure an old FPGA XC4005E, but in the WebPack is not > present (i've tried 4.2 and 3.3 version). > Any one know witch is the program that i have to use and where i can find > it? > > Thanks > Mauro > > -- > Mauro Pintus > www.geocities.com/triac11 > -- -- Marc Baker Xilinx Applications (408) 879-5375Article: 48680
Have tried that, Oddly the only way to get the options back it to UNINSTALL modelsim! Once it's uninstalled you get the options to use it but can't because it's not installed. Anyone else? Thanks Ralph "Speedy Zero Two" <david@manorsway.NOSPAMPLEASE.freeserve.co.uk> wrote in message news:ap47gk$844$1@newsg3.svr.pol.co.uk... > Ralph, > > If you click on the vbw file in the "sources in project", the processes for > current view" should get four simulation options. > > If you do not see these I suggest you reinstall > > Sorry best I can do > Dave > > "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote > in message news:8w9t9.161$8o1.18230@news.xtra.co.nz... > > I have been trying to simulate a design using the test bench waveform, but > I > > didn't have modelsim installed. So I have downloaded and installed it. > > > > However, after installing modelsim, selecting the .tbw file only gives me > > the option of viewing the file (before I installed modelsim I had options > to > > run the simulation) > > > > Does anyone have any idea what is going on here and how I get those > options > > back? > > > > Thanks > > Ralph > > > > > >Article: 48681
hmurray@suespammers.org (Hal Murray) writes: > >Is it simply a case of describing a series of registers and XOR's to fit my > >polynomial? > > Depends. > > The simple description of a CRC is bit serial. That takes many clocks > per word if you have a wide word. You can do N bits in parallel with > a big cloud of XORs. > > If you are good at software, you might want to write some hack code > to work out all the "details" of which way to shift and which way around > the polynomial goes and things like that. A web search on software See this article for a sample program to symbolically generate the xors for the polynomial X16 + X12 + X5 + 1. The Common Lisp program is only 45 lines long including comments and white space. It also includes a function to optimize xor expressions. http://groups.google.com/groups?safe=images&ie=UTF-8&oe=UTF-8&as_umsgid=87ptutz6wz.fsf%40filestore.home.gustad.com&lr=&hl=en Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48682
"Javier Garcia" <minosss@yahoo.com> wrote in message news:a92a77a9.0210220915.3c0650c3@posting.google.com... > Someone know where to buy fpga (Xilinx,Altera) in quantities of 1 to 5 > in Mexico or Usa ?? > > thanks in advance Bato, Try http://www.digikey.com. Use its search engine and try XC2S for example. I think you will find what you want there. Simon Ramirez, Consultant Oviedo, FL USAArticle: 48683
And I have found the problem. 1 webpac has a bug(ish) that makes it think modelsim is installed in c:\model... if you have nothing set so the processes show up when it's not installed. 2. I was setting my directory to my modelsim dir not modelsim\win32xoem Ralph "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:Hcit9.245$8o1.51307@news.xtra.co.nz... > Have tried that, > > Oddly the only way to get the options back it to UNINSTALL modelsim! Once > it's uninstalled you get the options to use it but can't because it's not > installed. > > Anyone else? > > Thanks > Ralph > > > > "Speedy Zero Two" <david@manorsway.NOSPAMPLEASE.freeserve.co.uk> wrote in > message news:ap47gk$844$1@newsg3.svr.pol.co.uk... > > Ralph, > > > > If you click on the vbw file in the "sources in project", the processes > for > > current view" should get four simulation options. > > > > If you do not see these I suggest you reinstall > > > > Sorry best I can do > > Dave > > > > "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> > wrote > > in message news:8w9t9.161$8o1.18230@news.xtra.co.nz... > > > I have been trying to simulate a design using the test bench waveform, > but > > I > > > didn't have modelsim installed. So I have downloaded and installed it. > > > > > > However, after installing modelsim, selecting the .tbw file only gives > me > > > the option of viewing the file (before I installed modelsim I had > options > > to > > > run the simulation) > > > > > > Does anyone have any idea what is going on here and how I get those > > options > > > back? > > > > > > Thanks > > > Ralph > > > > > > > > > > > >Article: 48684
This completely fixed the problem. Can you put this in the answers database? (Or better: fix it in the next service pack: It is just one file permission, right?) Thank you very much, Kolja Sulimma Martin Muggli <martin.muggli@xilinx.com> wrote in message news:<3DB445DE.F9D459C4@xilinx.com>... > Hi Kolja, > > It has been seen that if you do the following then you may be able to run > Modelsim without Admin privileges: > 1. Delete .mti_enc and .mti_enc2 in the WINDOWS directory, and delete the > mti_em file in the C:\Modeltech_xe\win32xoem directory. Note that these > files may be hidden in your system. > 2. Set the license file permissions to enable the use by the user and the > system. Note that the location of the license file should also be > specified in the LM_LICENSE_File environment variable. > > Regards, > Martin > > Kolja Sulimma wrote: > > > I hope that somebody out there can help me with this installation > > issue: > > > > For a lab course I need ISE 5.1i to run on a student accessible PC. > > Everything works fine if one is loged into an administrator account. > > But when I try to start Modelsim from a restricted account I get a > > message: > > "Your evaluation license is no longer valid. If this has happened in > > error, please contact Model Technology Customer Support for > > assistance. > > Evaluation Error Code : 104"Article: 48685
knowing about 10-E6% of what I need to know about this stuff, there is
probably something stupid I am doing here. But It seem like these
assign {carry_out,sum,x} = fn ? {a,carry_in} - { b,1'b1 }
:{a,carry_in} + { b,1'b1 } ;
assign {carry_out,sum,x} = {a,carry_in} + ( fn ? { ~b,1'b1 }: { b,1'b1 });
Generate a different carry output on subtraction.
If I input
carry_in = 1
a=32
b=32
fn=1
On the first I get a carry_out of 0 (expected) and on the second I get a
carry_out of 1 (unexpected)
Seems like writing the same thing a few ways can help find bugs.
Ralph
"John_H" <johnhandwork@mail.com> wrote in message
news:3DB46645.63543E05@mail.com...
> Addressing item 1 only, sythesizers will better understand how to
efficiently
> implement a single arithmetic chain rather than working backwars from a
mux of
> two arithmetic values. Try
>
> assign {carry_out,sum,x} = {a,carry_in} + ( fn ? -{ b,1'b1 }: { b,1'b1 });
>
> though the synth might still be confused by the 2's complement. To go
"whole
> hog" to the minimum solution, you may have to explicitly perform the
negative:
>
> assign {carry_out,sum,x} = {a,carry_in} + ( fn ? {~b,1'b1 }: { b,1'b1 });
>
> ( -n == ~n + 1 . . . -{n,1} == ~{n,1} + 1 == {~n,0} + 1 == {~n,1} )
>
> It's all much smaller now!
>
Article: 48686> Does this newsgroup allow commercial advertisements? You view this as a commercial advertisement allready? I always felt that one of the topics of this newsgroup is to discuss all the exciting new finished or planned designs of the groups contributors. When people start earning money with their projects, they should still be able to discuss them in this group. Take Ray Andraka for example, on of the most active contributors to this newsgroup: Whenever someone wants to know something about multipliers he posts a link to his homepage. The page about DSP in FPGA is extremly helpful. I learned a lot from it. And at the bottom of the page it says: "Call now to find out what Andraka Consulting Group can do for your DSP" Nothing wrong with that... Kolja SulimmaArticle: 48687
Hi, > Any programmable device can divide 120 MHz by five inside the chip. > Xilinx Virtex devices have a built-in delay-locked loop (DLL) circuit that > can divide the clock by 5 ( and also many other values) and guaranteed that > the 24 MHz output edges are synchronous and coincident ( within <100 ps) with > the incoming 120 MHz rising clock edge. > Without using the DLL or DCM your derived clock will trail the input clock by > 1 to 2 ns. (clock-to-Q plus some routing) I should have mentioned that the 24MHz clock is used by the device that is going to program the Xilinx part, so I can't use the Xilinx chip as the divide by 5. Would a 7490 (4 flipflops) work to do this divide by 5? Which series of 7490 would be best for low clock skew? cheers, Jamie MorkenArticle: 48688
Usually lower power, means battery operated, and battery operated means consumer market which in turn means low cost which Vertex is not. Your Cool-Runner idea may be more inline with what you want. Regards Matthias Dyer <dyer@tik.ee.ethz.ch> wrote in message news:<3daad887@pfaff.ethz.ch>... > In our lab we'd like to add an reconfigurable module to a mobile > Bluetooth-Node (BT & uC). Issues as low-power, flexibility and performance > are important for us. > > I first thought about a CoolRunner II implementation but I think we are too > limited with CPLDs. We also want to enable partial and dynamic > reconfiguration where I believe that the Virtex family is leading. > > Has anyone used Virtex FPGAs in an low power embedded design? > What system-level power saving possibilities do I have (not in the FPGA > design)? > > Or do you have other suggestions for other components? > > Thanks for any help > > Matthias Dyer > > > -- > ------------------------------------------------------------- > Matthias Dyer phone: +41-1-6327061 > Gloriastr. 35, ETZ G-63, fax: +41-1-6321035 > CH-8092 Zurich, Switzerland email: dyer@tik.ee.ethz.ch > > Computer Engineering and Networks Lab (TIK) > Swiss Federal Institute of Technology (ETH) Zuerich > -------------------------------------------------------------Article: 48689
Hi Matt, I'm currently working on a comm protocol desing at the speeds you are talking about. We are using Stratix (1S25), as it fits our needs perfectly. I highly suggest you check out the altera webpage and look into Stratix. Apex-II also supports the date rate you need, but I don't think the core can run at 200MHz. You would have to widen the data path and go at 100MHz if possible. Cheers, Xanatos "M Pedley" <Pedley@talk21.com> wrote in message news:b34821cd.0210220446.655db7d3@posting.google.com... > Are there any other companies other than Xilinx that produce FPGA's to > match there latest Virtex II designs. I require 400 MHz DDR (800 > Mbps) line side, with a 200MHz core containing at least 400 Kbits of > RAM. It is for a communications protocol so features similar to > Xilinx's DCM's that can centre a clock to a data eye (i.e. Phase > shifting) and perform lane deskew. > > I have nothing against Xilinx but just interested to see if anyone > else offered this kind of specification. Google search for High > Performance FPGA's didn't give me any useful results. > > Also, interested to hear anyones recommendations or concerns about the > claims that Xilinx make about their FPGAs, as an ASIC designer they > seem a bit too good!? > > Regards, > > MattArticle: 48690
In article <3daad887@pfaff.ethz.ch>, Matthias Dyer <dyer@tik.ee.ethz.ch> wrote: >In our lab we'd like to add an reconfigurable module to a mobile >Bluetooth-Node (BT & uC). Issues as low-power, flexibility and performance >are important for us. How low power? "low power" and FPGA don't match all that well, because switchable interconnect tends to be very high capacitance. You can help things out by floorplanning etc (Ray Andraka claims a 10-30% plus power win for good floorplanning) Gating clocks is probably a loss, but if you could restrict flip-flops to some columns, this should help reduce clock power. If you do want to use an FPGA, look at the Spartan IIe, it is .18 uM but low cost. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48691
Indeed... I was thinking of unsigned arithmatic where the result vector is the
same size as the input vector. To get the carry out, you extend this one bit.
To get the full implementation, extend the input side another bit on top. After
all, 6-6 is the same as 6+10 when you only look at the LSbits. To get a carry
out, you need 6-6 equal to 6+26 where the extra 16 is due to the sign. Look
only at the 5 bits and that carry out is zero as expected. So...
Original:
assign {carry_out,sum,x} = fn ? {a,carry_in} - { b,1'b1 }
:{a,carry_in} + { b,1'b1 } ;
which, if extended so the right side vector is the same size as the left side
vector, is
assign {carry_out,sum,x} = fn ? {1'b0,a,carry_in} - {1'b0, b,1'b1 }
:{1'b0,a,carry_in} + {1'b0, b,1'b1 } ;
What I showed you:
assign {carry_out,sum,x} = {a,carry_in} + ( fn ? {~b,1'b1 }: { b,1'b1 });
What I should've shown you:
assign {carry_out,sum,x} = {1'b0,a,carry_in} + ( fn ? {1'b1,~b,1'b1 }: {
1'b0,b,1'b1 });
( -n == ~n + 1 . . . -{0,n,1} == ~{0,n,1} + 1 == {1,~n,0} + 1 == {1,~n,1} )
This extends the sign out the extra bit needed for a proper carry out.
Article: 48692Jamie Morken wrote: > Hi, > > > I should have mentioned you should have > that the 24MHz clock is used by the device that is > going to program the > Xilinx part, so I can't use the Xilinx chip as the divide by 5. Would a > 7490 (4 flipflops) work > to do this divide by 5? Which series of 7490 would be best for low clock > skew? Yes the 7490, bless its soul, can do it, if you can get it out of its ill-deserved retirement. It's about the most obsolete solution you can possibly find... CMOS versions of the 74160 are a bit more appealing, and a PAL or CPLD might integrate additional functionality. Peter Alfke, Xilinx ApplicationsArticle: 48693
Kolja,
I merely asked if Commercial Advertisements were allowed. In any case,
the posting seemed to imply a free 6502 core. When I checked out the site,
it appeared that this was a "for pay only" core. In addition, Ray's
postings are in answer to a request for information. Also, the tag line at
the end of his posts is equivalent to using company letter-head to answer a
technical question. Frankly, the 6502 post did not bother me. I just asked
the question about advertisements. It seems that I have really stirred up a
hornets nest a couple of times lately. Sorry about that.
Theron Hicks
"Kolja Sulimma" <kolja@bnl.gov> wrote in message
news:25c81abf.0210221326.692b47f4@posting.google.com...
> > Does this newsgroup allow commercial advertisements?
>
> You view this as a commercial advertisement allready?
>
> I always felt that one of the topics of this newsgroup is to discuss
> all the exciting new finished or planned designs of the groups
> contributors.
>
> When people start earning money with their projects, they should still
> be able to discuss them in this group.
>
> Take Ray Andraka for example, on of the most active contributors to
> this newsgroup: Whenever someone wants to know something about
> multipliers he posts a link to his homepage. The page about DSP in
> FPGA is extremly helpful. I learned a lot from it. And at the bottom
> of the page it says: "Call now to find out what Andraka Consulting
> Group can do for your DSP"
>
> Nothing wrong with that...
>
> Kolja Sulimma
Article: 48694John Williams wrote > Interesting - so do IBM publish the specs necessary for a host to talk > to their CF hard disks? Or do they just say "This is a standard CF > IDE/ATAPI-style device"? This reference seems to contain the base info, including 8051 code for the true enthusiast: http://www.storage.ibm.com/hdd/micro/library/embed_micro.htmArticle: 48695
Peace, Shalom, Paix, Friede! IMHO commercialism is not the problem of this newsgroup. Even the guys who get a salary making FPGAs and boards (including yours truly) are usually sensitive and polite enough to avoid crass commercials. So let's not belabor a non-problem. Peter Alfke, Xilinx Theron Hicks wrote: > Kolja, > I merely asked if Commercial Advertisements were allowed. In any case, > the posting seemed to imply a free 6502 core. When I checked out the site, > it appeared that this was a "for pay only" core. In addition, Ray's > postings are in answer to a request for information. Also, the tag line at > the end of his posts is equivalent to using company letter-head to answer a > technical question. Frankly, the 6502 post did not bother me. I just asked > the question about advertisements. It seems that I have really stirred up a > hornets nest a couple of times lately. Sorry about that. > > Theron Hicks > > "Kolja Sulimma" <kolja@bnl.gov> wrote in message > news:25c81abf.0210221326.692b47f4@posting.google.com... > > > Does this newsgroup allow commercial advertisements? > > > > You view this as a commercial advertisement allready? > > > > I always felt that one of the topics of this newsgroup is to discuss > > all the exciting new finished or planned designs of the groups > > contributors. > > > > When people start earning money with their projects, they should still > > be able to discuss them in this group. > > > > Take Ray Andraka for example, on of the most active contributors to > > this newsgroup: Whenever someone wants to know something about > > multipliers he posts a link to his homepage. The page about DSP in > > FPGA is extremly helpful. I learned a lot from it. And at the bottom > > of the page it says: "Call now to find out what Andraka Consulting > > Group can do for your DSP" > > > > Nothing wrong with that... > > > > Kolja SulimmaArticle: 48696
You may want to consider a Xilinx CoolRunner-II CPLD. It has a built-in clock divider (128macrocell and larger devices) that can divide a clock by any even value up to 16. The CRII device also has dual-edge FFs, so if you divide a clock by 10, then run that into a TFF set to dual-edge mode, then out comes a divide by 5 clock signal. Now the question becomes what to do with all of your available macrocells!Article: 48697
They probably should, but on the other hand if they do then those need to be
open source to convince the masses to use them. These do exist in closed source
form with the core generator (xilinx) and LPMs (altera), but there is no access
to the source. After disecting several of them, I came away with the impression
that at least some of these cores are not very carefully optimized, and many
times don't do exactly what you want. In the end, it was easier for use to
write our own library for these type of functions so that we had control over
it.
Several years back, Xilinx had a library of macros in schematic form. Those
were easier to get inside and modify if needed. It turned out that many of
those macros could be improved significantly with a little more attention to the
architecture of the FPGA. Nowadays, most folks are not using these simple
macros because it is easier (and more portable) to just leave it to the
synthesis tools even if the results are not optimal.
Ralph Mason wrote:
> It seems that the optimisers are a few year behind software ones (or perhaps
> far more complex beasts)
>
> Given that, shouldn't the vendors provide libraries of pro build items that
> are parameterised (down to the target part) in implemented in the most
> efficient way? This way upgrades / part changes shouldn't be a problem.
>
> Simple things like
>
> adders
>
> muxes
>
> ripple counters / with compare
>
> etc
>
> etc
>
> Or am I misunderstanding / over simplifying the problem.
>
> Ralph
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3DB57678.9C326F8F@andraka.com...
> > Ours has a high degree of instantiation in stuff that gets used
> alot...adders, d
> > registers, delay queues etc are all 100%. For less often used, I'll
> often use the D
> > register then use RTL to describe the LUTs in front of it and let the
> mapper worry about
> > placing them, and for some of the control logic I just go to an all RTL
> taking care to
> > keep the inputs to the logic in front each register to 4 or 5. The
> motivation of course
> > is design turn time, which includes making the design hit the timing
> goals. Once you
> > have a library of some of the basic stuff, putting together pretty
> complicated data
> > paths goes quite quickly, and in the end you have a placed component that
> you know has a
> > good shot of making timing and should be left alone by the tools.
> >
> > Goran Bilski wrote:
> >
> > > Hi,
> > >
> > > I can only agree with Ray.
> > > My coding is mostly instanciation of Xilinx primitive surrounded with
> generate
> > > statement and generics.
> > >
> > > I have also found out that it takes me roughly 5-10 minutes to write the
> above
> > > combined adder/mux using LUT,MUXCY,XORCY and generate statements.
> > > It can take me almost a day trying to foul one synthesis tool to do the
> same and I
> > > might have to redo that day when I change synthesis tool or get a new
> version.
> > >
> > > I just want most result of the effort I put in my work and that's why
> roughly 90% of
> > > MicroBlaze is directly instanciated Xilinx primitives.
> > > What I also get by instanciating the primitives is a possibility of
> controlling the
> > > placement, which is much tougher if you stick to RTL.
> > > It's extremely easy to floorplan the above module and getting maximum
> performance.
> > >
> > > Why only 90% not 100% in MicroBlaze?
> > > Sometimes I know that even the stupidest synthesis tool can't go wrong
> and it's not
> > > in a critical section.
> > > Doing large boolean expression is faster in RTL and most synthesis tool
> can handle
> > > that.
> > >
> > > Göran
> > >
> > > Ray Andraka wrote:
> > >
> > > > Jan, Ralph,
> > > >
> > > > Long time ago we got tired of pushing on the rope for every design we
> did, so we
> > > > went ahead and created a library of parameterized structurally
> instantiated
> > > > things like d registers, various flavors of adders/subtractors, delay
> queues,
> > > > etc. Easy to do in VHDL with the generate statement, a real PITA in
> verilog
> > > > without the v2000 extensions. Because of some of the things like the
> generate,
> > > > I have become something of a VHDL bigot so you'll have to excuse that.
> Usually
> > > > I could get the tools to behave with inferred stuff if I structured
> the
> > > > inference to look like the hardware, something like this:
> > > >
> > > > neg_b<= b when sub='1' else not b;
> > > > cin<= 1 when sub='1' else 0;
> > > > sum_d<= a + neg_b+cin;
> > > >
> > > > The results vary by synth and version, but this structure seems to get
> there
> > > > most of the time.
> > > >
> > > > Jan Gray wrote:
> > > >
> > > > > Ralph Mason wrote
> > > > >
> > > > > > 1. As a learning process I have copped his adder, he says that it
> turns
> > > > > > into 17 LUT's although mine ends up at 52 - Is there some
> optimizations I
> > > > > am
> > > > > > missing here? are there any pragmas you can use in these
> situations to say
> > > > > > what you want? Can you get right down to the actual LUT level and
> connect
> > > > > > them up yourself? Using the free Xilinx tools can you actually see
> the way
> > > > > > it has connected the actual LUTs?
> > > > >
> > > > > First, congratulations on going to the trouble of actually looking
> under the
> > > > > hood and *inspecting* what came out of your tools. That is a very
> good
> > > > > practice.
> > > > >
> > > > > Welcome to "pushing on a rope".
> (fpgacpu.org/usenet/rope_pushing.html: "You
> > > > > know exactly what you want -- a particular optimal, hand-mapped,
> hand-placed
> > > > > layout for your datapath -- but the tools get in the way, and you
> spend
> > > > > hours trying to discover an incantation that persuades the tools to
> emit the
> > > > > desired result.")
> > > > >
> > > > > Here the goal was to generate a+b or a-b with cin and cout at a cost
> of one
> > > > > LUT per bit. The hardware is willing, but you will need to perform
> a bit of
> > > > > experimentation to discover an expression that the synthesis tool
> will
> > > > > repeatably synthesize into the desired hardware idiom.
> > > > >
> > > > > The construction you 'copped' did work for one version of some
> synthesis
> > > > > tool once. Of course that does not mean it works reliably across
> all tools
> > > > > and all versions of all tools!
> > > > >
> > > > > I like John_H's suggestion -- it may succeed more often than the
> mux(+,-)
> > > > > that I used.
> > > > >
> > > > > BTW IIRC in this specific instance it was also necessary to move the
> single
> > > > > assignment into its own module -- the synthesis tool created the
> inefficient
> > > > > mux(+, -) form if the assignment was inline in the parent module.
> > > > >
> > > > > > 2. Floorplaning - Is there any info on this, it seems that you
> don't need
> > > > > > to do it because the tools do it automatically, I am guessing
> sometimes
> > > > > you
> > > > > > can do it better yourself to give a faster device? It looks like
> a
> > > > > > laborious process - is it?
> > > > >
> > > > > It need not be laborious, but you have to learn the ropes. It think
> we old
> > > > > timers are fortunate because we grew up doing hierarchical
> schematics, and
> > > > > so writing the same hierarchical structural HDL is familiar and
> natural.
> > > > >
> > > > > It is long past time I investigated how to do this with XST Verilog
> and
> > > > > wrote it up for my site...
> > > > >
> > > > > > 3. General - The CPU I want to design is a RISC / CISC design
> where a pre
> > > > > > processor reads CISC instructions from ram and places RISC
> instructions
> > > > > (or
> > > > > > jumps to RISC subs) to do the same them in an internal pipeline
> for a
> > > > > RISC
> > > > > > internal cpu ( or perhaps many instances of the same RISC cpu and
> a single
> > > > > > pre processor to provide a kind of hardware multithreading) - Is
> there any
> > > > > > notes on existing designs like this that one could read.
> > > > >
> > > > > Interesting. If the "preprocessor" is hardware, this was done in
> e.g. Intel
> > > > > P6, in the AMD K6, in some VAX implementations, and so forth. If
> the
> > > > > "preprocessor" is software, this was done in e.g. SoftWindows,
> Digital's
> > > > > FX!32 and Transmeta. There's lots in the library (see e.g. IEEE
> Micro) and
> > > > > in Google! (Also time to update my resources/book section of my
> site.)
> > > > >
> > > > > Jan Gray, Gray Research LLC
> > > >
> > > > --
> > > > --Ray Andraka, P.E.
> > > > President, the Andraka Consulting Group, Inc.
> > > > 401/884-7930 Fax 401/884-7950
> > > > email ray@andraka.com
> > > > http://www.andraka.com
> > > >
> > > > "They that give up essential liberty to obtain a little
> > > > temporary safety deserve neither liberty nor safety."
> > > > -Benjamin Franklin, 1759
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48698Foundation 2.1i supports the XC4005E part. Someone said XILINX will give you a student copy of Foundation if you are affiliated with an educational institution. "Mauro Pintus" <triac11@yahoo.com> wrote in message news:<lw1t9.29916$dj7.189247@tornado.fastwebnet.it>... > Hi, I need to configure an old FPGA XC4005E, but in the WebPack is not > present (i've tried 4.2 and 3.3 version). > Any one know witch is the program that i have to use and where i can find > it? > > Thanks > MauroArticle: 48699
If you have a mif file, you can save it out to a hex file from within the Quartus II Memory editor. Open the file in the memory editor and then using the menu do File->Save As and select a Save as Type of Hexadecimal. - DS "Sudip Saha" <sudip.saha@philips.com> wrote in message news:ee79cf6.-1@WebX.sUN8CHnE... > Hi, > I have created through quartus .mif files for a lpm_rom(altera devices). > While simulating it in modelsim I am getting error as "Not a proper intel hex file". > Any clue why is not taking .mif file? > When I gave .hex file as initialization file, the simulation is correct. > But I want to create a hex file of 10kb. So it is very difficult to write all the data in hex file editor of quartus one by one.. > Any body can give me solution how to create a .hex file with my own hex data ?
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