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You can use a physical synthesis tool like Amplify and generally get enough improvement to save a speed grade. This is true for RTL code. If you are instantiating and placing everything then you may be done. - Ken Patrick Loschmidt wrote: > hamish@cloud.net.au schrieb: > >> I've done 700Mbs rate (350 MHz clock) in VirtexII-5 in my own code. It's >> not all that difficult to do; just keep the levels-of-logic down and >> hand place the flip flops to remove any chance of the placing letting >> you down. I never tried for any faster. > > > I reached the same rate and to my opinion it is not possible to get a > faster design due to the routing delays which are limited by the speed > grade. > > Regards, > Patrick >Article: 48751
If you were using an Altera part with its PLL then you could just bring the 24MHz into the chip, and have the PLL pump it up to 120MHz, edge aligned to your input clock. This is one of a couple of areas where a PLL can do something a DLL cannot. President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- "Jamie Morken" <jmorken@shaw.ca> wrote in message news:<CDjt9.554967$v53.23415152@news3.calgary.shaw.ca>... > Hi, > > > Any programmable device can divide 120 MHz by five inside the chip. > > Xilinx Virtex devices have a built-in delay-locked loop (DLL) circuit that > > can divide the clock by 5 ( and also many other values) and guaranteed > that > > the 24 MHz output edges are synchronous and coincident ( within <100 ps) > with > > the incoming 120 MHz rising clock edge. > > Without using the DLL or DCM your derived clock will trail the input clock > by > > 1 to 2 ns. (clock-to-Q plus some routing) > > I should have mentioned that the 24MHz clock is used by the device that is > going to program the > Xilinx part, so I can't use the Xilinx chip as the divide by 5. Would a > 7490 (4 flipflops) work > to do this divide by 5? Which series of 7490 would be best for low clock > skew? > > cheers, > Jamie MorkenArticle: 48752
I'm about to use a Xilinx CoolRunner CPLD (running at ~30uA) and am wondering what the best way is to measure the power consumption. I'm looking for something relatively simple, which doesn't need to be extremely accurate. Can I just measure the current draw across all the VCC inputs and multiply those by VCC? What is the easiest circuit to do this, since the currents will be so low - a BJT current amplifier? Thanks!Article: 48753
John wrote: > > I'm about to use a Xilinx CoolRunner CPLD (running at ~30uA) and am > wondering what the best way is to measure the power consumption. I'm > looking for something relatively simple, which doesn't need to be > extremely accurate. Can I just measure the current draw across all the > VCC inputs and multiply those by VCC? What is the easiest circuit to > do this, since the currents will be so low - a BJT current amplifier? > Thanks! The least intrusive method is to measure the Icc before the regulator, - this avoids any IR drop across the current sensing, but does include the regulator quiescent current - works best with a regulator designed for current sense. An alternative is to use a low value series resistor, but you need to watch peak currents, and keep the IR drop down. eg 10 ohms will drop 250mV at 25mA, and gives 300uV at 30uA We have also used resistors in parallel with Schottky diodes ( limits the peak Icc IR drop ), but the cost is reduced higher current accuracy. A rail-rail Opamp can be used to amplify this to average-multimeter ranges. -jgArticle: 48754
Just having bragged about how nice and non-commercial we are in this newsgroup, and I already have to launch a commercial: Virtex-II ( and Pro ) can also multiply the incoming clock by any integer number up to 32. It may be more mysterious to understand the DCM functionality, but it does this job just fine... Peter Alfke, Xilinx Applications ============================== Jay wrote: > If you were using an Altera part with its PLL then you could just > bring the 24MHz into the chip, and have the PLL pump it up to 120MHz, > edge aligned to your input clock. This is one of a couple of areas > where a PLL can do something a DLL cannot. > > President, Quadrature Peripherals > Altera, Xilinx and Digital Design Consulting > email: kayrock66@yahoo.com > http://fpga.tripod.com > ----------------------------------------------------------------------------- > > "Jamie Morken" <jmorken@shaw.ca> wrote in message news:<CDjt9.554967$v53.23415152@news3.calgary.shaw.ca>... > > Hi, > > > > > Any programmable device can divide 120 MHz by five inside the chip. > > > Xilinx Virtex devices have a built-in delay-locked loop (DLL) circuit that > > > can divide the clock by 5 ( and also many other values) and guaranteed > > that > > > the 24 MHz output edges are synchronous and coincident ( within <100 ps) > > with > > > the incoming 120 MHz rising clock edge. > > > Without using the DLL or DCM your derived clock will trail the input clock > > by > > > 1 to 2 ns. (clock-to-Q plus some routing) > > > > I should have mentioned that the 24MHz clock is used by the device that is > > going to program the > > Xilinx part, so I can't use the Xilinx chip as the divide by 5. Would a > > 7490 (4 flipflops) work > > to do this divide by 5? Which series of 7490 would be best for low clock > > skew? > > > > cheers, > > Jamie MorkenArticle: 48755
Dear All, I could not instantiate Xilinx 16 point FFT Core in schematic. Anyone have a working example of the 16 point FFT in schematics? Thanks in advance.Article: 48756
As long as the regulator chip current limits and not current foldbacks it really is not to much of a problem for simple single FPGA circuits. For multiple FPGA systems you may need to get a little tricky such as powering one FPGA at a time (sequentially). I used the LT1763 series regulator from linear technology with absolutely no problem on a Spartan2E. Theron Hicks "Geoffrey Furman" <geoff_furman@iisvr.com> wrote in message news:urdv6qkh82hlfb@corp.supernews.com... > Does anyone have real world experience with this. The spec is outrageous > for the SpartanII / IIE /Virtex families. > I could get no detailed information from Xilinx which helped. > I build low power systems with very tight packaging constraints and don't > believe that it is possible to power up one of these devices. > > Please comment on your successes and failures. This issue needs to be > brought out in the open > >Article: 48757
You can use Synplify 4.0.8/a (from the mid 90's, extremely buggy, only runs on a Sun, last version to support XC4000*) and Xilinx XACT (Y2K incompliant, only runs on an HP, last version to support XC4000*). This is what they STILL use at Lockheed Martin/BAE Systems when configuring XC4000s. Or you can throw them in the trash and use Atmel's clone and some real software. Atmel even promises to support their products, not just have buyers beta-test them and then get left in the cold. You can even call Atmel tech support, a HUMAN will answer on the first ring**, and have a software patch made for you and emailed to you in days!!! I swear! I almost fainted. * Versions after this may support XC4005E, I only tested for XC4000 ** I haven't tested this in the last 6 months, your milage may vary "Mauro Pintus" <triac11@yahoo.com> wrote in message news:<lw1t9.29916$dj7.189247@tornado.fastwebnet.it>... > Hi, I need to configure an old FPGA XC4005E, but in the WebPack is not > present (i've tried 4.2 and 3.3 version). > Any one know witch is the program that i have to use and where i can find > it? > > Thanks > MauroArticle: 48758
Does anyone have real world experience with this. The spec is outrageous for the SpartanII / IIE /Virtex families. I could get no detailed information from Xilinx which helped. I build low power systems with very tight packaging constraints and don't believe that it is possible to power up one of these devices. Please comment on your successes and failures. This issue needs to be brought out in the openArticle: 48759
agree you should be aware of the potential problems here, but I have not seen a problem in real life. I have powered 18 v300e devices from a 12 amp dc/dc device without problems - the large bulk caps took the strain during config, as long as the supply limits in a sensible fashion. /MikeJ "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:ap73he$1d2n$1@msunews.cl.msu.edu... > As long as the regulator chip current limits and not current foldbacks it > really is not to much of a problem for simple single FPGA circuits. For > multiple FPGA systems you may need to get a little tricky such as powering > one FPGA at a time (sequentially). I used the LT1763 series regulator from > linear technology with absolutely no problem on a Spartan2E. > > Theron Hicks > > "Geoffrey Furman" <geoff_furman@iisvr.com> wrote in message > news:urdv6qkh82hlfb@corp.supernews.com... > > Does anyone have real world experience with this. The spec is outrageous > > for the SpartanII / IIE /Virtex families. > > I could get no detailed information from Xilinx which helped. > > I build low power systems with very tight packaging constraints and don't > > believe that it is possible to power up one of these devices. > > > > Please comment on your successes and failures. This issue needs to be > > brought out in the open > > > > > >Article: 48760
MikeJ wrote > I have powered 18 v300e devices from a 12 amp dc/dc device without > problems - the large bulk caps took the strain during config, as long as the > supply limits in a sensible fashion. MikeJ - this was probably a typo, but the problem is _before_ config, during power-up.Article: 48761
Thank you everybody for your quick and excellent answer.
I've found Foundation on the Xilinx web pages, but it is not free like the
WebPack
Is it possible to find a limited or shareware version of Foundation,
downloadable from the web or that is the only available?
Thanks again
Ciao
Mauro
--
--
Mauro Pintus
www.geocities.com/triac11
--
"Seth" <skintigh@yahoo.com> ha scritto nel messaggio
news:ab6e8fe6.0210231421.ef0d4e7@posting.google.com...
> You can use Synplify 4.0.8/a (from the mid 90's, extremely buggy, only
> runs on a Sun, last version to support XC4000*) and Xilinx XACT (Y2K
> incompliant, only runs on an HP, last version to support XC4000*).
> This is what they STILL use at Lockheed Martin/BAE Systems when
> configuring XC4000s.
>
> Or you can throw them in the trash and use Atmel's clone and some real
> software.
>
> Atmel even promises to support their products, not just have buyers
> beta-test them and then get left in the cold. You can even call Atmel
> tech support, a HUMAN will answer on the first ring**, and have a
> software patch made for you and emailed to you in days!!! I swear! I
> almost fainted.
>
> * Versions after this may support XC4005E, I only tested for XC4000
> ** I haven't tested this in the last 6 months, your milage may vary
>
> "Mauro Pintus" <triac11@yahoo.com> wrote in message
news:<lw1t9.29916$dj7.189247@tornado.fastwebnet.it>...
> > Hi, I need to configure an old FPGA XC4005E, but in the WebPack is not
> > present (i've tried 4.2 and 3.3 version).
> > Any one know witch is the program that i have to use and where i can
find
> > it?
> >
> > Thanks
> > Mauro
Article: 48762
That is not entirely true. The VIrtexII DCM has the capability of multiplying a clock by an arbitrary integer
up to 32x, and yet it is a DLL not a PLL. The main disadvantage of a DLL is that it does not smooth out jitter
the way a PLL does. On the advantage side, unlike a PLL, it is strictly digital so it is nowhere near as
sensitive to power supply and parasitics as the PLL is. The DLLs in earlier Xilinx parts were restricted to 2x
and 4x for multiplication and divide by a range of values including 1.5 and 2.5.
Jay wrote:
> If you were using an Altera part with its PLL then you could just
> bring the 24MHz into the chip, and have the PLL pump it up to 120MHz,
> edge aligned to your input clock. This is one of a couple of areas
> where a PLL can do something a DLL cannot.
>
> President, Quadrature Peripherals
> Altera, Xilinx and Digital Design Consulting
> email: kayrock66@yahoo.com
> http://fpga.tripod.com
> -
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48763I don't think you tested very much. There never was a 4.x version of Synplify, we skipped from 3.x to 5.x because of beliefs in Asia about the number 4. The current version of Synplify supports XC4000 and XC3000 designs. - Ken Seth wrote: > You can use Synplify 4.0.8/a (from the mid 90's, extremely buggy, only > runs on a Sun, last version to support XC4000*) and Xilinx XACT (Y2K > incompliant, only runs on an HP, last version to support XC4000*). > This is what they STILL use at Lockheed Martin/BAE Systems when > configuring XC4000s. > > Or you can throw them in the trash and use Atmel's clone and some real > software. > > Atmel even promises to support their products, not just have buyers > beta-test them and then get left in the cold. You can even call Atmel > tech support, a HUMAN will answer on the first ring**, and have a > software patch made for you and emailed to you in days!!! I swear! I > almost fainted. > > * Versions after this may support XC4005E, I only tested for XC4000 > ** I haven't tested this in the last 6 months, your milage may vary > > "Mauro Pintus" <triac11@yahoo.com> wrote in message news:<lw1t9.29916$dj7.189247@tornado.fastwebnet.it>... > >>Hi, I need to configure an old FPGA XC4005E, but in the WebPack is not >>present (i've tried 4.2 and 3.3 version). >>Any one know witch is the program that i have to use and where i can find >>it? >> >>Thanks >> Mauro >>Article: 48764
Hi, I went to yahoo for "Lecture I2C Bus" and it returned me a bunch of french websites. Has anyone seen a good decent lecture notes on I2C bus? Thanks.Article: 48765
It depends. Using a Xilinx part, the number of merit is what percentage of your slices contain unrelated logic. If that number is high, then yes, you're probably too full. As was mentioned, you run the risk of not having the flexibility of fixing your bugs. But you're also making it very difficult to meet timing because your route delay may begin to dominate your timing budget. Ideally, I'm comfortable using about 80% of the chip and I try to size new designs to that spec. Our early Xilinx designs were 99% full with about 50-60% of the cells containing unrelated logic. We can't touch it. Every attempt to fix one small thing or another ended in failure because it's just too full. Another design is about 96% full however it has no slices with unrelated logic and it's been very flexible. These are also xcv600 size parts so those couple percent can mean a lot of gates/slices. But as your chip fills up, look at your static timing to see what the trade off between logic delays and route delays. You want to keep the ratio around 50-50. jason. joefrese@hotmail.com (Joe Frese) wrote in message news:<c176b8c2.0210230728.7c22fc87@posting.google.com>... > i have a completed fpga design that is implemented on a spartan2 > xc2s200. the design uses 96% of the part, and the suggestion has been > made that as such the part is "too full" and that perhaps i should > consider moving to a larger part (the 300e, to be precise). > > i'm curious: is this a common practice, to move to a larger part when > a certain percentage of the current device has been utilized? if so, > what's the maximum percentage of a part that one should feel > comfortable using? or, is it common and/or acceptable to ship a > product that features 99-100% fpga utilization? > > thanks in advance for your input. > > joeArticle: 48766
Hi BB, I want to design a 44780 chip first.... It is a very common LCD controller/driver. It is a low-end chip. http://ertw.dhis.org/Datasheets/LCD/LCD_44780.pdf I agree with Allan Herriman. LCD need high voltage for high mux display (~20V) It seems that FPGA cannot handle this.... Moreover, temperature compensation for LCD driver is another important topic..... So....general, it seems that FPGA does not provide a one chip solution for LCD driver... (FPGA may able to handle low-end LCD driver....) I think that I should do in this way......I think that LCD driver = digtial part (eg. MCU) + Analog parts. I try to implement the digital part by fpga and do analog by other analog ic.... Reala "Blackie Beard" <BlackBeard@FearlessImmortalWretch.com> wrote in message news:kFBt9.5662$wm6.3300@nwrddc01.gnilink.net... > Hi Reala; > > Can you send a link to the data sheet of the LCD > you are using, so I know whether it's what I'm > thinking about, or not? We may be talking apples > and oranges. Thanks, > > BB > > ==================================== > > "Reala" <-> wrote in message news:ap5qad$l8r237@imsp212.netvigator.com... > > Thank you for all of your quick reply. > > I am very happy if you can share the code with me. My email is > > realareala@yahoo.com.hk > > Thank you. > > > > ar...for my understanding, LCD is driven by AC , because DC will damage > the > > LCD. > > For simple LCD (eg. 7-segment, TN), we need 5V and 0V for On/OFF only. > > So, it seems that it is no a problem to implement by FPGA. However, i do > not > > have any experience about design LCD driver/controller, so I want to find > > some resources about this. > > > > For higher mux LCD (128x64, STN Scheme B), it may be driven by output > > pin(connected to > > LCD) with 4 different voltages (eg. 5V, 3V, 2V, 0V). > > (I means that the output pin output 4 different voltages) > > Can the FPGA output pin different voltages? It seems not? > > > > Moreover, for high speed operation (update 128 X 64 X 50 pixel per sec > > 50hz frame frequency). It may be a problem because we turn on and off the > > pixel..... > > I am not sure the output pin of FPGA can handle this or not...^_^ > > > > Reala > > "Blackie Beard" <BlackBeard@FearlessImmortalWretch.com> wrote in message > > news:tCpt9.512$IU6.334@nwrddc03.gnilink.net... > > > OK, let me see. Reala wrote he needs to > > > drive some bias voltage, and Ray says that > > > with LCDs, you have to make sure you don't > > > apply any DC bias. You must be talking two > > > different things. If you do need to drive a DC > > > bias, and it's not something that could cause > > > critical failure, I suppose you could control > > > the duty cycle into an RC network. Usually > > > the analog control is adjusted one time and > > > left, though. I've done an alphanumeric LCD > > > module that boots the controller chip and > > > accepts commands, if you want some code > > > for that, let me know... It's parameterized > > > for oscillator speed (most AN LCD's are > > > very slow). > > > > > > BB > > > =============================== > > > > > > "Ray Andraka" <ray@andraka.com> wrote in message > > > news:3DB60BF8.3813828C@andraka.com... > > > > Yes you can. Basically with LCDs, you have to make sure you don't > apply > > > any > > > > DC bias. What that means is that you drive both sides of the element > > > > alternately. An xor arrangement usually works fine for this. > > > > > > > > Reala wrote: > > > > > > > > > Is this possible to implement a LCD driver/controller by FPGA? > > > > > According to my understanding, LCD driver have some Analog part (eg. > > the > > > > > output pin for driving the LCD, Bias voltage). It seems that it is a > > > > > problem. > > > > > > > > > > Is there any example about the LCD driver design which it can find > in > > > the > > > > > internet? > > > > > > > > > > Thanks ^_^ > > > > > > > > -- > > > > --Ray Andraka, P.E. > > > > President, the Andraka Consulting Group, Inc. > > > > 401/884-7930 Fax 401/884-7950 > > > > email ray@andraka.com > > > > http://www.andraka.com > > > > > > > > "They that give up essential liberty to obtain a little > > > > temporary safety deserve neither liberty nor safety." > > > > -Benjamin Franklin, 1759 > > > > > > > > > > > > > > > > > > > > > > > > > > > >Article: 48767
Hi, I have posted gerbers on my website if anyone wants to roll their own. I have used these files to build a working Altera FPGA programmer cable. However... the files on this page are offered with absolutely no warantee or support. Use them at your own risk. http://home.teleport.com/~scd/free.htm Regards, Scott L BakerArticle: 48768
Dear all, I have a question on Xilinx Virtex2 LVDS buffer. The device has two voltage types of LVDS output buffer that is OBUF**_LVDS**_33 and OBUF**_LVDS**_25. The suffix 33 and 25 show Vcco values(3.3V and 2.5V respectivly) What is the difference between them and do the both buffers fit in AC/DC characteristics of LVDS standard? (The only difference is the value of Vcco and I don't need to consider which should be used in corresponding to LVDS standard??) I would appreciate hearing replies. Sincerely, HiroArticle: 48769
Sounds like you figured out that it doesn't. No big surprize. SH7 On Wed, 23 Oct 2002 18:45:54 GMT, eda_dude <dont@reply.net> wrote: > >Does XST support Verilog2001? >Article: 48770
This is not true. The current synplify tools can compile to XC4000 and 4000e. 4000E is also still supported
in the xilinx tools. For 4000, you need to go back to XACT6, which does in fact run on a PC. It ran under
win3.1, but if you skip the GUIs it will run under windows95 and 98.
Finally, Atmel's AT40K is NOT a clone of the Xilinx 4K, not by any stretch of the imagination. They made it
so that the device could be physically plugged into a 4000 socket, but that is about where the similarity
ends. The internal architecture is very different...no carry chains, no LUT RAMs (small memories instead,
IIRC they are 32x4 memories, 1 per 4x4 tile of LUTs), but it does support partial reconfiguration.
Seth wrote:
> You can use Synplify 4.0.8/a (from the mid 90's, extremely buggy, only
> runs on a Sun, last version to support XC4000*) and Xilinx XACT (Y2K
> incompliant, only runs on an HP, last version to support XC4000*).
> This is what they STILL use at Lockheed Martin/BAE Systems when
> configuring XC4000s.
>
> Or you can throw them in the trash and use Atmel's clone and some real
> software.
>
> Atmel even promises to support their products, not just have buyers
> beta-test them and then get left in the cold. You can even call Atmel
> tech support, a HUMAN will answer on the first ring**, and have a
> software patch made for you and emailed to you in days!!! I swear! I
> almost fainted.
>
> * Versions after this may support XC4005E, I only tested for XC4000
> ** I haven't tested this in the last 6 months, your milage may vary
>
> "Mauro Pintus" <triac11@yahoo.com> wrote in message news:<lw1t9.29916$dj7.189247@tornado.fastwebnet.it>...
> > Hi, I need to configure an old FPGA XC4005E, but in the WebPack is not
> > present (i've tried 4.2 and 3.3 version).
> > Any one know witch is the program that i have to use and where i can find
> > it?
> >
> > Thanks
> > Mauro
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48771As far as I know they work identically. It just gives you the option of using LVDS in a bank that has its VCCO at 2.5V or at 3.3V. They both maintain the 1.2V common-mode voltage on outputs, and have the same swing (whose peak is less than 2.5V). I think that for inputs the IOB is powered by VCCAUX. In either case, since the peak voltage is less than 2.5V, it will work for inputs. By the way, I believe that the latest software supports differential DCI, so LVDS inputs will be terminated right at the pads (if DCI is enabled). Bob "hiro" <hiro-ta@pd6.so-net.ne.jp> wrote in message news:ap7n53$oao$1@news01cb.so-net.ne.jp... > Dear all, > > I have a question on Xilinx Virtex2 LVDS buffer. > The device has two voltage types of LVDS output buffer > that is OBUF**_LVDS**_33 and OBUF**_LVDS**_25. > The suffix 33 and 25 show Vcco values(3.3V and 2.5V respectivly) > > What is the difference between them and do the both buffers fit in > AC/DC characteristics of LVDS standard? > (The only difference is the value of Vcco and I don't need to consider > which should be used in corresponding to LVDS standard??) > > I would appreciate hearing replies. > > Sincerely, > > Hiro >Article: 48772
Hi folks, I am doing some research into the Microblaze architecture - Xilinx doco states that there is no operating system support - it seems they (for now) expect microblaze to run a monolithic application. I've looked around but not found anything substantial - does anybody know about any operating system ports to microblaze, either free or otherwise? I found a press release from Xilinx and Wind River talking about vxWorks, but no further mention of it on either's website. I'd love to hear about any budding linux / uClinux / other ports, or indeed any microblaze developers' mailing lists and resources etc. thanks, JohnArticle: 48773
You don't need the 74xxx244 bus driver as long as the cable is short enough. My simple download cable is about one meter long (about 3 feet) and uses only 5 resistors, but my solution has a tiny disadvantage. When the download is done, it appears in MaxPlus-II a window with an OK-button, what informs you about a successful download. If you press it, the configuration get lost, so just dont do that and everything will work fine.Article: 48774
On Wed, 23 Oct 2002 11:48:59 +0200, "Noddy" <g9731642@campus.ru.ac.za> wrote: >I am a bit confused with all of this, or perhaps it is just the type of LCD >display that is being used. The one that I have used in the past (attached >to a microcontroller) runs off a 5 volt DC supply and has a small >microcomputer on board which accepts commands loaded into its instruction >register... non multiplexing. Each digit has a memory space which you write >data to. No need for any square wave inputs... or am I just barking at the >wrong end of the stick? The interface we've been discussing is on the *other* side of the controller chip, i.e between it and the actual display. Regards, Allan. >adrian > > >> >OK, let me see. Reala wrote he needs to >> >drive some bias voltage, and Ray says that >> >with LCDs, you have to make sure you don't >> >apply any DC bias. You must be talking two >> >different things. >> >> >If you do need to drive a DC >> >bias >> >> No, this is never done as it damages the LCD. Reala's "bias" is the >> supply voltage for the drivers. It determines the p-p voltage applied >> to the LCD. There is no DC component. >> >> For a non-multiplexed (or direct drive) LCD, the backplane is driven >> with a square wave, and the individual segments are driven with a >> square wave that is either in phase or out of phase with the backplane >> drive to turn the segment on or off respectively. As Ray suggested, >> this is done with an XOR per segment. >> The contrast is determined by the p-p voltage, but for non-multiplexed >> LCDs the voltage usually isn't that critical. >> It may be feasible to drive this sort of LCD from an FPGA. >> >> For a multiplexed LCD, there are multiple backplanes and multiple >> segment lines. There are multiple voltage levels (typically 4 levels, >> e.g. at 0V, vbias/3, 2*vbias/3 and vbias) used on both the backplanes >> and the segment lines. >> It is not feasible to drive this sort of LCD from an FPGA. >> As Jim suggested, the Philips LCD driver datasheets have good >> information, e.g.: >> http://www.semiconductors.philips.com/acrobat/datasheets/PCF8576C_7.pdf >> >> Large dot matrix displays require a multiplexing ratio so high that >> the contrast is unusably low. This led to the development of TFT >> displays, which have an individual driver for each (non-multiplexed) >> pixel. >> >> Regards, >> Allan. >> >> >, and it's not something that could cause >> >critical failure, I suppose you could control >> >the duty cycle into an RC network. Usually >> >the analog control is adjusted one time and >> >left, though. I've done an alphanumeric LCD >> >module that boots the controller chip and >> >accepts commands, if you want some code >> >for that, let me know... It's parameterized >> >for oscillator speed (most AN LCD's are >> >very slow). >> > >> >BB >> >=============================== >> > >> >"Ray Andraka" <ray@andraka.com> wrote in message >> >news:3DB60BF8.3813828C@andraka.com... >> >> Yes you can. Basically with LCDs, you have to make sure you don't >apply >> >any >> >> DC bias. What that means is that you drive both sides of the element >> >> alternately. An xor arrangement usually works fine for this. >> >> >> >> Reala wrote: >> >> >> >> > Is this possible to implement a LCD driver/controller by FPGA? >> >> > According to my understanding, LCD driver have some Analog part (eg. >the >> >> > output pin for driving the LCD, Bias voltage). It seems that it is a >> >> > problem. >> >> > >> >> > Is there any example about the LCD driver design which it can find in >> >the >> >> > internet? >> >> > >> >> > Thanks ^_^ >> >> >> >> -- >> >> --Ray Andraka, P.E. >> >> President, the Andraka Consulting Group, Inc. >> >> 401/884-7930 Fax 401/884-7950 >> >> email ray@andraka.com >> >> http://www.andraka.com >> >> >> >> "They that give up essential liberty to obtain a little >> >> temporary safety deserve neither liberty nor safety." >> >> -Benjamin Franklin, 1759 >> >> >> >> >> > >> > >> > >
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