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Hi,
Thank you very much for your reply.Do you mean Bx, BY act as
Data lines when initializing the LUT RAMs?Bx,BY can also be signal lines
during execution if you look at F5 and F6 mux.
That means during initialization,BX,BY are data lines.During execution
time,BX,BY are signal lines.Am I correct?BTW,what's the function of A4?
What do DG,DI A4 mean in the LUT control logic?I know D stands for
Data.But what's G?
I guess the function of the LUT control logic is:
When SR is high,both WEs in the LUT blocks are high.Then BX/BY
send out data through DG/DI to LUT.
sincerely
-------------
Kuan Zhou
ECSE department
On 23 Nov 2002, Muthu wrote:
> Kuan Zhou <zhouk@rpi.edu> wrote in message news:<Pine.SOL.3.96.1021122214053.15861A-100000@vcmr-86.server.rpi.edu>...
> > Hi,
> > I am a newbie in FPGA.Currently I am looking the Virtex TM
> > 2.5V datasheet.In Figure 5 of DS003-2.pdf Page 5, there is a detailed view
> > of Virtex Slice.But I can't understand what WSO,WSH,DI,DG do in the CLB.
> > Seems like WSO and WSH provide the WE signal and DI,DG provide the data.
> > Can anyone specify these control logics to me?
> >
> > Thank you very much!
> >
> >
> >
> > sincerely
> > -------------
> > Kuan Zhou
> > ECSE department
>
> Hi,
> If you see the diagram, there is 2 inputs Bx and By. These are Data
> input pins, from which the LUTs outputs will be initialised. These
> pins will act as a data input pins if you are using the LUT as a
> SelectRAM.
>
> That 2 Block what you metioned will control this initialisation of LUT
> to a particular value / reset condition
>
> correct me if i am wrong.
>
> Best regards,
> Muthu
>
>
Article: 49901hi all, formal ot question:) is anybody onthe way/already stopping/afraid of/angry about porting the java2 jvm to a xc2s fpga for usage in embedded devices - sombody which i may work together? direction: opencores.org thanks baxArticle: 49902
You usually get this when you're passing signals between sequential elements (flops, synchronous rams) clocked by different clock domains. The best way to handle this is to not do it. Use a single high frequency clock and then enables to get lower frequency operation. Floorplanner is that last approach you want to do but can work if you artificially increase the data delay by assigning the 2 sequential elements far enough away from each other (timing wise) so that the data delay is larger than the clock skew between the 2 domains. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0211231852.33ba9a8f@posting.google.com>... > hi,all > i am a newer to fpga, and i am using QUARTUS to target > EP20k200rc240-3v. > the problem is that: when i complied the project the complication > report always gave me the message "Circuit may not operate. 12017 > non-operational path(s) clocked by clock gclk have clock skew larger > than the data delay. See the Compilation Report for details." > can you tell me what's the matter with "clock skew and data delay"? > thanks a lot!Article: 49903
well, there are mang things to do if i change to not do it. and ,However , some of my design's functions are not influenced by these errors"clock skew larger than data delay", can i let these errors alone? thank you ! kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0211241444.39f4003c@posting.google.com>... > You usually get this when you're passing signals between sequential > elements (flops, synchronous rams) clocked by different clock domains. > The best way to handle this is to not do it. Use a single high > frequency clock and then enables to get lower frequency operation. > Floorplanner is that last approach you want to do but can work if you > artificially increase the data delay by assigning the 2 sequential > elements far enough away from each other (timing wise) so that the > data delay is larger than the clock skew between the 2 domains. > > Regards > > President, Quadrature Peripherals > Altera, Xilinx and Digital Design Consulting > email: kayrock66@yahoo.com > http://fpga.tripod.com > ----------------------------------------------------------------------------- > > wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0211231852.33ba9a8f@posting.google.com>... > > hi,all > > i am a newer to fpga, and i am using QUARTUS to target > > EP20k200rc240-3v. > > the problem is that: when i complied the project the complication > > report always gave me the message "Circuit may not operate. 12017 > > non-operational path(s) clocked by clock gclk have clock skew larger > > than the data delay. See the Compilation Report for details." > > can you tell me what's the matter with "clock skew and data delay"? > > thanks a lot!Article: 49905
Hi all, I am using CLKDLLE in Virtex-E device for generating 1X and 2X outputs. Out of these clocks I want to use 1X clock offchip (as an input to a microprocessor). Current and voltage ratings match between LVTTL 12mA output pin and microprocessor clock input. My question is -- is there any other special thing to be considered because this is a DLL output? Note: I can't use original clock itself instead of 1X because it is not of exactly 50% duty cycle which I require for the microprocessor.Article: 49906
Did you go through Subroto's attachment. It describes some cases where you have clock-skew larger than data delay. In FPGAs, FPGA tools support two types of floorplanning options that I know of. One is through pin assignments and letting the tool perform the logic optimization and floorplanning. The other one is targeting some compiled block of the project into some section of the target FPGA device and optimizing in the top-level with the tool. You have to read Quartus documents in order to find out the details. I think Quartus also includes some tutorial on this. However, you had better begin with Subroto's attachment. However, it looks like you have kind of sorted out the trouble already. Subroto's attachment has some good comments about the clock skews and your exact problem. If you could let me know your solution it will be educative to me. Thanks. Kumaran siriuswmx wrote: > thank you for your reply. > Yes, i doubt of the floorplanning ,too. But you know , i am too new to > know how edit the floorplan though i have opened it amng times, can > you give me some advice ? > > Kumaran Selvaratnam <selvars@yahoo.com> wrote in message news:<3DE07B15.4020509@yahoo.com>... > >>However, I think the problem is that you are not really doing >>anything with the creation of the clock network. >>For FPGAs the clock network is pre-designed during the FPGA fabric >>design considering the external clock source as the input. >>(correct me if I am wrong) >>I think the mapping software software takes care of the clock network by >>mapping appropriate logic at certain places to achieve the best results >>for the pre-existing clock-tree. Therefore, you may have to change the >>way log blocks are mapped between different clock-tree leaves. >>I think you may get this kind of errors due to poor floorplanning as well. >>Good luck. >>Kumaran >> >>Subroto Datta wrote: >> >> >>>Timing Analysis using Quartus is covered in detail in the following >>>Application Note: >>> >>>http://www.altera.com/literature/an/an123.pdf >>> >>>Typically when conditions like this occur, it is an indication that there >>>are setup or hold time violations. One way of minimizing clock skew is to >>>assign the clock to a global clock. >>> >>>- Subroto Datta >>> >>>Article: 49907
Hi Ray, I don't like to contradict you as I'm not a experienced fpga user, but from my hw know how it is very important and essential to have a good ground and power plane and of course a good blocking. As I noticed the XCS05 working up to 80mc, so I'm convinced that it's possible to work with self adhesive copper planes (sorry, I'm not quite sure if I use the right expression) on my bread board (with many holes, double faced, on top and bottom layer) and thin wires for the I/O's. I'm conscious that it's not the right design for a prototype pci card but its good enough for my first steps on fpga programming. In addition please could you tell me what you think about the printed board design of the following web project at: http://www.iearobotics.com/personal/juan/doctorado/jps-xpc84/jps-xpc84.html When comparing the layout with my intention of wire the fpga directly, it's not a big difference from the layout point of view? Thanks in advance for your experience. MarkusArticle: 49908
Anyone knows how to solve the following problem with ModelSim XE v5.6a? I'm trying to use the "Generate Expected Stimulation Results" for a testbench waveform. TIA. ======================================================================== # Loading C:/MODELTECH_XE_STARTER/WIN32XOEM/libswiftpli.dll # ** Error: (vsim-3193) Load of "C:/MODELTECH_XE_STARTER/WIN32XOEM/libswiftpli.dll" failed: One of the library files needed to run this application cannot be found. ... ... ... # Loading work.testbench(testbench_arch) # Error loading design Error loading design Tcl C:/Xilinx/data/projnav/__simulateAnnoTestBench.tcl detected a return code of '2' from program 'C:/Modeltech_xe_starter/win32xoem/vsim -c -do rs232_baudrategenerator_tb.ado' VSim failed to simulate annotated testbench Reason: Done: failed with exit code: 0001.Article: 49909
Hi I know I am asking alot here but can anyone point me in the direction to some source code for a PCI bridge MASTER, preferably in VHDL? I am working on a project and at times I have to take control of the PCI bus. Thanks for you time RyanArticle: 49910
"John Retta" <jretta@rtc-inc.com> wrote in message news:<argf8n$j4p$1@slb6.atl.mindspring.net>... > I have an application where I am using two CLKDLLs to generate a > 4x clock - 400 Mhz from a base of 100 Mhz. The applicable Xilinx > data sheet for Spartan IIe specifies a max Input clock frequency for > -7 speedgrade devices of 160 Mhz for CLKDLL, and 320Mhz for > CLKDLLHF. Well as i see the problem you have two CLKDLLs both of whom are operating at 2x output. For the first CLKDLL, your normal input frequency is 100 Mhz(base). It's output would be 200 Mhz(2x) which will be fed back to CLKFB of this DLL. There is no violation of the input frequency sepcification since it applies only to CLKIN pin(refer to xapp178). Now your problem lise in the second DLL. It is having a CLKIN of 200 Mhz which is what is violating the CLKIN requirement as specified in your datasheet. There is no problem with CLKFB input. you might be convinced into using CLKDLLHF as your second DLL(cascaded) but then a 2x is not aviable with a CLKDLLHF. so you are in a fix. unfortuantely i guess you cant do a 4x with the freq specs you specified. regards, Nachiket Kapre Design Engineer Paxonet Communications www.paxonet.com > > Does the max Input clock frequency refer to just the CLKIN frequency, > or does it also include the CLKFB input? > > For the second DLL, the CLKIN is 200 Mhz, but the CLKFB is 400 Mhz. > > Thanks in advance.Article: 49911
Hi, I have gone through some xilinx data sheet saying that, it is possible to acheive maximum of 60% logic delay and 40% routing delay. Can we reduce the Routing delay below 40%? Regards, MuthuArticle: 49912
Hi Subroto,
Thank you for your help. I've made several tests of scripts.
Finally, I get something which seems to work but there are points
that I still don't understand.
For example, I've made the following script and I get an back-annotated
".esf" file.
I don't understand why there is only node location assignment. Why
apex20ke_lcell aren' assigned to locations ?
It seems that the vqm file neither the BOTTOM.esf file contain apex cell
location. Is it ok ?
It's very strange as I thought that logiclock is used to prevent a new
placement and save time. Did I missed something ?
# Script for quartus2.0
# leonardo constraint on module BOTTOM : logiclock region name : llr_BOTTOM
source BOTTOM.tcl # BOTTOM.tcl is produced by leonardo
project open {./BOTTOM}
project set_active_cmp BOTTOM
cmp add_assignment "" "" "" "LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT" "On"
cmp add_assignment "" "" "" "LOGICLOCK_INCREMENTAL_COMPILE_FILE" "BOTTOM.vqm";
cmp add_assignment "" "" "" "LOGICLOCK_FITTER_TYPE" "On"
cmp start
while {[cmp is_running]} {
after 1000
FlushEventQueue
}
cmp logiclock_back_annotate "llr_BOTTOM" 1 1
project close
############################################################
Produces the following .esf file (partial file)
LOGICLOCK_REGION(llr_controleur_can)
{
LL_MEMBER_OF = llr_controleur_can;
LL_HEIGHT = 1;
LL_WIDTH = 2;
LL_ORIGIN = LAB_2_U2;
LL_STATE = LOCKED;
LL_AUTO_SIZE = OFF;
NOT_pret : LL_NODE_LOCATION = LAB_1_U2;
convstb_dup0 : LL_NODE_LOCATION = LAB_1_U2;
### Only node location ? What about cells ?
Thanks for your help.
Stephane
On Fri, 22 Nov 2002 03:36:45 +0000, Subroto Datta wrote:
> Hi Stephane,
>
> The following should help answer some of your questions.
>
> 1) Logiclock_import and logiclock_export ONLY deal with
> assignments/constraints. They are only useful when there are logiclock
> regions present.
> 2) When a VQM file is generated it is treated as though it were the top
> level, so yes there are IOs in it. In the QII 2.0 release the compiler will
> give the warnings that you are seeing wrt to IOs from the lower level; just
> ignore them. Later versions of Quartus do not issue these warnings.
>
> So, lets assume you have a lower level design: BOTTOM. And a top level
> design: TOP. TOP instantiates BOTTOM (perhaps multiple instances). When the
> user is finished working on BOTTOM, then he should use Logiclock_export to
> create a BOTTOM.ESF file which contains all the placement information and
> other constraints that were used. Also, they should generate a BOTTOM.VQM
> to preserve the synthesis.
>
> In the top level, the user should have a source file: TOP.VHD which makes
> instances of BOTTOM. To compile TOP, the user also needs to place an
> appropriate source file for BOTTOM in the TOP project directory. In this
> case they should use the BOTTOM.VQM file that was generated earlier. So the
> user should copy the BOTTOM.VQM and the BOTTOM.ESF file into the TOP project
> directory.
>
> Now they must use Logiclock_import to import the assignments/constraints
> from the BOTTOM.ESF file into the TOP.ESF file. This is accomplished by:
>
> #doing elaboration first:
>
> cmp start "analysis_and_elaboration" "analysis_and_elaboration"
>
> while {[cmp is_running]} {
> after 10
> update
> FlushEventQueue
> }
>
> #Now they run the import command
> cmp logiclock_import
>
> The project is now ready to be compiled.
>
> Hope this helps.
>
> - Subroto Datta
> Altera Corp.
>
>
Article: 49913Why don't you just use a synthesizable core? You could download a 8051 from Oregano's web page: www.oregano.at.Article: 49914
Hello everyone, I know that the operating temperatures for the commercial grade of an Altera ACEX1K device is from 0 to 70 Celsius. Can I power up the device at a lower temperature (-20? -30?) than this if I don't care about the functionnality of the logic? We're currently designing a subscriber unit that would be outside (in Canada...) and we'd like to be able to simply power up the whole board at a time to heat the systems (mostly by the RF components on the board) and hard reset everything once the system is at operating temperature. Would this cause any physical damage to the FPGA ACEX and EPROM used to program it?? Yes, I know that you would recommend using industrial grade, but we can't afford it since it's a high volume system and cost is a big factor in the success of this product. Thanks! MartinArticle: 49915
>I have gone through some xilinx data sheet saying that, it is possible >to acheive maximum of 60% logic delay and 40% routing delay. Can we >reduce the Routing delay below 40%? Maybe. How complicated is your problem? I'd try a tiny/toy test case and let the tools tell me how far I could go and still meet the timing budget. If you can't get a signal from one CLB to an adjacent one it's going to be very tough. (Try all compass directions, and maybe diagonals.) If you can go one hop, then you can build simple one-hot style state machines. For example, if you want to generate a pulse every 12 clocks, just chain 12 FFs in a row. Then you have to place them so that the key FF is where you want it. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49916
Hi John, > I'm about to use a Xilinx CoolRunner CPLD (running at ~30uA) and am > wondering what the best way is to measure the power consumption. I'm > looking for something relatively simple, which doesn't need to be > extremely accurate. Can I just measure the current draw across all the > VCC inputs and multiply those by VCC? What is the easiest circuit to > do this, since the currents will be so low - a BJT current amplifier? > Thanks! In particular, which CPLD device ? BrendanArticle: 49917
The quandary in which you find youself is repeated over and over in digital design: Should I go back and change it to make it right, or do I proceed forward with the initial approach and patch the errors as they appear. I don't know all the particulars of your situation, however, It's been my experience that you're better off going back and making it right. The rewrite is a deterministic amount of time and work, and usually proceeds faster than the initial design because after all, the hard part is the learning and at that point you've already done it, the easy part is the typing. Trying to move forward with hold violations can set you up for failure due to an unpredictable design. Unrelated changes can cause a previously working (you lucked out) circuit to cease operation or because temperature sensitive. It's tough to debug because the usual "cause and effect" way of finding problems does not seem to apply. I always try for an error free compilation, even if it means writting/changing source code with no other effect than to get rid of warning messages. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0211242015.2e44574b@posting.google.com>... > well, there are mang things to do if i change to not do it. > and ,However , some of my design's functions are not influenced by > these errors"clock skew larger than data delay", can i let these > errors alone? > thank you ! > kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0211241444.39f4003c@posting.google.com>... > > You usually get this when you're passing signals between sequential > > elements (flops, synchronous rams) clocked by different clock domains. > > The best way to handle this is to not do it. Use a single high > > frequency clock and then enables to get lower frequency operation. > > Floorplanner is that last approach you want to do but can work if you > > artificially increase the data delay by assigning the 2 sequential > > elements far enough away from each other (timing wise) so that the > > data delay is larger than the clock skew between the 2 domains. > > > > Regards > > > > President, Quadrature Peripherals > > Altera, Xilinx and Digital Design Consulting > > email: kayrock66@yahoo.com > > http://fpga.tripod.com > > ----------------------------------------------------------------------------- > > > > wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0211231852.33ba9a8f@posting.google.com>... > > > hi,all > > > i am a newer to fpga, and i am using QUARTUS to target > > > EP20k200rc240-3v. > > > the problem is that: when i complied the project the complication > > > report always gave me the message "Circuit may not operate. 12017 > > > non-operational path(s) clocked by clock gclk have clock skew larger > > > than the data delay. See the Compilation Report for details." > > > can you tell me what's the matter with "clock skew and data delay"? > > > thanks a lot!Article: 49918
> Thank you very much for your reply.Do you mean Bx, BY act as > Data lines when initializing the LUT RAMs?Bx,BY can also be signal lines > during execution if you look at F5 and F6 mux. > That means during initialization,BX,BY are data lines.During execution > time,BX,BY are signal lines.Am I correct?BTW,what's the function of A4? > What do DG,DI A4 mean in the LUT control logic?I know D stands for > Data.But what's G? > Make a design that instantiates a select RAM, such as RAM16X1S or RAM32X1S, run it through. Use the fpga_editor to view the inside of the slice, it'll give better idea on what those blocks are used for. A4 is for the MSB of input address implementing a RAM32X1S.Article: 49919
Hello, I need advice on an FPGA & evaluation board to be used with System Generator and MATLAB/Simulink. I would be most grateful if anybody could share his/her experience on the subject. My boss wants to cover a couple of research lines with this equipment, and he has decided that the FPGA must be a Virtex-II Pro for his research. I should be able to use that hardware from MATLAB to speed computations up. That would be the other line. Being a complete novice on the subject, the only eval.board I haven been able to find is http://www.insight-electronics.com/virtex2pro/ That board is not to be connected to a PCI socket, is it? Is there any Virtex-II Pro eval.board that connects to the PCI? The MathWorks' courses for System Generator use the Nallatech BenADDA daughter board. They don't explain which Nallatech motherboard is it connected to. Could System Generator be used with the Insight's board? Xilinx documentation also assumes "System Generator for DSP". There is another "System Generator for PowerPC". I think I need the latter. Is that right? For instance, in the "ISE Feature Matrix" comparing ISE Foundation to Alliance, BaseX and WebPack, "SysGen for DSP" appears as an option to all but WebPack. No mention is made to "Sysgen for PowerPC". I have a lot of questions, but I wouldn't like to frighten anyone willing to share experiences with a too lengthy list... ;-) can anyone help me? Thanks a lot for any suggestion/remark/advice/help/whatever :-) -javierArticle: 49920
Hello, i' ve some problem using Impact 4.2WP3.0 in win98SE. When i try to program the device (an XC9536) a fatal error occurs (a not valid operation occurs) and i must close the application. It's a very strange thing. What may it be? THankyou GiovanniArticle: 49921
Not a contradiction at all, besides I certainly make mistakes from time to
time. My point is that, yes, an FPGA can be successfully done in a wirewrap or
singlesided breadboard environment, BUT success may require alot of time
debugging signal and power integrity issues that the typical beginner is not
equipped to handle. Much depends on how many I/) you have switching, and how
much the power into the FPGA varies. If you only have a few I/O switching, and
you are careful to keep the power to the FPGA on low inductance runs with
bypassing right at the FPGA, plus a measure of luck, you'll likely get away
with it. If you've got lots of I/O switching, you've got a pretty poor chance
of success, especially if they all switch on the same edge.
The design is much easier, and more likely to succeed if you have a good solid
board design to avoid corrupting your results. To wit, we've had several
designs this year that have had signal and power integrity problems on
commercially produced multi-layer boards. Clock frequency has little to do
with it, rather it is edge speeds coupled with the number of I/O switching that
cause the most problems.
Markus Wolfgart wrote:
> Hi Ray,
>
> I don't like to contradict you as I'm not a experienced fpga user,
> but from my hw know how it is very important and essential to have
> a good ground and power plane and of course a good blocking.
> As I noticed the XCS05 working up to 80mc, so I'm convinced that
> it's possible to work with self adhesive copper planes (sorry, I'm
> not quite sure if I use the right expression) on my bread board
> (with many holes, double faced, on top and bottom layer) and thin
> wires for the I/O's.
> I'm conscious that it's not the right design for a prototype pci
> card but its good enough for my first steps on fpga programming.
>
> In addition please could you tell me what you think about the
> printed board design of the following web project at:
>
> http://www.iearobotics.com/personal/juan/doctorado/jps-xpc84/jps-xpc84.html
>
> When comparing the layout with my intention of wire the fpga
> directly, it's not a big difference from the layout point of view?
>
> Thanks in advance for your experience.
>
> Markus
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49922I am looking for vendors of PCI FPGA boards for production, not just prototyping. So far I know of Annapolis Microsystems which offers boards with Virtex chips and RAM. Can anyone recommend any others?Article: 49923
Hi all, When I program my spartan 2 using the ISE software using JTAG, it tells me that "programming succeeded." However, when I verify the design, it comes up with thousands of discrepancies in the design actually on the fpga. When I implement very simple logic like an AND gate, it works sporadicaly and does not work at all after shutting down the fpga. Any help or direction would be great. thanks! kyleArticle: 49924
Seth, HERON DSP Systems might be worth a look. They provide support for single or multiple FPGAs, along with options for 100MSPS+ A/D & D/A, and TMS320C6000 DSPs. http://www.traquair.com/catalog/heron.systems.html Regards, Steve. "Seth" <skintigh@yahoo.com> wrote in message news:ab6e8fe6.0211251516.2851d6bd@posting.google.com... > I am looking for vendors of PCI FPGA boards for production, not just > prototyping. > > So far I know of Annapolis Microsystems which offers boards with > Virtex chips and RAM. > > Can anyone recommend any others?
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