Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Be careful when you just look at the number of postings. (The long thread mistakenly called Xilinx webpack bugs... has really nothing to do with Xilinx) Many questions are being posted because people know that Xilinx very often can provide help or guidance in a timely fashion. Yes, Xilinx is a bigger company, with about 50% more sales than Altera, but that does not explain Altera's small presence in this newsgroup. I have needled tham many times. I consider postings about Xilinx parts and even problems a good thing. It gives us a chance to help the user community. Peter Alfke, Xilinx Applications qlyus wrote: > > Just took a look of a few pages of comp.arch.fpga Thread Subject: > > Jun 26, 2003 Xilinx Webpack bugs bugs bugs (17 articles) > Jun 26, 2003 CoreGen/Ngdbuild help (2 articles) > Jun 26, 2003 ERROR:iMPACT:583 (4 articles) > Jun 26, 2003 Addressable Register core generator (1 article) > Jun 26, 2003 Handelc, Plzzz help (1 article) P. Prasad > Jun 25, 2003 Xilinx ML300 JTAG Configuration Problem (1 article) > Jun 25, 2003 Xilinx XC3430A (2 articles) > Jun 25, 2003 Webpack 5.2i can't synthesize (1 article) > Jun 24, 2003 applying SCHMITT TRIGGER to CoolRunner-II CPLD's (2 articles) > > Xilinx related problems are overwhelming over Altera's. > > (1) Altera products are better? > (2) Altera users are smarter? > (3) Altera tech support ? > (3) Very few people use Altera (Altera market share smaller than Xilinx) ?Article: 57276
"qlyus" <qlyus@yahoo.com> ha scritto nel messaggio news:da71446f.0306260952.676b93d8@posting.google.com... > (3) Very few people use Altera (Altera market share > smaller than Xilinx) ? (5) In this specific newsgroup there is more knowledge of Xilinx devices, thanks to some Xilinx engineers who frequent it on a regular basis? The newsgroups are "self-calibrating", i.e. on the long period the questions tend to adapt to the skills of the habitual users. -- LorenzoArticle: 57277
Stephane Guyetant <sguyetan.dislikes.spam@IRISA.fr> writes:
> LUT:D=(A1*(A2*(A3*A4)))
>
> A LUT is basically a RAM with a 4bits address access so that the
> corresponding LUT should contain: 0x8000 because only one bit should be
> set to '1', the one pointed by address 0xF. Correct?
Yes. Strictly it has 7FFF in it, because the bits are inverted. But
that is hidden in any decent software.
> Now I want to change some constant and my new logical equation is for
> example D=(A1+A3). What if I parse the .BIT and write (jbits or similar)
> at the accurate location 0xCCFF?
Then it will do A1+A3, if you had the right value.
JBits is ideal for such stuff, such as in this code:
// do this once, quasi library functions
// config bit constants for abstracting position in CLB
final public static int LutFunction[][][][] =
{ { LUT.SLICE0_F, LUT.SLICE0_G },
{ LUT.SLICE1_F, LUT.SLICE1_G } };
// call the JBits stuff to do it
// Row, Col, Sli, Lut are globals, set elsewhere, could also be params
public static void lut(int Function) {
try {
Fpga.set(Row, Col, LutFunction[Sli][Lut],
Util.InvertIntArray(Util.IntToIntArray(Function, 16))); }
catch (ConfigurationException Ce) {
// pos() converts Row, Col, Sli, Lut to cccs/rrrl format string
System.out.println("Configuration exeption in lut() at " + pos());
System.out.println(Ce); } }
// constants for making up functions, computer does this for you :-)
// so A1+A3 = A1 OR A3 = I1|I3 = 0xAAAA|0xF0F0 = 0xFAFA
final public static int I1 = 0xAAAA, I2 = 0xCCCC, I3 = 0xF0F0, I4 = 0xFF00;
// do this for every LUT needing changing
// example function, a 2:1 Mux, I1 or I2, selected by I3
lut(I1&(~I3)|I2&I3);
Lots of more details of JBits usage in:
http://neil.franklin.ch/Projects/PDP-10/pdp10.java
--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith
- hardware runs the world, software controls the hardware
code generates the software, have you coded today?
Article: 57278Chris Carlen <crcarle@BOGUS.sandia.gov> wrote in message news:<bdchrq$fo1$1@sass2141.sandia.gov>... > Hi: > > I have a schematic design from Webpack 4.2 that I want to use in 5.2. I > went through the several hours of hell yesterday, finally finishing > today, figuring out how to use the new WEbpack which is a little more > convoluted than before, but I got it to work for a new test design. > > Now when I try to use my old design, it complained about the syntax in > the .ucf file, and that I should use the new .xcf format, which is > ridiculous since there is no apparent way to create this. The > constraints editor with Webpack 5.2i creates a .ucf file. > > So I even deleted my old .ucf file, and made a fresh one with the > contraints editor, and the darned program still gives the same errors: > > ========================================================================= > * HDL Analysis * > ========================================================================= > > Analyzing Entity <cross32> (Architecture <schematic>). > Entity <cross32> analyzed. Unit <cross32> generated. > > > Reading constraint file F:\xilinx\cross32\cross32.ucf. > WARNING:Xst:1574 - This style constraint file will be obsoleted in a > future release. > Please use the XCF file with a .xcf extension. > WARNING:Xst:45 - Unknown keyword: NET. > ERROR:Xst:46 - Syntax error in constraint file (line: 1). > > > My constraints file looks like this: > > NET "IO27" LOC = "p27"; > NET "IO9" LOC = "p9"; > NET "IO21" LOC = "p21"; > NET "IO40" LOC = "p40"; > etc. > > > Pretty goofy since the same exact syntax works just fine in the test > design I did to figure out how to use the Webpack 5.2i. > > What is going on here? > > > Thanks for input. The signal name in the UCF file has to be in lower case: I think that the Pin number has to be upper case. i.e. NET io27 LOC = P27 ; NET io9 LOC = P9 ; Bill HannaArticle: 57279
Paul Urbanus <urbpublic@hotmail.com> writes: > I have a design that I did almost 15 years ago that fits in a 20L10 PAL. > > I need to port this design to a 22V10, because these parts are more > readily available. > 1980s home computers. After I port the design, I'm going to release it > into the public domain so enthusiasts of this machine can modify it if > they want. To facilitate this, I'd like to make sure that whatever tool > I use to synthesize the design can be had for free. http://members.surfeu.de/matthias.prinke/electronics/galprog_e.html http://www.s-line.de/homepages/bosch/galasm/galasm.txt Both are source. Both though only support GAL16V8 and GAL20V8. Are you sure that is PAL20L10 and not PAL20L8? According to my (incomplete) data sheet collection, the only 10 output PALs were 20RA10 and 22V10. For an PAL20L8 the GAL20V8 would suffice. > I guess I could always use PALASM. Anywone if the latest version of this That seems to be the standard. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today?Article: 57280
Hello All I've been trying to configure a Spartan XL (XCS05XL) over the parallel port of my PC with my own software. I've been using the app note from Xilinx on "Configuring FPGAs Over a processor Bus". It explains how to download a .rbt (raw bit) file to the FPGA. I find that the INIT line goes low after the configuration starts. I understand that this indicates a bitstream or framing error. It occurs to me now that maybe I can't use a .rbt file to configure this specific device. Should I be using a .bit file? Does anyone know if this is the case. Thanks DenisArticle: 57281
Yes I would recommend it. We talked about this over lunch: SpartanXL is manufactured on a 0.35 micron process, which will be around for a long time. The present business seems healthy. So there is neither a technical nor a commercial reason to abandon the family. If we were to discontinue it, you get years of warning: Last buy, last ship, etc, and we then usually sign it over to an "after life" manufacturer. We still ship XC3100 and XC5200 that predate SpartanXL by several years. So, five years is a safe bet. Software is a different story, the current software does not even support it. Get an older version of our software, and keep it for your purposes. PeterAlfke, Xilinx Applications ================================== rickman wrote: > If this part were to be used in a new design, how long could we expect > it to be available? Would you recommend this part for designs that > would be in production for more than 5 years from now? > > -- > > Rick "rickman" Collins > > rick.collins@arius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57282
"Austin Lesea" <Austin.Lesea@xilinx.com> schrieb im Newsbeitrag news:3EFB0713.FEAEA82D@xilinx.com... > SpartanXL is my suggestion, > > Austin > > Arash Salarian wrote: > > > Hi, > > > > What's your suggestion for a low-power, battery operated FPGA design? What > > family do you suggest? I guess the design should need something like 20K~30K > > gates (yeah, I know this does not all that correct but I've not syntesized > > the design yet and can't give a good estimate on number of LEs or FFs...). > > From what I've seen in data-sheets, besides the power consumption, one major > > concern is the power-up and configuration current for SRAM based devices. > > Also I'd like to have the minimum number of VCC voltages on the board and > > other parts used in the design are 3.3v and can be safely run using a single > > rechargable battery with no need for DC-DC converter circuit (it means that > > they can work from 2.7v to 4.1v with no problem). > > > > Best Regards > > Arash > Spartan XL is a good product, we use the xcs20xl because of small bitstreams (compared to virtex and newer devices), which are stored in a flash based 8bit microcontroller. The build in chip oscillator and the io output mux is also very usable. The main disadvantage is, that there is no webpack support for HDL's (Verilog & VHDL). So the only way to use them with HDL's is to buy expensive 3rd party software. This fact keeps some very interested colleagues away from the fpga technology. Ok, you can argue that they should use the newer spartan2 chips. But we have hundreds of boards with spartanxl lying around... MIKEArticle: 57283
I need an FPGA board with a 64-bit 66MHz PCI bus and Linux drivers, and I need to be able to demo it, and I need it fast. If that's not demanding enough I can add more requirements. I have looked through 53 vendors so far and there are no real winners. Thanks in advance.Article: 57284
Chris Carlen wrote: > > Bob Perlman wrote: > > Hi - > > > > The this-tool-is-no-damn-good thread pops up every few weeks. I don't > > use the ECS schematic editor, so I can't comment on the its quality or > > lack thereof. And I certainly don't want to get embroiled in the > > schematics-vs-HDL debate which, along with cockroaches, will be the > > only thing to survive a nuclear holocaust. But I will make a couple > > of observations. > > > > First, use tools that have lots of users. Any tool developer will > > spend more time fixing and maintaining popular tools than those used > > only by a handful of people. And, the merits of HDLs aside, is there > > any doubt that even the least popular FPGA HDL synthesis tool has at > > least ten times as many users as ECS? I know, I know--this isn't > > fair. But that's the way it is. Unless you're Mr. Cisco, of course. > > > > Second, use only those tools that add real value. There are some > > Xilinx tools--the FPGA editor, PACE, the floorplanner--that have a > > useful GUI . In fact, these tools wouldn't make much sense without a > > GUI. But does Project Navigator really add that much value over and > > above a decent batch file that invokes tools from the command line? > > Maybe the uber-GUI that ties all the tools together makes sense for > > some users, but to me it's just one more thing that can break or do > > inexplicable things. All I'm saying is, don't use a tool just because > > it's there; the benefit should exceed the pain. > > > > And I agree - the Linear Tech SPICE tool is very nice. The fact that > > it's free doesn't hurt, either. > > Thanks for your input. > > I think I am interested in the schematic entry for a few reasons: > > 1. I am a beginner at this PLD stuff, and it is the easiest way to get > the chips to do something, without having to first learn HDL. > > 2. I am using CPLDs not FPGAs, with a heavy combinatorial emphasis, > rather than state machine, heavy FF stuff. For this reason I chose > Xilinx instead of Altera in the first place, as it seemed Altera didn't > have as nice of an offering in the CPLD department as the Coolrunner CPLDs. > > Also, I want to interface as easily as I can to 5V logic systems, and > the Coolrunner XPLA3 can do this directly, without added level > translation glue. I just use an HCT14 to convert the 3.3V drive from > the CPLD to 5V swings to send to the outside world. > > My application is somewhat wierd as well. We run engine research > laboratories, in which there is a "patch panel" of a whole bunch of BNC > connectors connected to a sampling of ANDs, ORs, etc. for gluing the > various electronic subsystems of the lab together. The scientists > frequently want to change their functionality, and sometimes want to add > special functionality that is a bit too complex for a panel with only > 20-30 gates. These "special functions" always sent me to the breadboard > to prototype something with discrete logic chips that could do it, then > I'd make a circuit board and install it somewhere on the rack space. > > I decided I wanted to build a patch panel that instead consists of a > generic matric of BNCs, that interfaces to a CPLD device of moderate > size. Then I can program the CPLD to be whatever arrangement of gates > the scientist needs, and even more complex special functions can likely > be accomodated with a few extra internal resources like a clock > generator for making digital delays to replace analog one-shots, etc. > > 3. The schematic is the only form of circuit design that the scientists > will understand, and so using schematic entry is the best way for us to > communicate, and makes the circuitry self-documenting. (In the past > things were laid out in pencil, then later drawn in a CAD program for > the lab documentation.) I think you should look at ABEL or CUPL HDL. Xilinx still offer ABEL flows, and have actually improved the handling of details in their latest WebPack. ABEL source is unchanged, but Xilinx changed some of the underlying flows, and that took a while to shake-out. ABEL is 'more direct' (syntax maps more closely to the resource) than VHDL/Verilog, and uses DOT extentions. eg : Reg.D = Sum # Of # Products; Reg.CK = ChooseCLK; Reg.CE = Reg2; Reg2.T = ToggleTerms; If you like schematics, you can think of this as a netlist. This is also very close to the eqn syntax used in the post-fit report files. ( so Source/ActualResult checking is quick) If the scientists can understand & -> AND and # -> OR, :) then they can make their own patch tables, given a template file to start with. A benefit of this, is they can NAME the nodes, with what they actually are/do, and EQN creation becomes less error prone, and easier to read than a schematic, where you have to trace to a net-tag to confirm gated signals. It is also much faster to create 'slight variants' from a commmon template. - jgArticle: 57285
"Seth" <skintigh_spam@yahoo.com> wrote in message news:65541f48.0306261249.2e82dd3f@posting.google.com... > I need an FPGA board with a 64-bit 66MHz PCI bus and Linux drivers, > and I need to be able to demo it, and I need it fast. > > If that's not demanding enough I can add more requirements. > > I have looked through 53 vendors so far and there are no real winners. > > Thanks in advance. Annapolis Micro Firebird, http://www.annapmicro.com/firebird_pci.html Bunch of stuff like the PCI speeds you require and a 1 to 2 million gate Virtex. Never tried one, though I wouldn't have to be asked twice if someone wanted me to play with one.Article: 57286
Gcaw (and other APEX 20KE users), During the checkout of the EP20K400E device we identified a problem similar to what you note. To avoid this, we recommend pulling nCONFIG low until VCCIO has reached a stable level whenever VCCINT (1.8V) is powered before VCCIO (3.3V in your case). This can be accomplished by using a power-monitoring circuit, or by using the POWER GOOD signal from the regulator if it is so equipped. Doing so prevents the high-current condition that you cite, and may be easier than switching the power-up sequencing. Powering VCCIO before VCCINT is another valid solution to this problem, as you found. We have documented these approaches on pages 96-99 of AN116: Configuring SRAM-Based LUT Devices. (http://www.altera.com/literature/an/an116.pdf) Also, please note that all Altera devices released after APEX 20KE (APEX II, APEX 20KC, Stratix, Cyclone, and so forth) do not have this restriction. On these devices VCCIO and VCCINT can be powered in either sequence. Sincerely, Greg Steinke Altera Applications gregs@altera.com gcaw99@hotmail.com (gcaw) wrote in message news:<6eb2ad89.0306231856.65f4c7de@posting.google.com>... > This is a follow-up to an email posted by Henning Trispel in July 2002 > where Henning identified a power sequencing issue with APEX 20KE > devices. > > Having spent 2 weeks trying to figure out what was wrong with my board > design I finally saw Henning's post that indicated that the VCCIO > (3.3v for me) needs to come up before the VCCCORE (1.8V). I made that > change to my board (delayed VCCCORE to come up about 50ms after VCCIO) > and it worked. > > Before making the change the EP20K400E would get very hot after about > 30 seconds after power on - far too hot to touch. Our design runs > quite cool so we knew we shouldn't need heatsinks. Of course we were > not prepared for this problem as Altera's site doesn't seem to have a > reference to it. > > Anyway, there certainly appears to be a power sequencing problem with > the EP20K400E. Hopefully this can save someone else the grief the we > have been through.Article: 57287
Lelik, Brad, The PLL in ACEX 1K devices can multiply by 1 or by 2. So while the device cannot directly generate 27 MHz from a 10 MHz clock, you could perhaps use some of the techniques mentioned by Brad in his post. Another approach would be to use Stratix devices. The Stratix PLL has a multiplier value (called m), a pre-scalar value (called n) and a post-scalar value (called g0 for the first global clock output). The Stratix PLL can generate 27 MHz from a 10 MHz input by setting m=54, n=1, g0=20. Stratix is required as the min Fin for the Cyclone PLL is 15 MHz. If you had a 15 MHz clock then the Cyclone PLL could generate a 27 MHz clock by setting m=27, n=1, g0=15. This sets the VCO to 405 MHz, the the postscalar brings it back down to 27 MHz. For either device, you do not need to compute the PLL values - if you tell Quartus the requirements it will compute the PLL settings for you. For more details on the PLL operations of these devices, please consult: Stratix: http://www.altera.com/literature/hb/stx/ch_1_vol_2.pdf Cyclone: http://www.altera.com/literature/hb/cyc/cyc_c51006.pdf Sincerely, Greg Steinke Altera Applications gregs@altera.com brad@tinyboot.com (Brad Eckert) wrote in message news:<4da09e32.0306240902.21977e0c@posting.google.com>... > lelik_bolik@hotbox.ru (Lelik Bolik) wrote in message news:<d9c9b7aa.0306232336.bbd6bd7@posting.google.com>... > > I have stable 10 MHz. Is it possible to get 27 MHz from this frequency > > using FPGA(Altera ACEX)?? And if it is then how?? Thanks for your > > answers! > > If a constant period is not important, multiply by 4 with a PLL and > multiply by 27/40 with a counter. The counter would remove almost > every other cycle of the 40 MHz. > > I think the ACEX has only one ClockBoost circuit and it multiplies by > two so you can only get 20 MHz. If so, maybe you could use a time > delay and XOR to get the 40 MHz clock. Time delays aren't a safe thing > to design in, but if you think the chips won't change too much then do > what you have to do.Article: 57288
Paul Urbanus wrote: > > I have a design that I did almost 15 years ago that fits in a 20L10 PAL. > This was written in ABEL, a PALASM like language, that was created by > Data IO (now Synario). > > I need to port this design to a 22V10, because these parts are more > readily available. This design is for a peripheral for one of the early > 1980s home computers. After I port the design, I'm going to release it > into the public domain so enthusiasts of this machine can modify it if > they want. To facilitate this, I'd like to make sure that whatever tool > I use to synthesize the design can be had for free. > > I'd prefer to use ABEL, because that would require the minimum amount of > design changes. Does anyone know if there are any old versions of ABEL > (by Data IO, now Synario) that have been released into the public > domain? If not, can anyone recall what form of copy protection, if any, > was used on the old DOS versions. > > I know that Cypress has their Warp VHDL compiler for simple PALs, > including the 22V10. But, it still costs about $100. Are any of the > earlier versions available for free? > > I guess I could always use PALASM. Anywone if the latest version of this > tool supports the 22V10? And where can I find it? > > Or, are there other options I'm not aware of. Your simplest path is to use Atmel's WINCUPL. This is not part of a much larger suite, so is much smaller/simpler to deploy. ABEL still exists, and Xilinx have that flow, as do Lattice, but you are getting closer to 1GByte of footprint. -jgArticle: 57289
Jim Granville wrote: > I think you should look at ABEL or CUPL HDL. > Xilinx still offer ABEL flows, and have actually improved the > handling of details in their latest WebPack. > ABEL source is unchanged, but Xilinx changed some of the > underlying flows, and that took a while to shake-out. What do you mean by "still offer?" It sounds like this is a dying breed or something. Perhaps you can enlighten me a bit more about the history of ABEL vs. other HDLs, and it's current usage in the PLD world? > ABEL is 'more direct' (syntax maps more closely to the resource) > than VHDL/Verilog, and uses DOT extentions. eg : > > Reg.D = Sum # Of # Products; > Reg.CK = ChooseCLK; > Reg.CE = Reg2; > Reg2.T = ToggleTerms; > > If you like schematics, you can think of this as a netlist. This is interesting. > If the scientists can understand & -> AND and # -> OR, :) then > they can make their own patch tables, given a template file to > start with. Some of them (the ones who don't know anything exists beyond an AND and OR gate) are criticising me for not still doing everything with wire-wrap and TTL. Not a very progressive bunch. Fortunately, most of them are into progress, but others not. I think schematics are really needed for them in general. But if I can produce the time to learn an HDL in the near future, I will consider ABEL. Thanks for the input. Good day! -- _______________________________________________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.Article: 57290
Iam currently working on IDE interface for VirtexII chips. I just used the Translation Voltage Clamp devices from TI. Look for TVC Logic Family on the TI website. http://focus.ti.com/docs/logic/catalog/overview/overview.jhtml?templateId=5043&path=templatedata/cm/ovw/data/tvc_overview They work well and without any problem. I have used them at UDMA 4 speeds. Brijesh Ed Stevens wrote: > Hi, > > I need to interface an IDE hard drive to a Spartan2E. The trouble is the > Spartan2E works at 3.3V and the signals coming out of the IDE hard drive are > 5V. Does anyone know a simple method to get around the voltage problem? I > don't suppose the Spartan2E could tollerate a 5V input? > > I found a company called BurchEd which sells an IDE interface to a Spartan2E > evaluation board. Looking at the picture of the IDE interface it has no > logic between the hard drive and the Spartan2E. How do they do it? > > Thanks for any help, > >Article: 57291
Program Announcement and Registration Open
6th MAPLD International Conference
Ronald Reagan Building and International Trade Center
Washington, D.C.
9-11 September 2003
Over 110 papers on programmable devices and technologies and
related aspects of digital engineering will be presented at
the 6th Military and Aerospace Programmable Logic Devices
(MAPLD) International Conference.
This year, there will be special emphasis on the following themes:
• Reliability of Hardware and Designs; Fault Tolerance
• Reconfigurable/Adaptive Computing Systems
• Long-term (> 15 years) Space Missions
• Hardware and Software: The Line is Blurring
• Radiation Hardening by Design
• Digital Signal Processing with Programmable Devices
• Design Security
• "War Stories" and Lessons Learned
CONFERENCE HOME PAGE - http://klabs.org/mapld03 contains registration
information, paper titles, authors, and abstracts, as well as
biographies of all invited speakers and Panel Session members. Late
abstract submissions will be accepted for the Poster Session.
Invited Speakers Include (more to be announced):
Theron M. Bradley Jr. Greg Hinckley
Chief Engineer, NASA President, Mentor Graphics Corporation
"Welcome and Opening Remarks" "Mil/Aero and PLD's: A CEO's View"
SEMINARS - Two seminars will be presented:
"Advanced Design: Digital Signal Processing, Programmable Device
Architecture, and Military/Aerospace Applications" and "Reconfigurable
Computing: FPGA-Based, General Purpose, High Performance Systems."
PANEL SESSION: We will have leading engineers and managers on our
panel for a spirited "discussion." One question left open from the
2002 panel on "Why Is Mars So Hard?" that will be discussed at the
2003 panel is ...
"Why Is Software So Hard?"
A Discussion of the Technical, Programmatic, and
Political Factors That Have Lead To Failures Over the
Last 40 Years and Its Impact for Future Systems
Introduction:
James Tomayko Carnegie Mellon University
Paul Cerruzi National Air and Space Museum
Opening Case Studies:
Tony Spear, JPL Magellan and Mars Pathfinder
John P. Dimtroff Aircraft Certification Engineer, FAA
Jack Garman Lockheed-Martin (NASA, retired)
Nancy Leveson Professor of Aeronautics and Astronautics, MIT
Jim Lewis SynthWorks Design Inc.
Fred Martin Averstar/Intermetrics
Steven S. Scott Chief Engineer, Goddard Space Flight Center
Kevin Tones NASA Johnson Space Center
TECHNICAL SESSIONS:
• Applications: Military and Aerospace
• Systems and Design Tools
• Radiation and Mitigation Techniques
• Processors: General Purpose and Arithmetic
• Reconfigurable Computing, Evolvable Hardware, and Security
• Birds of a Feather: Reconfigurable Computing
• Poster Session
The 6th MAPLD International Conference is hosted by the AIAA and the
NASA Office of Logic Design.
INDUSTRIAL and GOVERNMENT EXHIBIT RESERVATIONS
Actel Aeroflex UTMC AIAA
Aldec Altera Andraka Consulting
Annapolis Micro AstroExpo.com BAE Systems
Condor Engineering DSP Architectures IEEE
Lattice Semiconductor Mentor Graphics Nallatech
Northrop Grumman Quickflex Seakr
Space Micro Synplicity Synthworks Design
Xilinx NASA Office of Logic Design
For more information, please visit http://klabs.org/mapld03
or contact:
Richard Katz - Conference Chair NASA Goddard Space Flight Center
mapld2003@klabs.org Tel: (301) 286-9705
Article: 57292Peter Alfke wrote: > > Yes I would recommend it. > We talked about this over lunch: > SpartanXL is manufactured on a 0.35 micron process, which will be around > for a long time. The present business seems healthy. So there is neither > a technical nor a commercial reason to abandon the family. > If we were to discontinue it, you get years of warning: Last buy, last > ship, etc, and we then usually sign it over to an "after life" manufacturer. > We still ship XC3100 and XC5200 that predate SpartanXL by several years. > So, five years is a safe bet. > Software is a different story, the current software does not even > support it. Get an older version of our software, and keep it for your purposes. Err - WHY does the new SW not support this device, if it is still active and reccommended for new designs ? Low power, and Startup power, are important params in some designs. It might help retire the _really_ old devices like XC5200 ? - jgArticle: 57293
"qlyus" <qlyus@yahoo.com> (whoever he/she might be) wrote: > Just took a look of a few pages of comp.arch.fpga Thread Subject: ... > Xilinx related problems are overwhelming over Altera's. I think it is remarcable that a company like Xilinx has such a wide-open presence in a USENET newsgroup. Most companies would be dead-afraid of this and pretty much ban their employees from participating. Before you engage in Xilinx bashing you should think about just how valuable a resource their presence in this NG truly is. It's OK to engage in constructive criticism, that just makes things better. I see very little point in your score-keeping post that fails to put anything in context. Now, if you are looking for feedback in trying to decide which architecture to consider, well, there are a lot better ways to ask that question. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 57294
Chris Carlen wrote: > > Jim Granville wrote: > > I think you should look at ABEL or CUPL HDL. > > Xilinx still offer ABEL flows, and have actually improved the > > handling of details in their latest WebPack. > > ABEL source is unchanged, but Xilinx changed some of the > > underlying flows, and that took a while to shake-out. > > What do you mean by "still offer?" It sounds like this is a dying breed > or something. Perhaps you can enlighten me a bit more about the history > of ABEL vs. other HDLs, and it's current usage in the PLD world? It's not 'fashionable', but as Xilinx took the trouble to improve the back-end there are clearly many users. ( I'm not sure if Xilinx ABEL flows STILL support 16V8/20V8/22V10 - for a while they did, but if not, there is WinCUPL ) It's a bit like assembler/C/C++/C# : from a sales viewpoint, you can claim assembler is dead/gone. This however, distorts its USAGE, and many new designs use part or all assembler. - ie you cannot remove Assembler from designers toolboxes. The older HDLs like ABEL, CUPL and even Altera's AHDL, are similar - perfectly good, stable, and some would say better, for certain types of design. Personally, I prefer tools that do what I want, when I want, and are not 'design request' in nature. > > ABEL is 'more direct' (syntax maps more closely to the resource) > > than VHDL/Verilog, and uses DOT extentions. eg : > > > > Reg.D = Sum # Of # Products; > > Reg.CK = ChooseCLK; > > Reg.CE = Reg2; > > Reg2.T = ToggleTerms; > > > > If you like schematics, you can think of this as a netlist. > > This is interesting. > > > If the scientists can understand & -> AND and # -> OR, :) then > > they can make their own patch tables, given a template file to > > start with. > > Some of them (the ones who don't know anything exists beyond an AND and > OR gate) are criticising me for not still doing everything with > wire-wrap and TTL. Not a very progressive bunch. Fortunately, most of > them are into progress, but others not. I think schematics are really > needed for them in general. > > But if I can produce the time to learn an HDL in the near future, I will > consider ABEL. > > Thanks for the input. > > Good day!Article: 57295
I have a design in VHDL for a xc9572xl done using the web pack software. I am wanting to know how I can set the startup values of the registers. Thanks RalphArticle: 57296
Paul Leventis wrote: > Hi Carl, > > Sounds like that should work. The only limitation in Cyclone appears to be > data width, which you are side-stepping by tying off some of the data > inputs. > > Are SO-DIMM or DIMM modules that much cheaper than using DDR SDRAM chips > directly on your board? If you take that approach, you can build a x32 > memory sub-system without needing to waste any memory, but I guess you loose > the advantage of replaceable/expandable memory. > > - Paul > > >>Haven't used the DDR support in Cyclone yet. Am planning on using it in >>a project later this year. >> >>Anyway, the EP1C6 seem to be able to drive everything but the 64bit data >>bus, so I was planning on burning half the module, ie. only use 32bit >>data. SO-DIMM DDR modules are so cheap I don't mind paying for a 256MB >>module to get 128MB (128MB is still more than I need anyway), also, you >>can give away some addressing (ie. only drive enough address lines to >>drive 512MB) and with a little buffering on the FPGA you can probably >>ditch the byte mask lines and make all reads bus width (32 bit). >> >>This should get the pin budget under 70 pins, still give you ~1GBps peak >>theoretical transfer (more like 300-400MBps probably, though I haven't >>worked the numbers and this could be much worse), and allow you to use >>cheap commodity memory. >> >>As I said, untried, but I haven't read anything so far to discourage me. >> >>-Carl >> > > > Had another thought today, thanks to comp.arch It would also be possible to use a DDR bus MUX like the Philips CBTV4010. I'm unsure as to cost, but this would let you access the full DIMM with two accesses, Hi/Low. No more wasted storage. The CBTV4010 itself is overkill, rated to DDR400, in a TBGA64 package, but at least it doesn't take much board space. SO-DIMM can be quite cheap, but the principle reason is flexibility. With current SDRAM devices I can populate a board with anything from 32MB to 512MB with only one board design, and one production run. DDR SO-DIMMs are cheaper per MB but don't cover as wide a range. I'm not currently using DDR, I'm just evaluating it for a future board. DDR should offer equivalent performance with fewer pins, but the performance and cost benefits at the high end might not outweigh the cost benefit of being able to ship with cheap 32MB SDRAM SO-DIMMs at the low end. -CarlArticle: 57297
Patrick MacGregor wrote: > > In 20 years in this business (primarily telecom/datacom), I've never once > had a situation where bloat was allowed. Bloat = added cost that doesn't go Bloat is never good, but if you want to get the product really out you need to cut some corners. Especially with ASICs some random logic does not matter, you can fit ~200-300kgates/mm^2 (of course power usage can be a problem). > Having recently done an OC48 framer design (in a couple of weeks), I could > have easily aimed at something like a 1C6 or 1C12 Cyclone part. Instead I > aimed for a 1C3 part in the slowest speed grade. Works just fine, using > about 1/3 of the LCs. A 1C3 costs 1/2 of a 1C6 roughly, yet the 1C6 is not > "expensive". Choosing to design efficiently added exactly zero time penalty > but yielded tremendous cost savings. There shouldn't be any big differences between propely written HDL and schematics. Good high level RTL might even do better results because good synthesizers can do some quite amazing tricks to the design. For example sometimes FSM optimizations are very nice, quite few schematics designers can do those kinds of code transformations in their head. > One startup I worked for had an embedded designer assigned to one or more > ATM interface cards. These guys wrote in assembly only, and because of this > were able to keep up with ATM at OC-3 rates using a very slow, primitive > (i.e. inexpensive) micro. And what was the cost of maintaining that super optimized code after the guys left the company, and someone had to understand the code to fix bugs. And what was the engineering cost of that code compared to very straightforward implementation and little more expensive processor? It's always nice to make optimized code but sometimes it's not worth of it. > I regularly test whether or not an HDL can create logic more efficiently > than me. It can't. Not once has it implemented any type of decoding > function better than I can. It can match me in terms of resources utilized, > but it can't best me. By staying in the gates, I always have an instant Are you sure you can write good HDL? Different HDL coding styles can procude quite different results. > The best HDL folks I know are ones who use it like it was a schematic. So, > in my mind, why bother? And again, I've never had the luxury of NOT needing The best HDL guys I know use it completely differently than schematics. They use advanced datatypes for busses, functions , code generation and other advanced things (yes they are VHDL coders). And the code procuded is very concise, easy to read, produces very good synthesis results and is easy to debug in simulator. They might even use graphical editors for complex state machines because that is the fastest way to do them, and let the machine to optimize the design. > > I don't know where you got this, but this sounds like an exaggeration. > > I would say he had it backwards, but I bet the schematic usage is less > > than 20%. > > > I got this right from the horse's mouth. I didn't make it up. It was his > observation of designs he's seeing. Why would he lie? He has no vested > interest in any method his clients use. Simply the stats he sees. He might have been some schematic FAE :) I haven't heard about any schematics designs for a long time for bigger FPGAs. For some CPLDs schematics is quite common way of doing simple clock dividers etc. > Guess you missed it when I said I simulated the designs, right before > testing them on the bench. I never skip simulating. Again though, I prefer > the graphical waveform version as I get to see a nice, pretty picture of > what is happening and when. It is very simple to pull up any flop in the > design and see it relative to anything else. Makes debugging go 10 times > faster. And, once I'm happy with it, I can transfer the simulator results > back into the input file so that I can compare expected to generated results > should I make changes or add new stuff. What could be simpler? My debugging would be at least 10000 times slower with waves. I have hundreds of simulations all running in the millisecond range at high clockspeeds. Drawing even waveforms for those simulations would take years. In HDL it takes just 50kloc of code that is easy to understand and also checks the results :) How long would it take from you to draw waveforms for 5000 PCI-BUS transactions (single+burst mixed randomly for example). It's alaso quite easy to find problems at RTL level. I just imagine what it would be to find the problem from 5Mgate design in netlist format. > For the duhsigner, perhaps. Personally, I've never found any job too large > for schematics, whether doing ASICs or FPGAs. And, you need schematics to > design PCBs, so the extra practice doesn't hurt. How big designs have you really made and how repetitive have they been? I'd like to see someone do 1Mgate random logic with schematics. And that is quite small FPGA/ASIC nowadays. I have seen schematics for old 50kgate etc. chips and they already are many thick folders of schematics. --KimArticle: 57298
I do not know why you see my post is Xilinx bashing. I did not even try to criticise Xilinx. Are those posts of Xilinx problems real? Is it true that there are few Altera related? As a matter of fact, I am a long time or all time Xilinx user, I did not know (or did not want to know) altera product line well. I started to look at Altera Stratix closely when I started a big DSP project a couple of month ago. It looks very good in features and performance (as it says). The documentation is far better than Xilinx, for example, the DSP section of Stratix User Guider. Altera rep/distributor did not walk away as Xilinx people did when they heard small annual volume. My next step went to software. Again as a long time Xilinx user (since M1.2), I do not know anything of Altera backend software. Browsing and searching this NG is one way trying to gether this kind of information. I read this NG and Xilinx realated posts quite often. But I wonder there are very few Altera post, especially its software problem related, people talked more on chip to chip comparison. It even surprised me alittle when I counted the numbers of Xilinx vs Altera posts. I do not see your logic how my post affects the value of Xilinx appearance in this NG, and what kind of criticism is constructive or destructive. Don't you see Peter and Austin already appeared in this thread? -qlyus "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<a9OKa.2236$EH2.235198739@newssvr14.news.prodigy.com>... > "qlyus" <qlyus@yahoo.com> (whoever he/she might be) wrote: > > > Just took a look of a few pages of comp.arch.fpga Thread Subject: > ... > > Xilinx related problems are overwhelming over Altera's. > > > I think it is remarcable that a company like Xilinx has such a wide-open > presence in a USENET newsgroup. Most companies would be dead-afraid of this > and pretty much ban their employees from participating. > > Before you engage in Xilinx bashing you should think about just how valuable > a resource their presence in this NG truly is. It's OK to engage in > constructive criticism, that just makes things better. I see very little > point in your score-keeping post that fails to put anything in context. > > Now, if you are looking for feedback in trying to decide which architecture > to consider, well, there are a lot better ways to ask that question.Article: 57299
Have you looked at Nallatech? We have one of their PCI boards in use in an R&D project - I don't knbow all the performance details but I'm sure there's some Linux support. Glenn http://www.nallatech.com/ "Seth" <skintigh_spam@yahoo.com> wrote in message news:<65541f48.0306261249.2e82dd3f@posting.google.com>... > I need an FPGA board with a 64-bit 66MHz PCI bus and Linux drivers, > and I need to be able to demo it, and I need it fast. > > If that's not demanding enough I can add more requirements. > > I have looked through 53 vendors so far and there are no real winners. > > Thanks in advance.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z