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I understand that this is a software based medium, and therefore do not intend to mention my hardware services other than this one time. I have seen a few postings in which the writer inquired about assembling FPGA components onto their PCB or inquired about replacing devices. I want to mention that my company offers this service in addition to BGA restoration (re-balling). We have also upgraded hardware (removed and replaced BGA's) from one FPGA to another to increase gate count. We offer fast turn services and accept Visa/Mastercard.Article: 57101
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote: > I didn't say it was a perfect solution ... or the only one. :-) Further to that... I'm not up to speed on the latest and greatest in graphics adapter design. I know they are using 128 to 256 bit graphics memory interfaces and very powerful parallel rendering engines that can do such things as handle cursor painting and primitive rendering (lines, circles, etc.) with minimal host intervention. Then, of course, you have OpenGL capabilities. So, when you write a program in Windows (for example) and use the libraries' line drawing function, I'm not sure this has your code explicitly write to graphics RAM. More than likely it sends an OpenGL (or?) call to the graphics processor to draw that line. Are there any online resources to learn about the latest techniques in graphics adapter design? Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 57102
y_p_w@hotmail.com (y_p_w) writes: >So the question I have for those who have really done this is - >in the real world, could a master (or series of masters) issue >a STOP command followed by a START command - all on the same >SCL high period. The latest I2C spec doesn't explain whether >or not this could happen. Anything can happen. Please consider combinations of fast CPUs and sudden power-loss or reset in _all_ phases of the protocol. Remember for example the "I2C Edge Conditions" problem. Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Web: www.denx.de I have often regretted my speech, never my silence.Article: 57103
kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) writes: > Who uses MIPS? People who don't want to pay the license fees for ARM?Article: 57104
AFAIK: Currently the support for Virtex 2 devices is in progress. After that happend V2P will be the next. BTW: Who uses JBits? kind regards, thomas "tk" <tokwok@hotmail.com> schrieb im Newsbeitrag news:bd66mt$pnv$1@hkueee5.eee.hku.hk... > Hi, > > I wanna do partial reconfiguration on Virtex II Pro, does anybody know if > JBits supports V2P ? > > Thx in advance. > > tk > >Article: 57105
Tauno Voipio wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3EF744FB.AF2FB36E@yahoo.com... > > Tauno Voipio wrote: > > > > > > "y_p_w" <y_p_w@hotmail.com> wrote in message > > > news:591da479.0306230937.42883d68@posting.google.com... > > > > Hi- > > > > > > > > I'm currently in the process of creating a synthesizable Verilog > > > > F/S I2C slave, but have little experience with I2C in the real > > > > world. > > > > > > > > I'm reading the specs, and I feel I'm getting a pretty good > > > > understanding. If I'm getting this right, the SDA line will only > > > > change when the SCL line is low - except when the master is > > > > indicating a START or STOP command. > > > > > > > > So the question I have for those who have really done this is - > > > > in the real world, could a master (or series of masters) issue > > > > a STOP command followed by a START command - all on the same > > > > SCL high period. The latest I2C spec doesn't explain whether > > > > or not this could happen. > > > > > > > > This is key to me, since I'm trying to create an I2C slave that > > > > runs solely off the SDA and SCL signals. Whether or not I have > > > > to deal with START and STOP on the same SCL high period will > > > > impact the design choice I make. > > > > > > > > > > AFAIK, that's normal when the bus is idle in the meantime. > > > > > > The idle bus has all drivers loose and both lines up. When the master > ends a > > > transmission, the last thing is the STOP condition: SCL up, then SDA up. > > > When the next transmission starts, the first thing is the START > condition: > > > SCL still up, SDA down. > > > > I think he means the other way around, a START followed by a STOP with > > no clock transitions inbetween. In essence, this would be an "empty" > > frame. > > > > I have not worked with I2C before, so I don't know the answer. But I am > > interested since I will be making one as well. > > > > I have not checked opencores.org, but it seems likely that they would > > have a core for this. It might be a bit larger than you would want to > > use however. > > > > An empty frame is expressely forbidden in the specs. However, the logic must > still not hang up if such a condition should happen. > > Tauno Voipio > tauno voipio @ iki fi I guess that is the answer then. The condition should not occur, but if it does due to a defect in one component, it should not cause a problem in another component. To the OP, How does this change your design? I would think an empty frame would be handled like one that is not addressed to your device, no? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57106
"Tauno Voipio" <tauno.voipio@iki.fi.SPAMBAIT_REMOVE.invalid> wrote in message news:5LHJa.361$4q6.102@read3.inet.fi... > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3EF744FB.AF2FB36E@yahoo.com... > > Tauno Voipio wrote: > > > > > > "y_p_w" <y_p_w@hotmail.com> wrote in message > > > news:591da479.0306230937.42883d68@posting.google.com... > > > > Hi- > > > > > > > > I'm currently in the process of creating a synthesizable Verilog > > > > F/S I2C slave, but have little experience with I2C in the real > > > > world. > > > > > > > > I'm reading the specs, and I feel I'm getting a pretty good > > > > understanding. If I'm getting this right, the SDA line will only > > > > change when the SCL line is low - except when the master is > > > > indicating a START or STOP command. > > > > > > > > So the question I have for those who have really done this is - > > > > in the real world, could a master (or series of masters) issue > > > > a STOP command followed by a START command - all on the same > > > > SCL high period. The latest I2C spec doesn't explain whether > > > > or not this could happen. > > > > > > > > This is key to me, since I'm trying to create an I2C slave that > > > > runs solely off the SDA and SCL signals. Whether or not I have > > > > to deal with START and STOP on the same SCL high period will > > > > impact the design choice I make. > > > > > > > > > > AFAIK, that's normal when the bus is idle in the meantime. > > > > > > The idle bus has all drivers loose and both lines up. When the master > ends a > > > transmission, the last thing is the STOP condition: SCL up, then SDA up. > > > When the next transmission starts, the first thing is the START > condition: > > > SCL still up, SDA down. > > > > I think he means the other way around, a START followed by a STOP with > > no clock transitions inbetween. In essence, this would be an "empty" > > frame. > > > > I have not worked with I2C before, so I don't know the answer. But I am > > interested since I will be making one as well. > > > > I have not checked opencores.org, but it seems likely that they would > > have a core for this. It might be a bit larger than you would want to > > use however. > > > > An empty frame is expressely forbidden in the specs. However, the logic must > still not hang up if such a condition should happen. > > Tauno Voipio > tauno voipio @ iki fi > > Hi, I have done this with a Lattice 1016 (64 registers) The start condition, SCL high and SDA falling is to put the device in lets call it "address compare mode", if the address (Bit 1-7) matches the device goes into "read or write mode" depending on bit0 , otherwise the "I'm not interested mode", i.e. the "not address compare mode" and "not read read or write mode" This is determined at the rising edge of the 9th SCL pulse. So the start condition is a mode reset command. Note that controllers like the PCF8584 have slow rising and falling signals. Your FPGA will be ways too fast for this, so you will have to register the signals to determine the transitions. Example: clock speed 1Mhz (actual speed) SCL2 = SCL1 = SCL Not_SCL2 And SCL1 = transitionevent Tip: in read/write mode where the 9th SCL pulse is used for ACK generation you can also use the rising edge to generate a read or write pulse to communicate with a device. With this you can have a continuous 8-bit data stream into or from the device. Ideal for a graphical LCD-display (and whenever there is a connection with a high frequency and a low frequency device) Carel HarmsenArticle: 57107
Erik Bolton wrote: > > Hello All: > > I'm working on an old PCB design from a piece of test equipment and > I'm looking to replace a bunch of old logic chips with a single > PLD/FPGA. The only chip I'm having trouble reproducing the behavior > for is the delay line. It's somewhat of a special part. It's a 10 > bit programmable line that steps in 1 ns increments and has an initial > prop. delay of 6 ns. Also, like most delay lines, it isn't clock > driven. I've read about a fairly straight-foward method of using a > counter with an overflow bit to create a delay, but the problem is the > step size. Since I need 1 ns steps I'd have to drive the counter with > a 1 Ghz clock which seems a little impractical for this circuit. If > you guys have any suggestions as to how I might pull this off I'd > really appreciate it. Thanks in advance! > > -Erik Bolton First, I'd try the std commercial Digital-Delay devices (OnSemi et al) When you say 10bit, do you mean 6ns-1030ns in 1ns steps ? A counter will have two issues : Max clock speed, and the jitter. Check the system can tolerate the jitter, before going this route. Chain-of-gates delays lines are possible, but need some calibration scheme as they are process/temp/vcc dependant. < 1ns step is not a problem 1GHz is probably just appearing on FPGA radar - ask Peter A. FPGAs do have DLLs, which allow fractional cycle defines, so some gymnastics with those might give the 1ns resolution. -jgArticle: 57108
y_p_w wrote: > > Hi- > > I'm currently in the process of creating a synthesizable Verilog > F/S I2C slave, but have little experience with I2C in the real > world. > > I'm reading the specs, and I feel I'm getting a pretty good > understanding. If I'm getting this right, the SDA line will only > change when the SCL line is low - except when the master is > indicating a START or STOP command. > > So the question I have for those who have really done this is - > in the real world, could a master (or series of masters) issue > a STOP command followed by a START command - all on the same > SCL high period. The latest I2C spec doesn't explain whether > or not this could happen. > > This is key to me, since I'm trying to create an I2C slave that > runs solely off the SDA and SCL signals. Whether or not I have > to deal with START and STOP on the same SCL high period will > impact the design choice I make. > > Thanks in advance. Since this is also a possible noise condition, then yes, your logic certainly should cope with this. Normally it would, as the Start/Stop have highest priority, and 'the most recent one' would be expected to prevail. -jgArticle: 57109
We have a 33Mhz 3.3v PCI Card that contains a Spartan 2e and uses Xilinx PCI LogiCORE to implement the PCI interface, including bus mastering DMA. This has worked successfully in most PC Platforms till now (of course). Bus Mastering DMA works from the Host to the PCI Card. However it does not work going from the PCI Card to host memory. The PCI signals seemed to show a successful DMA write, however the data never appears in host memory. The PC we are failing on is a duel Xeon 2.4GHz with the Intel E701 chipset? Has anyone seen a problem like this or have any suggestions? Thanks, KarlArticle: 57110
Since my name came up... Any IC open-loop delay line will suffer from wide tolerances ( but resolution is no problem down to 50 pioseconds per step, using carry chains) The phase-shift control in Virtex-II gives you 50 ps granularity, but only with a free-running and precise oscillator. Using that will take some clever thinking, and may not work at all. You may be better of with the old-fashioned delay line... 1 GHz is almost in our reach, especially if one uses double-data-rate tricks. Peter Alfke ===================== Jim Granville wrote: > > Erik Bolton wrote: > > > > Hello All: > > > > I'm working on an old PCB design from a piece of test equipment and > > I'm looking to replace a bunch of old logic chips with a single > > PLD/FPGA. The only chip I'm having trouble reproducing the behavior > > for is the delay line. It's somewhat of a special part. It's a 10 > > bit programmable line that steps in 1 ns increments and has an initial > > prop. delay of 6 ns. Also, like most delay lines, it isn't clock > > driven. I've read about a fairly straight-foward method of using a > > counter with an overflow bit to create a delay, but the problem is the > > step size. Since I need 1 ns steps I'd have to drive the counter with > > a 1 Ghz clock which seems a little impractical for this circuit. If > > you guys have any suggestions as to how I might pull this off I'd > > really appreciate it. Thanks in advance! > > > > -Erik Bolton > > First, I'd try the std commercial Digital-Delay devices (OnSemi et al) > > When you say 10bit, do you mean 6ns-1030ns in 1ns steps ? > > A counter will have two issues : Max clock speed, and the jitter. > Check the system can tolerate the jitter, before going this route. > > Chain-of-gates delays lines are possible, but need some calibration > scheme as they are process/temp/vcc dependant. > < 1ns step is not a problem > > 1GHz is probably just appearing on FPGA radar - ask Peter A. > > FPGAs do have DLLs, which allow fractional cycle defines, so > some gymnastics with those might give the 1ns resolution. > > -jgArticle: 57111
Hi folks: As usual, I'm having headaches to get Webpack installed. I tried the web installer, but it gives this error, so I'm going to try the full download. Any tips on how to get past this error, as I might want to install on my home computer as well? Thanks. -- _______________________________________________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.Article: 57112
Hi: Just looking for a refresher on the current status of running ISE Webpack 5.2i on Linux. Is a Windows installation needed with Wine, or can vanilla Wine do the job? I searched at xilinx.com for "linux" and saw a bunch of tidbits, but is there any definitive document describing what must be done, or is it pretty much a no-brainer? Thanks for comments. Good day! -- _______________________________________________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.Article: 57113
"Tauno Voipio" <tauno.voipio@iki.fi.SPAMBAIT_REMOVE.invalid> wrote in message news:<5LHJa.361$4q6.102@read3.inet.fi>... > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3EF744FB.AF2FB36E@yahoo.com... > > Tauno Voipio wrote: > > > > > > "y_p_w" <y_p_w@hotmail.com> wrote in message > > > news:591da479.0306230937.42883d68@posting.google.com... > > > > Hi- > > > > > > > > I'm currently in the process of creating a synthesizable Verilog > > > > F/S I2C slave, but have little experience with I2C in the real > > > > world. > > > > > > > > I'm reading the specs, and I feel I'm getting a pretty good > > > > understanding. If I'm getting this right, the SDA line will only > > > > change when the SCL line is low - except when the master is > > > > indicating a START or STOP command. > > > > > > > > So the question I have for those who have really done this is - > > > > in the real world, could a master (or series of masters) issue > > > > a STOP command followed by a START command - all on the same > > > > SCL high period. The latest I2C spec doesn't explain whether > > > > or not this could happen. > > > > > > > > This is key to me, since I'm trying to create an I2C slave that > > > > runs solely off the SDA and SCL signals. Whether or not I have > > > > to deal with START and STOP on the same SCL high period will > > > > impact the design choice I make. > > > > > > > > > > AFAIK, that's normal when the bus is idle in the meantime. > > > > > > The idle bus has all drivers loose and both lines up. When the master > ends a > > > transmission, the last thing is the STOP condition: SCL up, then SDA up. > > > When the next transmission starts, the first thing is the START > condition: > > > SCL still up, SDA down. > > > > I think he means the other way around, a START followed by a STOP with > > no clock transitions inbetween. In essence, this would be an "empty" > > frame. > > > > I have not worked with I2C before, so I don't know the answer. But I am > > interested since I will be making one as well. > > > > I have not checked opencores.org, but it seems likely that they would > > have a core for this. It might be a bit larger than you would want to > > use however. > > > > An empty frame is expressely forbidden in the specs. However, the logic must > still not hang up if such a condition should happen. > > Tauno Voipio > tauno voipio @ iki fi Thanks for the answer. I actually re-read the spec, and noticed that a STOP following a START in the same SCL high period is illegal. I'm going to ignore an illegally applied STOP (i.e. illegal STOP ignored). I was also worried about the possibility of repeated STOP/ START/STOP/START sequences. However - as a follow-up question, would it be possible to see SCL toggle after a STOP before the next START command "in the real world"? None of the timing diagrams in the spec seem to address this possibility; all diagrams show SDA and SCL staying high for the foreseeable future. I'd guess that the thing to do is simply put put the I2C slave in a wait state until a START condition is seen. I wouldn't see any reason to toggle SCL between a STOP and the next START, but I haven't seen any real-world designs. Again - many thanks for the replies.Article: 57114
> An empty frame is expressly forbidden in the specs. However, the logic must > still not hang up if such a condition should happen. I feel it is a bit futile forbidding illegal events because sooner or later they will happen either through bugs or malfunction. Personally I would make my I2C slaves enter the idle state whenever they saw a stop condition (legal or not). Seems a fair and simple way of entering resetting slave state machines without sending any bytes, even if the spec forbids it. If it happens to be an illegal transition then the I2C spec does not oblige me to do anything in particular, so I can keep my I2C slave logic simple. If I had to implement things like roll-back after malformed messages, I might need large n-byte roll-back buffers.Article: 57115
On Mon, 23 Jun 2003 15:48:00 -0700, Chris Carlen wrote: > Hi: > > Just looking for a refresher on the current status of running ISE > Webpack 5.2i on Linux. > > Is a Windows installation needed with Wine, or can vanilla Wine do the job? > > I searched at xilinx.com for "linux" and saw a bunch of tidbits, but is > there any definitive document describing what must be done, or is it > pretty much a no-brainer? > > Thanks for comments. > > Good day! http://www.polybus.com/xilinx_on_linux.htmlArticle: 57116
On Mon, 23 Jun 2003 13:45:41 -0700, Eric Smith wrote: > kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) writes: >> Who uses MIPS? > > People who don't want to pay the license fees for ARM? MIPS is proprietary also.Article: 57117
Hi Martin, Finally got an answer for you on this. This is indeed a bug in the Quartus extractors; your test case was helpful in tracking down this problem. Apparently the extractor guys had been looking for a problem like this but hadn't been able to isolate it until now. A Software Problem Report has been filed and this should be addressed in a future version of Quartus or a service pack. Regards, Paul Leventis Altera Corp. "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:6GGIa.34485$RM6.474195@news.chello.at... > Since Leonardo is not longer available from Altera I'm trying to use Quartus > for synthesis. But I get a different output with Quartus. I tracked the > problem down and now my qustion is: Is it a bug or sloopy written VHDL? > > The problem is setting output to tristate. See following VHDL code: I asumed > that it is ok when the databus (d) is set to 'Z' in state 'idl' and this > will not change when changing state to 'rd1'. This was ok with Leonardo. But > with Quartus I have to set d to 'Z' again in every state. What is the > correct VHDL code? > > Martin > > process(clk, reset, din, mem_wr_addr, mem_rd, mem_wr) > begin > if (reset='1') then > state <= idl; > a <= "ZZZZZZZZZZZZZZZZZZZ"; > d <= "ZZZZZZZZ"; > .... > elsif rising_edge(clk) then > case state is > when idl => > a <= "ZZZZZZZZZZZZZZZZZZZ"; > d <= "ZZZZZZZZ"; > > if (mem_rd='1') then > a <= din(16 downto 0) & "00"; > nram_cs <= '0'; > ram_access <= '1'; > i := ram_cnt; > nrd <= '0'; > state <= rd1; > elsif (mem_wr='1') then > ... > when rd1 => > d <= "ZZZZZZZZ"; -- this line is necessary in Quartus but > NOT in Leonardo > i := i-1; > if (i=0) then > state <= rd2; > mem_din(7 downto 0) <= d; > a(1 downto 0) <= "01"; > i := ram_cnt; > end if; > > when rd2 => > d <= "ZZZZZZZZ"; -- same as in rd1 > i := i-1; > if (i=0) then > ... > > -------------------------------------------------------- > JOP - a Java Processor core for FPGAs now > on Cyclone: http://www.jopdesign.com/cyclone/ > >Article: 57118
I verified this with the DDR IP group today. The current DDR SDRAM MegaCore supports up to 48 bit DDR (when using "x8 mode" DDR) in Cyclone due to the way it uses global clocks. The IP group is in the process of evaluating and bench testing other solutions for supporting higher bit depths. Regards, Paul Leventis Altera Corp. "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:BduJa.176762$3Sm.149287@news01.bloor.is.net.cable.rogers.com... > Hi Naveed, > > According to the Cyclone Device Handbook > (http://www.altera.com/literature/lit-cyc.html), Section V, Chapter 10, > Cyclone supports DDR signaling at up to 133 Mhz, or DDR266. That > corresponds to "PC2100" signaling. > > As for interfacing with SDRAMs, we offer a DDR SDRAM controller MegaCore for > SDRAM interfaces, but I don't know if it supports PC DIMMs out of the box. > On top of this, according to the online documentation, Cyclone supports <=48 > bits data width, suggesting you are out of luck for the 64-bit and 72-bit > DIMMs in use in PCs. Note: this document lists the speed of operation as > preliminary and awaiting characterization, but then again, it hasn't been > updated since March. You're best off asking for the latest status by filing > a case with http://mysupport.altera.com. They will be happy to answer all > of your questions. > > But from what I can tell (see below) it looks like if you want to use > Cyclone, you won't be able to use PC-style DIMMs. > > ******* Warning: I knew nothing about DDR before tonight; read at your own > risk ;-) ****** > > Here's what I found in a quick scan of the JEDEC spec on PC DDR DIMMs: A > 64-bit DDR DIMM has the following pins: > 18 address/bank select pins > 64 data pins > 7 various strobe/select/enable > 8 byte-masks > 8 data strobes > 6 clocks? (not so sure about this one -- looks like three differential > clocks, but all three may be the same) > > plus some EEPROM control (SPD stuff, I imagine) and a bunch of power pins. > That makes for ~111 "user pins" in FPGA speak out of the 168 pins on the > package. The 1C6 has 185 pins, so from that perspective you look ok. > > However, Cyclone has a set special DQS pin that has a delay chain for > producing the shifting version of the DQS signal. You need one DQS signal > per byte of data -- and the number of DQS pins is limited to 3-4 in some > Cyclone devices, and 8 in the rest (see table in I/O Structure section of > Chapter 2 in Cyclone Handbook). So that gives you a theoretical limit of 64 > bits (or 72 bits with parity) of DDR data in a Cyclone 1C4, 1C12, or 1C20. > The 1C6 tops out at 32- (or 36-) bits. > > I'm not sure what tops us out at 48-bits in the bigger Cyclone members -- > I've fired a question of to the relevant design guys. > > Regards, > > Paul Leventis > Altera Corp. > > > "Naveed" <visualfor@yahoo.com> wrote in message > news:864a80dc.0306221557.21ad98ba@posting.google.com... > > Has anybody ever implemented off the shelf PC2100/3200 DDR module with > > Cyclone? Can Cyclone support 64-bit interface with standard modules? > >Article: 57119
On 23 Jun 2003 13:45:41 -0700, Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: >kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) writes: >> Who uses MIPS? > >People who don't want to pay the license fees for ARM? And would rather pay the license fee to MIPS Technologies? ObClue: The MIPS instruction set isn't freely available, certain aspects of it are patented, and MIPS is very agressive about defending their IP. Check any of the folks who've tried to do a public FPGA MIPS core.Article: 57120
This is a follow-up to an email posted by Henning Trispel in July 2002 where Henning identified a power sequencing issue with APEX 20KE devices. Having spent 2 weeks trying to figure out what was wrong with my board design I finally saw Henning's post that indicated that the VCCIO (3.3v for me) needs to come up before the VCCCORE (1.8V). I made that change to my board (delayed VCCCORE to come up about 50ms after VCCIO) and it worked. Before making the change the EP20K400E would get very hot after about 30 seconds after power on - far too hot to touch. Our design runs quite cool so we knew we shouldn't need heatsinks. Of course we were not prepared for this problem as Altera's site doesn't seem to have a reference to it. Anyway, there certainly appears to be a power sequencing problem with the EP20K400E. Hopefully this can save someone else the grief the we have been through.Article: 57121
Hi! I've written a nice little design using a BDF file. It works well. My question is I want to write a custom file(BDF) that has say 4 input and 1 output. I want to add this file to my project but some how I cannot include it to the master BDF file. Does anyone please have a sample of 2 BDF sample files where one file is a basic function and is resused 1 or more times in another BDF file? Please any suggestions are URLs are most welcomed. Thanks KipArticle: 57122
On Mon, 23 Jun 2003 17:04:12 GMT, "Jean Nicolle" <j.nicolle@sbcglobal.net> wrote: >Well, I wasn't aware of your posting, but looks like we came to the same >conclusions. Well, the design is rather obvious, so I guess any competent engineer would come up with an identical solution. The earliest reference I have found to this design is from Jerry Avins, in about 1968. (Search the comp.dsp archives for details - Jerry is a frequent poster there.) >Do you have a link to your post? It seems to have disappeared from Google. The message id was 35ca56ef.4862712@newshost Here is a slightly modified version converted to schematic (by Lasse) http://groups.google.com/groups?oi=djq&as_umsgid=%3C36C137B5.281D73D0%40kom.auc.dk%3E%231/1 Regards, Allan. >Jean > >"Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message >news:7k9dfvcak1nqs07rn6khdqdtjulot80sf8@4ax.com... >> On Sun, 22 Jun 2003 22:19:00 GMT, "Jean Nicolle" >> <j.nicolle@sbcglobal.net> wrote: >> >> >Hi all, >> > >> >I posted a new project, quadrature decoder in an FPGA. >> >http://www.fpga4fun.com/QuadratureDecoder.html >> >> This seems to be a straightforward translation of some VHDL I posted >> in 1998. >> >> Allan. >Article: 57123
Since I see that some Altera people are reading this group... the current version of Quartus II has a Linux version, which I have access to; however, it's a Winelib application and they only formally support RedHat 7.1, which is ancient by now. It does not work on my RedHat 9 workstation. Does Altera have any plans to upgrade this to a modern version of Linux? -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 57124
kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) writes: > Who uses MIPS? I wrote: > People who don't want to pay the license fees for ARM? Kenneth Seefried <ken@seefried.com> writes: > And would rather pay the license fee to MIPS Technologies? > > ObClue: The MIPS instruction set isn't freely available, certain > aspects of it are patented, and MIPS is very agressive about defending > their IP. Check any of the folks who've tried to do a public FPGA > MIPS core. Sorry, no shortage of clues about that here. But IINM the MIPS license is less expensive than the ARM license. Hence some people would rather use something other than an ARM, if a less expensive choice is available.
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