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Threads Starting May 2000
22196: 00/05/01: <dharmesh_halani@my-deja.com>: real clock generation
22199: 00/05/01: VIRMAN: Xilinx CPLD Make file
22201: 00/05/01: Mark Harvey: Re: Xilinx CPLD Make file
22202: 00/05/01: Dave Vanden Bout: Re: Xilinx CPLD Make file
22210: 00/05/02: Rick Filipkiewicz: Re: Xilinx CPLD Make file
22203: 00/05/01: Dave Vanden Bout: PR: XESS Introduces Low-Cost Triscend CSoC Development Kit
22205: 00/05/01: <rajesh52@hotmail.com>: Verilog FAQ
22208: 00/05/01: Vern Dunbrack: Xilinx Applications Engineer
22212: 00/05/02: Kelvin Law: test
22214: 00/05/02: R. T. Finch: new2fpga
22239: 00/05/02: Eric: Re: new2fpga
22242: 00/05/02: Dan: soldering quad flat packs
22248: 00/05/03: <rob_dickinson@my-deja.com>: Re: soldering quad flat packs
22250: 00/05/03: Rickman: Re: soldering quad flat packs
22254: 00/05/03: <rob_dickinson@my-deja.com>: Re: soldering quad flat packs
22265: 00/05/03: Theron Hicks: Re: new2fpga
22215: 00/05/02: Jamil Khatib: random integer
22220: 00/05/02: <gazit@my-deja.com>: Re: random integer
22231: 00/05/02: Ray Andraka: Re: random integer
22216: 00/05/02: <mlzfgl@4r5g6hv5.net>: L.E,G.A,L C,A.B,L.E T,V D,E-S,C.R,A.M,B.L,E.R............. 3277
22224: 00/05/02: The ATM man: VDHL and ASIC people
22228: 00/05/02: Utku Ozcan: Re: VDHL and ASIC people
22232: 00/05/02: The ATM man: Re: VDHL and ASIC people
22225: 00/05/02: Patrick Schulz: Performance of Xilinx LogiCORE PCI Real 64/66
22227: 00/05/02: jimmy roberts: Foundation question.
22229: 00/05/02: <ed@earth.wustl.edu>: Start Up Reset after config on Virtex design
22235: 00/05/02: Chris Dunlap: Re: Start Up Reset after config on Virtex design
22386: 00/05/07: Hal Murray: Re: Start Up Reset after config on Virtex design
22240: 00/05/02: eSjteTuV: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
22245: 00/05/02: David Grugett: Free CPLD SW at Lattice Seminar
22251: 00/05/03: Sebastien Favard (Gordh): Search simple design
22252: 00/05/03: <as@asic.cc>: Digital Design/systems/CAD Engineer (MSEE) looking for position in California, USA
22253: 00/05/03: #YEO WEE KWONG#: Wait until statement problem in synthesis
22312: 00/05/04: <eml@riverside-machines.com.NOSPAM>: Re: Wait until statement problem in synthesis
22328: 00/05/05: #YEO WEE KWONG#: Code request
22399: 00/05/08: Alan Fitch: Re: Code request
22255: 00/05/03: Maurice: Bidirectional bus
22262: 00/05/03: Rickman: Re: Bidirectional bus
22266: 00/05/03: Laurent Gauch: Re: Bidirectional bus
22357: 00/05/05: <acushing@doble.com>: Re: Bidirectional bus
22270: 00/05/03: Tom McLaughlin: INIT pin on Virtex FPGAs
22407: 00/05/08: Tom McLaughlin: Re: INIT pin on Virtex FPGAs
22408: 00/05/08: Rickman: Re: INIT pin on Virtex FPGAs
22419: 00/05/09: Philip Freidin: Re: INIT pin on Virtex FPGAs
22276: 00/05/04: º¸¶ó³Ý: [Q] Virtex FPGA : compile time error message
22288: 00/05/04: JWKIM: Re: [Q] Virtex FPGA : compile time error message
22283: 00/05/04: Sebastien Favard (Gordh): Init/ line - CRC error ???
22284: 00/05/04: Andreas Doering: Re: Init/ line - CRC error ???
22287: 00/05/04: Sebastien Favard (Gordh): Re: Init/ line - CRC error ???
22285: 00/05/04: Nicolas Matringe: Re: Init/ line - CRC error ???
22286: 00/05/04: Sebastien Favard (Gordh): Re: Init/ line - CRC error ???
22289: 00/05/04: Sebastien Favard (Gordh): Re: Init/ line - CRC error ???
22290: 00/05/04: Nicolas Matringe: Re: Init/ line - CRC error ???
22294: 00/05/04: Philip Freidin: Re: Init/ line - CRC error ???
22339: 00/05/05: Sebastien Favard (Gordh): Re: Init/ line - CRC error ???
22359: 00/05/05: Philip Freidin: Re: Init/ line - CRC error ???
22373: 00/05/06: Sebastien Favard (Gordh): Configuration process %-(
22374: 00/05/06: Catalin Baetoniu: Re: Configuration process %-(
22626: 00/05/15: Philip Freidin: Re: Configuration process %-(
22293: 00/05/04: Jamil Khatib: Vital glitch
22300: 00/05/04: <Oliver.W@gmx.ch>: Re: Vital glitch
22295: 00/05/04: Sebastien Favard (Gordh): [BitGen] - pb option UserClk
22315: 00/05/04: Christian Mautner: Re: [BitGen] - pb option UserClk
22341: 00/05/05: Sebastien Favard (Gordh): Re: [BitGen] - pb option UserClk
22346: 00/05/05: Rickman: Re: [BitGen] - pb option UserClk
22361: 00/05/05: Christian Mautner: Re: [BitGen] - pb option UserClk
22380: 00/05/06: Rickman: Re: [BitGen] - pb option UserClk
22390: 00/05/07: Christian Mautner: Re: [BitGen] - pb option UserClk
22392: 00/05/07: Rickman: Re: [BitGen] - pb option UserClk
22573: 00/05/12: <eml@riverside-machines.com.NOSPAM>: Re: [BitGen] - pb option UserClk
22360: 00/05/05: Christian Mautner: Re: [BitGen] - pb option UserClk
22371: 00/05/06: Sebastien Favard (Gordh): Re: [BitGen] - pb option UserClk
22365: 00/05/05: Mark Proctor: Re: [BitGen] - pb option UserClk
22370: 00/05/06: Sebastien Favard (Gordh): Re: [BitGen] - pb option UserClk
22296: 00/05/04: Tony Burch: [Ann] Lowest Cost FPGA Proto Kits SALE
22297: 00/05/04: <e97bjli@thn.htu.se>: How to connect JTAG to XCS10pc84 FPGA device
22311: 00/05/04: <a@z.com>: Re: How to connect JTAG to XCS10pc84 FPGA device
22356: 00/05/05: VIRMAN: Re: How to connect JTAG to XCS10pc84 FPGA device
22302: 00/05/04: George Davis: RF System Design Engineer
22305: 00/05/04: George Davis: Product Applications Engineer
22308: 00/05/04: George Davis: Mixed Signal Design
22317: 00/05/04: Christian Mautner: edif
22343: 00/05/05: Utku Ozcan: Re: edif
22350: 00/05/05: Phil Endecott: Re: edif
22351: 00/05/05: Phil Endecott: Re: edif
22358: 00/05/05: Christian Mautner: Re: edif
22362: 00/05/05: Christian Mautner: Re: edif
22363: 00/05/05: Jon Elson: Re: edif
22376: 00/05/06: Christian Mautner: Re: edif
22387: 00/05/07: Jon Elson: Re: edif
22389: 00/05/07: Mark Harvey: Re: edif
22323: 00/05/04: Paul Bunyk: Q: simplest FPGA structure for novel technology demonstration
22326: 00/05/04: John Larkin: Re: Q: simplest FPGA structure for novel technology demonstration
22352: 00/05/05: Paul Bunyk: Re: Q: simplest FPGA structure for novel technology demonstration
22369: 00/05/06: <spp@bob.eecs.berkeley.edu>: Re: Q: simplest FPGA structure for novel technology demonstration
22372: 00/05/06: Tom Burgess: Re: Q: simplest FPGA structure for novel technology demonstration
22409: 00/05/08: Paul Bunyk: Re: Q: simplest FPGA structure for novel technology demonstration
22381: 00/05/06: Rickman: Re: Q: simplest FPGA structure for novel technology demonstration
22410: 00/05/08: Paul Bunyk: Re: Q: simplest FPGA structure for novel technology demonstration
22603: 00/05/12: Iain McClatchie: Re: Q: simplest FPGA structure for novel technology demonstration
22367: 00/05/06: Brian Drummond: Re: Q: simplest FPGA structure for novel technology demonstration
22330: 00/05/05: M R Wheeler: MaxPlus9.5/6 License problems
22344: 00/05/05: <boniolopez@my-deja.com>: Your opinion Arexsys design tools and SDL description methodology
22345: 00/05/05: Michael Barr: ANNOUNCE: Embedded Systems Glossary and Bibliography
22347: 00/05/05: OneStone: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22377: 00/05/06: Rennie Allen: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22388: 00/05/07: OneStone: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22449: 00/05/09: Rennie Allen: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22478: 00/05/10: OneStone: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22490: 00/05/10: David Brown: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22393: 00/05/08: Jerry Avins: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22394: 00/05/08: Jon Kirwan: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22402: 00/05/09: OneStone: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22418: 00/05/08: Jon Kirwan: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22581: 00/05/12: George Neuner: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22405: 00/05/08: Jerry Avins: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22398: 00/05/08: Clay S. Turner: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22403: 00/05/09: OneStone: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22420: 00/05/08: Eric Weaver: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22421: 00/05/08: Jerry Avins: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22423: 00/05/08: Joel Kolstad: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22427: 00/05/09: Peter J. Kootsookos: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22437: 00/05/09: John Stewart: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22439: 00/05/09: David Brown: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22450: 00/05/09: Robert Lied: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22470: 00/05/09: Dave Hansen: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
23135: 00/06/15: Michael Barr: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22432: 00/05/09: Johan Kwisthout: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22436: 00/05/09: PeterS: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22444: 00/05/10: OneStone: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22447: 00/05/09: PeterS: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22452: 00/05/09: Rennie Allen: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22480: 00/05/10: OneStone: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22482: 00/05/10: Rennie Allen: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22486: 00/05/10: OneStone: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22479: 00/05/10: OneStone: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22493: 00/05/10: Johan Kwisthout: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22438: 00/05/09: David Brown: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22451: 00/05/09: Rennie Allen: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22481: 00/05/10: OneStone: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22491: 00/05/10: David Brown: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22492: 00/05/10: Johan Kwisthout: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22555: 00/05/11: Jerry Avins: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
22559: 00/05/12: Herman: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
22563: 00/05/12: Johan Kwisthout: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
22580: 00/05/12: Arie de Muynck: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
22594: 00/05/12: Jerry Avins: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
22598: 00/05/12: Mike Albaugh: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
22601: 00/05/13: Herman: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
22445: 00/05/09: Bill Williams: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22458: 00/05/09: Jerry Avins: Re:OT ANNOUNCE: Embedded Systems Glossary and Bibliography
22627: 00/05/15: Lasse Langwadt Christensen: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22468: 00/05/09: robert bristow-johnson: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22494: 00/05/10: Geir Frode Raanes: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22349: 00/05/05: Kang Liat Chuan: Porting design from xc40150xv to xcv300
22364: 00/05/05: Matt Gavin: Virtex clock buffers
22384: 00/05/07: David Bishop: Re: Virtex clock buffers
22397: 00/05/08: Rick Filipkiewicz: Re: Virtex clock buffers
22401: 00/05/08: Matt Gavin: Re: Virtex clock buffers
22406: 00/05/08: Phil Endecott: Re: Virtex clock buffers
22396: 00/05/08: Phil Endecott: Re: Virtex clock buffers
22416: 00/05/08: Jon Elson: Re: Virtex clock buffers
22639: 00/05/15: Marc K.: Re: Virtex clock buffers
22404: 00/05/08: J. Boss: Programming FPGA
22414: 00/05/08: Andy Peters: Re: Programming FPGA
22415: 00/05/08: Jon Elson: Re: Programming FPGA
22434: 00/05/09: Theron Hicks: Re: Programming FPGA
22424: 00/05/09: Maurice: Re: Programming FPGA
22460: 00/05/09: J. Boss: Re: Programming FPGA
22411: 00/05/08: Uwe Bonnes: Non-BGA High Pin Count FPGA/CPLD
22413: 00/05/08: Greg Neff: Re: Non-BGA High Pin Count FPGA/CPLD
22435: 00/05/09: Rickman: Re: Non-BGA High Pin Count FPGA/CPLD
22412: 00/05/08: Nick: How do I lock down Macro Routing
22422: 00/05/08: Andy Krumel: Xilinx Block Select Ram+ and LeonardoSpectrum
22429: 00/05/09: Phil Endecott: Re: Xilinx Block Select Ram+ and LeonardoSpectrum
22441: 00/05/09: Rick Filipkiewicz: Re: Xilinx Block Select Ram+ and LeonardoSpectrum
22425: 00/05/09: Eddy: Timing Analyzer drains System recources
22426: 00/05/09: Thorsten Bunte: Altera Megafunction in Exemplar Leonardo
22459: 00/05/09: Xanatos: Re: Altera Megafunction in Exemplar Leonardo
22504: 00/05/10: Georg Berliner: Re: Altera Megafunction in Exemplar Leonardo
22428: 00/05/09: William LenihanIii: pipeline shiftreg in virtex
22456: 00/05/09: Andy Peters: Re: pipeline shiftreg in virtex
22461: 00/05/09: Rick Filipkiewicz: Re: pipeline shiftreg in virtex
22506: 00/05/10: Andy Peters: Re: pipeline shiftreg in virtex
22485: 00/05/10: Emil Blaschek: Re: pipeline shiftreg in virtex
22473: 00/05/10: Ray Andraka: Re: pipeline shiftreg in virtex
22513: 00/05/10: Gary Spivey: Re: pipeline shiftreg in virtex
22517: 00/05/10: Rickman: Re: pipeline shiftreg in virtex
22531: 00/05/11: William LenihanIii: Re: pipeline shiftreg in virtex
22561: 00/05/12: Ray Andraka: Re: pipeline shiftreg in virtex
22597: 00/05/12: Rick Filipkiewicz: Re: pipeline shiftreg in virtex
22605: 00/05/13: Ray Andraka: Re: pipeline shiftreg in virtex
22545: 00/05/11: Gary Spivey: Re: pipeline shiftreg in virtex
22430: 00/05/09: <shahzad2512@my-deja.com>: Good books on FEC
22433: 00/05/09: Tomasz Brychcy: Nets or regs
22457: 00/05/09: Utku Ozcan: Re: Nets or regs
22440: 00/05/09: myself: Xilinx fpga board schematics?
22469: 00/05/10: Ray: Re: Xilinx fpga board schematics?
22471: 00/05/09: Laurent Gauch: Re: Xilinx fpga board schematics?
22551: 00/05/11: <elynum@my-deja.com>: Re: Xilinx fpga board schematics?
22570: 00/05/12: myself: Re: Xilinx fpga board schematics?
22442: 00/05/09: Andy Holt: HELP - what to choose?
22443: 00/05/09: Andy Holt: Re: HELP - what to choose?
22455: 00/05/09: Dave Vanden Bout: Re: HELP - what to choose?
22632: 00/05/15: Andy Holt: Re: HELP - what to choose?
22633: 00/05/15: Peter Alfke: Re: HELP - what to choose?
22661: 00/05/17: Lasse Langwadt Christensen: Re: HELP - what to choose?
22474: 00/05/10: Ray Andraka: Re: HELP - what to choose?
22483: 00/05/10: Rickman: Re: HELP - what to choose?
22499: 00/05/10: Don Husby: Re: HELP - what to choose?
22524: 00/05/11: Ray Andraka: Re: HELP - what to choose?
22602: 00/05/13: Tony Burch: Re: HELP - what to choose?
22622: 00/05/14: <vsundaram@my-deja.com>: Re: HELP - what to choose?
22446: 00/05/09: Jo: FPGA Development - EDA Administration
22448: 00/05/09: Carsten =?iso-8859-1?Q?N=F6ding?=: virtex e lvds clock recovery
22453: 00/05/09: Marc K.: Re: virtex e lvds clock recovery
22487: 00/05/10: Emil Blaschek: Re: virtex e lvds clock recovery
22454: 00/05/09: Nicolas Matringe: Looking for Altera programmer in France
22465: 00/05/09: <csjacobs@my-deja.com>: Re: Looking for Altera programmer in France
22477: 00/05/10: Ashok Mahadevan: Re: Looking for Altera programmer in France
22462: 00/05/09: Anthony Ellis - LogicWorks: Spartan II
22463: 00/05/09: Anthony Ellis - LogicWorks: Spartan II support with Foundation Base Express
22464: 00/05/09: Anthony Ellis - LogicWorks: Spartan II support with Foundation Base Express
22466: 00/05/09: Rickman: Re: Spartan II
22467: 00/05/09: Long: EETools Topmax
22505: 00/05/10: Andy Peters: Re: EETools Topmax
22516: 00/05/10: Norm Dresner: Re: EETools Topmax
22526: 00/05/11: Keith R. Williams: Re: EETools Topmax
22541: 00/05/11: Kenneth Casselman: Re: EETools Topmax
22472: 00/05/09: Don McCarley: Error with Quartus for Altera APEX20K device: clock skew is greater then data delay
22475: 00/05/10: Xanatos: Re: Error with Quartus for Altera APEX20K device: clock skew is greater then data delay
22498: 00/05/10: Don McCarley: Re: Error with Quartus for Altera APEX20K device: clock skew is greater
22525: 00/05/11: Ray Andraka: Re: Error with Quartus for Altera APEX20K device: clock skew is greater
22755: 00/05/23: Michel Le Mer: Re: Error with Quartus for Altera APEX20K device: clock skew is greater then data delay
22476: 00/05/09: R. T. Finch: Xilinx Student Edition 1.5 License.dat
22484: 00/05/10: Joachim Hoch: Re: Xilinx Student Edition 1.5 License.dat
22488: 00/05/10: Jon Kirwan: Re: Xilinx Student Edition 1.5 License.dat
22489: 00/05/10: Alan Fitch: Re: Xilinx Student Edition 1.5 License.dat
22527: 00/05/11: R. T. Finch: Re: Xilinx Student Edition 1.5 License.dat
22530: 00/05/10: Jon Kirwan: Re: Xilinx Student Edition 1.5 License.dat
22495: 00/05/10: Patrick Schulz: appropriate ASIC Prototyping Board
22520: 00/05/10: Anna Acevedo: Re: appropriate ASIC Prototyping Board
22533: 00/05/11: Patrick Schulz: Re: appropriate ASIC Prototyping Board
22552: 00/05/11: Jonas Thor: Re: appropriate ASIC Prototyping Board
22522: 00/05/11: Ray Andraka: Re: appropriate ASIC Prototyping Board
22532: 00/05/11: Patrick Schulz: Re: appropriate ASIC Prototyping Board
22542: 00/05/11: Ray Andraka: Re: appropriate ASIC Prototyping Board
22673: 00/05/17: Malachy Devlin: appropriate ASIC Prototyping Board
22496: 00/05/10: <e97bjli@thn.htu.se>: Spartan XCS10
22503: 00/05/10: Yang Li: ASIC question
22507: 00/05/10: <chadlamb@my-deja.com>: Re: virtex configuration with synplify
22606: 00/05/13: Austin Franklin: Re: virtex configuration with synplify
22611: 00/05/13: Rick Filipkiewicz: Re: virtex configuration with synplify
22508: 00/05/10: Mark Harvey: SpartanXL driving 5V CMOS input
22510: 00/05/10: Bob Perlman: Re: SpartanXL driving 5V CMOS input
22511: 00/05/10: Dave Vanden Bout: Re: SpartanXL driving 5V CMOS input
22515: 00/05/10: Bob Perlman: Re: SpartanXL driving 5V CMOS input
22518: 00/05/10: Dave Vanden Bout: Re: SpartanXL driving 5V CMOS input
22512: 00/05/10: Greg Neff: Re: SpartanXL driving 5V CMOS input
22514: 00/05/10: Peter Alfke: Re: SpartanXL driving 5V CMOS input
22523: 00/05/10: rk: Re: SpartanXL driving 5V CMOS input
22548: 00/05/11: Peter Alfke: Re: SpartanXL driving 5V CMOS input
22549: 00/05/11: Greg Neff: Re: SpartanXL driving 5V CMOS input
22726: 00/05/19: Lasse Langwadt Christensen: Re: SpartanXL driving 5V CMOS input
22519: 00/05/10: Don McCarley: clock skew doesn't compute with Altera
22521: 00/05/11: Jim Patterson: Info on using Reconfig feature of Virtex?
22543: 00/05/11: Ray Andraka: Re: Info on using Reconfig feature of Virtex?
22528: 00/05/11: Emil Blaschek: alexander decoder
22534: 00/05/11: MK Yap: Shifting with STD_LOGIC_VECTOR???
22536: 00/05/11: Alan Fitch: Re: Shifting with STD_LOGIC_VECTOR???
22539: 00/05/11: Laurent Gauch: Re: Shifting with STD_LOGIC_VECTOR???
22558: 00/05/12: MK Yap: Re: Shifting with STD_LOGIC_VECTOR???
22535: 00/05/11: Steven Sanders: FPGA emulators?
22537: 00/05/11: Nicolas Matringe: Re: FPGA emulators?
22540: 00/05/11: Steven Sanders: Re: FPGA emulators?
22553: 00/05/11: Rickman: Re: FPGA emulators?
22567: 00/05/12: Utku Ozcan: Re: FPGA emulators?
22547: 00/05/11: Anurag Tiwari: Re: FPGA emulators?
22538: 00/05/11: Laurent Gauch: Re: FPGA emulators?
22544: 00/05/11: Ray Andraka: Re: FPGA emulators?
22546: 00/05/11: Vipan Kakkar: floorplanning
22550: 00/05/11: Pete Dudley: simulation of Xilinx Coregen modules in schematic environment
22557: 00/05/12: Kang Liat Chuan: Re: simulation of Xilinx Coregen modules in schematic environment
22574: 00/05/12: peter dudley: Re: simulation of Xilinx Coregen modules in schematic environment
22600: 00/05/12: rk: Re: simulation of Xilinx Coregen modules in schematic environment
22554: 00/05/11: John Fielden: Reccomend an ASIC emulation board
22560: 00/05/12: Ray Andraka: Re: Reccomend an ASIC emulation board
22562: 00/05/12: Patrick Schulz: Re: Reccomend an ASIC emulation board
22592: 00/05/12: John Gallagher: Re: Reccomend an ASIC emulation board
22674: 00/05/17: Malachy Devlin: Reccomend an ASIC emulation board
22697: 00/05/18: Patrick Schulz: Re: Reccomend an ASIC emulation board
22556: 00/05/12: Adam Donlin: SpartanXL config. via XC18V00?
22564: 00/05/12: <shahzad2512@my-deja.com>: Future of FPGAs?
22572: 00/05/12: Victor the Cleaner: Re: Future of FPGAs?
22608: 00/05/13: Peter: Re: Future of FPGAs?
22625: 00/05/15: Victor the Cleaner: Re: Future of FPGAs?
22628: 00/05/15: Andy Holt: Re: Future of FPGAs?
22629: 00/05/15: Rick Filipkiewicz: Re: Future of FPGAs?
22631: 00/05/15: Andy Holt: Re: Future of FPGAs?
22578: 00/05/12: Nicholas C. Weaver: Re: Future of FPGAs?
22579: 00/05/12: Robert Posey: Re: Future of FPGAs?
22583: 00/05/12: myself: Re: Future of FPGAs?
22587: 00/05/12: Ulf Samuelsson: Re: Future of FPGAs?
22582: 00/05/12: Joel Kolstad: Re: Future of FPGAs?
22588: 00/05/12: Don Husby: Re: Future of FPGAs?
22590: 00/05/12: Steve Casselman: Re: Future of FPGAs?
22565: 00/05/12: <shahzad2512@my-deja.com>: Do you know xilinx FPGAs well?
22575: 00/05/12: Ray Andraka: Re: Do you know xilinx FPGAs well?
22593: 00/05/12: <eml@riverside-machines.com.NOSPAM>: Re: Do you know xilinx FPGAs well?
22584: 00/05/12: Joel Kolstad: Re: Do you know xilinx FPGAs well?
22604: 00/05/13: Ray Andraka: Re: Do you know xilinx FPGAs well?
22621: 00/05/14: <vsundaram@my-deja.com>: Re: Do you know xilinx FPGAs well?
22623: 00/05/14: Rickman: Re: Do you know xilinx FPGAs well?
22624: 00/05/14: Rickman: Re: Do you know xilinx FPGAs well?
22635: 00/05/15: Steve Casselman: Re: Do you know xilinx FPGAs well?
22693: 00/05/18: EKC: Re: Do you know xilinx FPGAs well?
22732: 00/05/21: Richard Erlacher: Re: Do you know xilinx FPGAs well?
22566: 00/05/12: <shahzad2512@my-deja.com>: Do you know xilinx FPGAs well?
22569: 00/05/12: Dave Vanden Bout: Re: Do you know xilinx FPGAs well?
22586: 00/05/12: Ulf Samuelsson: Re: Do you know xilinx FPGAs well?
22568: 00/05/12: Sharp: asic vs fpga
22576: 00/05/12: Ray Andraka: Re: asic vs fpga
22589: 00/05/12: Ulf Samuelsson: Re: asic vs fpga
22571: 00/05/12: Tim Courtney: Xilinx Virtex SRL16
22577: 00/05/12: Ray Andraka: Re: Xilinx Virtex SRL16
22585: 00/05/13: embargo: Help-help
22591: 00/05/12: Tom McLaughlin: CLKing external RAM from FPGA (Virtex E)
22599: 00/05/12: Rickman: Re: CLKing external RAM from FPGA (Virtex E)
22637: 00/05/15: Marc K.: Re: CLKing external RAM from FPGA (Virtex E)
22649: 00/05/16: Marc K.: Re: CLKing external RAM from FPGA (Virtex E)
22708: 00/05/18: Douglas Armstrong: Re: CLKing external RAM from FPGA (Virtex E)
22709: 00/05/19: Marc K.: Re: CLKing external RAM from FPGA (Virtex E)
22765: 00/05/23: Marc K.: Re: CLKing external RAM from FPGA (Virtex E)
22595: 00/05/12: Frank Van de Sande: foundation
22609: 00/05/13: Björn Lindegren: SV: foundation
23154: 00/06/15: Xilinx CAE Cory: Re: foundation
22596: 00/05/12: <oleg@writeme.com>: Cheap Quicklogic parts....
22607: 00/05/13: Johan Küstner: Altera Schematic
22615: 00/05/14: Adams: Re: Altera Schematic
22619: 00/05/14: Johan Küstner: Re: Altera Schematic
22620: 00/05/14: <vsundaram@my-deja.com>: Re: Altera Schematic
22610: 00/05/13: Björn Lindegren: Prom
22614: 00/05/13: <dave_bernard@my-deja.com>: Re: Prom
22612: 00/05/13: Adams: See if this code can work.
22634: 00/05/15: Andy Peters: Re: See if this code can work.
22613: 00/05/13: Don Golding: New Robot info and general news site
22616: 00/05/14: Tom Burgess: Re: New Robot info and general news site
22617: 00/05/14: J. Boss: Bidirectional BUS!!!
22618: 00/05/14: Rickman: Re: Bidirectional BUS!!!
22650: 00/05/16: Joshua Lamorie: Re: Bidirectional BUS!!!
22630: 00/05/15: Peter Schulz: XC1804 JTAG Programming Problems
22636: 00/05/15: Simon Ramirez: Re: XC1804 JTAG Programming Problems
22712: 00/05/19: David Brown: Re: XC1804 JTAG Programming Problems
22640: 00/05/16: <m_rajanikant@my-deja.com>: c -> FPGA netlist compiler
22646: 00/05/16: Ian Miller: Re: c -> FPGA netlist compiler
22667: 00/05/17: Jan Guffens: Re: c -> FPGA netlist compiler
22641: 00/05/16: Douglas Armstrong: Propogation Delay
22662: 00/05/16: Marc K.: Re: Propogation Delay
22706: 00/05/18: Douglas Armstrong: Re: Propogation Delay
22707: 00/05/18: Marc K.: Re: Propogation Delay
22642: 00/05/16: JX: Where can I find resource for USB?
22660: 00/05/17: Lasse Langwadt Christensen: Re: Where can I find resource for USB?
22843: 00/05/26: Rickman: Re: Where can I find resource for USB?
22852: 00/05/27: Brian Drummond: Re: Where can I find resource for USB?
22643: 00/05/16: Sebastien Favard: [search] - ISA PnP specs
22845: 00/05/27: Rickman: Re: [search] - ISA PnP specs
22644: 00/05/16: Sebastien Favard: [Part II] - Pb FPGA Xilinx config process
22717: 00/05/19: Philip Freidin: Re: [Part II] - Pb FPGA Xilinx config process
22807: 00/05/25: Sebastien Favard: Re: [Part II] - Pb FPGA Xilinx config process
22645: 00/05/16: Benoît HAMON: Foundation to Mentor
22647: 00/05/16: Jean-Luc Nagel: PC104+ FPGA Board
22648: 00/05/16: Patrick Schulz: Re: PC104+ FPGA Board
22665: 00/05/16: James T. White: Re: PC104+ FPGA Board
22666: 00/05/17: Jean-Luc Nagel: Re: PC104+ FPGA Board
22678: 00/05/17: Rick Collins: Re: PC104+ FPGA Board
22695: 00/05/18: Jean-Luc Nagel: Re: PC104+ FPGA Board
22723: 00/05/19: Rickman: Re: PC104+ FPGA Board
22651: 00/05/16: Simon Bilodeau: Best choice between FPGA and CPLD
22655: 00/05/16: Rick Collins: Re: Best choice between FPGA and CPLD
22656: 00/05/16: <iglasner@my-deja.com>: Re: Best choice between FPGA and CPLD
22675: 00/05/17: Chris Shenton: Re: Best choice between FPGA and CPLD
22679: 00/05/17: Simon Bilodeau: Re: Best choice between FPGA and CPLD
22680: 00/05/17: Andy Peters: Re: Best choice between FPGA and CPLD
22698: 00/05/18: Patrick Schulz: Re: Best choice between FPGA and CPLD
22738: 00/05/21: Robert Weber: Re: Best choice between FPGA and CPLD
22652: 00/05/16: Arnold Beland: SMT 7 segment display ??
22657: 00/05/16: Spehro Pefhany: Re: SMT 7 segment display ??
22659: 00/05/16: Dave Miller: Re: SMT 7 segment display ??
22668: 00/05/17: Jens Hildebrandt: Re: SMT 7 segment display ??
22685: 00/05/17: Peter: Re: SMT 7 segment display ??
22658: 00/05/16: Tim Shoppa: Re: SMT 7 segment display ??
22663: 00/05/17: Ray Andraka: Re: SMT 7 segment display ??
22669: 00/05/17: gerald coe: Re: SMT 7 segment display ??
22670: 00/05/17: Paul Burke: Re: SMT 7 segment display ??
22671: 00/05/17: Tim Shoppa: Re: SMT 7 segment display ??
22672: 00/05/17: Spehro Pefhany: Re: SMT 7 segment display ??
22677: 00/05/17: Russ.Shaw: Re: SMT 7 segment display ??
22653: 00/05/16: Tom McLaughlin: .adr files for JTAG programmer
22654: 00/05/16: Tom McLaughlin: Re: .adr files for JTAG programmer
22664: 00/05/17: Ashok Mahadevan: Q: Creating custom flip-flops in Altera MAX+Plus II
22705: 00/05/18: Steve Dewey: Re: Q: Creating custom flip-flops in Altera MAX+Plus II
22735: 00/05/21: Johan Küstner: Re: Creating custom flip-flops in Altera MAX+Plus II
22676: 00/05/17: Vipan Kakkar: macros for reuse
22681: 00/05/17: hartenst@rhrk.uni-kl.de: FPL 2000 - Roadmap to Reconfigurable Systems
22682: 00/05/17: Alun: Xilinx USB Multilinx download verrrrrrry slow
22683: 00/05/17: Alun: Re: Xilinx USB Multilinx download verrrrrrry slow
22684: 00/05/17: Larry Doolittle: Spartan II availability and pricing
22686: 00/05/17: Ray Andraka: Re: Spartan II availability and pricing
22687: 00/05/17: Rick Collins: Re: Spartan II availability and pricing
22688: 00/05/18: Ray Andraka: Re: Spartan II availability and pricing
22690: 00/05/18: Rick Collins: Re: Spartan II availability and pricing
22691: 00/05/18: Ray Andraka: Re: Spartan II availability and pricing
22727: 00/05/19: Rickman: Re: Spartan II availability and pricing
22847: 00/05/27: Rickman: Re: Spartan II availability and pricing
22968: 00/06/06: Larry Doolittle: Re: Spartan II availability and pricing
22689: 00/05/18: A.: Traning for Nallatech??
22719: 00/05/19: Allan James Cantle: Traning for Nallatech??
22692: 00/05/18: Tomasz Brychcy: Translate to verilog
22724: 00/05/19: Richard Iachetta: Re: Translate to verilog
22694: 00/05/18: William LenihanIii: PCI & Virtex
22699: 00/05/18: Lutz Kleberhoff: Re: PCI & Virtex
22696: 00/05/18: Eircom: Help with macrocell , explain it to me
22700: 00/05/18: <rob_dickinson@my-deja.com>: Re: Help with macrocell , explain it to me
22718: 00/05/19: Lee Weston: Re: Help with macrocell , explain it to me
22701: 00/05/18: Tony Burch: [Final Ann] New FPGA Proto Kits Sale Extended for a short time
22702: 00/05/18: maespin: verilog modules into viewlogic designs
22742: 00/05/22: Utku Ozcan: Re: verilog modules into viewlogic designs
22703: 00/05/18: Trent Worthington: tag programming software
22704: 00/05/18: Tim: Apex LVDS
22710: 00/05/19: Seb C: DCT and FPGA !!!!
22963: 00/06/06: Jamil Khatib: Re: DCT and FPGA !!!!
22711: 00/05/18: J.W. Krych: FPGA emultaion of a microprocessor
22713: 00/05/19: Nicholas C. Weaver: Re: FPGA emultaion of a microprocessor
22714: 00/05/19: Ray Andraka: Re: FPGA emultaion of a microprocessor
22715: 00/05/19: Norbert Hoppe: Re: FPGA emultaion of a microprocessor
22721: 00/05/19: Don Husby: Re: FPGA emultaion of a microprocessor
22725: 00/05/19: Ulf Samuelsson: Re: FPGA emultaion of a microprocessor
22716: 00/05/19: Thorsten Bunte: Printed magazines
22731: 00/05/20: Leroy Davis: Re: Printed magazines
22720: 00/05/19: Holger Azenhofer: 68k - core
22722: 00/05/19: Edward L. Hepler: Re: 68k - core
23052: 00/06/11: Left blanks: Re: 68k - core, a free core 1, and 2 worth money = time.
23166: 00/06/16: Mike Johnson: Re: 68k - core, a free core 1, and 2 worth money = time.
22728: 00/05/19: Sreedhar Sampath: Processor
22729: 00/05/20: Al McCormick: Tech: looking for Allpro programming software
23522: 00/06/28: Fred: Re: Tech: looking for Allpro programming software
22730: 00/05/20: Arkady Skorokhod: What is ASIC and FPGA?
22736: 00/05/21: l'landre: Help for a novice of Xilinx Foundation
22739: 00/05/21: Christian Mautner: Re: Help for a novice of Xilinx Foundation
22740: 00/05/21: Ray Andraka: Re: Help for a novice of Xilinx Foundation
22737: 00/05/21: Andy Krumel: Dynamically configuring Vertex/Spartan II
22743: 00/05/22: Simon Zhang: About Xilinx DLL
22744: 00/05/22: Dan: Web page for FPGA design jobs???
22795: 00/05/24: Robert: Re: Web page for FPGA design jobs???
22805: 00/05/25: <lkostov@my-deja.com>: Re: Web page for FPGA design jobs???
22745: 00/05/22: Rickman: Xilinx tools
22749: 00/05/22: Christian Mautner: Re: Xilinx tools
22760: 00/05/23: Nial Stewart: Re: Xilinx tools
22839: 00/05/26: Nial Stewart: Re: Xilinx tools
22751: 00/05/22: Andy Peters: Re: Xilinx tools
22752: 00/05/22: Rickman: Re: Xilinx tools
22761: 00/05/23: Simon: Re: Xilinx tools
22754: 00/05/23: Jim Granville: Re: Xilinx tools
22759: 00/05/23: Eric: Re: Xilinx tools becoming "RentWare"
22766: 00/05/23: Dave Vanden Bout: Re: Xilinx tools becoming "RentWare"
22762: 00/05/23: Simon Ramirez: Re: Xilinx tools
22746: 00/05/22: khoi ha: Coregen generated FIFO not working
22808: 00/05/25: Paul T. Shultz: Re: Coregen generated FIFO not working
22876: 00/05/29: Rémi SEGLIE: Re: Coregen generated FIFO not working
22747: 00/05/22: VIBHOR GARG: Programming Virtex FPGAs using VPR and JBits
22748: 00/05/22: Technisource Inc.: US-IL-In desperate need of FPGA engineer
22750: 00/05/22: Ray Andraka: Re: US-IL-In desperate need of FPGA engineer
22753: 00/05/23: Dan: % use of schematic vs VHDL ???
22797: 00/05/24: Stuart Clubb: Re: % use of schematic vs VHDL ???
22756: 00/05/23: Simon Zhang: Xilinx Virtex E
22773: 00/05/23: Utku Ozcan: Re: Xilinx Virtex E
22822: 00/05/25: Utku Ozcan: Re: Xilinx Virtex E
22796: 00/05/24: Magnus Homann: Re: Xilinx Virtex E
23198: 00/06/17: peter dudley: Re: Xilinx Virtex E
22757: 00/05/23: jon: Actel Pro Asic ?
22758: 00/05/23: jon: Actel Pro Asic ?
22767: 00/05/23: John Eaton: Re: Actel Pro Asic ?
22763: 00/05/23: Christian Habermann: Virtex: Verify and Readback; Capture_Virtex
22764: 00/05/23: Ben: A Question on XILINX Configuration PROM
22768: 00/05/23: Rickman: Xilinx Logic Cell counts and carry chains
22770: 00/05/23: Nicholas C. Weaver: Re: Xilinx Logic Cell counts and carry chains
22771: 00/05/23: Larry Doolittle: Re: Xilinx Logic Cell counts and carry chains
22777: 00/05/24: Ray Andraka: Re: Xilinx Logic Cell counts and carry chains
22780: 00/05/24: Simon: Re: Xilinx Logic Cell counts and carry chains
22772: 00/05/23: Ray Andraka: Re: Xilinx Logic Cell counts and carry chains
22790: 00/05/24: Rickman: Re: Xilinx Logic Cell counts and carry chains
22794: 00/05/24: Hal Murray: Re: Xilinx Logic Cell counts and carry chains
22801: 00/05/25: Ray Andraka: Re: Xilinx Logic Cell counts and carry chains
23827: 00/07/11: Steve Casselman: Re: Xilinx Logic Cell counts and carry chains
23832: 00/07/12: rickman: Re: Xilinx Logic Cell counts and carry chains
23992: 00/07/19: Steve Casselman: Re: Xilinx Logic Cell counts and carry chains
23995: 00/07/19: rickman: Re: Xilinx Logic Cell counts and carry chains
24066: 00/07/25: glen herrmannsfeldt: Re: Xilinx Logic Cell counts and carry chains
24072: 00/07/26: Ray Andraka: Re: Xilinx Logic Cell counts and carry chains
24073: 00/07/26: rickman: Re: Xilinx Logic Cell counts and carry chains
24047: 00/07/24: Ray Andraka: Re: Xilinx Logic Cell counts and carry chains
23994: 00/07/19: John Larkin: Re: Xilinx Logic Cell counts and carry chains
22769: 00/05/23: Jann: FPGA implementation of LCD controller
22776: 00/05/23: Joel Kolstad: Re: FPGA implementation of LCD controller
22786: 00/05/24: Jann: Re: FPGA implementation of LCD controller
22774: 00/05/23: Suttipan Limanond: ISA interface on FPGA or CPLD
22778: 00/05/24: Ray Andraka: Re: ISA interface on FPGA or CPLD
22781: 00/05/24: Laurent Gauch: Re: ISA interface on FPGA or CPLD
22787: 00/05/24: Steen Larsen: Re: ISA interface on FPGA or CPLD
22791: 00/05/24: Rickman: Re: ISA interface on FPGA or CPLD
22775: 00/05/24: <shahzad2512@my-deja.com>: 8087 in FPGA?
22779: 00/05/24: kamal: Re: 8087 in FPGA?
22792: 00/05/24: Andy Peters: Re: 8087 in FPGA?
22798: 00/05/24: Kevin Dale Kirmse: Re: 8087 in FPGA?
22803: 00/05/25: Ray Andraka: Re: 8087 in FPGA?
22825: 00/05/25: Andy Peters: Re: 8087 in FPGA?
22826: 00/05/25: Larry Doolittle: Re: 8087 in FPGA?
22827: 00/05/25: Rickman: Re: 8087 in FPGA?
22830: 00/05/25: Ray Andraka: Re: 8087 in FPGA?
22844: 00/05/27: Ray Andraka: Re: 8087 in FPGA?
22833: 00/05/25: Allen Litton: Re: 8087 in FPGA?
22849: 00/05/27: Peter: Re: 8087 in FPGA?
22850: 00/05/27: Tom Burgess: Re: 8087 in FPGA?
22799: 00/05/24: Rickman: Re: 8087 in FPGA?
22800: 00/05/25: Jan Gray: Re: 8087 in FPGA?
22782: 00/05/24: <shahzad2512@my-deja.com>: V23 and DTMF core?
22785: 00/05/24: Eric: Re: V23 and DTMF core?
22783: 00/05/24: Simon Bilodeau: Why I can't place power symbols on my schematic?
22784: 00/05/24: Simon Bilodeau: Re: Why I can't place power symbols on my schematic?
22831: 00/05/25: Dominic: Re: Why I can't place power symbols on my schematic?
22788: 00/05/24: Don: Re: Error with Quartus for Altera APEX20K device: clock skew is greater
22814: 00/05/25: Michel Le Mer: Re: Error with Quartus for Altera APEX20K device: clock skew is greater then data delay
22789: 00/05/24: myself: Simple 256k Dram tester code?
22853: 00/05/27: Rickman: Re: Simple 256k Dram tester code?
22793: 00/05/24: Seb C: Implementation in FPGA
22802: 00/05/25: Ray Andraka: Re: Implementation in FPGA
22804: 00/05/25: R. T. Finch: Verilog assignment
22821: 00/05/25: Utku Ozcan: Re: Verilog assignment
22806: 00/05/25: <lkostov@my-deja.com>: Help for Spartan XCS10
22824: 00/05/25: Andy Peters: Re: Help for Spartan XCS10
22834: 00/05/26: <lkostov@my-deja.com>: Re: Help for Spartan XCS10
22943: 00/06/05: Hans Kester: Re: Help for Spartan XCS10
22809: 00/05/25: Sebastien Favard: Search Spartan for small quantity
22888: 00/05/30: Leon Heller: Re: Search Spartan for small quantity
22810: 00/05/25: Saqib: Fire Wire
22811: 00/05/25: Saqib: Fire Wire
22828: 00/05/25: Utku Ozcan: Re: Fire Wire
22812: 00/05/25: Saqib: CRC
22820: 00/05/25: Marc K.: Re: CRC
22835: 00/05/26: Chris Shenton: Re: CRC
22813: 00/05/25: Steve Holle: Programming using *.rbt file
22829: 00/05/25: Philip Freidin: Re: Programming using *.rbt file
22838: 00/05/26: Steve Holle: Re: Programming using *.rbt file
22815: 00/05/25: Michel Le Mer: Apex supply problem
22819: 00/05/25: Tom Burgess: Re: Apex supply problem
22823: 00/05/25: Michel Le Mer: Re: Apex supply problem
22848: 00/05/27: Tom Burgess: Re: Apex supply problem
22916: 00/06/02: Michel Le Mer: Re: Apex supply problem
22816: 00/05/25: Angel Ramiro Manzano: PCI core
22818: 00/05/25: Marc K.: Re: PCI core
22817: 00/05/25: Seb C: Implementation using FPGA
22832: 00/05/25: Dominic: PCI LogiCore M1 Implementation
22836: 00/05/26: Oliver Maischberger: Q:Itegration of FPGA functionality in an ASIC?
22859: 00/05/28: Hyun-Taek Chang: Re: Q:Itegration of FPGA functionality in an ASIC?
22837: 00/05/26: closset: Abel conversion to VHDL
22842: 00/05/26: Rick Filipkiewicz: Re: Abel conversion to VHDL
22840: 00/05/26: jorge quintino: help
22841: 00/05/26: Swapnajit Mittra: Verilog PLI website
22846: 00/05/27: Paul Sutton: AVNET Virtex Board
22851: 00/05/27: <baneshwar_s@my-deja.com>: implementation of mplrs using wallace,counters
22854: 00/05/27: <neli_dimitrova@my-deja.com>: Fitting problems with WebPack
22870: 00/05/29: Klaus Falser: Re: Fitting problems with WebPack
22855: 00/05/27: Jan Lellmann: Buying FPGAs in Germany
22856: 00/05/28: Peter Alfke: Re: Buying FPGAs in Germany
22862: 00/05/29: Tony Burch: Re: Buying FPGAs in Germany
22864: 00/05/28: Jon Kirwan: Re: Buying FPGAs in Germany
22857: 00/05/28: Roman Inin: Help ! Can't receive Free Cypress PCI Target Core !
22858: 00/05/28: rk: Registration and CFP - 2000 MAPLD International Conference
22860: 00/05/28: Björn Lindegren: STD_LOGIC_VECTOR problem.....
22861: 00/05/28: Rickman: Re: STD_LOGIC_VECTOR problem.....
22865: 00/05/28: The Elftmanns: Re: STD_LOGIC_VECTOR problem.....
22867: 00/05/29: Carlhermann Schlehaus: Re: STD_LOGIC_VECTOR problem.....
22863: 00/05/29: <dave_admin@my-deja.com>: VirtexE prototype board
22934: 00/06/04: Allan James Cantle: VirtexE prototype board
22961: 00/06/06: <tonycornock@my-deja.com>: Re: VirtexE prototype board
22866: 00/05/28: <nestor@ece.concordia.ca>: Design of Phase-Locked Loop (PLL) - 2 alternatives
22868: 00/05/29: Rickman: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22890: 00/05/30: Nestor: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22901: 00/05/30: John Larkin: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22892: 00/05/30: Nestor: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22903: 00/05/31: Rickman: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22871: 00/05/29: Ray Andraka: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22889: 00/05/30: Nestor: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22907: 00/05/31: Ray Andraka: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22893: 00/05/30: Nestor: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22874: 00/05/29: dmac: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22894: 00/05/30: Nestor: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22882: 00/05/30: David R Brooks: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22883: 00/05/30: Jim Granville: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22896: 00/05/30: Nestor: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22895: 00/05/30: Nestor: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22899: 00/05/31: David R Brooks: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22902: 00/05/31: Peter Alfke: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22891: 00/05/30: John Janusson: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22910: 00/05/31: Robert Weber: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22869: 00/05/29: Bernard Bertrand: search PCB programmer VHDL
22885: 00/05/30: <lkostov@my-deja.com>: Re: search PCB programmer VHDL
22886: 00/05/30: Bernard Bertrand: Re: search PCB programmer VHDL
22872: 00/05/29: <mariab52@my-deja.com>: Problem with databus for external ROM using 'Z'
22873: 00/05/29: <mariab52@my-deja.com>: Problem with databus for external RAM using 'Z'
22875: 00/05/29: Vipan Kakkar: Help with Coregen
22881: 00/05/29: Ray Andraka: Re: Help with Coregen
22922: 00/06/02: jgarrigo: RE: Help with Coregen
22941: 00/06/05: Ray Andraka: Re: Help with Coregen
22962: 00/06/06: Simmler Harald: Re: Help with Coregen
22971: 00/06/06: Ray Andraka: Re: Help with Coregen
22877: 00/05/29: <bingoeugene@my-deja.com>: Altera FPGA downloader/programmer 1.8 - 5.5 V
22878: 00/05/29: Simon Bilodeau: question about logic simulator from Xilinx Foundation F2.1i
22879: 00/05/29: Simon Bilodeau: Re: question about logic simulator from Xilinx Foundation F2.1i
22880: 00/05/29: Bob Perlman: Re: question about logic simulator from Xilinx Foundation F2.1i
22887: 00/05/30: Simon Bilodeau: Re: question about logic simulator from Xilinx Foundation F2.1i
22904: 00/05/31: Bob Perlman: Re: question about logic simulator from Xilinx Foundation F2.1i
22884: 00/05/30: Matt Owens: FPGA Jobs in Germany
22897: 00/05/30: Jian F. Weng: Implement LMS
22900: 00/05/30: Muzaffer Kal: Re: Implement LMS
22898: 00/05/30: Jian F. Weng: Implement LMS
22905: 00/05/31: Alun: 1 minute to download a Virtex xcv1000!
22906: 00/05/31: Georgi Beloev: Re: search PCB programmer VHDL
22909: 00/05/31: Saqib.: Verilog Questions??
23145: 00/06/15: <kayrock@geocities.com>: Re: Verilog Questions??
23179: 00/06/16: <kgbee@my-deja.com>: Re: Verilog Questions??
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