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Dear friends:
I have a vhdl description for an FIR filter make one of the tap as a
core to use it to implement the FIR filter in FPGA. I was trying to
build one tap as a core using the Xilinx COREGEN, but don't know how to
do it. Coregen library has FIR filter, but I want to build a core from
my vhdl description of the tap, which is shown below:
Could anyone help me that ... if it is possible to build a core from the
vhdl description I have ... if yes then what commands (in the COREGEN)
should be given and what files (e.g. .xco etc.).
entity FIRTAP is
port(
CLK_S : in std_logic_vector( 8 downto 0);
RSTn_S : in std_logic_vector( 8 downto 0);
LDCOEF : in std_logic;
COEFi : in std_logic_vector(15 downto 0);
COEFo : out std_logic_vector(15 downto 0);
I : in std_logic_vector(15 downto 0);
O : out std_logic_vector(15 downto 0);
PI : in std_logic_vector(63 downto 0);
PO : out std_logic_vector(63 downto 0));
end FIRTAP;
Regards,
Vipan
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Content-Type: text/x-vcard; charset=us-ascii;
name="v.kakkar.vcf"
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Content-Description: Card for Vipan Kakkar
Content-Disposition: attachment;
filename="v.kakkar.vcf"
begin:vcard
n:Kakkar;Vipan
tel;work:+31 15 2786202
x-mozilla-html:FALSE
org:Delft University of Technology;Information Technology & Systems
version:2.1
email;internet:v.kakkar@its.tudelft.nl
title:TWAIO
adr;quoted-printable:;;Room 17.060, Information Technology & Systems,=0D=0ATUDelft, Mekelweg 4, ;DELFT;;2628 CD;HOLLAND
x-mozilla-cpt:;0
fn:Vipan Kakkar
end:vcard
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Article: 22876Hello, I think you talk about "fifosyncvht". I've got problem with that model too. In fact, it's because of use of "WAIT UNTIL c_i'EVENT" because it's meaning is not quite clear in VHDL 87 : "With VHDL-87, attributes of signals in the condition clause do not cause their signals to be added to the wait statement's sensitivity list. This has been corrected in VHDL-93," Simply comment the instruction above and add "c_i" in the sensitivity list of the process. (5 changes). "Paul T. Shultz" <paul@csciences.com> a écrit dans le message news: 9U7X4.260$HD6.7056@iad-read.news.verio.net... > Khoi, > > I had problems with the same FIFO a while ago. There are two simple things > to check. First the reset is active high and is synchronous. Second the WE > and RE signals are active high. I hope this helps. > > Regards, > > Paul T. Shultz > paul@csciences.com > Chesapeake Sciences Corporation > 1127B Benfield Blvd., Millersville, MD 21108 USA > TEL (410) 923-1300 x3070 FAX (410) 923-2669 > > khoi ha <kha@fallschurch.esys.com> wrote in message > news:39296769.357B44ED@fallschurch.esys.com... > > Hello, > > > > I created a 255 deep by 32 bit fifo using Coregen and I am having > > problem getting it to simulate. The device does not seem to be doing > > anything, even the reset input does not work. I know this is a lot to > > ask but hopefully there is something I missed that are easy to see. I > > followed exactly what the Coregen's user manual told me to do. Here are > > > > my tools environment: > > > > Window NT > > Using Virtex 1000 series > > Using Modelsim PE/VHDL 5.3b > > Using Coregen 2.1i > > Using C_IP5 > > > > Attached is my vhdl file that instantiated the files (.vho) produced by > > Coregen. > > > > Thanks > > Khoi Ha > > Raytheon Systems > > (703)560-5000 x4481 > > > > > > > >Article: 22877
Altera Downloader/Programmer - replacement for ByteBlaster and ByteBlaster MV, works from 1.8 V - 5.5 V, just $75 versus Altera $150 solution. Please visit: http://welcome.to/nefdesign.com Tel/Fax: 408-446-1694 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22878
Hi, i am in a design using a XC9500 IC from Xilinx and I have a problem with the logic simulator : the Q output from the FDC is always undefined, even if I clock the input. Any idea Thanks Simon begin 666 problem.bmp M0DT^2P```````#X````H````] $``"P!```!``$```````!+``#$#@``Q X` M`````````````````/___P#_____________________________________ M______________________________________________ `____________ M____________________________________________________________ M___________P`/______________________________________________ M____________________________________\ #_____________________ M____________________________________________________________ M__ `________________________________________________________ M___________________________P`/______________________________ M____________________________________________________\ #_____ M____________________________________________________________ M__________________ `________________________________________ M___________________________________________P`/______________ M____________________________________________________________ M________\ #_________________________________________________ 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M___________________[________________________________________ M__________________ `____W___________________^_______________ M___________________________________________P`/___]__________ M__________O_______________________________________________^^ M/'______\ #____?___________________[________________________ M________________________7=N_______ `____W___________________ M^________________________________________________UW[_______P M`/___]____________________O_________________________________ M______________[M^_______\ #____?___________________[________ M_______________________________________^[?O_______ `____W___ M________________^___________________________________________ M_____NW;O______P`/___]____________________O_________________ M______________________________WV/'______\ #____?____________ M_______[____________________________________________________ M______ `____W___________________^___________________________ M_______________________________P`/___]____________________O_ M________________________________________________________\ #_ M___?___________________[____________________________________ M______________________ `____W___________________^___________ M_______________________________________________P`/___]______ M______________O_____________________________________________ M____________\ #____?___________________[____________________ M______________________________________ `____W_______________ M____^_______________________________________________________ M___P`/___]____________________O_____________________________ M____________________________\ #____?________________________ M______________________________________________________ `____ MW___________________________________________________________ M___________________P`/___]__________________________________ M____________________________________________\ #____?________ M____________________________________________________________ M__________ `____W___________________________________________ M___________________________________P`/___]__________________ M____________________________________________________________ M\ #____?____________________________________________________ M__________________________ `____W___________________________ M___________________________________________________P`/___]__ M__________________O_________________________________________ M________________\ #____?___________________[________________ M__________________________________________ `____W___________ M________^___________________________________________________ M_______P`/___]____________________O_________________________ M________________________________\ #____?___________________[ M__________________________________________________________ ` M____W___________________^___________________________________ M_______________________P`/___]____________________O_________ M________________________________________________\ #____?____ M_______________[____________________________________________ M______________ `____W___________________^___________________ M_______________________________________P`/___]______________ M____________________________________________________________ M____\ #____ ```````````````````````````````````````````````` M````````````````````````````````__<'W_______________________ M_______________________________________________________P`/_U M7]__________________________________________________________ M____________________\ #_^N_?________________________________ M______________________________________________ `__KWW_______ M____________________________________________________________ M___________P`/_ZM]__________________________________________ M____________________________________\ #__<_?________________ M___[________________________________________________________ M__ `____W___________________^_______________________________ M___________________________P`/___]____________________O_____ M____________________________________________________\ #____? M___________________[________________________________________ M__________________ `____W___________________^_______________ M___________________________________________P`/___]__________ M__________O_________________________________________________ M________\ #____?___________________[________________________ M__________________________________ `____W___________________ M^__________________________________________________________P M`/___]____________________O_________________________________ M________________________\ #____?___________________[________ M__________________________________________________ `____W___ M________________^___________________________________________ M_______________P`/___]____________________O_________________ M________________________________________\ #____?____________ M_______[____________________________________________________ M______ `____P `````````````````````````````````````````````` M`````````````````````````````````/_W;]____________________O_ M________________________________________________________\ #_ M]6_?___________________[____________________________________ M______________________ `__KOW___________________^___________ M_______________________________________________P`/_Z[]______ M______________O_____________________________________________ M____________\ #_^L_?___________________[____________________ M______________________________________ `__WOW_______________ M____^_______________________________________________________ M___P`/___]____________________O_____________________________ M____________________________\ #____?___________________[____ M______________________________________________________ `____ MW___________________^_______________________________________ M___________________P`/___]____________________O_____________ M____________________________________________\ #____?________ M____________________________________________________________ M__________ `____W___________________________________________ M___________________________________P`/___]__________________ M____________________________________________________________ M\ #____?____________________________________________________ M__________________________ `____W___________________________ M___________________________________________________P`/___]__ M____________________________________________________________ M________________\ #____?____________________________________ M__________________________________________ `____W___________ M____________________________________________________________ M_______P`/_W3\ ````````````````````````````````````````````` M``````````````````````````````````#_]3??___________________[ M__________________________________________________________ ` M__JWW___________________^___________________________________ M_______________________P`/_ZM]____________________O_________ M________________________________________________\ #_^K??____ M_______________[____________________________________________ M______________ `__W/W___________________^___________________ M_______________________________________P`/___]______________ M______O_____________________________________________________ M____\ #____?___________________[____________________________ M______________________________ `____W___________________^___ M_______________________________________________________P`/__ M_]____________________O_____________________________________ M____________________\ #____?___________________[____________ M______________________________________________ `____W_______ M____________^_______________________________________________ M___________P`/___]____________________O_____________________ M____________________________________\ #____?________________ M___[________________________________________________________ M__ `____W___________________^_______________________________ M___________________________P`/___]____________________O_____ M____________________________________________________\ #____? M___________________[________________________________________ M__________________ `____W___________________^_______________ M___________________________________________P`/___]__________ M__________O_________________________________________________ M________\ #____?___________________[________________________ M__________________________________ `````'___________________ M^__________________________________________________________P M`/________________________O_________________________________ M________________________\ #________________________[________ M__________________________________________________ `________ M________________^___________________________________________ M_______________P`!__________________________________________ M________________________________________\ #_________________ M____________________________________________________________ M______ `____________________________________________________ M_______________________________P`!__________________________ M________________________________________________________\ #_ M____________________________________________________________ M______________________ `____________________________________ M_______________________________________________P`!__________ M____________________________________________________________ M____________\ #_____________________________________________ M______________________________________ `____________________ M____^_______________________________________________________ M___P`/________________________O_____________________________ M____________________________\ #________________________[____ M______________________________________________________ `____ M____________________^_______________________________________ M___________________P`/________________________O_____________ M____________________________________________\ #_____________ M___________[________________________________________________ M__________ `________________________^_______________________ M___________________________________P`/______________________ M__O_________________________________________________________ "\ `` ` endArticle: 22879
I forget to tell that the purpose of the FCD is to pulse when i get edge on the clock input. Any idea what should I do else? Simon Bilodeau <simon.bilodeau@htrc.com> a écrit dans le message : tpAY4.2264$B_1.60485@weber.videotron.net... > Hi, i am in a design using a XC9500 IC from Xilinx and I have a problem > with the logic simulator : the Q output from the FDC is always undefined, > even if I clock the input. > > Any idea > > Thanks > > Simon > > >Article: 22880
On Mon, 29 May 2000 16:28:09 -0400, "Simon Bilodeau" <simon.bilodeau@htrc.com> wrote: The late-but-somehow-immortal Henny Youngman told the following joke. A man walks into a doctor and says, "Doctor, it hurts when I do that." The doctor says, "Don't do that." You are attempting to asynchronously reset a flip-flop with its own Q output. Don't do that. It confuses the simulator (as you've seen), and in the actual hardware will produce a pulse of unknown width that may or may not be wide enough to do what you want to do. (If Murphy has any say in it, it will do what you want in the prototype but not in the production units.) Before I can suggest how to fix this, I need to have a better idea of just what you're trying to accomplish. Bob Perlman >Hi, i am in a design using a XC9500 IC from Xilinx and I have a problem >with the logic simulator : the Q output from the FDC is always undefined, >even if I clock the input. > >Any idea > >Thanks > >Simon > ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 22881
Unless you intend to package and sell the CORE, there is really no need to put it under coregen. Coregen is not much more than a pretty wrapper for edif netlist files. Instead, just instantiate your code as a component in a hierarchical VHDL design. If you are trying to do placement as well, I've found the best way to do it hierarchically is to put placement attributes right into the VHDL, which means you build the components from the structural level (I think this is probably why you want to create a component under the COREGEN). Alternatively, you can instantiate your core as a blackbox in VHDL under which you have an edif netlist (that is all coregen does with it). Look under the design guides for mixed schematic/HDL design methodology for details on instantiating black boxes in your design. Vipan Kakkar wrote: > Dear friends: > > I have a vhdl description for an FIR filter make one of the tap as a > core to use it to implement the FIR filter in FPGA. I was trying to > build one tap as a core using the Xilinx COREGEN, but don't know how to > do it. Coregen library has FIR filter, but I want to build a core from > my vhdl description of the tap, which is shown below: > > Could anyone help me that ... if it is possible to build a core from the > vhdl description I have ... if yes then what commands (in the COREGEN) > should be given and what files (e.g. .xco etc.). > > entity FIRTAP is > port( > CLK_S : in std_logic_vector( 8 downto 0); > RSTn_S : in std_logic_vector( 8 downto 0); > LDCOEF : in std_logic; > COEFi : in std_logic_vector(15 downto 0); > COEFo : out std_logic_vector(15 downto 0); > I : in std_logic_vector(15 downto 0); > O : out std_logic_vector(15 downto 0); > PI : in std_logic_vector(63 downto 0); > PO : out std_logic_vector(63 downto 0)); > end FIRTAP; > > Regards, > Vipan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 22882
nestor@ece.concordia.ca wrote: ... :2nd Structure: :-------------- :Mostly digital 2nd order PLL, with only the VCXO and some other :components being analog. : : : Digital Digital DAC followed by 100MHz :Fref --> Phase/ --> 1st Order --> an Analog Low --> VCXO : Frequency Active Pass Filter (analog) : Comparator Loop Filter | : /|\ | : | | : | | : ------- Divide-by-4 <-------------------------- : (Digital) : :-DAC: Digital-to-Analog Converter :-The analog Low Pass Filter can be a simple RC network to smooth out :the DAC staircase output. :-If I use the Phase/Frequency Comparator shown in the Xilinx or :Lattice AppNotes, I probably need to include something between it and :the digital loop filter, since the comparator produces only high and :low levels, not actual values that are needed at the loop filter :inputs. I propose a counter of some sort but I am open to other :suggestions. :-The phase/frequency comparator is the same as the one shown in the :Xilinx and Lattice AppNotes (see 1st structure above). : The problem here is, that as the loop approaches lock, the phase detector emits increasingly narrow pulses. That is, a spectrum having its energy at increasingly high frequencies. Once a significant amount of this energy is present above the digital filter's Nyquist frequency, the loop will fail, hunting back and forth about null, but never converging. If this is acceptable, you may get by, but if a spectrally pure (constant frequency) clock is desired, no. The sampling detector using a sinusoidal input does work, as it produces a truly analog output.Article: 22883
David R Brooks wrote: > > nestor@ece.concordia.ca wrote: > > ... > :2nd Structure: > :-------------- > :Mostly digital 2nd order PLL, with only the VCXO and some other > :components being analog. > : > : > : Digital Digital DAC followed by 100MHz > :Fref --> Phase/ --> 1st Order --> an Analog Low --> VCXO > : Frequency Active Pass Filter (analog) > : Comparator Loop Filter | > : /|\ | > : | | > : | | > : ------- Divide-by-4 <-------------------------- > : (Digital) > : > :-DAC: Digital-to-Analog Converter > :-The analog Low Pass Filter can be a simple RC network to smooth out > :the DAC staircase output. > :-If I use the Phase/Frequency Comparator shown in the Xilinx or > :Lattice AppNotes, I probably need to include something between it and > :the digital loop filter, since the comparator produces only high and > :low levels, not actual values that are needed at the loop filter > :inputs. I propose a counter of some sort but I am open to other > :suggestions. > :-The phase/frequency comparator is the same as the one shown in the > :Xilinx and Lattice AppNotes (see 1st structure above). > : > The problem here is, that as the loop approaches lock, the phase > detector emits increasingly narrow pulses. That is, a spectrum having > its energy at increasingly high frequencies. Once a significant amount > of this energy is present above the digital filter's Nyquist > frequency, the loop will fail, hunting back and forth about null, but > never converging. If this is acceptable, you may get by, but if a > spectrally pure (constant frequency) clock is desired, no. > The sampling detector using a sinusoidal input does work, as it > produces a truly analog output. Grab the data on the Philips HEF4046 / 74HC4046/7046/9046 family. They have various simple phase detectors in this family By using a Tristate drive, ( FPGA std ) you can use the RC filter as the DAC, and thus simplify the FPGA core. This type of tristate drive does have a small charge injection effect, as the pulse width cannot trend to 0.0nS, so some systems use a deliberate bias to avoid this effect. Higher performance systems can use more than one Phase Detector, one for fast lock, and the second one with higher phase gain is used once inside a lock window. Sample and holds can also provide an effective means of removal of the Phase integration section ( typ triangle pulse ), and allow feed of smooth DC into the VCO. This will cost a 74HC1G66 or similar, as I have not (yet) seen Analog SW gates in FPGA IO. - jg -- ======= 80x51 Tools & IP Specialists ========= = Want to work smarter than C ? = http://www.DesignTools.co.nz/modbench.htm = http://www.DesignTools.co.nzArticle: 22884
I do extensive work with Xilinx Virtex and XC4000 series FPGAs and PCB design and am looking for a job in Germany. Does anyone out there know of any companies in Germany that do this kind of work (and are looking for engineers)? Thanks in advance, Matt OwensArticle: 22885
Hello, I'm novice in working with FPGA and I search also for any kind of information about them. Could you tell me more about this free PCB programmer and from where I could get it. Thank you! Latchezar Kostov In article <39321D70.3AC402F7@olfac.univ-lyon1.fr>, Bernard Bertrand <bertrand@olfac.univ-lyon1.fr> wrote: > Hello, > > I start working in VHDL and I purchase a free PCB programmer > for programming CPLD or FPGA chip(Xillinx, Altera, Cypress...) > > Thank you for any information. > > B.Bertrand > bertrand@olfac.univ-lyon1.fr > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22886
lkostov@my-deja.com wrote: Hello Latchezar Kostov I don't have this free PCB I search this. Look again my E-mail. Best Regards > Hello, I'm novice in working with FPGA and I search also for any kind of > information about them. Could you tell me more about this free PCB programmer > and from where I could get it. > > Thank you! > Latchezar Kostov > > In article <39321D70.3AC402F7@olfac.univ-lyon1.fr>, > Bernard Bertrand <bertrand@olfac.univ-lyon1.fr> wrote: > > Hello, > > > > I start working in VHDL and I purchase a free PCB programmer > > for programming CPLD or FPGA chip(Xillinx, Altera, Cypress...) > > > > Thank you for any information. > > > > B.Bertrand > > bertrand@olfac.univ-lyon1.fr > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 22887
I need to pulse on the enable line of a 3 to 8 demux that will allow to reset a flip-flop (I use A0-3) to choose the flip-flop. I only need a short pulse to do that. Simon Bob Perlman <bobperl@best_no_spam_thanks.com> a écrit dans le message : 3932e99c.13144661@nntp.best.com... > On Mon, 29 May 2000 16:28:09 -0400, "Simon Bilodeau" > <simon.bilodeau@htrc.com> wrote: > > The late-but-somehow-immortal Henny Youngman told the following joke. > A man walks into a doctor and says, "Doctor, it hurts when I do that." > The doctor says, "Don't do that." > > You are attempting to asynchronously reset a flip-flop with its own Q > output. Don't do that. It confuses the simulator (as you've seen), > and in the actual hardware will produce a pulse of unknown width that > may or may not be wide enough to do what you want to do. (If Murphy > has any say in it, it will do what you want in the prototype but not > in the production units.) > > Before I can suggest how to fix this, I need to have a better idea of > just what you're trying to accomplish. > > Bob Perlman > > > >Hi, i am in a design using a XC9500 IC from Xilinx and I have a problem > >with the logic simulator : the Q output from the FDC is always undefined, > >even if I clock the input. > > > >Any idea > > > >Thanks > > > >Simon > > > > ----------------------------------------------------- > Bob Perlman > Cambrian Design Works > Digital Design, Signal Integrity > http://www.best.com/~bobperl/cdw.htm > Send e-mail replies to best<dot>com, username bobperl > -----------------------------------------------------Article: 22888
In article <392D10AE.51F87133@utc.fr>, Sebastien Favard <Sebastien.Favard@utc.fr> wrote: > Hi, > > I search Spartan XS05 for a small quantity. Here I know a vendor that he > sell me it ar $20 !!!!! yes $20 and not $2 :( > > If anyone know a web-buisness or others.... I bought a small quantity of XS05XL-4PC84C a few months ago from Microcall (Now Insight-Memec) here in the UK for 5.72 UKP each. Leon -- Leon Heller, G1HSM Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22889
On Mon, 29 May 2000 13:45:07 GMT, Ray Andraka <ray@andraka.com> wrote: >If you are looking at an analog PLL with a digital feedback, you might try >an 88915 (IDT, motorola), which is a fairly standard low cost vanilla PLL >made for clock replication. It has the VCO, phase comparator and loop >filter in one 20 pin(?) SOIC package along with low skew outputs for 2x, 5 >1x and a halx x output. Since the feedback and reference input is >external, it is easy to add dividers in the feedback and reference paths >to permit frequency synthesis. I've put the dividers as well as >monitoring circuits in both FPGAs and CPLDs with good results. The only >external component needed for the loop filter is a ceramic cap, so the >parts count is low and there is no design tweaking. With the buffered low >skew outputs, you may have enough clock drivers for your whole system, and >you get the 1x,2x and 1/2x outputs already made and deskewed for you. Thanks, Ray, for your suggestion. The part you propose seems to do all that I want and at the frequency that I want (IDT's). The only catch that I see is that the reference signal must always be present. Because I will use an intermittent reference tone in order to share the same channel with other data transmissions, I don't think I can use this chip directly since the non-clock data will cause the chip to behave incorrectly. From what I understand, there is no hold function for the generated frequency in the block diagram. I will still pursue this alternative as a backup solution. >> >> P.S.: As a side question, I am thinking of implementing the PLL to >> synthesize the system's clock without always having the reference >> frequency present. This requires the freezing of the comparator >> outputs or the loop filter outputs, as well as a periodic refresh by >> retransmitting the reference at regular intervals. I am not sure, >> though, if this can cause the loop to temporarily lose lock or >> possibly cause it to start up anew using a completely different phase >> value. However, I think the frequency should not vary much. Any >> comments? > >You don't want to use the VCO in a freee running mode like this. It is >not a very stable source without a reference, so it will drift >considerably. You might be able to construct a simple DPLL to >replicate/synthesize the reference from a crystal source and then use the >PLL to multiply that reference up to your system clock. The DPLL could >then be used to discover the correct count values and then hold those >counts when the reference dissappears. In order to avoid "floating" the input of the VCXO, I was thinking of freezing the DAC output to the last valid voltage level, so that the VCXO could maintain a stable frequency until the next reference tone refresh. Regards. Nestor nestor@ece.concordia.caArticle: 22890
On Mon, 29 May 2000 02:54:22 -0400, Rickman <spamgoeshere4@yahoo.com> wrote: >I took a look at a book I have by Roland E. Best called "Phase Locked >Loops". It covers most of the types pretty well although I have never >built one from it. He describes several types of digital PLLs, but none >of them would be easy to use at the high frequencies you are describing. >They all need a digital clock that runs at rates much higher than your >100 MHz. I think your second design with a digital loop filter will have >the same problem. To use a counter as you describe, I think you will >need a very fast clock that can count many cycles in the 40 nS period of >your reference clock. Thanks for your very descriptive response, Rick. If I reduce my oscillator frequency by say 100 times so that the reference now equals 1MHz, then I could run the counter fast enough (maybe 100MHz) and still be using a low enough reference to satisfy jitter requirements. Would you know the amount by which the jitter will be reduced using the new reference? > >Best does describe one circuit that uses a "Zero Crossing" Phase >Detector (PD) that uses the reference clock to ADC sample the input >signal (assuming it is not a digital clock but a sinewave). The >resulting digital sample stream can be converted back to analog and used >as the VCXO control signal. The filter block can be a simple averaging >filter which can be easily done in the FPGA with an accumulator and a >delay block, or as an IIR filter with only an accumulator. I am thinking of a first-order digital loop filter which sums two components: the direct path with a gain G1 applied to it, and an accumulator branch with a gain G2 applied to it (either before of after the accumulator). > >BTW, I don't think in your digital loop filter circuit that you need an >analog filter after the DAC. At this point the DAC output is the control >signal and any filtering will just add a delay to the loop and possibly >make it unstable. The normal purpose of a loop filter is to average an >AC signal to eliminate fluctuations within a cycle. Too much filtering >is bad. The small steps you will expect from a digital loop filter >should not cause problems in your VCXO. You are correct. I expect small voltage adjustments to the VCXO and so the ADC will already be slowly changing. This output signal can be used directly to control the VCXO. > >If you really need to disconnect your refrence from the circuit for >extended periods of time, a digital loop filter will allow you to >implement a better "hold" circuit than an analog filter. You simply hold >the last VCXO control signal to the DAC. The hard part will be detecting >that your reference is gone before the PLL starts to hunt. I assume you >would have control over this and put it into hold mode before the signal >goes away. > I can take care of this since I since in advance the duration of the transmitted reference during initialization or re-acquisition fo the loop. > >nestor@ece.concordia.ca wrote: >> >> Hi everyone. >> >> Back in late February I posted a message in order to gain some insight >> in designing a digital phase-locked loop (DPLL) for frequency >> synthesis to be used as the master clock of an FPGA system. I had >> received a number of useful replies (thanks to all who provided >> feedback) and links to some application notes that have helped me to >> better understand the design of a PLL. I have consulted some other >> references on PLL design as well, including Gardner's and Rohde's >> books. >...snip... >> All your suggestions are very much appreciated. Thanks in advance, >> >> Nestor >> nestor@ece.concordia.ca >> >> P.S.: As a side question, I am thinking of implementing the PLL to >> synthesize the system's clock without always having the reference >> frequency present. This requires the freezing of the comparator >> outputs or the loop filter outputs, as well as a periodic refresh by >> retransmitting the reference at regular intervals. I am not sure, >> though, if this can cause the loop to temporarily lose lock or >> possibly cause it to start up anew using a completely different phase >> value. However, I think the frequency should not vary much. Any >> comments? > >I think that reconnecting the reference will cause a disruption in the >output frequency as the circuit locks in. But I don't think you will >come to a different phase value unless the reference freq has changed. My reference frequency will always be generated from the same source, hence the frequency should remain constant. However, I am not 100% certain I can guarantee the same phase always arriving at the PLL (although theoretically the phase should not change if the path to the PLL does not change), and I worry that the different phase can cause the PLL to output a sincewave with a different phase. How do you explain that the the re-locked frequency can change? Is it because the PLL can re-lock using a completely different start frequency, even when the output frequency is held constant in the absence of the reference? I await your comments. Thanks. Nestor nestor@ece.concordia.ca >If I understand these things properly, the VCXO is like a spring on the >gas pedal. To go a given speed, you will always be pressing the spring a >certain amount (the phase error in this case). To go faster, you will >need a larger phase error which presses on the pedal harder. The only >way around this is to use an integrator function in the loop and then >you will have to damp oscillations. > >I hope I am not coming across like an expert at this, I am not. This is >just free advice, so it is likely worth what you are paying. ;)Article: 22891
Hi Nestor... A few suggestions... 1) If you want to minimize jitter (i.e. <30ps RMS), a digital PLL is not your best choice... The minimum jitter is always going to be a function of the sample clock as you must quantize the Phase Comp's error signal... The error voltage produced by this quantization and sample uncertainty in the DAC will result in poor jitter performance vs your 1st Structure at greater complexity and cost... 2) If your really, really, really worried about jitter (sadly, I am...), you should be aware of the concept of deadband. Deadband exists in all phase comp's where the output error signal is comprised of two signals, such as the 'up' and 'down' signals in the Xilinx and Lattice examples. The difference in propagation times for these two paths will result in a "dead" region in the phase/voltage characteristic of the phase comp, which in turn manifests itself as jitter for certain input frequencies. Dedicated PLL chips are designed to minimize this effect, but a FPGA may have very different P&R dependant propagation delays for the 'up' and 'down' signals. There's a good description of deadband in Behzad Razavi's PLL tutorial in the preface of "Monolithic Phase-Locked Loops and Clock Recovery Circuits, Theory and Design" ISBN 0-7803-1149-3. 3) On your comment about 'freezing' the control voltage... Without understanding exactly what you application is, the general answer will be that the VCO frequency will always drift wrt to the reference clock if your running open look, creating an asynchronous condition... If your designing around an asynchronous condition, the steps you would have to take to make it work for a small (frozen) frequency drift would be about the same as a few hundred ppm of frequency drift (ie. unfrozen, free running VCXO)... I'd want to be quite sure that adding the 'freezing' capability was really necessary given the extra cost and complexity. Having a simple loop with a long time constant will likely likely work better... The one case where this freezing may be useful is in an application where a TCXO or OCXO needs to be calibrated... You can let the T(O)CXO lock on to the reference signal, and store the frozen value as a calibration value in EEPROM... EEPROM based digital pots work great for this... 4) I would avoid exotic schemes like selectable filter constants or phase comps... They're very difficult to implement properly. Good Luck, John nestor@ece.concordia.ca wrote in message ... >Hi everyone. > >Back in late February I posted a message in order to gain some insight >in designing a digital phase-locked loop (DPLL) for frequency >synthesis to be used as the master clock of an FPGA system. I had >received a number of useful replies (thanks to all who provided >feedback) and links to some application notes that have helped me to >better understand the design of a PLL. I have consulted some other >references on PLL design as well, including Gardner's and Rohde's >books...Article: 22892
On Mon, 29 May 2000 02:54:22 -0400, Rickman <spamgoeshere4@yahoo.com> wrote: >I took a look at a book I have by Roland E. Best called "Phase Locked >Loops". It covers most of the types pretty well although I have never >built one from it. He describes several types of digital PLLs, but none >of them would be easy to use at the high frequencies you are describing. >They all need a digital clock that runs at rates much higher than your >100 MHz. I think your second design with a digital loop filter will have >the same problem. To use a counter as you describe, I think you will >need a very fast clock that can count many cycles in the 40 nS period of >your reference clock. Thanks for your very descriptive response, Rick. If I reduce my oscillator frequency by say 100 times so that the reference now equals 1MHz, then I could run the counter fast enough (maybe 100MHz) and still be using a low enough reference to satisfy jitter requirements. Would you know the amount by which the jitter will be reduced using the new reference? > >Best does describe one circuit that uses a "Zero Crossing" Phase >Detector (PD) that uses the reference clock to ADC sample the input >signal (assuming it is not a digital clock but a sinewave). The >resulting digital sample stream can be converted back to analog and used >as the VCXO control signal. The filter block can be a simple averaging >filter which can be easily done in the FPGA with an accumulator and a >delay block, or as an IIR filter with only an accumulator. I am thinking of a first-order digital loop filter which sums two components: the direct path with a gain G1 applied to it, and an accumulator branch with a gain G2 applied to it (either before of after the accumulator). > >BTW, I don't think in your digital loop filter circuit that you need an >analog filter after the DAC. At this point the DAC output is the control >signal and any filtering will just add a delay to the loop and possibly >make it unstable. The normal purpose of a loop filter is to average an >AC signal to eliminate fluctuations within a cycle. Too much filtering >is bad. The small steps you will expect from a digital loop filter >should not cause problems in your VCXO. You are correct. I expect small voltage adjustments to the VCXO and so the ADC will already be slowly changing. This output signal can be used directly to control the VCXO. > >If you really need to disconnect your refrence from the circuit for >extended periods of time, a digital loop filter will allow you to >implement a better "hold" circuit than an analog filter. You simply hold >the last VCXO control signal to the DAC. The hard part will be detecting >that your reference is gone before the PLL starts to hunt. I assume you >would have control over this and put it into hold mode before the signal >goes away. > I can take care of this since I since in advance the duration of the transmitted reference during initialization or re-acquisition fo the loop. > >nestor@ece.concordia.ca wrote: >> >> Hi everyone. >> >> Back in late February I posted a message in order to gain some insight >> in designing a digital phase-locked loop (DPLL) for frequency >> synthesis to be used as the master clock of an FPGA system. I had >> received a number of useful replies (thanks to all who provided >> feedback) and links to some application notes that have helped me to >> better understand the design of a PLL. I have consulted some other >> references on PLL design as well, including Gardner's and Rohde's >> books. >...snip... >> All your suggestions are very much appreciated. Thanks in advance, >> >> Nestor >> nestor@ece.concordia.ca >> >> P.S.: As a side question, I am thinking of implementing the PLL to >> synthesize the system's clock without always having the reference >> frequency present. This requires the freezing of the comparator >> outputs or the loop filter outputs, as well as a periodic refresh by >> retransmitting the reference at regular intervals. I am not sure, >> though, if this can cause the loop to temporarily lose lock or >> possibly cause it to start up anew using a completely different phase >> value. However, I think the frequency should not vary much. Any >> comments? > >I think that reconnecting the reference will cause a disruption in the >output frequency as the circuit locks in. But I don't think you will >come to a different phase value unless the reference freq has changed. My reference frequency will always be generated from the same source, hence the frequency should remain constant. However, I am not 100% certain I can guarantee the same phase always arriving at the PLL (although theoretically the phase should not change if the path to the PLL does not change), and I worry that the different phase can cause the PLL to output a sincewave with a different phase. How do you explain that the the re-locked frequency can change? Is it because the PLL can re-lock using a completely different start frequency, even when the output frequency is held constant in the absence of the reference? I await your comments. Thanks. Nestor nestor@ece.concordia.ca >If I understand these things properly, the VCXO is like a spring on the >gas pedal. To go a given speed, you will always be pressing the spring a >certain amount (the phase error in this case). To go faster, you will >need a larger phase error which presses on the pedal harder. The only >way around this is to use an integrator function in the loop and then >you will have to damp oscillations. > >I hope I am not coming across like an expert at this, I am not. This is >just free advice, so it is likely worth what you are paying. ;)Article: 22893
On Mon, 29 May 2000 13:45:07 GMT, Ray Andraka <ray@andraka.com> wrote: >If you are looking at an analog PLL with a digital feedback, you might try >an 88915 (IDT, motorola), which is a fairly standard low cost vanilla PLL >made for clock replication. It has the VCO, phase comparator and loop >filter in one 20 pin(?) SOIC package along with low skew outputs for 2x, 5 >1x and a halx x output. Since the feedback and reference input is >external, it is easy to add dividers in the feedback and reference paths >to permit frequency synthesis. I've put the dividers as well as >monitoring circuits in both FPGAs and CPLDs with good results. The only >external component needed for the loop filter is a ceramic cap, so the >parts count is low and there is no design tweaking. With the buffered low >skew outputs, you may have enough clock drivers for your whole system, and >you get the 1x,2x and 1/2x outputs already made and deskewed for you. Thanks, Ray, for your suggestion. The part you propose seems to do all that I want and at the frequency that I want (IDT's). The only catch that I see is that the reference signal must always be present. Because I will use an intermittent reference tone in order to share the same channel with other data transmissions, I don't think I can use this chip directly since the non-clock data will cause the chip to behave incorrectly. From what I understand, there is no hold function for the generated frequency in the block diagram. I will still pursue this alternative as a backup solution. >> >> P.S.: As a side question, I am thinking of implementing the PLL to >> synthesize the system's clock without always having the reference >> frequency present. This requires the freezing of the comparator >> outputs or the loop filter outputs, as well as a periodic refresh by >> retransmitting the reference at regular intervals. I am not sure, >> though, if this can cause the loop to temporarily lose lock or >> possibly cause it to start up anew using a completely different phase >> value. However, I think the frequency should not vary much. Any >> comments? > >You don't want to use the VCO in a freee running mode like this. It is >not a very stable source without a reference, so it will drift >considerably. You might be able to construct a simple DPLL to >replicate/synthesize the reference from a crystal source and then use the >PLL to multiply that reference up to your system clock. The DPLL could >then be used to discover the correct count values and then hold those >counts when the reference dissappears. In order to avoid "floating" the input of the VCXO, I was thinking of freezing the DAC output to the last valid voltage level, so that the VCXO could maintain a stable frequency until the next reference tone refresh. Regards. Nestor nestor@ece.concordia.caArticle: 22894
On Mon, 29 May 2000 15:19:39 +0100, dmac <dmac@cutme.matter200.demon.co.uk> wrote: > >Hi Nestor, > >I don't have your original request for info and so have lost track of >your intended application but offer some info from what you have given. > >I have not used type 2 but have used type 1 extensively with success. It >is a superbly simple circuit and so wins hands down in my book - you >could have the basics working in no time. > >I notice that you are intending a comparison frequency of 25MHz in the >phase comparator section. I would avoid this - notice that Peter's Xil >Apps note uses a comparison freq of around 5kHz. The benefits of this >are jitter reduction, filter simplicity (audio range) and simpler >stability calcs. A lower comparison frequency is easily achieved by >dividing the reference and feedback paths by the same amount. Thanks, Dave, for your response. I read the xilinx AppNote too and noticed this low reference, but Peter doesn't mention what frequency he intends to generate with that reference. I do agree that the design will be simpler since certain sections could operate slower. Do you know perhaps how the jitter depends on the reference tone? I would like to perforom some calculations to determine the maximum reference frequency that can also provide a small enough jitter. So far I know that the jitter is related to the loop variance which can be derived from the loop bandwidth. Any comments are welcome. Nestor nestor@ece.concordia.ca > >Peter also mentions ... >... >Watch out also for the type of VCXO used. At the frequency you are >talking, the mfr may use a lower rate item with a freq tripler stage. >Ours did - I think 'cos we wanted a big spread (+/-250ppm) - this will >have greater jitter. 3rd overtone VCXO (the alternative) has, I think, >lower pull range. As you are looking for +/-300ppm, watch out. If you >can reduce the spread, do, as lower spread oscs will be better behaved >and easier (cheaper) to procure. I will see if I can use a narrower range VCXO (+/-150ppm tuning range).Article: 22895
On Tue, 30 May 2000 07:41:19 +0800, David R Brooks <daveb@iinet.net.au> wrote: >: ... > The problem here is, that as the loop approaches lock, the phase >detector emits increasingly narrow pulses. That is, a spectrum having >its energy at increasingly high frequencies. Once a significant amount >of this energy is present above the digital filter's Nyquist >frequency, the loop will fail, hunting back and forth about null, but >never converging. If this is acceptable, you may get by, but if a >spectrally pure (constant frequency) clock is desired, no. Thanks for your response, David. I do want as pure a clock as possible, but I can tolerate some amount of jitter, as long as the effect you describe does not cause the PLL to lose and re-acquire lock. Can the narrow width pulses at the phase detector output cause the PLL to enter a pattern of lock loss and re-acquisition? > The sampling detector using a sinusoidal input does work, as it >produces a truly analog output. Can you provide some more details on this topic? Are you suggesting that to use the phase detector (described in the xilinx appnote) in conjunction with a sinusoidal input, or is this a completely different phase detector? If the latter is the case, could you provide a reference or a brief explanation on its structure and behaviour (if possible)? I would lie to examine as many options as I can before committing to a specific design. Thanks in advance, Nestor nestor@ece.concordia.caArticle: 22896
On Tue, 30 May 2000 12:29:58 +1200, Jim Granville <jim.granville@designtools.co.nz> wrote: >David R Brooks wrote: >> > ... > > Higher performance systems can use more than one Phase Detector, >one for fast lock, and the second one with higher phase gain is used >once inside a lock window. > Hi Jim. Thanks for your reply. This is an interesting concept that can obviously reduce lock time. I was under the impression that the loop filter coefficients were usually varied to control acquisition and tracking behavior (this should be true in a purely digital implementation). I will need to look into your suggestion in more detail. Regards, Nestor nestor@ece.concordia.caArticle: 22897
Hi everyone:
I have a problem of implmenting my LMS algorithm in an Altera
FLEX10K100A using VHDL. The weight update is like this
W(t+1)=W(t) + mu * e(t) *X(t)
where W(t): weight coefficient vector, and each element is with 20 bits.
mu: stepsize=0.001
e(t): 8 bits error signal
X(t): signal vector in FFE and DFE and each element is with 8
bits.
The requirements are 1) the design occpies the space as small as possible
and 2) the LMS is able to operating at 25MHz.
Although it is possible to design pipeline stages for 8X8 multiplication,
some delay will be incurred such that I need extra shift registers for W(t)
to get the addition synchronized and this may incurease the complexity.
On the other hand, if I directly do the multiplcation by using the available
block, the speed is below the expectation.
Any reference and suggestions are highly appreciated!
Thanks
James
Article: 22898
Hi everyone:
I have a problem of implmenting my LMS algorithm in an Altera
FLEX10K100A using VHDL. The weight update is like this
W(t+1)=W(t) + mu * e(t) *X(t)
where W(t): weight coefficient vector, and each element is with 20 bits.
mu: stepsize=0.001
e(t): 8 bits error signal
X(t): signal vector in FFE and DFE and each element is with 8
bits.
The requirements are 1) the design occpies the space as small as possible
and 2) the LMS is able to operating at 25MHz.
Although it is possible to design pipeline stages for 8X8 multiplication,
some delay will be incurred such that I need extra shift registers for W(t)
to get the addition synchronized and this may incurease the complexity.
On the other hand, if I directly do the multiplcation by using the available
block, the speed is below the expectation.
Any reference and suggestions are highly appreciated!
Thanks
James
Article: 22899
nestor@ece.concordia.ca (Nestor) wrote:
:On Tue, 30 May 2000 07:41:19 +0800, David R Brooks
:<daveb@iinet.net.au> wrote:
:>: ...
:> The sampling detector using a sinusoidal input does work, as it
:>produces a truly analog output.
:
:Can you provide some more details on this topic? Are you suggesting
:that to use the phase detector (described in the xilinx appnote) in
:conjunction with a sinusoidal input, or is this a completely
:different phase detector? If the latter is the case, could you
:provide a reference or a brief explanation on its structure and
:behaviour (if possible)? I would lie to examine as many options as I
:can before committing to a specific design.
:
This is a different type (also mentioned in Best). It requires a
reference signal having a finite slope to its waveform. Triangular or
sinusoidal will work, but rectangular pulses will not. The loop gain
is a function of the reference slope (determined by frequency &
amplitude).
It matches well with a switched-capacitor loop filter, but anything
which works by taking regular samples (eg digital filter) should work.
Imagine a PLL with a sinusoidal reference input, and a sampling
filter, which is clocked from the VCO (divided as necessary). Suppose
further, that the sample is presently taken on the rising "edge" of
the reference waveform. If now the VCO speeds up, the sample is taken
earlier, and a lower voltage is read. So (after filtering) the VCO
control voltage is reduced, and it slows down. Vice versa, for a VCO
which slows down, a later (higher) voltage is sampled, so speeding up
the VCO. If the PLL starts up sampling on the falling "edge", it will
be unstable, & will quickly shift to the rising "edge".
OK, let's try at a drawing (monospaced type, please):
S1 S2
/\ __ __
/ \/ ---o o-+-o o--+--------> Control voltage
Vref | |
=== ===
| C1 | C2
V V
S1 and S2 are driven by non-overlapping clocks derived from the VCO.
Together with C1, they simulate a resistance, with an input-sampling
function. This resistance, with C2, is a basic low-pass filter.
If the ON-resistance of S1 is low enough for C1 to follow the input
voltage while S1 is closed, then the sample is taken at the instant S1
opens.
This phase-detector has a transfer function similar to the reference
input, ie periodic. Consequently it has a limited capture range.
However this is unlikely to be a problem in a single-frequency
application, using a VCXO.
I built such a PLL some years ago for a Master's thesis: I found a
3rd capacitor necessary (in my application), to simulate the second
resistor of a common pole/zero filter. The circuit was entirely
fabricated on a chip, with the filter clocking at 132kHz (same as the
reference), the VCO running around 4.5MHz and divided down.
This design had to capture over a wide range, yielding a spectrally
pure output. This necessitated a frequency-lock to adjust the loop
parameters roughly into lock, then turning over control to the
sampler.
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