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Threads Starting May 2005
83488: 05/05/01: Harel Ashwal: Xilinxs XCF16 PROMS Eng. Samples Bugs?
83489: 05/05/01: Preben Holm: Xilinx input path: Why does the optional delay element with inputFF
83497: 05/05/01: Peter Alfke: Re: Xilinx input path: Why does the optional delay element with inputFF help me?
83559: 05/05/03: Preben Holm: Re: Xilinx input path: Why does the optional delay element with inputFF
83591: 05/05/03: Preben Holm: Re: Xilinx input path: Why does the optional delay element with inputFF
83642: 05/05/04: Eric Crabill: Re: Why does the optional delay element with input FF help me?
83498: 05/05/01: Peter Alfke: Re: Xilinx input path: Why does the optional delay element with inputFF help me?
83579: 05/05/03: Peter Alfke: Re: Xilinx input path: Why does the optional delay element with inputFF help me?
83604: 05/05/03: Peter Alfke: Re: Xilinx input path: Why does the optional delay element with inputFF help me?
83490: 05/05/01: <andyesquire@hotmail.com>: PCI-X target chip with simple backend interface....
83503: 05/05/01: Antti Lukats: Re: PCI-X target chip with simple backend interface....
83530: 05/05/02: <andyesquire@hotmail.com>: Re: PCI-X target chip with simple backend interface....
83491: 05/05/01: Frank de Groot: Cheap PowerPC G4 PCI coprocessor board for the PC
83627: 05/05/04: Ron Huizen: Re: Cheap PowerPC G4 PCI coprocessor board for the PC
83492: 05/05/01: design: cross clock timing constraints
83509: 05/05/01: Symon: Re: cross clock timing constraints
83531: 05/05/02: Symon: Re: cross clock timing constraints
83510: 05/05/01: Peter Alfke: Re: cross clock timing constraints
83519: 05/05/02: design: Re: cross clock timing constraints
83494: 05/05/01: Philipp Grabher: Microblaze FSL interface timing diagram
83500: 05/05/01: Paul Hartke: Re: Microblaze FSL interface timing diagram
83496: 05/05/01: <jjohnson@cs.ucf.edu>: Virtex4 and ISE reality check?
83502: 05/05/01: Antti Lukats: Re: Virtex4 and ISE reality check?
83508: 05/05/01: Antti Lukats: Re: Virtex4 and ISE reality check?
83512: 05/05/01: Paul Leventis (at home): Re: Virtex4 and ISE reality check?
83504: 05/05/01: Marc Randolph: Re: Virtex4 and ISE reality check?
83513: 05/05/01: Peter Alfke: Re: Virtex4 and ISE reality check?
83533: 05/05/02: Peter Alfke: Re: Virtex4 and ISE reality check?
83517: 05/05/02: vitoal18t: Reasonable Entry Level Dev. Board....
83523: 05/05/02: Neo: Re: Reasonable Entry Level Dev. Board....
83518: 05/05/02: Voxer: OPB Intc - HELP !!!!
83621: 05/05/04: digi: re:OPB Intc - HELP !!!!
83520: 05/05/02: Joey: Frequency Limit !!
83524: 05/05/02: Kolja Sulimma: Re: Frequency Limit !!
83525: 05/05/02: Tod Adamson: WTB: Xilinx 6.2i EDK
83526: 05/05/02: Antti Lukats: Re: Xilinx 6.2i EDK
83553: 05/05/02: Tod Adamson: Re: Xilinx 6.2i EDK
83555: 05/05/03: Antti Lukats: Re: Xilinx 6.2i EDK
83574: 05/05/03: Kolja Sulimma: Re: Xilinx 6.2i EDK
83527: 05/05/02: JD_Design: Xilinx V4 Power Calculations
83573: 05/05/03: Austin Lesea: Re: Xilinx V4 Power Calculations
83593: 05/05/03: Austin Lesea: Re: Xilinx V4 Power Calculations
83605: 05/05/03: Austin Lesea: Re: Xilinx V4 Power Calculations
83639: 05/05/04: Austin Lesea: Re: Xilinx V4 Power Calculations
83702: 05/05/05: Ed McGettigan: Re: Xilinx V4 Power Calculations
83706: 05/05/05: Austin Lesea: Re: Xilinx V4 Power Calculations
83725: 05/05/05: Ray Andraka: Re: Xilinx V4 Power Calculations
83761: 05/05/06: Austin Lesea: Re: Xilinx V4 Power Calculations
83587: 05/05/03: JD_Design: Re: Xilinx V4 Power Calculations
83590: 05/05/03: JD_Design: Re: Xilinx V4 Power Calculations
83601: 05/05/03: Brendan Cullen: Re: Xilinx V4 Power Calculations
83602: 05/05/03: JD_Design: Re: Xilinx V4 Power Calculations
83637: 05/05/04: JD_Design: Re: Xilinx V4 Power Calculations
83694: 05/05/05: JD_Design: Re: Xilinx V4 Power Calculations
83710: 05/05/05: JD_Design: Re: Xilinx V4 Power Calculations
83529: 05/05/02: Praveen: Performing Readback from Impact
83539: 05/05/02: Neil Glenn Jacobson: Re: Performing Readback from Impact
83552: 05/05/02: Neil Glenn Jacobson: Re: Performing Readback from Impact
83556: 05/05/03: Antti Lukats: Re: Performing Readback from Impact
83580: 05/05/03: Neil Glenn Jacobson: Re: Performing Readback from Impact
83545: 05/05/02: Praveen: Re: Performing Readback from Impact
83536: 05/05/02: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: writing with impact to eeprom
83540: 05/05/02: Neil Glenn Jacobson: Re: writing with impact to eeprom
83543: 05/05/02: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: writing with impact to eeprom
83537: 05/05/02: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: 200+ MHz through a SCSI cable
83564: 05/05/03: Gabor: Re: 200+ MHz through a SCSI cable
83571: 05/05/03: =?ISO-8859-1?Q?Benjamin_Menk=FCc?=: Re: 200+ MHz through a SCSI cable
83575: 05/05/03: =?ISO-8859-1?Q?Benjamin_Menk=FCc?=: Re: 200+ MHz through a SCSI cable
83726: 05/05/06: Thomas Rudloff: Re: 200+ MHz through a SCSI cable
83577: 05/05/03: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: I got it!
83632: 05/05/04: John_H: Re: I got it!
83699: 05/05/05: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: I got it!
83704: 05/05/05: John_H: Re: I got it!
83705: 05/05/05: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: I got it!
83541: 05/05/02: AL: Re: Force sequential assigment
83542: 05/05/02: AL: Re: Force sequential assigment
83544: 05/05/02: Markus Knauss: JTAG communication Problems in Quartus using Signal Tap
83546: 05/05/02: Ben Twijnstra: Re: JTAG communication Problems in Quartus using Signal Tap
83557: 05/05/03: Markus Knauss: Re: JTAG communication Problems in Quartus using Signal Tap
83558: 05/05/03: Laurent Gauch: Re: JTAG communication Problems in Quartus using Signal Tap
83569: 05/05/03: Ben Twijnstra: Re: JTAG communication Problems in Quartus using Signal Tap
83583: 05/05/03: Markus Knauss: Re: JTAG communication Problems in Quartus using Signal Tap
83585: 05/05/03: Amontec, Larry: Re: JTAG communication Problems in Quartus using Signal Tap
83549: 05/05/02: Thomas Fischer: Re: JTAG communication Problems in Quartus using Signal Tap
83582: 05/05/03: Markus Knauss: Re: JTAG communication Problems in Quartus using Signal Tap
83643: 05/05/04: Ben Twijnstra: Re: JTAG communication Problems in Quartus using Signal Tap
83691: 05/05/05: Markus Knauss: Re: JTAG communication Problems in Quartus using Signal Tap
83550: 05/05/03: Rafa: JTAG without parallel port
83551: 05/05/02: Uwe Bonnes: Re: JTAG without parallel port
83560: 05/05/03: Hendra: Re: JTAG without parallel port
83578: 05/05/03: John Adair: Re: JTAG without parallel port
83561: 05/05/03: Rudolf Usselmann: Memec/Insight LX25LC Board Flash Troubles
83563: 05/05/03: CODE_IS_BAD: Max freq. of operation in FPGA?
83565: 05/05/03: Marc Randolph: Re: Max freq. of operation in FPGA?
83614: 05/05/03: CODE_IS_BAD: Re: Max freq. of operation in FPGA?
83617: 05/05/03: Marc Randolph: Re: Max freq. of operation in FPGA?
83566: 05/05/03: el231bat: Re: LM4550 Audio Codec
83568: 05/05/03: Paul Boven: DCM, constraints and routing (Xilinx Spartan 3)
83588: 05/05/03: Berty: Re: DCM, constraints and routing (Xilinx Spartan 3)
83658: 05/05/04: Vladislav Muravin: Re: DCM, constraints and routing (Xilinx Spartan 3)
83572: 05/05/03: Mohammed A Khader: Negative hold time from Quartus
83584: 05/05/03: Berty: Re: Negative hold time from Quartus
83576: 05/05/03: Berty: Re: Force sequential assigment
83594: 05/05/03: AL: Re: Force sequential assigment
83581: 05/05/03: bart: Multiply Accumulate FPGA/DSP
83596: 05/05/03: Sylvain Munaut: Re: Multiply Accumulate FPGA/DSP
83597: 05/05/03: Thomas Womack: Re: Multiply Accumulate FPGA/DSP
83598: 05/05/03: Thomas Womack: Re: Multiply Accumulate FPGA/DSP
83600: 05/05/03: Symon: Re: Multiply Accumulate FPGA/DSP
83618: 05/05/04: ahosyney: Re: Multiply Accumulate FPGA/DSP
83626: 05/05/04: Tobias Weingartner: Re: Multiply Accumulate FPGA/DSP
83653: 05/05/04: Ben Twijnstra: Re: Multiply Accumulate FPGA/DSP
83667: 05/05/04: Ben Twijnstra: Re: Multiply Accumulate FPGA/DSP
83733: 05/05/05: Ray Andraka: Re: Multiply Accumulate FPGA/DSP
83734: 05/05/06: Bob Perlman: Re: Multiply Accumulate FPGA/DSP
83738: 05/05/05: Ray Andraka: Re: Multiply Accumulate FPGA/DSP
83628: 05/05/04: bart: Re: Multiply Accumulate FPGA/DSP
83641: 05/05/04: Peter Alfke: Re: Multiply Accumulate FPGA/DSP
83657: 05/05/04: Peter Alfke: Re: Multiply Accumulate FPGA/DSP
83735: 05/05/05: Peter Alfke: Re: Multiply Accumulate FPGA/DSP
83586: 05/05/03: <walterwang@gmail.com>: VHDL help with adding modules
83608: 05/05/03: John M: Re: VHDL help with adding modules
83615: 05/05/03: CODE_IS_BAD: Re: VHDL help with adding modules
83620: 05/05/04: digi: re:VHDL help with adding modules
83589: 05/05/03: Joseph: Simulating custom peripherals
83622: 05/05/04: digi: re:Simulating custom peripherals
83722: 05/05/05: Joseph: Re: Simulating custom peripherals
83813: 05/05/06: Joseph: Re: Simulating custom peripherals
83899: 05/05/09: Joseph: Re: Simulating custom peripherals
83903: 05/05/09: Paul Hartke: Re: Simulating custom peripherals
83904: 05/05/09: Joseph: Re: Simulating custom peripherals
83595: 05/05/03: AL: Re: Force sequential assigment
83610: 05/05/03: bta3: Altera Excalibur EBI problem
83624: 05/05/04: Mike Lewis: Re: Altera Excalibur EBI problem
83723: 05/05/05: bta3: Re: Altera Excalibur EBI problem
84142: 05/05/13: <seannstifler69@hotmail.com>: Re: Altera Excalibur EBI problem
83611: 05/05/03: Mayil: ERROR: NgdBuild:604 - logical block
83612: 05/05/03: Paul Hartke: Re: ERROR: NgdBuild:604 - logical block
83662: 05/05/04: Mayil: Re: ERROR: NgdBuild:604 - logical block
83623: 05/05/04: Wenju Fu: Gated clock problem
83630: 05/05/04: John_H: Re: Gated clock problem
83680: 05/05/05: Wenjun Fu: Re: Gated clock problem
83638: 05/05/04: Symon: Re: Gated clock problem
83681: 05/05/05: Wenjun Fu: Re: Gated clock problem
83707: 05/05/05: Symon: Re: Gated clock problem
83655: 05/05/04: Vladislav Muravin: Re: Gated clock problem
83663: 05/05/04: Symon: Re: Gated clock problem
83683: 05/05/05: Wenjun Fu: Re: Gated clock problem
83679: 05/05/05: Wenjun Fu: Re: Gated clock problem
83631: 05/05/04: Robert: New Altera Software Dev Board with VGA full color?
83634: 05/05/04: Pete: embedded linux for v2pro PPC?
83636: 05/05/04: Dan Henry: Re: embedded linux for v2pro PPC?
83640: 05/05/04: John McCaskill: Re: embedded linux for v2pro PPC?
83810: 05/05/07: Alex Gibson: Re: embedded linux for v2pro PPC?
83821: 05/05/07: Simon Peacock: Re: embedded linux for v2pro PPC?
83848: 05/05/08: Alex Gibson: Re: embedded linux for v2pro PPC?
83644: 05/05/04: Kevin Brown: Availability of the Xilinx ML481 Development Board
83659: 05/05/04: Peter Alfke: Re: Availability of the Xilinx ML481 Development Board
83664: 05/05/04: Peter Alfke: Re: Availability of the Xilinx ML481 Development Board
83698: 05/05/05: Kevin Brown: Re: Availability of the Xilinx ML481 Development Board
83700: 05/05/05: Peter Alfke: Re: Availability of the Xilinx ML481 Development Board
83645: 05/05/04: dave_baker_100@yahoo.co.uk: Saturating an integer
83646: 05/05/04: Symon: Re: Saturating an integer
83648: 05/05/04: Symon: Re: Saturating an integer
83656: 05/05/04: Ben Twijnstra: Re: Saturating an integer
83672: 05/05/04: Symon: Re: Saturating an integer
83647: 05/05/04: dave_baker_100@yahoo.co.uk: Re: Saturating an integer
83649: 05/05/04: dave_baker_100@yahoo.co.uk: Re: Saturating an integer
83670: 05/05/04: JJ: Re: Saturating an integer
83650: 05/05/04: dave_baker_100@yahoo.co.uk: Newbie VHDL/FPGA question
83654: 05/05/04: John_H: Re: Newbie VHDL/FPGA question
83671: 05/05/05: Jeremy Stringer: Re: Newbie VHDL/FPGA question
83676: 05/05/05: Adam: Re: Newbie VHDL/FPGA question
83684: 05/05/05: dave_baker_100@yahoo.co.uk: Re: Newbie VHDL/FPGA question
83660: 05/05/04: EveEllsworth: Does this group allow JobPostings?
83665: 05/05/04: Symon: Re: Does this group allow JobPostings?
83666: 05/05/04: Peter Alfke: Re: Does this group allow JobPostings?
83688: 05/05/05: fred: Re: Does this group allow JobPostings?
83716: 05/05/05: David: Re: Does this group allow JobPostings?
83661: 05/05/04: Marco: Help
83711: 05/05/05: Rob Gaddi: Re: Help
83668: 05/05/04: JJ: Re: Does this group allow JobPostings?
83675: 05/05/04: Aroul: How to add DCM as customized IP using FSL channel
83678: 05/05/05: Mac: Re: Does this group allow JobPostings?
83686: 05/05/05: Nick: Altera SDRam ip core
83687: 05/05/05: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: how to constrain this
83690: 05/05/05: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: how to constrain this
83697: 05/05/05: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: found out why, still some questions
83692: 05/05/05: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: DCM constraints
83693: 05/05/05: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: DCM constraints
83701: 05/05/05: Brijesh: Re: how to constrain this
83703: 05/05/05: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: how to constrain this
83721: 05/05/06: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: cascaded dcms
83759: 05/05/06: Brijesh: Re: cascaded dcms
83760: 05/05/06: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: cascaded dcms
83689: 05/05/05: <zkwjy@tiscali.it>: Xilinx Prom programming
83732: 05/05/05: Shreyas Kulkarni: Re: Xilinx Prom programming
83791: 05/05/06: Big Boy: re:Xilinx Prom programming
83695: 05/05/05: jason.stubbs: System Ace: How many FPGA's in the JTAG chain before require buffers?
83718: 05/05/05: Hal Murray: Re: System Ace: How many FPGA's in the JTAG chain before require buffers?
83719: 05/05/05: Austin Lesea: Re: System Ace: How many FPGA's in the JTAG chain before require
83737: 05/05/05: Marc Randolph: Re: System Ace: How many FPGA's in the JTAG chain before require buffers?
83696: 05/05/05: 3.14: MicroBlaze latencies
83708: 05/05/05: Roger: VIIPro on-chip LVDS termination
83709: 05/05/05: Ed McGettigan: Re: VIIPro on-chip LVDS termination
83717: 05/05/05: Roger: Re: VIIPro on-chip LVDS termination
83720: 05/05/05: Ed McGettigan: Re: VIIPro on-chip LVDS termination
83712: 05/05/05: Rob Gaddi: Clock Gating
83714: 05/05/05: Mike Treseler: Re: Clock Gating
83715: 05/05/05: Peter Alfke: Re: Clock Gating
83731: 05/05/06: Thomas Rudloff: Re: Clock Gating
83713: 05/05/05: Luc: DVI implementation
83747: 05/05/06: =?ISO-8859-1?Q?Benjamin_Menk=FCc?=: Re: DVI implementation
83882: 05/05/09: Martin Thompson: Re: DVI implementation
83890: 05/05/09: =?ISO-8859-1?Q?Benjamin_Menk=FCc?=: Re: DVI implementation
83936: 05/05/10: Martin Thompson: Re: DVI implementation
83963: 05/05/10: =?ISO-8859-1?Q?Benjamin_Menk=FCc?=: Re: DVI implementation
83998: 05/05/11: Martin Thompson: Re: DVI implementation
83724: 05/05/06: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: including components, i.e. SRL16
83739: 05/05/05: Jim George: Re: including components, i.e. SRL16
83746: 05/05/06: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: including components, i.e. SRL16
83740: 05/05/05: Mark Sasten: Re: including components, i.e. SRL16
83745: 05/05/06: John Adair: Re: including components, i.e. SRL16
83766: 05/05/06: Duane Clark: Re: including components, i.e. SRL16
83834: 05/05/07: John Adair: Re: including components, i.e. SRL16
83728: 05/05/05: nara_chak45: re:How to control peripheral say a small DC motor using ML300
83729: 05/05/05: nara_chak45: EDK "libSecurity.dll"
83787: 05/05/06: <tomchan95124@yahoo.com>: Re: EDK "libSecurity.dll"
83730: 05/05/05: nara_chak45: How to control peripheral say a small DC motor using ML300
83934: 05/05/10: nara_chak45: re:How to control peripheral say a small DC motor using ML300
83736: 05/05/05: <dan.nilsen@gmail.com>: quantization and rate control
83743: 05/05/06: Neo: Spartan-3 boards comparison
83748: 05/05/06: =?ISO-8859-1?Q?Benjamin_Menk=FCc?=: Re: Spartan-3 boards comparison
83749: 05/05/06: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: creating testbench with data from logic analyzer
83750: 05/05/06: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: wrong place
83751: 05/05/06: Mouarf: FPGA choice advice needed
83753: 05/05/06: Teo: Re: FPGA choice advice needed
83755: 05/05/06: Mouarf: Re: FPGA choice advice needed
83758: 05/05/06: Mouarf: Re: FPGA choice advice needed
83756: 05/05/06: Teo: Re: FPGA choice advice needed
83757: 05/05/06: John M: Re: FPGA choice advice needed
83780: 05/05/06: Teo: Re: FPGA choice advice needed
83828: 05/05/07: John Adair: Re: FPGA choice advice needed
83840: 05/05/07: Mouarf: Re: FPGA choice advice needed
83842: 05/05/08: info_: Re: FPGA choice advice needed
83843: 05/05/08: Mouarf: Re: FPGA choice advice needed
83855: 05/05/08: info_: Re: FPGA choice advice needed
83872: 05/05/09: John Adair: Re: FPGA choice advice needed
83752: 05/05/06: Sean Durkin: Parallel Cable IV opened in "Compatibility Mode"
83769: 05/05/06: Thomas Rudloff: Re: Parallel Cable IV opened in "Compatibility Mode"
83771: 05/05/06: Brannon: Re: Parallel Cable IV opened in "Compatibility Mode"
83773: 05/05/06: Symon: Re: Parallel Cable IV opened in "Compatibility Mode"
83811: 05/05/07: Marc: Re: Parallel Cable IV opened in "Compatibility Mode"
83851: 05/05/08: Nitro: Re: Parallel Cable IV opened in "Compatibility Mode"
83861: 05/05/08: Sean Durkin: Re: Parallel Cable IV opened in "Compatibility Mode"
83951: 05/05/10: Sean Durkin: Re: Parallel Cable IV opened in "Compatibility Mode"
83762: 05/05/06: Brijesh: Using capacitor to slow the rise time.
83764: 05/05/06: Austin Lesea: Re: Using capacitor to slow the rise time.
83767: 05/05/06: John_H: Re: Using capacitor to slow the rise time.
83770: 05/05/06: Bob Perlman: Re: Using capacitor to slow the rise time.
83776: 05/05/06: Ray Andraka: Re: Using capacitor to slow the rise time.
83777: 05/05/06: Symon: Re: Using capacitor to slow the rise time.
83781: 05/05/06: Brijesh: Re: Using capacitor to slow the rise time.
83795: 05/05/07: Philip Freidin: Re: Using capacitor to slow the rise time.
83797: 05/05/07: Thomas Rudloff: Re: Using capacitor to slow the rise time.
83830: 05/05/07: Jeff Cunningham: Re: Using capacitor to slow the rise time.
83835: 05/05/07: Bob Perlman: Re: Using capacitor to slow the rise time.
83850: 05/05/08: Jeff Cunningham: Re: Using capacitor to slow the rise time.
83853: 05/05/08: Philip Freidin: Re: Using capacitor to slow the rise time.
84054: 05/05/12: Jeremy Stringer: Re: Using capacitor to slow the rise time.
83993: 05/05/11: Jeremy Stringer: Re: Using capacitor to slow the rise time.
83887: 05/05/09: Brijesh: Re: Using capacitor to slow the rise time.
83820: 05/05/07: Kolja Sulimma: Re: Using capacitor to slow the rise time.
83812: 05/05/07: JoeG: Re: Using capacitor to slow the rise time.
83763: 05/05/06: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: on chip termination for DVI (TMDS) possible?
83765: 05/05/06: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: a note
83772: 05/05/06: Ken: Will this DCM cascade track a frequency offset clock?
83774: 05/05/06: Vladislav Muravin: Re: Will this DCM cascade track a frequency offset clock?
83775: 05/05/06: Symon: Re: Will this DCM cascade track a frequency offset clock?
83933: 05/05/10: Ken: Re: Will this DCM cascade track a frequency offset clock?
83778: 05/05/06: johnp: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83814: 05/05/06: Marc Randolph: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83893: 05/05/09: johnp: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83960: 05/05/10: Peter Alfke: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83964: 05/05/10: Peter Alfke: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83968: 05/05/10: johnp: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83975: 05/05/10: Peter Alfke: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83990: 05/05/10: Marc Randolph: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83779: 05/05/06: Peter Soerensen: Cant link with xil_malloc() function
84213: 05/05/15: Qi Sun: Re: Cant link with xil_malloc() function
83782: 05/05/06: ma: newbie question
83784: 05/05/06: Mike Treseler: Re: newbie question
83823: 05/05/07: ma: Re: newbie question
83833: 05/05/07: Mike Treseler: Re: newbie question
83841: 05/05/07: ma: Re: newbie question
83925: 05/05/09: pnowe: Re: newbie question
83785: 05/05/06: Eric: Re: newbie question
83789: 05/05/06: Praveen: Re: newbie question
83803: 05/05/06: Hal Murray: Re: newbie question
83827: 05/05/07: <andyesquire@hotmail.com>: Re: newbie question
84196: 05/05/14: Ray Andraka: Re: newbie question
84199: 05/05/14: JJ: Re: newbie question
83783: 05/05/06: Austin Lesea: 40% less SEU's! in V4: another good reason to choose Xilinx
83786: 05/05/06: Ben Twijnstra: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83790: 05/05/07: Thomas Rudloff: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83796: 05/05/06: austin: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83794: 05/05/06: austin: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83826: 05/05/07: Ben Twijnstra: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83831: 05/05/07: austin: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83836: 05/05/07: Ben Twijnstra: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83838: 05/05/07: austin: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83788: 05/05/06: Peter Alfke: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83798: 05/05/07: Piotr Wyderski: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83805: 05/05/06: austin: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
84303: 05/05/17: Paul Leventis (at home): Re: 40% less SEU's! in V4: another good reason to choose Xilinx
84333: 05/05/17: Austin Lesea: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83792: 05/05/06: Big Boy: Xilinx ISE 6.3 verilog simulation problem
84032: 05/05/11: Big Boy: re:Xilinx ISE 6.3 verilog simulation problem
84040: 05/05/11: Berty: Re: Xilinx ISE 6.3 verilog simulation problem
84097: 05/05/12: Big Boy: re:Xilinx ISE 6.3 verilog simulation problem
84107: 05/05/12: Gabor: Re: Xilinx ISE 6.3 verilog simulation problem
83793: 05/05/07: Hw: Metastability / MUX question
83799: 05/05/07: Thomas Rudloff: Re: Metastability / MUX question
83808: 05/05/07: Hw: Re: Metastability / MUX question
83865: 05/05/08: Ben Twijnstra: Re: Metastability / MUX question
83804: 05/05/06: Peter Alfke: Re: Metastability / MUX question
83816: 05/05/06: Peter Alfke: Re: Metastability / MUX question
83868: 05/05/08: Peter Alfke: Re: Metastability / MUX question
83800: 05/05/07: Piotr Wyderski: Which chip should I use?
83801: 05/05/07: Thomas Rudloff: Re: Which chip should I use?
83822: 05/05/07: Piotr Wyderski: Re: Which chip should I use?
83824: 05/05/07: Thomas Rudloff: Re: Which chip should I use?
83825: 05/05/07: Piotr Wyderski: Re: Which chip should I use?
83849: 05/05/07: Paul Leventis (at home): Re: Which chip should I use?
83856: 05/05/08: Piotr Wyderski: Re: Which chip should I use?
83941: 05/05/10: Kolja Sulimma: Re: Which chip should I use?
83858: 05/05/08: Rudolf Usselmann: Re: Which chip should I use?
83859: 05/05/08: Piotr Wyderski: Re: Which chip should I use?
83905: 05/05/10: Rudolf Usselmann: Re: Which chip should I use?
83953: 05/05/10: Piotr Wyderski: Re: Which chip should I use?
83954: 05/05/10: Piotr Wyderski: Re: Which chip should I use?
83806: 05/05/06: Eric Smith: Re: Which chip should I use?
83845: 05/05/07: Teo: Re: Which chip should I use?
83871: 05/05/09: Thomas Stanka: Re: Which chip should I use?
83802: 05/05/06: Minimum: IP core supply
83919: 05/05/09: CPU2000: Re: IP core supply
84418: 05/05/18: Eric Smith: Re: IP core supply
83922: 05/05/09: Minimum: Re: IP core supply
83923: 05/05/09: Minimum: Re: IP core supply
83928: 05/05/09: Neo: Re: IP core supply
84020: 05/05/11: Minimum: Re: IP core supply
84416: 05/05/18: Minimum: Re: IP core supply
83807: 05/05/06: jack: how can i join the comp.arch.fpga group
83815: 05/05/06: Joseph: Re: how can i join the comp.arch.fpga group
83817: 05/05/07: Philip Freidin: Re: how can i join the comp.arch.fpga group
83809: 05/05/06: jack: how can i add my math library libm.a in my project
83818: 05/05/07: Leon Heller: Re: how can i add my math library libm.a in my project
83846: 05/05/07: Athena: Re: how can i add my math library libm.a in my project
83847: 05/05/07: Athena: Re: how can i add my math library libm.a in my project
83829: 05/05/07: Preben Holm: Clock delay vs. clock skew
83832: 05/05/07: JoeG: Re: Clock delay vs. clock skew
83844: 05/05/07: Peter Alfke: Re: Clock delay vs. clock skew
83910: 05/05/09: Preben Holm: Re: Clock delay vs. clock skew
83911: 05/05/09: Peter Alfke: Re: Clock delay vs. clock skew
83956: 05/05/10: Janes: Re: Clock delay vs. clock skew
83852: 05/05/08: Athena: float computing: how to add libm.a
84129: 05/05/12: glen herrmannsfeldt: Re: float computing: how to add libm.a
83854: 05/05/08: Gunter Knittel: Fake Buffers in ECS
83977: 05/05/10: Eric Crabill: Re: Fake Buffers in ECS
84184: 05/05/13: Gunter Knittel: Re: Fake Buffers in ECS
83857: 05/05/08: Jason Wu: Parallel Cable IV operating in "Compatibility Mode" under linux kernel 2.6.x
83863: 05/05/08: Ben Twijnstra: Re: Parallel Cable IV operating in "Compatibility Mode" under linux kernel 2.6.x
83860: 05/05/08: <jaxato@gmail.com>: Re: Which chip should I use?
83862: 05/05/08: looking for Xilinx ppc consultant: Looking for Xilinx Power-PC consultant
83864: 05/05/08: CPU2000: Re: Looking for Xilinx Power-PC consultant
83967: 05/05/10: looking for Xilinx ppc consultant: Re: Looking for Xilinx Power-PC consultant
83866: 05/05/08: kittyawake@gmail.com: EDK: user logic on opb bus in microblaze system
83867: 05/05/08: Paul Hartke: Re: EDK: user logic on opb bus in microblaze system
83869: 05/05/08: Hendra: Flagging XST to suppress the warning
83908: 05/05/09: Gabor: Re: Flagging XST to suppress the warning
83873: 05/05/09: Laurent Gauch: Max7000ae and GCLRn
83892: 05/05/09: Mike Treseler: Re: Max7000ae and GCLRn
83874: 05/05/09: lina: how to add library
83875: 05/05/09: <praveen.kantharajapura@gmail.com>: true dual port memory v/s simple dual port memory
83883: 05/05/09: Mike Lewis: Re: true dual port memory v/s simple dual port memory
83932: 05/05/10: mk: Re: true dual port memory v/s simple dual port memory
83955: 05/05/10: David: Re: true dual port memory v/s simple dual port memory
84302: 05/05/17: Paul Leventis (at home): Re: true dual port memory v/s simple dual port memory
84197: 05/05/14: Ray Andraka: Re: true dual port memory v/s simple dual port memory
83891: 05/05/09: Peter Alfke: Re: true dual port memory v/s simple dual port memory
83927: 05/05/09: <praveen.kantharajapura@gmail.com>: Re: true dual port memory v/s simple dual port memory
83930: 05/05/09: Peter Alfke: Re: true dual port memory v/s simple dual port memory
83949: 05/05/10: Jochen: Re: true dual port memory v/s simple dual port memory
83957: 05/05/10: Peter Alfke: Re: true dual port memory v/s simple dual port memory
83876: 05/05/09: CODE_IS_BAD: 8051 IP core
83881: 05/05/09: Markus Meng: Re: 8051 IP core
83897: 05/05/09: Ziggy: Re: 8051 IP core
83917: 05/05/09: CPU2000: Re: 8051 IP core
84207: 05/05/14: Ziggy: Re: 8051 IP core
84057: 05/05/12: info_: Re: 8051 IP core
84072: 05/05/11: CODE_IS_BAD: Re: 8051 IP core
84103: 05/05/12: AVG: Re: 8051 IP core
84081: 05/05/12: AVG: Re: 8051 IP core
84091: 05/05/12: Fred: Re: 8051 IP core
84096: 05/05/12: Ed McGettigan: Re: 8051 IP core
84256: 05/05/16: Fred: Re: 8051 IP core
84287: 05/05/16: CODE_IS_BAD: Re: 8051 IP core
84315: 05/05/17: AVG: Re: 8051 IP core
84318: 05/05/17: CODE_IS_BAD: Re: 8051 IP core
84320: 05/05/17: AVG: Re: 8051 IP core
84323: 05/05/17: CODE_IS_BAD: Re: 8051 IP core
83877: 05/05/09: Roger: Xilinx VIIPro mixed configuration voltages
83878: 05/05/09: John Adair: Re: Xilinx VIIPro mixed configuration voltages
84045: 05/05/11: Philip Freidin: Re: Xilinx VIIPro mixed configuration voltages
83879: 05/05/09: Laurent Gauch: Quartus II - multicyle option
83880: 05/05/09: Laurent Gauch: Re: Quartus II - multicyle option
83884: 05/05/09: ARRON: Uart16550 can't receive data over 16byte a time
83886: 05/05/09: John_H: Re: Uart16550 can't receive data over 16byte a time
83888: 05/05/09: Aurelian Lazarut: Re: Uart16550 can't receive data over 16byte a time
83937: 05/05/10: Simon Peacock: Re: Uart16550 can't receive data over 16byte a time
84022: 05/05/11: ARRON: Re: Uart16550 can't receive data over 16byte a time
84046: 05/05/11: John_H: Re: Uart16550 can't receive data over 16byte a time
84063: 05/05/11: Big Boy: re:Uart16550 can't receive data over 16byte a time
84141: 05/05/13: ARRON: Re: Uart16550 can't receive data over 16byte a time
84161: 05/05/13: Big Boy: re:Uart16550 can't receive data over 16byte a time
84201: 05/05/14: Simon Peacock: Re: re:Uart16550 can't receive data over 16byte a time
84212: 05/05/14: ARRON: Re: Uart16550 can't receive data over 16byte a time
83885: 05/05/09: GianniG: TRACE and Modelsim Timing Help
83902: 05/05/09: John M: Re: TRACE and Modelsim Timing Help
83906: 05/05/09: Symon: Re: TRACE and Modelsim Timing Help
83947: 05/05/10: GianniG: Re: TRACE and Modelsim Timing Help
83889: 05/05/09: Fred: Altera: Maxplus rules!
83907: 05/05/10: Jim Granville: Re: Altera: Maxplus rules!
83942: 05/05/10: Fred: Re: Altera: Maxplus rules!
83909: 05/05/09: Ben Twijnstra: Re: Altera: Maxplus rules!
83945: 05/05/10: Fred: Re: Altera: Maxplus rules!
83914: 05/05/09: Steve: Re: Altera: Maxplus rules!
83944: 05/05/10: Fred: Re: Altera: Maxplus rules!
83915: 05/05/09: David: Re: Altera: Maxplus rules!
83943: 05/05/10: Fred: Re: Altera: Maxplus rules!
83916: 05/05/09: <rkruger@altera.com>: Re: Altera: Maxplus rules!
83894: 05/05/09: geoffrey wall: dcm's for increasing clock speed
83895: 05/05/09: John_H: Re: dcm's for increasing clock speed
83896: 05/05/09: Peter Alfke: Re: dcm's for increasing clock speed
83900: 05/05/09: John M: Re: dcm's for increasing clock speed
83898: 05/05/09: <alanmyler@yahoo.com>: Altera Quartus Timing Models
83938: 05/05/10: Simon Peacock: Re: Altera Quartus Timing Models
83992: 05/05/11: Simon Peacock: Re: Altera Quartus Timing Models
83939: 05/05/10: <alanmyler@yahoo.com>: Re: Altera Quartus Timing Models
83989: 05/05/10: GMM50: Re: Altera Quartus Timing Models
83901: 05/05/09: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: DDR speed of the XUPV2P Board from Digilent
83912: 05/05/09: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: DDR speed of the XUPV2P Board from Digilent
83918: 05/05/09: CPU2000: Re: DDR speed of the XUPV2P Board from Digilent
83921: 05/05/10: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: DDR speed of the XUPV2P Board from Digilent
83926: 05/05/10: Alex Gibson: Re: DDR speed of the XUPV2P Board from Digilent
83931: 05/05/09: Pete Fraser: Re: DDR speed of the XUPV2P Board from Digilent
83962: 05/05/10: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: DDR speed of the XUPV2P Board from Digilent
83966: 05/05/10: =?ISO-8859-15?Q?Benjamin_Menk=FCc?=: Re: DDR speed of the XUPV2P Board from Digilent
83994: 05/05/11: Simon Peacock: Re: DDR speed of the XUPV2P Board from Digilent
84071: 05/05/12: John Williams: Re: DDR speed of the XUPV2P Board from Digilent
84087: 05/05/12: =?ISO-8859-1?Q?Benjamin_Menk=FCc?=: Re: DDR speed of the XUPV2P Board from Digilent
84239: 05/05/16: John Williams: Re: DDR speed of the XUPV2P Board from Digilent
84261: 05/05/16: =?ISO-8859-1?Q?Benjamin_Menk=FCc?=: Re: DDR speed of the XUPV2P Board from Digilent
156599: 14/05/08: GaborSzakacs: Re: DDR speed of the XUPV2P Board from Digilent
156597: 14/05/07: <impanaeng@gmail.com>: Re: DDR speed of the XUPV2P Board from Digilent
156601: 14/05/08: impana: Re: DDR speed of the XUPV2P Board from Digilent
83920: 05/05/09: jeycrisis: Configuring an XC3S400 Spartan 3 with JTAG
83946: 05/05/10: Aurelian Lazarut: Re: Configuring an XC3S400 Spartan 3 with JTAG
83965: 05/05/10: Aurelian Lazarut: Re: Configuring an XC3S400 Spartan 3 with JTAG
84014: 05/05/11: Aurelian Lazarut: Re: Configuring an XC3S400 Spartan 3 with JTAG
84015: 05/05/11: Laurent Gauch: Re: Configuring an XC3S400 Spartan 3 with JTAG
83961: 05/05/10: jeycrisis: Re: Configuring an XC3S400 Spartan 3 with JTAG
83974: 05/05/10: jeycrisis: Re: Configuring an XC3S400 Spartan 3 with JTAG
83929: 05/05/10: Invalid IP: Clock speed problem. How can I proceed?
83935: 05/05/10: <ALuPin@web.de>: CAM implementation on Lattice EC
83940: 05/05/10: <kedarpapte@gmail.com>: PCI PCIX LoGi Core Problem
83948: 05/05/10: <stud_lang_jap@yahoo.com>: dividing the clcok by 2.5
83950: 05/05/10: Philip Freidin: Re: dividing the clcok by 2.5
83952: 05/05/10: <news@rtrussell.co.uk>: Re: dividing the clcok by 2.5
83959: 05/05/10: Symon: Re: dividing the clcok by 2.5
83980: 05/05/10: Peter Alfke: Re: dividing the clcok by 2.5
83969: 05/05/10: <fastgreen2000@yahoo.com>: Virtex4 running at 360Mhz DDR
83970: 05/05/10: Symon: Re: Virtex4 running at 360Mhz DDR
83972: 05/05/10: Symon: Re: Virtex4 running at 360Mhz DDR
83983: 05/05/10: Symon: Re: Virtex4 running at 360Mhz DDR
84030: 05/05/11: Ajay Roopchansingh: Re: Virtex4 running at 360Mhz DDR
84042: 05/05/11: Symon: Re: Virtex4 running at 360Mhz DDR
83971: 05/05/10: <fastgreen2000@yahoo.com>: Re: Virtex4 running at 360Mhz DDR
83978: 05/05/10: John_H: Re: Virtex4 running at 360Mhz DDR
83981: 05/05/10: Symon: Re: Virtex4 running at 360Mhz DDR
83982: 05/05/11: John_H: Re: Virtex4 running at 360Mhz DDR
83984: 05/05/10: Symon: Re: Virtex4 running at 360Mhz DDR
83988: 05/05/10: austin: Re: Virtex4 running at 360Mhz DDR
83995: 05/05/10: Symon: Re: Virtex4 running at 360Mhz DDR
84029: 05/05/11: Austin Lesea: Re: Virtex4 running at 360Mhz DDR
84039: 05/05/11: Symon: Re: Virtex4 running at 360Mhz DDR
84044: 05/05/11: Austin Lesea: Re: Virtex4 running at 360Mhz DDR
84051: 05/05/11: Symon: Re: Virtex4 running at 360Mhz DDR
84053: 05/05/11: Austin Lesea: Re: Virtex4 running at 360Mhz DDR
84090: 05/05/12: Austin Lesea: Re: Virtex4 running at 360Mhz DDR
84105: 05/05/12: Symon: Re: Virtex4 running at 360Mhz DDR
84093: 05/05/12: Austin Lesea: Re: Virtex4 running at 360Mhz DDR
84116: 05/05/13: Jim Granville: Re: Virtex4 running at 360Mhz DDR
84118: 05/05/12: Austin Lesea: Re: Virtex4 running at 360Mhz DDR
84330: 05/05/17: Austin Lesea: Re: Virtex4 running at 360Mhz DDR
84041: 05/05/11: Philip Freidin: Re: Virtex4 running at 360Mhz DDR
84047: 05/05/11: Austin Lesea: Re: Virtex4 running at 360Mhz DDR
84286: 05/05/16: Paul Leventis (at home): Re: Virtex4 running at 360Mhz DDR
84417: 05/05/18: Symon: Re: Virtex4 running at 360Mhz DDR
84476: 05/05/19: Symon: Re: Virtex4 running at 360Mhz DDR
84854: 05/05/30: Paul Leventis (at home): Re: Virtex4 running at 360Mhz DDR
84899: 05/05/31: Symon: Re: Virtex4 running at 360Mhz DDR
84304: 05/05/17: Paul Leventis (at home): Re: Virtex4 running at 360Mhz DDR
83979: 05/05/10: Peter Alfke: Re: Virtex4 running at 360Mhz DDR
83991: 05/05/10: Brian Davis: Re: Virtex4 running at 360Mhz DDR
84064: 05/05/11: Brian Davis: Re: Virtex4 running at 360Mhz DDR
84068: 05/05/11: Brian Davis: Re: Virtex4 running at 360Mhz DDR
84102: 05/05/12: <fastgreen2000@yahoo.com>: Re: Virtex4 running at 360Mhz DDR
84235: 05/05/15: Brian Davis: Re: Virtex4 running at 360Mhz DDR
84319: 05/05/17: <fastgreen2000@yahoo.com>: Re: Virtex4 running at 360Mhz DDR
84422: 05/05/18: Paul Leventis: Re: Virtex4 running at 360Mhz DDR
84452: 05/05/19: John M: Re: Virtex4 running at 360Mhz DDR
83973: 05/05/10: Teo: Add on bus
83985: 05/05/10: Quiet Desperation: 2.5/3.3 LVPECL in Virtex
83987: 05/05/10: Symon: Re: 2.5/3.3 LVPECL in Virtex
84000: 05/05/11: John Adair: Re: 2.5/3.3 LVPECL in Virtex
83996: 05/05/11: John Savard: Xilinx versus Elixent; other radically different concepts?
83997: 05/05/11: Hal Murray: Re: Xilinx versus Elixent; other radically different concepts?
84013: 05/05/11: Gabor: Re: Xilinx versus Elixent; other radically different concepts?
84074: 05/05/12: John Savard: Re: Xilinx versus Elixent; other radically different concepts?
84049: 05/05/11: Gavin Scott: Re: Xilinx versus Elixent; other radically different concepts?
84076: 05/05/12: JJ: Re: Xilinx versus Elixent; other radically different concepts?
83999: 05/05/11: rupert: ACTEL design problems
84001: 05/05/11: Neo: An FPGA eval board at $49!!
84004: 05/05/11: Antti Lukats: Re: An FPGA eval board at $49!!
84008: 05/05/11: Mouarf: Re: An FPGA eval board at $49!!
84010: 05/05/11: Mouarf: Re: An FPGA eval board at $49!!
84009: 05/05/11: Neo: Re: An FPGA eval board at $49!!
84012: 05/05/11: =?ISO-8859-1?Q?Benjamin_Menk=FCc?=: Re: An FPGA eval board at $49!!
84114: 05/05/12: Tommy Thorn: Re: An FPGA eval board at $49!!
84023: 05/05/11: Ziggy: Re: An FPGA eval board at $49!!
84397: 05/05/18: Gabor: Re: An FPGA eval board at $49!!
84002: 05/05/11: <asoc35@dsl.pipex.com>: Any Virtex 4 development/prototyping boards out there???
84003: 05/05/11: Antti Lukats: Re: Any Virtex 4 development/prototyping boards out there???
84005: 05/05/11: John Adair: Re: Any Virtex 4 development/prototyping boards out there???
84036: 05/05/11: uxello: Re: Any Virtex 4 development/prototyping boards out there???
84077: 05/05/12: Peter Ryser: Re: Any Virtex 4 development/prototyping boards out there???
84006: 05/05/11: Patrick: strange Microblaze error
84027: 05/05/11: Paul Hartke: Re: strange Microblaze error
84007: 05/05/11: <nkishorebabu123@rediffmail.com>: Test the code on FPGA Board...
84017: 05/05/11: Ed McGettigan: Re: Test the code on FPGA Board...
84019: 05/05/11: Mike Lewis: Re: Test the code on FPGA Board...
84011: 05/05/11: <kevin@firebolt.com>: FPGA/Embedded Design Training
84058: 05/05/11: Eric: Re: FPGA/Embedded Design Training
84061: 05/05/11: Kryten: Re: FPGA/Embedded Design Training
84016: 05/05/11: Joey: Frequency limitations?
84024: 05/05/11: Paul Hartke: Re: Frequency limitations?
84018: 05/05/11: Lina: how to use libm.a and libc.a
84025: 05/05/11: Paul Hartke: Re: how to use libm.a and libc.a
84033: 05/05/11: Herb T: Analog to Digital Converted (ADC) & Spartan 3
84034: 05/05/11: Peter Alfke: Re: Analog to Digital Converted (ADC) & Spartan 3
84035: 05/05/11: Herb T: Re: Analog to Digital Converted (ADC) & Spartan 3
84037: 05/05/11: Andy Peters: Re: Analog to Digital Converted (ADC) & Spartan 3
84038: 05/05/11: Herb T: Re: Analog to Digital Converted (ADC) & Spartan 3
84048: 05/05/11: <rarteaga@gmail.com>: Slice Virtex II = Equivalent gates ??
84052: 05/05/11: Peter Alfke: Re: Slice Virtex II = Equivalent gates ??
84056: 05/05/12: info_: Re: Slice Virtex II = Equivalent gates ??
84062: 05/05/11: Marc Randolph: Re: Slice Virtex II = Equivalent gates ??
84078: 05/05/12: Jon Beniston: Re: Slice Virtex II = Equivalent gates ??
84106: 05/05/12: Philip Freidin: Re: Slice Virtex II = Equivalent gates ??
84108: 05/05/12: Peter Alfke: Re: Slice Virtex II = Equivalent gates ??
84060: 05/05/11: jgknowla1: Minimum circuit to get Spartan-3 running
84080: 05/05/12: Gabor: Re: Minimum circuit to get Spartan-3 running
84126: 05/05/13: Tony Burch: Re: Minimum circuit to get Spartan-3 running
84084: 05/05/12: jgknowla1: Re: Minimum circuit to get Spartan-3 running
84098: 05/05/12: Big Boy: re:Minimum circuit to get Spartan-3 running
84134: 05/05/12: Ziggy: Re: Minimum circuit to get Spartan-3 running
84065: 05/05/11: Ken: Looking for Rapid prototyping system, ?Quickturn ASIC-Emulator?
84082: 05/05/12: <alanmyler@yahoo.com>: Re: Looking for Rapid prototyping system, ?Quickturn ASIC-Emulator?
84086: 05/05/12: johnp: Re: Looking for Rapid prototyping system, ?Quickturn ASIC-Emulator?
84066: 05/05/11: Weddick: Counting Clocks
84099: 05/05/12: Benjamin Todd: Re: Counting Clocks
84100: 05/05/12: Benjamin Todd: Re: Counting Clocks
84067: 05/05/11: Lina: How to use XMD debugger
84070: 05/05/11: Paul Hartke: Re: How to use XMD debugger
84069: 05/05/11: John W. Lockwood: Tutorial on debug of packet processing in FPGA hardware using Identify
84110: 05/05/12: Mike Treseler: Re: Tutorial on debug of packet processing in FPGA hardware using
84073: 05/05/12: Antti Lukats: EDK 7.1 XMD and platform USB cable
97513: 06/02/23: pejdstran: Re: EDK 7.1 XMD and platform USB cable
84079: 05/05/12: <ALuPin@web.de>: Input Maximum Delay timing assignment in Altera
84136: 05/05/13: Subroto Datta: Re: Input Maximum Delay timing assignment in Altera
84191: 05/05/14: Subroto Datta: Re: Input Maximum Delay timing assignment in Altera
84234: 05/05/16: Subroto Datta: Re: Input Maximum Delay timing assignment in Altera (Delay settings in Quartus)
84139: 05/05/12: <ALuPin@web.de>: Re: Input Maximum Delay timing assignment in Altera
84085: 05/05/12: <ALuPin@web.de>: Auto-select clock for virtual pins
84289: 05/05/17: Vaughn Betz: Re: Auto-select clock for virtual pins
84365: 05/05/17: Vaughn Betz: Re: Auto-select clock for virtual pins
84507: 05/05/19: Vaughn Betz: Re: Auto-select clock for virtual pins
84560: 05/05/21: Vaughn Betz: Re: Auto-select clock for virtual pins
84295: 05/05/17: <ALuPin@web.de>: Re: Auto-select clock for virtual pins
84309: 05/05/17: <ALuPin@web.de>: Re: Auto-select clock for virtual pins
84377: 05/05/18: <ALuPin@web.de>: Re: Auto-select clock for virtual pins
84519: 05/05/20: <ALuPin@web.de>: Re: Auto-select clock for virtual pins
84088: 05/05/12: Giox: High radix multiplier
84089: 05/05/12: abeaujean@gillam-fei.be: Re: High radix multiplier
84128: 05/05/12: glen herrmannsfeldt: Re: High radix multiplier
84467: 05/05/19: Giox: Re: High radix multiplier
84092: 05/05/12: fpgabuilder: initializing fifo pointers to simulate overflow
84112: 05/05/12: Mike Treseler: Re: initializing fifo pointers to simulate overflow
84192: 05/05/13: fpgabuilder: Re: initializing fifo pointers to simulate overflow
84194: 05/05/13: Peter Alfke: Re: initializing fifo pointers to simulate overflow
84264: 05/05/16: Berty: Re: initializing fifo pointers to simulate overflow
85592: 05/06/11: fpgabuilder: Re: initializing fifo pointers to simulate overflow
84094: 05/05/12: W A: How to turn off auto bufg insertion in ISE 7.1 ???
84172: 05/05/13: Gabor: Re: How to turn off auto bufg insertion in ISE 7.1 ???
84195: 05/05/13: W A: Re: How to turn off auto bufg insertion in ISE 7.1 ???
84101: 05/05/12: Peter Alfke: "Mine is bigger than yours..."
84104: 05/05/12: Mike Treseler: Re: "Mine is bigger than yours..."
84119: 05/05/12: Hal Murray: Re: "Mine is bigger than yours..."
84193: 05/05/13: Ray Andraka: Re: "Mine is bigger than yours..."
84109: 05/05/13: Rudolf Usselmann: Re: "Mine is bigger than yours..."
84138: 05/05/13: Rudolf Usselmann: Re: "Mine is bigger than yours..."
84144: 05/05/13: David: Re: "Mine is bigger than yours..."
84168: 05/05/13: Antti Lukats: Re: "Mine is bigger than yours..."
84307: 05/05/17: Alex Freed: Re: "Mine is bigger than yours..."
84311: 05/05/17: Paul Leventis (at home): Re: "Mine is bigger than yours..."
84352: 05/05/17: Antti Lukats: Re: "Mine is bigger than yours..."
84367: 05/05/17: Vaughn Betz: Re: "Mine is bigger than yours..."
84210: 05/05/14: Piotr Wyderski: Re: "Mine is bigger than yours..."
84111: 05/05/12: Dave Greenfield: Re: "Mine is bigger than yours..."
84120: 05/05/12: Ben Twijnstra: Re: "Mine is bigger than yours..."
84175: 05/05/13: Luc: Re: "Mine is bigger than yours..."
84121: 05/05/12: Peter Sommerfeld: Re: "Mine is bigger than yours..."
84122: 05/05/12: <kempaj@yahoo.com>: Re: "Mine is bigger than yours..."
84125: 05/05/12: Peter Sommerfeld: Re: "Mine is bigger than yours..."
84165: 05/05/13: <kempaj@yahoo.com>: Re: "Mine is bigger than yours..."
84291: 05/05/16: <ecpark@gmail.com>: Re: "Mine is bigger than yours..."
84300: 05/05/17: Paul Leventis (at home): Re: "Mine is bigger than yours..."
84336: 05/05/18: Alex Gibson: Re: "Mine is bigger than yours..."
84423: 05/05/19: Alex Gibson: Re: "Mine is bigger than yours..."
84366: 05/05/18: jtw: Re: "Mine is bigger than yours..."
84349: 05/05/17: Paul Leventis: Re: "Mine is bigger than yours..."
84350: 05/05/17: Paul Leventis: Re: "Mine is bigger than yours..."
84113: 05/05/12: Rob Gaddi: To Xilinx: Problem with Digilent Spartan III Starter Kit Documentation
84166: 05/05/13: Rob Gaddi: Re: To Xilinx: Problem with Digilent Spartan III Starter Kit Documentation
84167: 05/05/13: Steven K. Knapp: Re: To Xilinx: Problem with Digilent Spartan III Starter Kit Documentation
84115: 05/05/12: Antti Lukats: EDK 7.1 with xilinx ML401 ref design
84284: 05/05/16: Peter Sørensen: Re: EDK 7.1 with xilinx ML401 ref design
84117: 05/05/12: Joseph H Allen: V4 vs. Stratix-II...
84123: 05/05/12: Ben Twijnstra: Re: V4 vs. Stratix-II...
84124: 05/05/12: Peter Sommerfeld: Re: V4 vs. Stratix-II...
84187: 05/05/13: Joseph H Allen: Re: V4 vs. Stratix-II...
84200: 05/05/14: Simon Peacock: Re: V4 vs. Stratix-II...
84131: 05/05/12: Austin Lesea: Re: V4 vs. Stratix-II...
84133: 05/05/12: Tommy Thorn: Re: V4 vs. Stratix-II...
84135: 05/05/12: austin: Re: V4 vs. Stratix-II...
84137: 05/05/13: Jim Granville: Re: V4 vs. Stratix-II...
84155: 05/05/13: Austin Lesea: Re: V4 vs. Stratix-II...fabric only thread...LUT details...
84160: 05/05/13: Rudolf Usselmann: Re: V4 vs. Stratix-II...fabric only thread...LUT details...
84170: 05/05/13: Antti Lukats: Re: V4 vs. Stratix-II...fabric only thread...LUT details...
84174: 05/05/13: Austin Lesea: Re: V4 vs. Stratix-II...fabric only thread...LUT details...
84308: 05/05/17: Paul Leventis (at home): Re: V4 vs. Stratix-II...
84164: 05/05/13: Nicholas Weaver: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
84176: 05/05/13: c d saunter: Re: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
84218: 05/05/15: Jim Granville: Re: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
84310: 05/05/17: Paul Leventis (at home): Re: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
84331: 05/05/17: Mike Treseler: Re: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
84306: 05/05/17: Paul Leventis (at home): Re: V4 vs. Stratix-II...
84335: 05/05/17: Austin Lesea: Re: V4 vs. Stratix-II...
84347: 05/05/17: Austin Lesea: Re: V4 vs. Stratix-II...
84353: 05/05/18: Jim Granville: Re: V4 vs. Stratix-II...
84355: 05/05/17: Austin Lesea: Re: V4 vs. Stratix-II...
84127: 05/05/12: Michael Dreschmann: Update Picoblaze Code in Bitstream
84158: 05/05/13: Gabor: Re: Update Picoblaze Code in Bitstream
84171: 05/05/13: Michael Dreschmann: Re: Update Picoblaze Code in Bitstream
84159: 05/05/13: Gabor: Re: Update Picoblaze Code in Bitstream
84190: 05/05/13: Shalin Sheth: Re: Update Picoblaze Code in Bitstream
84231: 05/05/16: John Williams: Re: Update Picoblaze Code in Bitstream
84233: 05/05/16: Jim Granville: Re: Update Picoblaze Code in Bitstream
84236: 05/05/16: John Williams: Re: Update Picoblaze Code in Bitstream
84140: 05/05/12: Geogle: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84148: 05/05/13: Uwe Bonnes: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84206: 05/05/14: Uwe Bonnes: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84321: 05/05/17: Jason Tang: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84568: 05/05/21: Uwe Bonnes: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84607: 05/05/23: Uwe Bonnes: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84198: 05/05/13: Geogle: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84243: 05/05/16: Geogle: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84561: 05/05/20: Geogle: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84604: 05/05/22: Geogle: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84143: 05/05/13: ARRON: how can i save my received data into the SDRAM?
84147: 05/05/13: Simon Peacock: Re: how can i save my received data into the SDRAM?
84150: 05/05/13: ARRON: Re: how can i save my received data into the SDRAM?
84156: 05/05/13: Mike Lewis: Re: how can i save my received data into the SDRAM?
84214: 05/05/14: ARRON: Re: how can i save my received data into the SDRAM?
84145: 05/05/13: pasacco: Q)BRAM VHDL simulation in modelsim
84146: 05/05/13: AVG: Re: Q)BRAM VHDL simulation in modelsim
84151: 05/05/13: pasacco: Re: Q)BRAM VHDL simulation in modelsim
84149: 05/05/13: Frank van Eijkelenburg: PowerPC and application in external RAM
84177: 05/05/13: Peter Ryser: Re: PowerPC and application in external RAM
84178: 05/05/13: Peter Ryser: Re: PowerPC and application in external RAM
84305: 05/05/17: Frank van Eijkelenburg: Re: PowerPC and application in external RAM
84152: 05/05/13: John M: Re: V4 vs. Stratix-II...
84153: 05/05/13: <ALuPin@web.de>: Tristate-Master-Slave testbench description
84180: 05/05/13: sps: Re: Tristate-Master-Slave testbench description
84185: 05/05/13: Duane Clark: Re: Tristate-Master-Slave testbench description
84299: 05/05/17: <ALuPin@web.de>: Re: Tristate-Master-Slave testbench description
84312: 05/05/17: Neo: Re: Tristate-Master-Slave testbench description
84373: 05/05/18: <ALuPin@web.de>: Re: Tristate-Master-Slave testbench description
84154: 05/05/13: Marco: Handling Interrupt
84608: 05/05/23: digi: re:Handling Interrupt
84157: 05/05/13: Philipp: Whats going on here?
84162: 05/05/13: Antti Lukats: Re: Whats going on here?
84182: 05/05/13: Antti Lukats: Re: Whats going on here?
84189: 05/05/13: Falk Brunner: Re: Whats going on here?
84181: 05/05/13: joe4702: Re: Whats going on here?
84163: 05/05/13: Peter Alfke: Re: V4 vs. Stratix-II...fabric only thread...LUT details...
84169: 05/05/13: <ash.ok7@gmail.com>: Re: how can i save my received data into the SDRAM?
84179: 05/05/13: Antti Lukats: microblaze and 64 bit memory over PLB bus
84232: 05/05/16: John Williams: Re: microblaze and 64 bit memory over PLB bus
84292: 05/05/17: Antti Lukats: Re: microblaze and 64 bit memory over PLB bus
86876: 05/07/07: krishna1234: Re: microblaze and 64 bit memory over PLB bus
84183: 05/05/13: Lukasz Salwinski: floorplanning
84202: 05/05/14: Simon Peacock: Re: floorplanning
84209: 05/05/14: Ray Andraka: Re: floorplanning
84216: 05/05/15: Simon Peacock: Re: floorplanning
84211: 05/05/14: Phil Hays: Re: floorplanning
84222: 05/05/15: Simon Peacock: Re: floorplanning
84227: 05/05/15: Lukasz Salwinski: Re: floorplanning
84228: 05/05/15: Phil Hays: Re: floorplanning
84205: 05/05/14: JJ: Re: floorplanning
84215: 05/05/15: Simon Peacock: Re: floorplanning
84223: 05/05/15: Simon Peacock: Re: floorplanning
84229: 05/05/15: Paul Boven: Re: floorplanning
85475: 05/06/10: Jeremy Stringer: Re: floorplanning
84221: 05/05/15: JJ: Re: floorplanning
84224: 05/05/15: JJ: Re: floorplanning
84245: 05/05/16: Neo: Re: floorplanning
84265: 05/05/16: Berty: Re: floorplanning
84410: 05/05/18: jtw: Re: floorplanning
84269: 05/05/16: Gabor: Re: floorplanning
84475: 05/05/19: Philip Freidin: Re: floorplanning
85549: 05/06/10: Marc Randolph: Re: floorplanning
84186: 05/05/13: Gunter Knittel: Virtex-II Switch Matrix Performance
84203: 05/05/14: John Adair: Re: Virtex-II Switch Matrix Performance
84414: 05/05/18: Gunter Knittel: Re: Virtex-II Switch Matrix Performance
84188: 05/05/13: Robert Au: Quartus II Fitter Problem
84208: 05/05/14: info_: Re: Quartus II Fitter Problem
84288: 05/05/17: Vaughn Betz: Re: Quartus II Fitter Problem
84290: 05/05/17: Vaughn Betz: Re: Quartus II Fitter Problem
84204: 05/05/14: JJ: Re: floorplanning
84217: 05/05/15: Ronald H. Nicholson Jr.: FPGA design under Mac OS X ?
84219: 05/05/15: JJ: Re: FPGA design under Mac OS X ?
84225: 05/05/15: B. Joshua Rosen: Re: FPGA design under Mac OS X ?
84257: 05/05/16: Alex Gibson: Re: FPGA design under Mac OS X ?
84297: 05/05/17: Phil Tomson: Re: FPGA design under Mac OS X ?
84317: 05/05/17: Alex Gibson: Re: FPGA design under Mac OS X ?
84267: 05/05/16: Michel Billaud: Re: FPGA design under Mac OS X ?
84279: 05/05/16: Jan Panteltje: Re: FPGA design under Mac OS X ?
84296: 05/05/17: Phil Tomson: Re: FPGA design under Mac OS X ?
84316: 05/05/17: B. Joshua Rosen: Re: FPGA design under Mac OS X ?
84361: 05/05/17: Simon: Re: FPGA design under Mac OS X ?
84385: 05/05/18: B. Joshua Rosen: Re: FPGA design under Mac OS X ?
84508: 05/05/19: Simon: Re: FPGA design under Mac OS X ?
84557: 05/05/21: Tommy Thorn: Re: FPGA design under Mac OS X ?
84262: 05/05/16: Andy Peters: Re: FPGA design under Mac OS X ?
84293: 05/05/17: Phil Tomson: Re: FPGA design under Mac OS X ?
84351: 05/05/17: Andy Peters: Re: FPGA design under Mac OS X ?
84389: 05/05/18: JJ: Re: FPGA design under Mac OS X ?
84399: 05/05/18: Andy Peters: Re: FPGA design under Mac OS X ?
84220: 05/05/15: JJ: Re: floorplanning
84226: 05/05/15: Piotr Wyderski: Serial communication
84230: 05/05/15: Candida Ferreira: Universal logic modules vs NAND-like modules
84246: 05/05/16: JJ: Re: Universal logic modules vs NAND-like modules
84247: 05/05/16: Candida Ferreira: Re: Universal logic modules vs NAND-like modules
84259: 05/05/16: Mike Treseler: Re: Universal logic modules vs NAND-like modules
84328: 05/05/17: Mike Treseler: Re: Universal logic modules vs NAND-like modules
84552: 05/05/20: Michel Billaud: Re: Universal logic modules vs NAND-like modules
84554: 05/05/20: Michel Billaud: Re: Universal logic modules vs NAND-like modules
84260: 05/05/16: Candida Ferreira: Re: Universal logic modules vs NAND-like modules
84273: 05/05/16: mk: Re: Universal logic modules vs NAND-like modules
84276: 05/05/17: Michel Billaud: Re: Universal logic modules vs NAND-like modules
84313: 05/05/17: Candida Ferreira: Re: Universal logic modules vs NAND-like modules
84555: 05/05/20: Candida Ferreira: Re: Universal logic modules vs NAND-like modules
84258: 05/05/16: rickman: Re: Universal logic modules vs NAND-like modules
84325: 05/05/17: Gabor: Re: Universal logic modules vs NAND-like modules
84540: 05/05/20: rickman: Re: Universal logic modules vs NAND-like modules
84542: 05/05/20: rickman: Re: Universal logic modules vs NAND-like modules
84544: 05/05/20: Gabor: Re: Universal logic modules vs NAND-like modules
84237: 05/05/15: <fpga00@gmail.com>: Microblaze interrupt problem
84238: 05/05/16: bxbxb3: wide ROM
84241: 05/05/15: Peter Alfke: Re: wide ROM
84301: 05/05/17: Paul Leventis (at home): Re: wide ROM
84240: 05/05/15: <praveen.kantharajapura@gmail.com>: SPI interface cpol & cpha
84248: 05/05/16: Unbeliever: Re: SPI interface cpol & cpha
84252: 05/05/16: Aurelian Lazarut: Re: SPI interface cpol & cpha
84254: 05/05/16: Unbeliever: Re: SPI interface cpol & cpha
84255: 05/05/16: Iwo Mergler: Re: SPI interface cpol & cpha
84249: 05/05/16: <praveen.kantharajapura@gmail.com>: Re: SPI interface cpol & cpha
84277: 05/05/16: Berty: Re: SPI interface cpol & cpha
84242: 05/05/16: Luke Darnell: Xilinx : Clock Swallowing
84244: 05/05/16: John Adair: Re: Xilinx : Clock Swallowing
84263: 05/05/16: Symon: Re: Xilinx : Clock Swallowing
84480: 05/05/19: Lasse Langwadt Christensen: Re: Xilinx : Clock Swallowing
84250: 05/05/16: Lina: why is it wrong with "sin"?
84253: 05/05/16: Aurelian Lazarut: Re: why is it wrong with "sin"?
84468: 05/05/19: Ben Jones: Re: why is it wrong with "sin"?
84251: 05/05/16: Nicolas Matringe: Altera Apex20KE PLL output jitter problem
84697: 05/05/24: <gregs@altera.com>: Re: Altera Apex20KE PLL output jitter problem
84698: 05/05/24: austin: Re: Altera Apex20KE PLL output jitter problem
84704: 05/05/24: John_H: Re: Altera Apex20KE PLL output jitter problem
84802: 05/05/27: Austin Lesea: Re: Altera Apex20KE PLL output jitter problem
84787: 05/05/27: Nicolas Matringe: Re: Altera Apex20KE PLL output jitter problem
84266: 05/05/16: Andy Peters: Re: floorplanning
84270: 05/05/16: Sarah: Silicon Valley FPGA position
84466: 05/05/19: <mukesh.chugh@gmail.com>: Re: Silicon Valley FPGA position
84478: 05/05/19: Symon: Re: Silicon Valley FPGA position
84274: 05/05/16: Peter Alfke: Bullshit Achieves Literary Status
84275: 05/05/16: Peter Alfke: Re: Bullshit Achieves Literary Status
84370: 05/05/17: John Larkin: Re: Bullshit Achieves Literary Status
84498: 05/05/19: John_H: Re: Bullshit Achieves Literary Status
84502: 05/05/19: John_H: Re: Bullshit Achieves Literary Status
84513: 05/05/20: Paul Leventis (at home): Re: Bullshit Achieves Literary Status
84550: 05/05/21: Jim Granville: Re: Bullshit Achieves Literary Status
84533: 05/05/20: Simon Peacock: Re: Bullshit Achieves Literary Status
84549: 05/05/20: Bob Perlman: Re: Bullshit Achieves Literary Status
84496: 05/05/19: Peter Alfke: Re: Bullshit Achieves Literary Status
84500: 05/05/19: Peter Alfke: Re: Bullshit Achieves Literary Status
84510: 05/05/19: Peter Alfke: Re: Bullshit Achieves Literary Status
84528: 05/05/20: Neo: Re: Bullshit Achieves Literary Status
84530: 05/05/20: Jon Beniston: Re: Bullshit Achieves Literary Status
84547: 05/05/20: Peter Alfke: Re: Bullshit Achieves Literary Status
84278: 05/05/16: Len: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84280: 05/05/16: Peter Alfke: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84298: 05/05/17: Antti Lukats: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84281: 05/05/16: Len: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84282: 05/05/16: <kempaj@yahoo.com>: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84327: 05/05/17: Aurelian Lazarut: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84358: 05/05/18: Paul Boven: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84283: 05/05/16: Len: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84285: 05/05/16: Peter Alfke: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84294: 05/05/17: <giachella.g@laben.it>: Registers replication on Xilinx IOBs
84362: 05/05/17: Avrum: Re: Registers replication on Xilinx IOBs
84363: 05/05/18: Jeremy Stringer: Re: Registers replication on Xilinx IOBs
84369: 05/05/17: Marc Randolph: Re: Registers replication on Xilinx IOBs
84398: 05/05/18: Big Boy: re:Registers replication on Xilinx IOBs
84314: 05/05/17: Christoph Lauer: edk sram interface - board definitions files xbd
84322: 05/05/17: <amir.intisar@gmail.com>: delays
84324: 05/05/17: Gabor: Re: delays
84326: 05/05/17: Unbeliever: Re: delays
84329: 05/05/17: Aurelian Lazarut: Re: delays
84344: 05/05/17: Symon: Re: delays
84384: 05/05/18: <amir.intisar@gmail.com>: Re: delays
84332: 05/05/17: <fpga00@gmail.com>: Help needed!!interrupt handling in microblaze system
84375: 05/05/18: =?ISO-8859-1?Q?G=F6ran_Bilski?=: Re: Help needed!!interrupt handling in microblaze system
84334: 05/05/17: Chris: Virtex-2 JTAG problem
84338: 05/05/17: Antti Lukats: Re: Virtex-2 JTAG problem
84339: 05/05/17: Aurelian Lazarut: Re: Virtex-2 JTAG problem
84341: 05/05/17: Aurelian Lazarut: Re: Virtex-2 JTAG problem
84346: 05/05/17: John Adair: Re: Virtex-2 JTAG problem
84412: 05/05/18: Chris: Re: Virtex-2 JTAG problem
84433: 05/05/19: Antti Lukats: Re: Virtex-2 JTAG problem
84337: 05/05/17: Antti Lukats: open support question to Xilinx. should be fairly simple to answer.
84413: 05/05/18: Michael McGuirk: Re: open support question to Xilinx. should be fairly simple to answer.
84432: 05/05/19: Antti Lukats: Re: open support question to Xilinx. should be fairly simple to answer.
84464: 05/05/19: Rob Gaddi: Re: open support question to Xilinx. should be fairly simple to answer.
84465: 05/05/19: Antti Lukats: Re: open support question to Xilinx. should be fairly simple to answer.
84681: 05/05/25: Alex Gibson: Re: open support question to Xilinx. should be fairly simple to answer.
84340: 05/05/17: jason.stubbs: Virtex 4 MGTVREF pin reference circuit
84342: 05/05/17: dani: Jam Byte-Code Player for 8051
84343: 05/05/17: Antti Lukats: Re: Jam Byte-Code Player for 8051
84380: 05/05/18: Antti Lukats: Re: Jam Byte-Code Player for 8051
84379: 05/05/18: dani: Re: Jam Byte-Code Player for 8051
84383: 05/05/18: dani: Re: Jam Byte-Code Player for 8051
84487: 05/05/19: GMM50: Re: Jam Byte-Code Player for 8051
84489: 05/05/19: Antti Lukats: Re: Jam Byte-Code Player for 8051
84556: 05/05/20: Subroto Datta: Re: Jam Byte-Code Player for 8051
84345: 05/05/17: Paul Leventis: Re: V4 vs. Stratix-II...
84348: 05/05/17: Paul Leventis: Re: V4 vs. Stratix-II...
84354: 05/05/17: gallen: Which Simulators
84356: 05/05/17: Mike Treseler: Re: Which Simulators
84378: 05/05/18: John Adair: Re: Which Simulators
84396: 05/05/18: Ray Andraka: Re: Which Simulators
84421: 05/05/19: Phil Tomson: Re: Which Simulators
84425: 05/05/18: John McGrath: Re: Which Simulators
84430: 05/05/19: jtw: Re: Which Simulators
84457: 05/05/19: gretzteam: Re: Which Simulators
84357: 05/05/18: Fred C: About back annotated simulations...
84359: 05/05/17: Mike Treseler: Re: About back annotated simulations...
84368: 05/05/17: Vaughn Betz: Re: About back annotated simulations...
84392: 05/05/18: Mike Treseler: Re: About back annotated simulations...
84394: 05/05/18: Fred C: Re: About back annotated simulations...
84426: 05/05/18: Vaughn Betz: Re: About back annotated simulations...
84472: 05/05/19: Ray Andraka: Re: About back annotated simulations...
84360: 05/05/17: Phil Hays: Re: About back annotated simulations...
84429: 05/05/19: Bob Perlman: Re: About back annotated simulations...
84511: 05/05/19: Phil Hays: Re: About back annotated simulations...
84532: 05/05/20: Ray Andraka: Re: About back annotated simulations...
84364: 05/05/17: randomdude@gmail.com: VHDL array question
84374: 05/05/18: Jochen: Re: VHDL array question
84376: 05/05/18: randomdude@gmail.com: Re: VHDL array question
84387: 05/05/18: Marc Randolph: Re: VHDL array question
84395: 05/05/18: randomdude@gmail.com: Re: VHDL array question
84428: 05/05/18: Marc Randolph: Re: VHDL array question
84469: 05/05/19: Ray Andraka: Re: VHDL array question
84371: 05/05/17: Geogle: Detaching the schematic viewer under ISE Webpack
84372: 05/05/18: Antti Lukats: Re: Detaching the schematic viewer under ISE Webpack
84402: 05/05/18: W A: Re: Detaching the schematic viewer under ISE Webpack
84527: 05/05/20: Geogle: Re: Detaching the schematic viewer under ISE Webpack
84381: 05/05/18: Andreas Loew: Xilinx IP: PCI Express
84382: 05/05/18: Antti Lukats: Re: Xilinx IP: PCI Express
84403: 05/05/18: Eric Crabill: Re: Xilinx IP: PCI Express
84386: 05/05/18: <m_oylulan@hotmail.com>: CORDIC bit-serial vs. bit-parallel
84405: 05/05/18: GMM50: Re: CORDIC bit-serial vs. bit-parallel
84407: 05/05/18: John_H: Re: CORDIC bit-serial vs. bit-parallel
84471: 05/05/19: Ray Andraka: Re: CORDIC bit-serial vs. bit-parallel
85472: 05/06/09: Ray Andraka: Re: CORDIC bit-serial vs. bit-parallel
85292: 05/06/07: <m_oylulan@hotmail.com>: Re: CORDIC bit-serial vs. bit-parallel
84388: 05/05/18: Henning Zabel: Linux on Xilinx ml310
84400: 05/05/18: beeraka@gmail.com: Re: Linux on Xilinx ml310
84390: 05/05/18: ARRON: For accessing my SDRAM,what should i do?
84391: 05/05/18: Antti Lukats: Re: For accessing my SDRAM,what should i do?
84424: 05/05/18: ARRON: Re: For accessing my SDRAM,what should i do?
84538: 05/05/20: ARRON: Re: For accessing my SDRAM,what should i do?
84569: 05/05/21: jeffsen (toberemoved): Re: For accessing my SDRAM,what should i do?
84585: 05/05/21: ARRON: Re: For accessing my SDRAM,what should i do?
84678: 05/05/24: ARRON: Re: For accessing my SDRAM,what should i do?
84393: 05/05/18: pasacco: Q, BRAM initializing using INIT_0X
84470: 05/05/19: pasacco: Re: Q, BRAM initializing using INIT_0X
84401: 05/05/19: Rudolf Usselmann: DDR2 based Xilinx Development boards ?
84404: 05/05/18: Austin Lesea: Re: DDR2 based Xilinx Development boards ?
84406: 05/05/18: Rob Gaddi: Problems with Constraints (Xilinx, ISE 6.3)
84408: 05/05/18: Gabor: Re: Problems with Constraints (Xilinx, ISE 6.3)
84409: 05/05/18: Symon: Re: Problems with Constraints (Xilinx, ISE 6.3)
84444: 05/05/19: Klaus Falser: Re: Problems with Constraints (Xilinx, ISE 6.3)
84411: 05/05/18: <Kjacek@cyanic.org>: XPS: Create/Import File structure
84415: 05/05/18: Berty: Re: Problems with Constraints (Xilinx, ISE 6.3)
84420: 05/05/18: nara_chak45: where are the PAO files for the system.bsp stored???
84431: 05/05/18: abilashreddy@yahoo.com: Why do VHDL gate level models simulate slower than verilog
84449: 05/05/19: Neo: Re: Why do VHDL gate level models simulate slower than verilog
84450: 05/05/19: JJ: Re: Why do VHDL gate level models simulate slower than verilog
85396: 05/06/09: Jeremy Stringer: Re: Why do VHDL gate level models simulate slower than verilog
84434: 05/05/18: CODE_IS_BAD: How many logic cells are there in one slice
84435: 05/05/18: Marc Randolph: Re: How many logic cells are there in one slice
84439: 05/05/19: Thomas Entner: Re: How many logic cells are there in one slice
84454: 05/05/19: Paul Leventis (at home): Re: How many logic cells are there in one slice
84451: 05/05/19: Marc Randolph: Re: How many logic cells are there in one slice
84474: 05/05/19: Philip Freidin: Re: How many logic cells are there in one slice
84436: 05/05/18: sankalp.singhal: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84437: 05/05/18: CODE_IS_BAD: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84445: 05/05/19: David Brown: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board
84438: 05/05/18: sankalp.singhal: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84441: 05/05/19: sankalp.singhal: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84443: 05/05/19: CODE_IS_BAD: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84479: 05/05/19: dwesterg@gmail.com: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84493: 05/05/19: Peter Sommerfeld: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84534: 05/05/20: sankalp.singhal: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84440: 05/05/19: Neill A: Actel Designer on Linux
84446: 05/05/19: Hans: Re: Actel Designer on Linux
84516: 05/05/19: Thomas Stanka: Re: Actel Designer on Linux
85061: 05/06/03: Neill A: Re: Actel Designer on Linux
84442: 05/05/19: sankalp.singhal: how to debug a C/C++ application in NIOS II IDE
84447: 05/05/19: Ken: Xilinx V2Pro DCM config and settling time questions
84448: 05/05/19: Jochen: Re: Xilinx V2Pro DCM config and settling time questions
84522: 05/05/20: Ken: Re: Xilinx V2Pro DCM config and settling time questions
84477: 05/05/19: Peter Alfke: Re: Xilinx V2Pro DCM config and settling time questions
84526: 05/05/20: Ken: Re: Xilinx V2Pro DCM config and settling time questions
84453: 05/05/19: <amir.intisar@gmail.com>: Spartan 3 CPI
84455: 05/05/19: John Adair: Re: Spartan 3 CPI
84458: 05/05/19: Kolja Sulimma: Re: Spartan 3 CPI
84484: 05/05/19: Antti Lukats: Re: Spartan 3 CPI
84491: 05/05/19: Antti Lukats: Re: Spartan 3 CPI
84482: 05/05/19: Sandro: Re: Spartan 3 CPI
84483: 05/05/19: Peter Alfke: Re: Spartan 3 CPI
84485: 05/05/19: Symon: Re: Spartan 3 CPI
84490: 05/05/19: <jaxatwork@gmail.com>: Re: Spartan 3 CPI
84456: 05/05/19: James A: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84459: 05/05/19: John Adair: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84462: 05/05/19: James A: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84461: 05/05/19: Jochen: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84463: 05/05/19: James A: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84514: 05/05/20: James A: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84497: 05/05/19: Peter Alfke: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84515: 05/05/20: JoeG: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84563: 05/05/21: James A: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84566: 05/05/21: JoeG: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84460: 05/05/19: John Adair: Pushing PicoBlaze
84473: 05/05/19: Brane2: Xilinx Webpack on Gentoo-64bit ?
84481: 05/05/19: Andy Peters: Re: For accessing my SDRAM,what should i do?
84486: 05/05/19: Gabor: Coloring by clock?
84488: 05/05/19: Mike Treseler: Re: Coloring by clock?
84494: 05/05/19: John Adair: Re: Coloring by clock?
84545: 05/05/20: Mike Treseler: Re: Coloring by clock?
84492: 05/05/19: Gabor: Re: Coloring by clock?
84499: 05/05/19: Symon: Re: Coloring by clock?
84517: 05/05/20: Thomas Stanka: Re: Coloring by clock?
84546: 05/05/20: Symon: Re: Coloring by clock?
84590: 05/05/22: <usenet_10@stanka-web.de>: Re: Coloring by clock?
84495: 05/05/19: Joel: Serial Input Review and Questions
84505: 05/05/19: Weddick: Re: Serial Input Review and Questions
84501: 05/05/20: Marco: ISE and Linux
84553: 05/05/20: Eric Smith: Re: ISE and Linux
84564: 05/05/21: Marco: Re: ISE and Linux
84570: 05/05/21: Marco: Re: ISE and Linux
84571: 05/05/21: B. Joshua Rosen: Re: ISE and Linux
84572: 05/05/21: Marco: Re: ISE and Linux
84630: 05/05/23: Eric Smith: Re: ISE and Linux
84503: 05/05/20: Stephen Lohning: Simulation of rocket IO in virtex 2 pro
84504: 05/05/19: B. Joshua Rosen: Re: Simulation of rocket IO in virtex 2 pro
84548: 05/05/20: Duane Clark: Re: Simulation of rocket IO in virtex 2 pro
84652: 05/05/24: Neo: Re: Simulation of rocket IO in virtex 2 pro
84506: 05/05/20: Jeremy Stringer: Jobs going in New Zealand
84518: 05/05/20: Simon Peacock: Re: Jobs going in New Zealand
84639: 05/05/24: Jeremy Stringer: Re: Jobs going in New Zealand
84640: 05/05/23: Antti Lukats: Re: Jobs going in New Zealand
84648: 05/05/23: BobJ: Re: Jobs going in New Zealand
84850: 05/05/31: Jeremy Stringer: Re: Jobs going in New Zealand
156280: 14/02/04: hary: RE: Jobs going in New Zealand
156281: 14/02/05: hamilton: Re: Jobs going in New Zealand
84509: 05/05/19: Mike: FFT with FPGA
84512: 05/05/19: Mike: Re: FFT with FPGA
84523: 05/05/20: Ben Jones: Re: FFT with FPGA
84536: 05/05/20: Luc: Re: FFT with FPGA
84520: 05/05/20: Neo: Re: FFT with FPGA
84521: 05/05/20: Johnschool: A Short Pulse Catcher
84529: 05/05/20: Neo: Re: A Short Pulse Catcher
84543: 05/05/20: Jonathan Bromley: Re: A Short Pulse Catcher
85044: 05/06/03: Jonathan Bromley: Re: A Short Pulse Catcher
84541: 05/05/20: Johnschool: Re: A Short Pulse Catcher
84653: 05/05/24: Johnschool: Re: A Short Pulse Catcher
84788: 05/05/27: Johnschool: Re: A Short Pulse Catcher
84524: 05/05/20: cromr: Synopsys Designware IP... can be used for Xilinx FPGA??
84537: 05/05/20: Jon Beniston: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
84730: 05/05/25: Mike Lewis: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
84779: 05/05/26: cromr: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
85120: 05/06/05: Ken McElvain: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
84737: 05/05/25: Jon Beniston: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
84525: 05/05/20: Shakith: Memec Virtex-4 LX25 LC
84531: 05/05/20: John Adair: Re: Memec Virtex-4 LX25 LC
84535: 05/05/20: Ralf: ALTERA EPXA1 SDRAM BUG
84539: 05/05/20: ivan: How to download uClinux on Virtex4 Board.
84582: 05/05/22: Rudolf Usselmann: Re: How to download uClinux on Virtex4 Board.
84584: 05/05/21: Jason Wu: Re: How to download uClinux on Virtex4 Board.
84680: 05/05/25: Alex Gibson: Re: How to download uClinux on Virtex4 Board.
84588: 05/05/22: ivan: Re: How to download uClinux on Virtex4 Board.
84551: 05/05/20: Andy Peters: Re: For accessing my SDRAM,what should i do?
84558: 05/05/21: Gary Pace: VHDL vs. Schematic Capture
84562: 05/05/21: Sylvain Munaut: Re: VHDL vs. Schematic Capture
84565: 05/05/21: Kasper Pedersen: Re: VHDL vs. Schematic Capture
84853: 05/05/31: JoeG: Re: VHDL vs. Schematic Capture
84567: 05/05/21: JoeG: Re: VHDL vs. Schematic Capture
84573: 05/05/21: John Adair: Re: VHDL vs. Schematic Capture
84574: 05/05/21: dave: Re: VHDL vs. Schematic Capture
84576: 05/05/21: Subroto Datta: Re: VHDL vs. Schematic Capture
84577: 05/05/21: dave: Re: VHDL vs. Schematic Capture
84578: 05/05/21: Subroto Datta: Re: VHDL vs. Schematic Capture
84708: 05/05/24: Austin Franklin: Re: VHDL vs. Schematic Capture
84715: 05/05/25: Thomas Entner: Re: VHDL vs. Schematic Capture
84731: 05/05/25: Austin Franklin: Re: VHDL vs. Schematic Capture
84734: 05/05/25: Duane Clark: Re: VHDL vs. Schematic Capture
84735: 05/05/25: dave: Re: VHDL vs. Schematic Capture
84747: 05/05/25: Austin Franklin: Re: VHDL vs. Schematic Capture
84764: 05/05/26: dave: Re: VHDL vs. Schematic Capture
84777: 05/05/26: Austin Franklin: Re: VHDL vs. Schematic Capture
84625: 05/05/23: Jon Elson: Re: VHDL vs. Schematic Capture
84810: 05/05/27: Jon Elson: Re: VHDL vs. Schematic Capture
84629: 05/05/23: Peter Alfke: Re: VHDL vs. Schematic Capture
84644: 05/05/23: Jansyn: Re: VHDL vs. Schematic Capture
84651: 05/05/24: Philip Freidin: Re: VHDL vs. Schematic Capture
84687: 05/05/24: John_H: Re: VHDL vs. Schematic Capture
84667: 05/05/24: Gabor: Re: VHDL vs. Schematic Capture
84736: 05/05/25: JJ: Re: VHDL vs. Schematic Capture
84812: 05/05/27: Peter Alfke: Re: VHDL vs. Schematic Capture
84828: 05/05/29: Ankit Raizada: Re: VHDL vs. Schematic Capture
84831: 05/05/29: Mounard le Fougueux: Re: VHDL vs. Schematic Capture
85334: 05/06/07: Austin Franklin: Re: VHDL vs. Schematic Capture
84855: 05/05/30: <ccon67@netscape.net>: Re: VHDL vs. Schematic Capture
84559: 05/05/20: Steven J. Hill: Reading the contents of a FPGA in-circuit.
84579: 05/05/21: GMM50: Re: Reading the contents of a FPGA in-circuit.
84575: 05/05/21: Marco: How to make a 1.44MHz clock?
84580: 05/05/21: Moti Cohen: Re: How to make a 1.44MHz clock?
84581: 05/05/21: John_H: Re: How to make a 1.44MHz clock?
84586: 05/05/22: Marco: Re: How to make a 1.44MHz clock?
84587: 05/05/22: Marco: Re: How to make a 1.44MHz clock?
84618: 05/05/23: John_H: Re: How to make a 1.44MHz clock?
84626: 05/05/23: John_H: Re: How to make a 1.44MHz clock?
84631: 05/05/23: Marco: Re: How to make a 1.44MHz clock?
84594: 05/05/22: Peter Alfke: Re: How to make a 1.44MHz clock?
84583: 05/05/21: Joseph: Custom IP and BFM simulation help
84592: 05/05/22: Paul Hartke: Re: Custom IP and BFM simulation help
84589: 05/05/22: Peter Alfke: Re: How to make a 1.44MHz clock?
84591: 05/05/22: Arlet: Re: How to make a 1.44MHz clock?
84593: 05/05/22: Andrew Lohbihler: Looking for core that does a vector product
84595: 05/05/22: Ben Twijnstra: Re: Looking for core that does a vector product
84596: 05/05/22: fred: Re: Looking for core that does a vector product
84616: 05/05/23: Luc: Re: Looking for core that does a vector product
84713: 05/05/25: Ray Andraka: Re: Looking for core that does a vector product
84597: 05/05/22: Jim George: GHDL under x86_64 Linux
84612: 05/05/23: <tgingold_nospam@yahoo.com>: Re: GHDL under x86_64 Linux
84599: 05/05/22: <googlinggoogler@hotmail.com>: spartan 3 designing board
84602: 05/05/22: austin: Re: spartan 3 designing board
84606: 05/05/23: Sylvain Munaut: Re: spartan 3 designing board
84600: 05/05/22: Luke Darnell: Virtex4 Block Ram : ISE6.3 Problem
84603: 05/05/22: Marc Randolph: Re: Virtex4 Block Ram : ISE6.3 Problem
84617: 05/05/23: Aurelian Lazarut: Re: Virtex4 Block Ram : ISE6.3 Problem
84609: 05/05/23: gralsto: FSM stops working
84610: 05/05/23: John Adair: Re: FSM stops working
84611: 05/05/23: Neo: Re: FSM stops working
84614: 05/05/23: Jim Wu: Re: FSM stops working
84634: 05/05/23: Gabor: Re: FSM stops working
84645: 05/05/23: gralsto: re:FSM stops working
84646: 05/05/23: gralsto: re:FSM stops working
84661: 05/05/24: Marc Randolph: Re: re:FSM stops working
84613: 05/05/23: Frank van Eijkelenburg: using less brams for powerpc code
84615: 05/05/23: Krzysztof Szczepanski: RISCWatch and JTAG
84745: 05/05/25: Nju Njoroge: Re: RISCWatch and JTAG
84619: 05/05/23: Falk Brunner: CPLD Fitting problem
84621: 05/05/23: <ALuPin@web.de>: Re: CPLD Fitting problem
84624: 05/05/23: John Adair: Re: CPLD Fitting problem
84636: 05/05/23: Falk Brunner: Re: CPLD Fitting problem
84620: 05/05/23: Tom: Nondeterministic ISE Placement
84663: 05/05/24: Marc Randolph: Re: Nondeterministic ISE Placement
84623: 05/05/23: Antti Lukats: more and more and more issues with Xilinx tools
84627: 05/05/23: Mike Harrison: Re: more and more and more issues with Xilinx tools
84628: 05/05/23: Antti Lukats: Re: more and more and more issues with Xilinx tools
84633: 05/05/23: Symon: Re: more and more and more issues with Xilinx tools
84635: 05/05/23: Antti Lukats: Re: more and more and more issues with Xilinx tools
84649: 05/05/24: Antti Lukats: Re: more and more and more issues with Xilinx tools
84684: 05/05/24: Duane Clark: Re: more and more and more issues with Xilinx tools
84693: 05/05/24: Matthieu MICHON: Re: more and more and more issues with Xilinx tools
84655: 05/05/24: Geogle: Re: more and more and more issues with Xilinx tools
84692: 05/05/24: zeeman_be: Re: more and more and more issues with Xilinx tools
84695: 05/05/24: Antti Lukats: Re: more and more and more issues with Xilinx tools
84711: 05/05/25: Ray Andraka: Re: more and more and more issues with Xilinx tools
84637: 05/05/23: pasacco: Project Navigator mapping problem with CLK and BRAM
84668: 05/05/24: Gabor: Re: Project Navigator mapping problem with CLK and BRAM
84722: 05/05/25: pasacco: Re: Project Navigator mapping problem with CLK and BRAM
84763: 05/05/26: Gabor: Re: Project Navigator mapping problem with CLK and BRAM
84638: 05/05/24: Rudolf Usselmann: System Reset / GSR with Virtex 2 & Virtex 4
84641: 05/05/23: John_H: Re: System Reset / GSR with Virtex 2 & Virtex 4
84671: 05/05/24: Rudolf Usselmann: Re: System Reset / GSR with Virtex 2 & Virtex 4
84685: 05/05/24: John_H: Re: System Reset / GSR with Virtex 2 & Virtex 4
84642: 05/05/23: Peter Alfke: Re: System Reset / GSR with Virtex 2 & Virtex 4
84643: 05/05/23: methi: Mapping problem due to invalid pins in UCF file
84658: 05/05/24: Aurelian Lazarut: Re: Mapping problem due to invalid pins in UCF file
84676: 05/05/24: Sean Durkin: Re: Mapping problem due to invalid pins in UCF file
84677: 05/05/24: Aurelian Lazarut: Re: Mapping problem due to invalid pins in UCF file
84686: 05/05/24: Aurelian Lazarut: Re: Mapping problem due to invalid pins in UCF file
84694: 05/05/24: Yttrium: Re: Mapping problem due to invalid pins in UCF file
84673: 05/05/24: methi: Re: Mapping problem due to invalid pins in UCF file
84682: 05/05/24: methi: Re: Mapping problem due to invalid pins in UCF file
84689: 05/05/24: methi: Re: Mapping problem due to invalid pins in UCF file
84696: 05/05/24: methi: Re: Mapping problem due to invalid pins in UCF file
84725: 05/05/25: Aurelian Lazarut: Re: Mapping problem due to invalid pins in UCF file
84647: 05/05/23: AnonymousFC3: QUARTUS on Linux.
84650: 05/05/24: Ben Twijnstra: Re: QUARTUS on Linux.
84660: 05/05/24: arvan: Re: QUARTUS on Linux.
84654: 05/05/24: lovesinghal@gmail.com: Xilinx Virtex 4 Configuration Frames
84656: 05/05/24: techie: how to apply different stimulus files to a test bench
84702: 05/05/24: Bob Perlman: Re: how to apply different stimulus files to a test bench
84657: 05/05/24: adrian: using a SDRAM FIFO
84659: 05/05/24: <amyler@eircom.net>: Re: using a SDRAM FIFO
84679: 05/05/24: Aurelian Lazarut: Re: using a SDRAM FIFO
84683: 05/05/24: Ed McGettigan: Re: using a SDRAM FIFO
84662: 05/05/24: Antti Lukats: Xilinx Answer Record 21127
84664: 05/05/24: Marc Randolph: Re: Xilinx Answer Record 21127
84914: 05/06/01: Jeremy Stringer: Re: Xilinx Answer Record 21127
84665: 05/05/24: Nicolas Matringe: Re: Xilinx Answer Record 21127
84675: 05/05/24: Antti Lukats: Re: Xilinx Answer Record 21127
84712: 05/05/25: Sean Durkin: Re: Xilinx Answer Record 21127
84714: 05/05/25: Antti Lukats: Re: Xilinx Answer Record 21127
84666: 05/05/24: John Adair: Re: Xilinx Answer Record 21127
84669: 05/05/24: icegray: ethernet
84690: 05/05/24: Berty: Re: ethernet
84798: 05/05/27: Piotr Wyderski: Re: ethernet
84716: 05/05/25: AVG: Re: ethernet
84717: 05/05/25: icegray: Re: ethernet
84718: 05/05/25: icegray: Re: ethernet
84720: 05/05/25: AVG: Re: ethernet
84721: 05/05/25: icegray: Re: ethernet
84724: 05/05/25: AVG: Re: ethernet
84797: 05/05/27: Piotr Wyderski: Re: ethernet
84818: 05/05/28: icegray: Re: ethernet
84670: 05/05/24: <zoinks@mytrashmail.com>: cannot get compedklib tool to work
84705: 05/05/24: Ryan Laity: Re: cannot get compedklib tool to work
84726: 05/05/25: <zoinks@mytrashmail.com>: Re: cannot get compedklib tool to work
84672: 05/05/24: <ALuPin@web.de>: Programmer + Cable
84674: 05/05/24: John Adair: Re: Programmer + Cable
84688: 05/05/24: Brad Smallridge: Bresenham Algorithms
84700: 05/05/24: Ben Twijnstra: Re: Bresenham Algorithms
84703: 05/05/24: Jake Janovetz: Re: Bresenham Algorithms
84706: 05/05/24: Ben Twijnstra: Re: Bresenham Algorithms
84709: 05/05/24: Jake Janovetz: Re: Bresenham Algorithms
84785: 05/05/27: Ray Andraka: Re: Bresenham Algorithms
84701: 05/05/24: Ben Twijnstra: Re: Bresenham Algorithms
84710: 05/05/25: Ray Andraka: Re: Bresenham Algorithms
84699: 05/05/24: Yttrium: warning place and route ise7.1?
84707: 05/05/24: donghun: Re: warning place and route ise7.1?
84742: 05/05/25: Yttrium: Re: warning place and route ise7.1?
84775: 05/05/26: Yttrium: Re: warning place and route ise7.1?
84746: 05/05/25: Peter Alfke: Re: warning place and route ise7.1?
84748: 05/05/25: Gabor: Re: warning place and route ise7.1?
84723: 05/05/25: Jedi: Lattice ROM file tool....
84752: 05/05/26: Matt North: Re: Lattice ROM file tool....
84727: 05/05/25: Piotr Wyderski: Single-endec clocks
84728: 05/05/25: <amyler@eircom.net>: Re: Single-endec clocks
84738: 05/05/25: Piotr Wyderski: Re: Single-endec clocks
84751: 05/05/26: Rene Tschaggelar: Re: Single-endec clocks
84759: 05/05/26: Piotr Wyderski: Re: Single-endec clocks
84768: 05/05/26: Piotr Wyderski: Re: Single-endec clocks
84760: 05/05/26: <amyler@eircom.net>: Re: Single-endec clocks
84732: 05/05/25: Frank van Eijkelenburg: powerpc startup
84749: 05/05/25: Peter Ryser: Re: powerpc startup
84757: 05/05/26: Frank van Eijkelenburg: Re: powerpc startup
84767: 05/05/26: Peter Ryser: Re: powerpc startup
84784: 05/05/27: Frank van Eijkelenburg: Re: powerpc startup
84960: 05/06/01: Peter Ryser: Re: powerpc startup
85038: 05/06/03: Frank van Eijkelenburg: Re: powerpc startup
84733: 05/05/25: kurapati: generate systemACE file
89875: 05/09/28: rsotam: re:generate systemACE file
84739: 05/05/25: Andrew Holme: lpm_counter bug?
84740: 05/05/25: John_H: Re: lpm_counter bug?
84741: 05/05/25: Peter Sommerfeld: Re: lpm_counter bug?
84743: 05/05/25: Andrew Holme: Re: lpm_counter bug?
84744: 05/05/25: Andrew Holme: Re: lpm_counter bug?
84750: 05/05/26: Hw: Ethernet / digital logic questions
84753: 05/05/26: Jon Beniston: Re: Ethernet / digital logic questions
84754: 05/05/26: Simon Peacock: Re: Ethernet / digital logic questions
84766: 05/05/26: Big Boy: re:Ethernet / digital logic questions
84769: 05/05/26: Berty: Re: Ethernet / digital logic questions
84790: 05/05/27: Hw: Re: Ethernet / digital logic questions
84780: 05/05/27: Mac: Re: Ethernet / digital logic questions
84807: 05/05/27: Berty: Re: Ethernet / digital logic questions
84755: 05/05/26: Love Singhal: Virtex 4 configuration frames
84774: 05/05/26: Vic Vadi: Re: Virtex 4 configuration frames
84783: 05/05/27: Love Singhal: Re: Virtex 4 configuration frames
84792: 05/05/27: kurapati: Re: Virtex 4 configuration frames
84756: 05/05/26: Jedi: ARC A4
84758: 05/05/26: Jon Beniston: Re: ARC A4
84761: 05/05/26: <nospam@nospam.com>: State Machines.. and their efficiency.
84762: 05/05/26: Aurelian Lazarut: Re: State Machines.. and their efficiency.
84765: 05/05/26: Jake Janovetz: Re: State Machines.. and their efficiency.
84770: 05/05/26: Eric Crabill: Re: State Machines.. and their efficiency.
84771: 05/05/26: vax, 9000: What's the difference between Altera EPM1270T144C5 and EPM1270T144C5N?
84773: 05/05/26: John_H: Re: What's the difference between Altera EPM1270T144C5 and EPM1270T144C5N?
84776: 05/05/26: <smensor@altera.com>: Re: What's the difference between Altera EPM1270T144C5 and EPM1270T144C5N?
84772: 05/05/26: Jack: V2pro configuration problem - PROM SIZE
84778: 05/05/26: Jim George: Async FIFO coregen wizard
84808: 05/05/27: <fpgaguy@aedinc.net>: Re: Async FIFO coregen wizard
84781: 05/05/26: CODE_IS_BAD: 2:1 mux in one LUT
84786: 05/05/27: John Adair: Re: 2:1 mux in one LUT
84782: 05/05/27: Antti Lukats: ISE 7.1 small advice about project files (.ISE extension)
84791: 05/05/27: Jim Granville: Re: ISE 7.1 small advice about project files (.ISE extension)
84796: 05/05/27: Martin Schoeberl: Re: ISE 7.1 small advice about project files (.ISE extension)
84799: 05/05/27: Gabor: Re: ISE 7.1 small advice about project files (.ISE extension)
84789: 05/05/27: siedon: Q.Timing Simulation using ModelSim for a Xilinx Spartan 2E
84793: 05/05/27: kurapati: compact flash configuration on ml403 board
84794: 05/05/27: Leon Heller: Xilinx Parallel Cable III flying lead repair
84795: 05/05/27: John Adair: Re: Xilinx Parallel Cable III flying lead repair
84800: 05/05/27: Alex: Wrong type name (subtitution) in post-place & route simulation model.
84801: 05/05/27: Marco: Accessing BRAM as a SRAM
84806: 05/05/27: Marco: Re: Accessing BRAM as a SRAM
84811: 05/05/27: Peter Alfke: Re: Accessing BRAM as a SRAM
84815: 05/05/28: Philip Freidin: Re: Accessing BRAM as a SRAM
84816: 05/05/28: Marco: Re: Accessing BRAM as a SRAM
84820: 05/05/28: Philip Freidin: Re: Accessing BRAM as a SRAM
84825: 05/05/28: Marco: Re: Accessing BRAM as a SRAM
84817: 05/05/28: Marco: Re: Accessing BRAM as a SRAM
84803: 05/05/27: yijun_lily@yahoo.com: Design flow of Spartan3 for my own embedded processor and HW logic?
84804: 05/05/27: Marco: Re: Design flow of Spartan3 for my own embedded processor and HW logic?
84805: 05/05/27: alpha: Hard Ethernet MAC for Virtex-4 FX12
87171: 05/07/18: kurapati: re:Hard Ethernet MAC for Virtex-4 FX12
84809: 05/05/27: jjlindula@hotmail.com: Incremental Compilation in Quartus 4.2
84835: 05/05/30: Vaughn Betz: Re: Incremental Compilation in Quartus 4.2
84966: 05/06/01: <sesh67@yahoo.com>: Re: Incremental Compilation in Quartus 4.2
84813: 05/05/28: Wenchang: Synplify 8.1 vs. Quartus II 5.0 QoR
84814: 05/05/28: Subroto Datta: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
84823: 05/05/28: Subroto Datta: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
84834: 05/05/30: Vaughn Betz: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
84824: 05/05/28: Jon Beniston: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
84837: 05/05/30: Ben Twijnstra: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
84846: 05/05/30: Ken McElvain: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
84819: 05/05/28: HiTech: FPGA Boards
84877: 05/05/31: Jorge: Re: FPGA Boards
84821: 05/05/28: Michael Dreschmann: Control asynchronous SRAM like synchronous SRAM
84822: 05/05/28: Jan Gray: Re: Control asynchronous SRAM like synchronous SRAM
84829: 05/05/29: Michael Dreschmann: Re: Control asynchronous SRAM like synchronous SRAM
84847: 05/05/30: Brian Davis: Re: Control asynchronous SRAM like synchronous SRAM
84826: 05/05/29: TA: beginer
84827: 05/05/29: Squidge: Re: beginer
84830: 05/05/29: Dave Vanden Bout: Re: beginer
84832: 05/05/29: Steven J. Hill: [NEWBIE] Linux WebPack questions...
84833: 05/05/29: <praveen.kantharajapura@gmail.com>: Keypad controller implementation
84836: 05/05/29: Andrew FPGA: Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series DCI"
84843: 05/05/30: austin: Re: Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series
84844: 05/05/30: John Adair: Re: Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series DCI"
84849: 05/05/30: Andrew FPGA: Re: Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series DCI"
84838: 05/05/30: ANANTHARAJ.T.V.: ISE 6.1 - Fatal Error
84840: 05/05/30: Antti Lukats: Re: ISE 6.1 - Fatal Error
84839: 05/05/30: tvar_vlsi: Xilinx ISE 6.1i - Fatal Error
84884: 05/05/31: Vladislav Muravin: Re: Xilinx ISE 6.1i - Fatal Error
84841: 05/05/30: <praveen.kantharajapura@gmail.com>: SPI slave select signals
84842: 05/05/30: Mike Lewis: Re: SPI slave select signals
84845: 05/05/30: <amyler@eircom.net>: Nios speed down
84852: 05/05/30: Paul Leventis (at home): Re: Nios speed down
84848: 05/05/30: M.Randelzhofer: Xilinx CPLD fitter trouble, OK in Foundation4.1, bad in 6.3,7.1
84851: 05/05/30: Bob Perlman: StateCAD 7.1i is broken?
84888: 05/05/31: Mike Treseler: Re: StateCAD 7.1i is broken?
84856: 05/05/31: Sean Durkin: Magical Mystery Tour of ISE environment variables
84857: 05/05/31: Uwe Bonnes: Re: Magical Mystery Tour of ISE environment variables
84858: 05/05/31: Sean Durkin: Re: Magical Mystery Tour of ISE environment variables
84864: 05/05/31: John Adair: Re: Magical Mystery Tour of ISE environment variables
84911: 05/05/31: Jim George: Re: Magical Mystery Tour of ISE environment variables
85143: 05/06/06: Martin Thompson: Re: Magical Mystery Tour of ISE environment variables
84859: 05/05/31: Joseph Tan: Nios II - Booting software from Flash
84865: 05/05/31: Jedi: Re: Nios II - Booting software from Flash
84908: 05/05/31: Joseph Tan: Re: Nios II - Booting software from Flash
85685: 05/06/13: Joseph Tan: Re: Nios II - Booting software from Flash
84860: 05/05/31: zoinks@mytrashmail.com: program simulation of the ML310 with XPS+ModelSim
84861: 05/05/31: BQ: Problems with SDRAM and Altera Cyclone
84869: 05/05/31: John McGrath: Re: Problems with SDRAM and Altera Cyclone
84871: 05/05/31: BQ: Re: Problems with SDRAM and Altera Cyclone
84870: 05/05/31: Gabor: Re: Problems with SDRAM and Altera Cyclone
84872: 05/05/31: BQ: Re: Problems with SDRAM and Altera Cyclone
84879: 05/05/31: GMM50: Re: Problems with SDRAM and Altera Cyclone
84862: 05/05/31: Kalle: Timing summary
84863: 05/05/31: Kalle: Re: Timing summary
84866: 05/05/31: Marc Randolph: Re: Timing summary
84882: 05/05/31: Vladislav Muravin: Re: Timing summary
84867: 05/05/31: Marco: opb bram controller
85169: 05/06/06: digi: re:opb bram controller
84868: 05/05/31: Marco: Accessing Bram
84904: 05/06/01: John Williams: Re: Accessing Bram
84932: 05/06/01: Marco: Re: Accessing Bram
84949: 05/06/01: Joey: Re: Accessing Bram
84951: 05/06/01: Marco: Re: Accessing Bram
84976: 05/06/02: Joey: Re: Accessing Bram
84873: 05/05/31: Sven: Configuration-Frames for Virtex-II (Pro)
84905: 05/06/01: John Williams: Re: Configuration-Frames for Virtex-II (Pro)
84874: 05/05/31: Dave: What is a typical job scope when FPGAs are involved?
84878: 05/05/31: JJ: Re: What is a typical job scope when FPGAs are involved?
84886: 05/05/31: Rene Tschaggelar: Re: What is a typical job scope when FPGAs are involved?
84887: 05/05/31: Mac: Re: What is a typical job scope when FPGAs are involved?
84876: 05/05/31: Big Boy: Problem with Synplify 7.7.1, startup block vs clock input
84906: 05/05/31: Big Boy: re:Problem with Synplify 7.7.1, startup block vs clock input
84880: 05/05/31: Jorge: JTAG Programming Problem
84883: 05/05/31: Vladislav Muravin: Re: JTAG Programming Problem
84912: 05/05/31: Jim George: Re: JTAG Programming Problem
84988: 05/06/02: <billaud@labri.u-bordeaux.fr>: Re: JTAG Programming Problem
84885: 05/05/31: John_H: Xilinx DDR output registers
84898: 05/05/31: Gabor: Re: Xilinx DDR output registers
84902: 05/05/31: Duane Clark: Re: Xilinx DDR output registers
84903: 05/05/31: John_H: Re: Xilinx DDR output registers
84926: 05/06/01: Philip Freidin: Re: Xilinx DDR output registers
84947: 05/06/01: John_H: Re: Xilinx DDR output registers
84889: 05/05/31: Jedi: Altera NIOS2 50.0 SOPC periphals broken???
84892: 05/05/31: Jedi: Re: Altera NIOS2 50.0 SOPC periphals broken???
84890: 05/05/31: <ccon67@netscape.net>: How fast multiplier in VirtexE?
84891: 05/05/31: Yttrium: regional clk to dcm? possible or not?
84971: 05/06/02: Krzysztof Szczepanski: Re: regional clk to dcm? possible or not?
84893: 05/05/31: <pvnguyen@mail.ucf.edu>: Implementing sin function in fpga
84896: 05/05/31: Piotr Wyderski: Re: Implementing sin function in fpga
84897: 05/05/31: John_H: Re: Implementing sin function in fpga
84900: 05/05/31: Berty: Re: Implementing sin function in fpga
84901: 05/05/31: Piotr Wyderski: Re: Implementing sin function in fpga
84909: 05/05/31: Peter Alfke: Re: Implementing sin function in fpga
84935: 05/06/01: Piotr Wyderski: Re: Implementing sin function in fpga
84931: 05/06/01: <pvnguyen@mail.ucf.edu>: Re: Implementing sin function in fpga
84933: 05/06/01: Peter Alfke: Re: Implementing sin function in fpga
84941: 05/06/01: <pvnguyen@mail.ucf.edu>: Re: Implementing sin function in fpga
84894: 05/05/31: Gabor: Re: FPGA Boards
84895: 05/05/31: maddy: Re: FPGA Boards
84907: 05/05/31: John Larkin: need a book: Hilbert transform
84910: 05/06/01: Joerg: Re: need a book: Hilbert transform
84913: 05/05/31: John Larkin: Re: need a book: Hilbert transform
84915: 05/06/01: Terry Given: Re: need a book: Hilbert transform
84937: 05/06/01: John Larkin: Re: need a book: Hilbert transform
84946: 05/06/02: Terry Given: Re: need a book: Hilbert transform
84916: 05/06/01: Mike Monett: Re: need a book: Hilbert transform
84938: 05/06/01: John Larkin: Re: need a book: Hilbert transform
84973: 05/06/02: Mike Monett: Re: need a book: Hilbert transform
84929: 05/06/01: Fred Bloggs: Re: need a book: Hilbert transform
84939: 05/06/01: John Larkin: Re: need a book: Hilbert transform
85006: 05/06/02: new.online.de: Re: need a book: Hilbert transform
85009: 05/06/02: John Larkin: Re: need a book: Hilbert transform
85010: 05/06/02: Joerg: Re: need a book: Hilbert transform
85011: 05/06/03: Terry Given: Re: need a book: Hilbert transform
85014: 05/06/02: Joerg: Re: need a book: Hilbert transform
85012: 05/06/02: John Larkin: Re: need a book: Hilbert transform
85013: 05/06/02: Joerg: Re: need a book: Hilbert transform
85015: 05/06/02: Mike Monett: Re: need a book: Hilbert transform
85024: 05/06/03: Mac: Re: need a book: Hilbert transform
84918: 05/05/31: Eug: problems with Ultra DMA operations with ATA HDD
84950: 05/06/01: <ccon67@netscape.net>: Re: problems with Ultra DMA operations with ATA HDD
128411: 08/01/24: xiaoxiao008: Re: problems with Ultra DMA operations with ATA HDD
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