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john.deepu@gmail.com wrote: > I wanted to sort 48 8bit unsigned numbers And do you want the 384 bit result for a new set of numbers every 10 ns? Can you wait 1 ms for the result? Is it fine to keep the inputs and outputs in a BlockRAM or are you presenting them parallel?Article: 85276
Aurash, That seems to be correct (on oscilloscope: 1.5 V, 2.5 V and 3.3 V) Pierre "Aurelian Lazarut" <aurash@xilinx.com> a écrit dans le message de news:d83uk0$ps62@cliff.xsj.xilinx.com... > Pierre, > First I would check the power supply > AurashArticle: 85277
Vaugn, Page 3, lists a number of "in-rush" requirements. http://focus.ti.com/lit/ml/slyb113a/slyb113a.pdf I won't bore you with listing all of your other power supply partners web site links all listing power on surges. And, XPower requires you have a test bench of transistions for your design. I suppose you worked really hard to verify that your test bench was accurate? No, I suspected not. Maybe you designed a single 16 bit counter in an LX60 part? Easy ways to misuse all tools. Don't bore me. Post when you have something useful to say. And if there is no in-rush (power on surge), then straighten out your seven plus vendors collaterial. Not to mention your own collaterial. Austin Vaughn Betz wrote: >>For the record, I was referring to the Excel spreadsheet 'accuracy'. >> >>Use of the verilog test bench file with the XPower tool results in a far >>better estimate, given the customer actually has captured what is really >>happening in their simulation. > > > We've checked XPower's accuracy, and it is much worse than +/-50%. I agree > it should be significantly better than the web tool, given that it knows the > placement and routing, and is connected to a simulator to get good toggle > rates. That leads me to expect a very large error bar on the web tool. > > > >>But, have you fixed the power on surge problem in Cyclone II? > > > There is no power-on surge on Cyclone II. > > Interestingly, Xilinx's web site does not claim there is a power-on surge > for Stratix II anymore, nor does it claim any power-on surge for Cyclone II. > It appears that your marketing folks have removed their earlier claims > related to power-on surge, presumably because they are easily contradicted > by a lab measurement. > > Vaughn > Altera > [v b e t z (at) altera.com] > >Article: 85278
It is, Unspecified. Since there is no feedback, there will be some number of 100's of ps delay from CLKIN to an associated CLKFX output edge. It will vary with process, voltage, and temperature. If this is important, you should resynchronize the CLKIN domain to the CLKFX domain (using FF's in the CLB's). Austin al82 wrote: > Can anyone tell me which is the phase delay between input and > output(CLKFX) when there is no feedback (Input frequency less than > 24MHz) > > Thanks >Article: 85279
Hi some info from the Lattice roadshow seminar at Mentor 1) 0.9 and 0.65 !? products are coming... 2) new FPGA products to be exptected (when you are back from sommer vaccation..) that goes for new FPGA products (not low end), not just some new device/derivate of existing things 3) something new is coming to the PLD offering as well (same timeline as above?) 4) serdes 2.5G+ will be included in some of the new devices 5) Lattice has completly solved the NBTI (and other submicron) issues (as much as I understood it means all the V4 NBTI like issues, things why xilinx is not shipping V4 silicon with working MGTs and why Stratix IIGX is delayed) are solved 6) EC family pricing can meed the S3 pricing in all cases where xilinx is not dumping on the high volumes 7) ECP and XP prices are EC+10% please dont take those above as some official announcements, its only the answers I got ;) and possible my interpretation what may not be entirely accurate Antti PS there was lots of free stuff from Mentor, incl. free lunch and optical usb mouseArticle: 85280
Just a reminder, the seminar starts in a few hours. Still time to sign up, learn, and enjoy. To join us on Tuesday, June 7 at 11 am Pacific Time, 2 pm East Coast time, 1900 in England, and 2000 in Central Europe (sorry, very early in Asia), register by clicking on http://seminar2.techonline.com /s/xilinx_jun0705 To join us for the same seminar, one day later and four hours earlier, on Wednesday, June 8 at 7 am Pacific Time, 10 am East Coast time, 1500 in England, and 1600 in Central Europe (sorry, even earlier in Asia), register by clicking on http://seminar2.techonline.com /s/xilinx_jun0805 Peter Alfke, Xilinx PS. I will soon publish the best way to access the archived seminars.Article: 85281
Eric, > I passed your comments on to those working on the architecture wizard for > RocketIO. Based on your comment, I suggested that they consider not only > "1-lane" and "2-lane", but "dual 1-lane" as valid configurations for > architecture wizard generated output. Thanks for passing my comments. The wizard actually doesn't use the concept of lanes. I think I have seen it in some earlier version, but I am not sure. It does ask how many tranceievers to bond but only if the Receiver is enabled on the first page. > I also suggested that they add an > option for, "I don't want CRC block functions, please hide those ports from > me..." which would cause them to be tied off inside the module instead of > brought to ports. I think there has to be a mode where the generated module has only a parallel data bus input/output, a clock and the serial output/input and perhaps a few status signals. Everything else has to be optional and grouped according to the functionality. > Yes, what you've got right now for a single lane, transmit only function > certainly seems like a lot of extra ports! The best I can offer you > currently is to sit with the user guide and go through the module's input > ports one at a time, determining what value to assign to either deassert > them or leave them in a benign state. It is tedioius but not too hard > (having done it myself...) That's what I am doing, but the manual is not always clear and many of the pins require deep understanding of the MGBT operation. For example, the port I am currently looking at is the ENMCOMMAALIGN. Here is what the RocketIO manual says about it: "Selects realignment of incoming serial bitstream on minuscomma. When set to logic 1, realigns serial bitstream byte boundary to where minus-comma is detected." The Aurora manual does not mention the ENMCOMMAALIGN, although "Enable comma alignment" can be found in some of the state diagrams. But which mode? According to the Table 3-6 in the RocketIO manual (ug076) there are at least 3 different enable modes. This is all very confusing. If Aurora requires this to be set in any way, then obviously it has to be done by the wizard. Thanks, /MikhailArticle: 85282
I use the free version of Target downloaded from http://www.pcbpool.com/ppus/service_downloads.html Which does up to six layers and and has no pin limit or board size limit. Ken www.claymore-electronic.co.ukArticle: 85283
Gabor wrote: > > Sylvain Munaut wrote: > >>>And this is what they call "low cost". I'm not angry, I'm just very tired >>>of having more and more problems to get the FPGAs I need. As far as I know >>>XC3S4000 costs around 150$ for "small" quantities, I don't think it has to >>>be considered a high-end device. >> >>Doh who told you that ? >>I bought like 10 of XC3S400 FT256 for <30$ piece >> >> >> Sylvain > > > Count the zeroes... > Oh ... ;)Article: 85284
Specify a new section for your variables, and add this section to your
linker script with the fixed address.
E.g.:
int fixed_data __attribute__ ((section ("YOURSECTION"))) = 0;
Article: 85285Rick, Sorry the only thing for *assembly language* is to study the instruction set reference for each, which is published with each processor's documentation. I think if anything going to Nios II would be a bit more simple as it is closer to 'standard' style RISC... no register windows or corresoponding instructions to worry about. Jesse Kempa Altera jkempa -at- altera -dot- comArticle: 85286
The 'service pack 7_1_01' is a update for the EDK 7.1 I think. But I'm sure when you want EDK 7.1 you must buy it. It not possible update EDK 6.3 with EDK 7.1 without pay somethink.Article: 85287
I tried both ISE/EDK 7.1 and 6.3 (all with latest service pack, but tested very quicly), and I'm having some problems with 7.1. For example, a Microblaze design that fit in 6.3 doesn't fit as tight in 7.1. Moreover, I'm using Spartan-3 (FG456, speed: -4) with 66.6MHz clock, and I can't meet the timing requirement in 7.1, while 6.3 meet it. Moreover, for the same design, 6.3 give 6 level of logic in the critical path, while 7.1 give 9 levels. Also, with 7.1, when doing synthesis, I get a lot of warnings, like 'Packer: ... can not be packed with the carry due to conflict ...'. Some other warnings too. With 6.3, no such warnings. I'm currently testing on a workstation with 6.3, and I'll verify if some of the other issues I was having are there or not. Anyone having bad experience with 7.1?Article: 85288
Hi,
I'm trying to use a NIOS Kit Eval Board (Stratix10).
I would like to do a small application :
=> incr a counter value in FPGA (VHDH code)
=> convert this value Hex to Dec in FPGA (C code)
=> use NIOS (UART) to display this Dec value in IHM (SOPC, Hyperterm, ...)
I'm searching samples. Could you help me ?.
Thanks in advance.
Benoit.
Article: 85289I feel that I'm having some luck and can read from just about any register now, but can't get it to write to any. This is seeming like a voltage problem to me but I can't be sure. I've tried directly connecting 3.3 and 5v to the drives data lines and having the fpga pulse the diow while pointing to a register but no luck even with that when I tried to read back from the register I tried writing to. Any reason that shouldn't work? It complies with all the minimum timings, no max timings are listed for some stuff so I figured there are no real maximum. cs_post...@hotmail.com wrote: > 5v inputs apparently can cause damage over time. I used series > resistors to get a simple IDE interface up and running on the digilent > S3 kit a while back... don't remember the particulars, other than that > it was a couple days of frustration before I learned to talk to the > drive, but after that it went quite well. Unless you are doing one of > the really high speed modes, small resistors should not cause you > signal integrity problems. Be carefull of the polarity of some of the > control signals - some of the various writeups online can imply > misleading things. But the various microncontroller projects are good > examples for how to initialize the drive (strongly suggest LBA mode).Article: 85290
k.hopkins@btinternet.com wrote: > I use the free version of Target downloaded from > > http://www.pcbpool.com/ppus/service_downloads.html > > Which does up to six layers and and has no pin limit or board size > limit. And limits to only use pcbpool.com service...which is around same price excluding shipping/vat as here in europe including shipping/vat (o; rickArticle: 85291
Thank you for all your suggestions. I think Eagle is going to be the best choice for me, and it sounds like people have had good success with it. EricArticle: 85292
I don't know if anyone is still reading this thread, but could I ask a couple of more questions? I am using (or trying to use) the iterative CORDIC algorithm written in software. I've read Ray Andraka's paper on designing a bit serial processor, in which he writes that when considering whether or not to use a bit-serial design: "...the application for the processor must be able to tolerate any pipeline delay introduced by the serial processor. The latency in a parallel system is frequently as high or higher than the equivalent serial system so this is rarely a concern." I find this statement confusing. I thought that the advantage of the bit-parallel was that it has a much lower latency = number of iterations, while the bit-serial has a latency = word width * number of iterations. So why is the "latency in a parallel system as high or higher?" Thankyou, MeesArticle: 85293
"Chuck Bodgers" <chuck@bojit.net> schrieb im Newsbeitrag news:42a4a6d7$0$1694$ed2e19e4@ptn-nntp-reader04.plus.net... > > I need to double an input clk of 13.5mhz to 27 mhz...but the DCM core > > in xilinx can take frequencies from 24 Mhz and up only... > > Best way is PLL, but if not .... Before I would use a XOR-doubles clock inside a nowadays FPGA/CPLD for a real product (not just lab stuff), I would rather try a cheap VCO based PLL. Regards FalkArticle: 85294
Eric wrote: > What is the best FREE Schematic & PCB Layout software available that > will run on Windoze XP? > Define best. Other than that try Eagles at cadsoft.com. Works on all platforms, has a free version and an upgrade path. ianArticle: 85295
"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag news:d82bln$pse5@cliff.xsj.xilinx.com... > CLKFX must still be greater than 24 MHz, which is OK, because 13.5 X 2 = > 27 MHz. Maybe it should be noted that when using the DCM, the input clock has to match some tight jitter specification. If the 13.5 MHz clock comes from a lousy RC-oscillator, it wont work reliable. Regards FalkArticle: 85296
"Eric" <ericjohnholland@hotmail.com> schrieb im Newsbeitrag news:1118089616.876057.102010@o13g2000cwo.googlegroups.com... > I've also looked at Eagle Layout at cadsoft.de, but the size limitation > of 100 x 80mm on the free version is a negative. It would work for my > current project. Eagle is nice. I used it for a lot of homebrew stuff. There is a software called BAE, which is less limited and for only 49 Euro (AFAIK). But I did'nt use it, just heard good comments about it. Regards FalkArticle: 85297
<john.deepu@gmail.com> schrieb im Newsbeitrag news:1118147185.854541.278530@g49g2000cwa.googlegroups.com... > Hi Stephane. > I wanted to sort 48 8bit unsigned numbers Just some ideas. Hold the numbers in a BRAM. Create a small FSM to pull out the numbers, store them in a temporary register and compare. Bubble sort is usually the easiest but slowest approach in software. Maybe this is also true for an FPGA. Misc sort is fastest, so it sould be for hardware too. You could use both ports aof a BRAm to simultaneously access two pieces of data to increase speed. Regards FalkArticle: 85298
In article <3gm4uiFd4i81U2@individual.net> you wrote: : <john.deepu@gmail.com> schrieb im Newsbeitrag : news:1118147185.854541.278530@g49g2000cwa.googlegroups.com... : > Hi Stephane. : > I wanted to sort 48 8bit unsigned numbers : Just some ideas. Hold the numbers in a BRAM. Create a small FSM to pull out : the numbers, store them in a temporary register and compare. Bubble sort is : usually the easiest but slowest approach in software. Maybe this is also : true for an FPGA. Misc sort is fastest, so it sould be for hardware too. You : could use both ports aof a BRAm to simultaneously access two pieces of data : to increase speed. Bubble sort should actually be quite fast - you can store all 48 values in registers, then compare and swap if necessary odd pairs on odd clock cycles and even pairs on even cycles. After 48 cycles the registers should hold a sorted data set. Probably this aproach is about as fast as you can get? The speedup comes from the fact that many many bubble sort opperations can occour in parallel. Is this the most hardware efficient sort that runs at this speed though? If possible data should be shifted sequentially into and out of (or at least out of) the registers as a readout mux would be a resource hog. Using a Generate statement in VHDL (or equiv in Verilog) I'm guessing the sort will come to less than 100 lines of code. cheers cdsArticle: 85299
Hi, I need to add a pair of 8 bit (unsigned) integers to get a 9 bit (unsigned) result at 250 MHz, preferably in an XC3S50-4. Using the Coregen adder/subtractor V7 with maximum pipelining (9) and RPM on, the best cycle time I can get is 4.55 ns. At each pipeline level the critical path is a LUT, a MUXCY, and another LUT. Can anyone point me at some hints for a faster implementation (besides going to a faster part? TIA Paul Smith Indiana University Physics
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