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Messages from 85425

Article: 85425
Subject: Re: Available under the terms of the SignOnce IP License
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 09 Jun 2005 07:56:51 -0700
Links: << >>  << T >>  << A >>
Marco,

http://www.xilinx.com/company/sales/sales_offices.htm

For in country support (in Italian),

Italy
Via Riccardo Lombardi 19/16
20153 Milano
ITALIA
Tel: +39.02.489.229.1
Fax: +39.02.489.229.252
roberto.rosaia@xilinx.com

Austin

Article: 85426
Subject: Re: Spartan 3 Starter kit group formed
From: "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at>
Date: Thu, 9 Jun 2005 16:57:02 +0200
Links: << >>  << T >>  << A >>
> I've just formed a Yahoo group for users of the Xilinx/Digilent Spartan 3 Starter Kit:
>
> http://groups.yahoo.com/group/s3_kit
>
> It'll take a couple of days before it will show up in the group listings, but the above link should work for anyone wishing to 
> join.
>
>
Hi Leon,

a good idea. Just joined it ;-)
I think special yahoo groups are useful to not flood c.a.f with very
specific topics.

Cheers,
Martin

<ad>
I've also formed a yahoo group for Java processors, and specifically
for JOP. BTW a port of JOP for the S3K is available.

http://groups.yahoo.com/group/java-processor/

more infos on JOP at:
http://www.jopdesign.com/
</ad> 



Article: 85427
Subject: Re: Can I use a 18k ram as 2 single-port ram?
From: "Adarsh Kumar Jain" <adarsh.jain@cern.ch>
Date: Thu, 9 Jun 2005 17:04:28 +0200
Links: << >>  << T >>  << A >>
As Peter points out, by splitting the memory into 2 independent blocks,
there is no way in which you should see the problem which Vladislav
mentions, if you have done your splitting correct and the control of the
address lines is designed correctly.
i recently had to go through all this, as i had to implement a design which
needed more than the number of BRAMs i had on my Xilinx and since the size
requirements were
such that i could fit 4 of my memories into one BRAM(which would have been
great..but alas not possible...), i split all the RAMs i had, into two, in
this way.
I was also wondering if people do this with Dual Port Rams often ?
adarsh




"Peter Alfke" <alfke@sbcglobal.net> wrote in message
news:1118327246.775542.254240@f14g2000cwb.googlegroups.com...
> Vladislav, what you wrote is correct, but totally irrelevant to this
> thread.
> Once you divide the memory into two, you can do anything you want in
> the two memories.
> The problem you mention only occurs when you do NOT separate the memory
> between the two ports.
> Peter Alfke
>



Article: 85428
Subject: Re: How to convert Matlab to HDL?
From: "Jon Beniston" <jon@beniston.com>
Date: 9 Jun 2005 08:05:36 -0700
Links: << >>  << T >>  << A >>
> Hi all,
>
> Is there any tools to convert Matlab M-language to HDL? Thanks!
> 

I quite like this: http://www.pspad.com/

Cheers,
Jon


Article: 85429
Subject: Re: Lattice LFEC20 DDR SDRAM connection
From: ALuPin@web.de
Date: 9 Jun 2005 08:07:02 -0700
Links: << >>  << T >>  << A >>
For the differential clock signals you should use
dedicated clock pins.

Are you trying to design your own controller ?

Rgds
Andr=E9


Article: 85430
Subject: Re: DDR desing with FPGA
From: ALuPin@web.de
Date: 9 Jun 2005 08:09:00 -0700
Links: << >>  << T >>  << A >>
Which FPGA are you going to use ?
IP-Core or own controller ?

Rgds
Andr=E9


Article: 85431
Subject: Re: DDR desing with FPGA
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 9 Jun 2005 17:11:39 +0200
Links: << >>  << T >>  << A >>
<ALuPin@web.de> schrieb im Newsbeitrag
news:1118329740.940580.15000@g43g2000cwa.googlegroups.com...
Which FPGA are you going to use ?
IP-Core or own controller ?

Rgds
André

V4LX, DDR2 chips that decided already IP core we might to roll our own at
the end

antti



Article: 85432
Subject: Re: faster Spartan III adder
From: "John_H" <johnhandwork@mail.com>
Date: Thu, 09 Jun 2005 15:50:10 GMT
Links: << >>  << T >>  << A >>
You're getting the longer times because you're going through 2 levels of
logic.  The second LUT you mentioned will cause some grief but with proper
constraints even that might be reasonable.  Located right next to each
other, a carry chain feeding a LUT might get the timing you need but you
need to coerce the tools.

Falks's results are most definitely from a carry chain without the extra
logic level.


Or code the thing so you don't have that output level of logic.
"Paul Smith" <ptsmith@nospam.indiana.edu> wrote in message
news:d89k4c$hpl$1@rainier.uits.indiana.edu...
> Hi Falk,
>
> What temperature/voltage did you get these results at?  At 85 C and 1.14
> volts I'm getting just over 4 ns in an XC3S50-4
>
> Paul



Article: 85433
Subject: Mapping Dual Port Ram into Microblaze address space
From: "Marco" <marcotoschi_no_spam@email.it>
Date: Thu, 9 Jun 2005 18:01:53 +0200
Links: << >>  << T >>  << A >>
Hallo,
I have created a user logic template for obp bus with Create/Import Wizard 
of EDK with the feature: user logic address range support.

Into file user_logic.vhd I have created a Dual port ram with core generator 
to replace the ram example.

Is it possible to map port B of dual port ram into microblaze address space?

In this way I could use a C pointer that points to microblaze mapped address 
space.

Otherwise the only way to access it is to use Xio_in  and Xio_out ?

Many Thanks in advance to everyone
Marco

Sorry for my bad english 



Article: 85434
Subject: Re: Can I use a 18k ram as 2 single-port ram?
From: "Peter Alfke" <peter@xilinx.com>
Date: 9 Jun 2005 09:09:46 -0700
Links: << >>  << T >>  << A >>
If you like living dangerously, you can allow the full address space on
both ports, run the addresses on one port in ascending order starting
at 0, on the other port in descending order starting at max, and MAKE
SURE that the two addresses NEVER overlap...
That could even make the partition adaptive. Clever, but not for the
faint-of-heart.

Peter Alfke, Xilinx Applications


Article: 85435
Subject: execute ppc code from external ram
From: "Frank van Eijkelenburg" <someone@work.com>
Date: Thu, 9 Jun 2005 18:10:21 +0200
Links: << >>  << T >>  << A >>
We have made a memory controller which handles accesses from/to ddr sdram. A 
bootloader is running in bram and we download an application into external 
ram. The code in the external ram is exactly what we downloaded. If we jump 
to it, the powerpc starts executing from it and for some reason it comes in 
bram again (it's running the bootloader code). AFAIK there is no jump in the 
application and there was no reset.

If we use the debugger to download the application to external ram (with dow 
<file> <address>) and run the code, everything is working fine. When I built 
the application, I use the following makefile:

=======================
#################################################################
# Makefile
#################################################################

CC      = powerpc-eabi-gcc
AR      = powerpc-eabi-ar
OBJCOPY = powerpc-eabi-objcopy
OBJDUMP = powerpc-eabi-objdump


CFLAGS  = -O2 -g

SRC  = ./src
INC  = ./include

C_INC = ../include

OBJS = appl.o tl_debug.o uart.o

TOPDIR = ../ppc405_0/code
SYSTEMDIR = ../../ppc_system/ppc405_0
INCLUDEDIR = $(SYSTEMDIR)/include
LIBDIR = $(SYSTEMDIR)/lib
INCLUDES = -I$(INCLUDEDIR) -I$(INC) -I$(C_INC)
LIBS = -L$(LIBDIR) -L$(TOPDIR)

LIBRARIES =

# Linker options for the elf file
LFLAGS = -Wl,-defsym -Wl,_START_ADDR=0x00000000

VPATH = $(SRC)

appl.o   : appl.c
tl_debug.o  : tl_debug.c
uart.o   : uart.c

all:
 @echo "Makefile to build application which runs on DDR SDRAM"
 @echo "   - RAM base address: 0x00000000"
 @echo "   - application is placed in DDR SDRAM by bootloader"
 @echo ""
 @echo "Usage: make appl"

appl: $(INCLUDEDIR)/xparameters.h $(OBJS) makefile
 $(CC) $(CFLAGS) -o appl.elf $(OBJS) $(LFLAGS) $(LIBS) $(LIBRARIES)
 @echo "appl.elf created at location 0x00000000"
 @echo ""
 $(OBJDUMP) -D -b elf32-powerpc appl.elf > appl.txt
 $(OBJCOPY) -I elf32-powerpc -R .boot -R .boot0 -O binary -S appl.elf 
appl.bin

%.o:%.c
 $(CC) $(CFLAGS) -c $< -o $@ $(INCLUDES)

%.o:%.s
 $(CC) $(CFLAGS) -c $< -o $@

clean:
 rm -f $(OBJS) appl.elf appl.bin appl.txt

$(INCLUDEDIR)/xparameters.h:
 $(error Make sure you have built the libraries for the bootloader)

=======================

Do I have to use a linker file for locating different sections at the right 
place? What could be the reason for working in the debugger (gdb) and not 
working without debugger?

TIA,
Frank




Article: 85436
Subject: pcb layers on BGAs Spartan-3
From: calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid (calaf)
Date: Thu, 09 Jun 2005 11:17:34 -0500
Links: << >>  << T >>  << A >>
Hi all, I am new in this forum, and I have not found a question as the
stated below. Sorry if it has already done.  I have been designing
with Spartan-3 and as a consequence of the number of different power
suply and the pinout distribution on the board it is impossible to me
to have a very reduced number of pcb layers. Allowing for simetries
between powers and gnd layers on the stack I almost can't decrease
from ten. Is there any idea I am missing?  maybe as 2.5 V is only
used in configuration I can create islands on the 3.3V layer and
share the ground layer return between both power supply?
I think there must be something else that allow me to work effitienly
wilt fewer layers.
Thanks in advance


Article: 85437
Subject: re:How to add a lib to the core used
From: digitreaco@yahoo-dot-de.no-spam.invalid (digi)
Date: Thu, 09 Jun 2005 11:17:34 -0500
Links: << >>  << T >>  << A >>
Do you have choose .prj file in Wizard?


Article: 85438
Subject: Re: Mapping Dual Port Ram into Microblaze address space
From: "Frank van Eijkelenburg" <someone@work.com>
Date: Thu, 9 Jun 2005 18:17:45 +0200
Links: << >>  << T >>  << A >>

"Marco" <marcotoschi_no_spam@email.it> wrote in message 
news:d89oml$j4e$1@news.ngi.it...
> Hallo,
> I have created a user logic template for obp bus with Create/Import Wizard 
> of EDK with the feature: user logic address range support.
>
> Into file user_logic.vhd I have created a Dual port ram with core 
> generator to replace the ram example.
>
> Is it possible to map port B of dual port ram into microblaze address 
> space?

Yes, connect the address bits of the opb bus to your bram port. Make a state 
machine which steers the enable and write_enable and the acknowledge to the 
opb bus.

>
> In this way I could use a C pointer that points to microblaze mapped 
> address space.

Yes you can.

>
> Otherwise the only way to access it is to use Xio_in  and Xio_out ?

AFAIK, you should always be able to access your custom device by using 
pointers

>
> Many Thanks in advance to everyone
> Marco
>
> Sorry for my bad english
> 



Article: 85439
Subject: Re: faster Spartan III adder
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 9 Jun 2005 18:31:04 +0200
Links: << >>  << T >>  << A >>

"Paul Smith" <ptsmith@nospam.indiana.edu> schrieb im Newsbeitrag
news:d89k4c$hpl$1@rainier.uits.indiana.edu...
> Hi Falk,
>
> What temperature/voltage did you get these results at?  At 85 C and 1.14
> volts I'm getting just over 4 ns in an XC3S50-4

OK, my 3.5ns was with a -4 device. With -5, 85C and 1.14V its 3.98 ns. Hmm.
Maybe its better to have two adders runnung ant half the speed and MUXing
the results.

Regards
Falk




Article: 85440
Subject: Re: Spartan 3 ata interface
From: Terradestroyer@gmail.com
Date: 9 Jun 2005 09:33:41 -0700
Links: << >>  << T >>  << A >>
I actually have the spin down and spin up commands working perfectly on
most of my test drives here, so that should be a pretty good indication
I hope. Only one of the drives don't seem reliable and that is when it
is told to spin up, just keeps giving me an abort error unless I send
the command about 10 times, but the other 2 drives I have here do it
flawlessly, only ever have to send the command once.

I figured that the LBA low/mid/high and sectors could be read back when
written too, But as of right know I have only tested reading back after
writing on the one that won't spin back up without 10 or 15 commands.
The only reason that is is because it was the first drive I got
working, and then I found out that the DIOR and DIOW lines are also
inverted and that was why the other drives didn't respond. (doesn't
really explain why that one did... hmm).

Again thanx for your help, Its the little things that are hanging me up
and for me its just a really big learning experience.


Article: 85441
Subject: Re: Can I use a 18k ram as 2 single-port ram?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 9 Jun 2005 18:38:57 +0200
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag
news:1118333386.904961.64570@g43g2000cwa.googlegroups.com...
> If you like living dangerously, you can allow the full address space on
> both ports, run the addresses on one port in ascending order starting
> at 0, on the other port in descending order starting at max, and MAKE
> SURE that the two addresses NEVER overlap...
> That could even make the partition adaptive. Clever, but not for the
> faint-of-heart.

Hmm. Same risk level as every stack on every processor (unless memory
protection can avoid the stack reaching data storage places)

Regards
Falk




Article: 85442
Subject: Re: XP for NIOS2
From: kempaj@yahoo.com
Date: 9 Jun 2005 09:39:18 -0700
Links: << >>  << T >>  << A >>
Hi Piotr,

Can you kindly send me an email so I have your address? A colleague of
mine tried sending you an email to discuss the Altera university
program in more detail but the email bounced.

Jesse Kempa
jkempa --at-- altera --dot-- com


Article: 85443
Subject: Re: pcb layers on BGAs Spartan-3
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 9 Jun 2005 09:47:09 -0700
Links: << >>  << T >>  << A >>
"calaf" <calaf_calaf_calaf@yahoo-dot-es.no-spam.invalid> wrote in message
news:SfOdnUiCl8oD9jXfRVn_vg@giganews.com...
> Hi all, I am new in this forum, and I have not found a question as the
> stated below. Sorry if it has already done.  I have been designing
> with Spartan-3 and as a consequence of the number of different power
> suply and the pinout distribution on the board it is impossible to me
> to have a very reduced number of pcb layers. Allowing for simetries
> between powers and gnd layers on the stack I almost can't decrease
> from ten. Is there any idea I am missing?  maybe as 2.5 V is only
> used in configuration I can create islands on the 3.3V layer and
> share the ground layer return between both power supply?
> I think there must be something else that allow me to work effitienly
> wilt fewer layers.
> Thanks in advance
>
Without knowing what PCB technology you're using, it's impossible to say.
Here are a few questions off the top of my head.
Can you use microvias? What's your minimum track width? Minimum gap between
tracks? What's the biggest BGA package on the board? Are you prepared to
swap pins on the FPGA to aid the routing process? Is your volume enough to
make it worth spending a lot of time on the layout? How fast are your
risetimes and how long are your traces? Do you have Hyperlynx? Are you gonna
insist on a plane for each of your power supplies, or do you know what
you're doing? ;-)

256 pin BGA, 4mil tack/gap, uvias, two ground planes, routed powers,
quick(ish) turnaround, long and fast traces = 6 layers, maybe even 4 with
one ground plane if you're quite talented and have a lot of time.
Cheers, Syms.
p.s. Simetry (sic)? Pah, I spit on symmetry.



Article: 85444
Subject: Re: pcb layers on BGAs Spartan-3
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 09 Jun 2005 09:49:33 -0700
Links: << >>  << T >>  << A >>
Calaf,

See below,

Austin

calaf wrote:

> Hi all, I am new in this forum, and I have not found a question as the
> stated below. Sorry if it has already done.  I have been designing
> with Spartan-3 and as a consequence of the number of different power
> suply and the pinout distribution on the board it is impossible to me
> to have a very reduced number of pcb layers. Allowing for simetries
> between powers and gnd layers on the stack I almost can't decrease
> from ten. Is there any idea I am missing?

No.  I am sure you have looked at it carefully, and the result is that 
the pcb's are definitely more complex for the newer technologies.

   maybe as 2.5 V is only
> used in configuration I can create islands on the 3.3V layer and
> share the ground layer return between both power supply?

Vccaux is used for the DCM, the IO predrivers, and the pass gate 
regulators (for interconnect).  As such, noise on Vccaux will add to 
overall jitter.  A dedicated plane for Vccaux may be too expensive, and 
not required.  It may be shared with 2.5V IO Vcco banks, for example, 
but bypassing must be done well (see the SI web pages for pcb guidelines 
and bypassing guidelines on support.xilinx.com).

http://www.xilinx.com/products/design_resources/signal_integrity/resource/si_power.htm

Using more advanced bypass capacitors like X2Y style:

http://www.x2y.com/

or the other advanced caps:

http://www.avxcorp.com/docs/Catalogs/licc.pdf

results in less area for the caps, and better bypassing overall, and may 
allow reduced plane area, as plane C from power to ground plane is 
effective above 100 MHz, where bypass capacitors are hardly able to do 
anything at all.

> I think there must be something else that allow me to work effitienly
> wilt fewer layers.
> Thanks in advance
> 

As mentioned above, there are techniques you can use, and tradeoffs you 
can make.  Please work with your local Xilinx FAE, or Xilinx Disti FAE, 
as they have resources they can use to address the issue.  In fact, my 
FPGA Lab supports the field in their endeavours, along with other groups 
within Xilinx to provide the best solutions.

Article: 85445
Subject: Re: Motion controller design with CPLD
From: "GMM50" <george.martin@att.net>
Date: 9 Jun 2005 10:22:06 -0700
Links: << >>  << T >>  << A >>


Leeinhyuk wrote:
> Hi there
> I would like to design Motion Controller (Single axis) with Xilinx FPGA or
> CPLD.
> Please send me if you have design examples or application note.
> Best regards
> IH Lee
> leeih@chollian.net

http://www.embedded-designer.com/articles/NIOS/Designing_with_NIOS_Part_1.html

Check it out.

george


Article: 85446
Subject: Re: In-system configuration
From: "GMM50" <george.martin@att.net>
Date: 9 Jun 2005 10:22:58 -0700
Links: << >>  << T >>  << A >>
I'm do just that with Altera's FPGAs

george


Article: 85447
Subject: Re: Memory management : microblaze system
From: Paulo Dutra <paulo.dutra@NOSPAM.NOSPAM>
Date: Thu, 09 Jun 2005 10:24:44 -0700
Links: << >>  << T >>  << A >>
 From a hardware pointview, you can disable write access to the
bram_block. Ofcourse, this presumes that you have initialized your
memories with data2mem.

Essentially making your RAM a ROM. Assign the WEN port to GND.

BEGIN bram_block
  PARAMETER INSTANCE = bram1
  PARAMETER HW_VER = 1.00.a
  PORT BRAM_WEN_A = net_gnd
  PORT BRAM_WEN_B = net_gnd
  BUS_INTERFACE PORTA = opb_porta
END


fpga00@gmail.com wrote:
> hello all,
>    I have some questions related to memory management in a microblaze
> system.I am collecting some data which get from uart into a bram on the
> opb bus.I have used a pointer in my code to do this.I want a section of
> bram in which i can write this data.In other words a section of memeory
> starting from a particular addr. and size of say 32kb.I dont want any
> other data to be written in this space.I am not sure of what changes i
> am supposed to make in my linker script.Should i increase the size of
> my heap?How do i make sure that the starting addr i.e the addr. to
> which my pointer is initialized is into a safe space so that no other
> data overwrites or comes in between.??
> Please share some info. abt this.
> I am having tough time with this prob.
> thanx.
> 

Article: 85448
Subject: Re: faster Spartan III adder
From: Paul Smith <ptsmith@nospam.indiana.edu>
Date: Thu, 09 Jun 2005 13:38:06 -0500
Links: << >>  << T >>  << A >>
Hi Peter,

I'm using the coregen adder/subtractor v7 (from ISE 7.1.02i); if I tell 
it to generate an adder it seems to generate the same logic as the 
synthesis tool does from VHDL.

For a latency of 1, I get 4.186 ns for 85 C and 1.14 volts.

The critical path seems to be from input A(5) to Q(8); this seems very 
strange; I would have expected the critical path to be from A or B (0) 
to Q(8).

I'm going to try various values for the latency; I would think internal 
pipelining would speed things up.

paul

Peter Alfke wrote:

> Paul, if you want to be fast, run lean.
> You want to add, so pick an adder, not an adder/subtractor.
> This design should only take 9 or 10 LUTs, and the carry chain should
> be just combinatorial. And you don't have an active carry input to the
> LSB. So eliminate that path from the speed analysis.
> Try to get the basic functionality (without the routing) as fast as
> possible. Then apply some floorplanning.
> Peter Alfke, Xilinx.
> 

Article: 85449
Subject: Re: ispLSI1016
From: Fabio G. <7+5@supereva.it>
Date: Thu, 09 Jun 2005 18:58:39 GMT
Links: << >>  << T >>  << A >>
"learnfpga" <learnfpga@gmail.com> ha scritto:

>sorry for the trouble. i guess its because of my options. try it now.

Still have the same problem:

> - These recipients of your message have been processed by the mail server:
>learnfpga@gmail.com; Failed; 5.3.4 (message too big for system)
>
>    Remote MTA gmail-smtp-in.l.google.com: network error
>
>
> - SMTP protocol diagnostic: 552 5.7.0 Illegal Attachment 73si2893101rna

Try to send an attachment to yourself and check if you can receive it...

When you will give me a valid address I will send you the file.

However I can tell you right now that unfortunately the package I have
is for ispLever 4.0 , so maybe you will not be able to use it with isp
5.0.

Let me know what to do.

Bye

--
Per rispondermi via email sostituisci il risultato
dell'operazione (in lettere) dall'indirizzo
-*-
To reply via email write the correct sum (in letters)
in the email address



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2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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