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Austin Lesea wrote: > Vaugn, > > Page 3, lists a number of "in-rush" requirements. > > http://focus.ti.com/lit/ml/slyb113a/slyb113a.pdf > These little arguments between Altera and Xilinx can often be entertaining and informative, but sometimes they get a bit repetitive. As far as I have ever read, there has been no "in-rush" issue with Cyclone II or Stratix II devices. There apparently was some in-rush on some engineering samples, or at least there was the *possibility* of in-rush, and thus Altera had their worst-case specs set according. Altera says they don't have in-rush, and power-supply manufacturers like TI say they don't have in-rush. So could you please either drop this line of attack, or provide Altera and their users with actual evidence of this "problem" ? There are enough issues for which Xilinx chips provide a real and tangible advantage over Altera chips for you to concentrate on them - the "in-rush" claims smack of FUD, which is not becoming of you. I've also looked at the in-rush values quoted for the original Cyclone and Stratix devices (being a user of both). Frankly, it's not an issue - you'd have to have a design running under worst-case conditions and with a practically empty chip before the size of the in-rush current becomes an issue compared to the run-time current of the device. DavidArticle: 85351
Thanks for your reply, >From what you say I gather that: - CLKFX will always be delayed (from associated CLKIN edge) - The delay will be short (not likely more than 2ns) Is that correct? Thank youArticle: 85352
Hi all, is it legal to connect two INOUT ports in VHDL? If legal then what precautions we have to take to ensure proper operation (ex. some control signal to specify i/p or o/p)? ThanxArticle: 85353
a BRAM-based "software like" solution will surely be the most area efficient; anyway, for signal processing, John might need real time? here is another solution to find the MEDIAN of M values of N bits. inputs are stored in M registers. (You might want to shift them along your sampled values) design a M bits inputs, 1 bit output module. The output value is 1 if the number of ones is greater than the number of zeroes. Plug this on all MSb, the output is the MSb of the final result. Now design quite the same module, but with Mx2+1 inputs. The Mx2 are from your M values, starting with D_M(N downto N-1), the lonely input 'i' is the previous module's output. for each pair, if i=D_M(N), keep D_M(N-1) as is. if not, take not(D_M(N-1)). plug the eventually modified M bits, and plug them into a M-->1 module just like in step 1. you instanciate N-1 of such modules, and chain them. N outputs make the median value requested. for small M, you can do it in one cycle. with 48, you'll get poor performance, so you'll design a sequential counter, or pipeline the modules. If you try, give feedback, it's interresting. ------------------------------- Now consider this: the method was patented in 92 by Thomson. I don't know if it is still pending... How can they dare patent such a method for a given algorithm? Would you dare patenting for example a fast carry adder??? I think it is a weak patent (haven't checked the claims), because just an implementation of a well know algorithm, and an anteriority shall be findable. c d saunter wrote: > Falk Brunner (Falk.Brunner@gmx.de) wrote: > : "c d saunter" <christopher.saunter@durham.ac.uk> schrieb im Newsbeitrag > : news:d84pvd$5pu$1@heffalump.dur.ac.uk... > > : > Bubble sort should actually be quite fast - you can store all 48 values in > : > registers, then compare and swap if necessary odd pairs on odd clock > : cycles > : > and even pairs on even cycles. After 48 cycles the registers should hold > : > a sorted data set. > > : This sounds like a almost full parallel approach. Could be quite fast, but > : also quite resouce hungry. > > Yup. Unless the OP posts some details about desired performance it's impossible > to know which one is best... > > : Thats why a BRAM is quite handy. Using both ports you can pull two datas out > : in one cycle, compare, and write them back on a second cycle. > > Indeed. There is a nice intermediate level of parallelism availible by using > LUT RAMs to build units 16 words deep, each of which sort sequentially, with > every other set of sorts crossing the LUT RAM boundaries. This would also be > the most complicated case to code :-) > > cheers > cdsArticle: 85354
Try the following post: http://groups.google.de/group/comp.lang.vhdl/browse_thread/thread/2aba60f08c8cf41d/44cc9804aa6fdad6?q=INOUT+ALuPin&rnum=9&hl=de#44cc9804aa6fdad6 > Hi all, > is it legal to connect two INOUT ports in VHDL? If legal then what > precautions we have to take to ensure proper operation (ex. some > control signal to specify i/p or o/p)? ThanxArticle: 85355
Terradestroyer@gmail.com wrote: > I feel that I'm having some luck and can read from just about any > register now, but can't get it to write to any. This is seeming like a > voltage problem to me but I can't be sure. I've tried directly > connecting 3.3 and 5v to the drives data lines and having the fpga > pulse the diow while pointing to a register but no luck even with that > when I tried to read back from the register I tried writing to. Any > reason that shouldn't work? Are you sure the register you are writing to is readable? I don't have the spec in front of me, but in some devices write register are not readable, or return other information when read than what was written to them. If you want to see if the drive is hearing you, try sending the spin-down command ;-) Of course, that's not reliable as older drives might not support it.Article: 85356
Erik Walthinsen escreveu: > Jim Granville wrote: > >> Try mentioning this link, might hurry them along a bit... >> http://www.altera.com/buy/devices/buy-devices.html > > Except that they have '0' stock of most chips themselves. ;-( > >> Xilinx only have CPLDs here : > > As of a month ago, they listed a reasonable selection of in-stock > Spartan3 parts for prototyping work. Apparently they decided they don't > like people actually *buying* their parts. > > I'm pretty much newbie to FPGAs, but I've got in mind a decent-sized > project that needs quantity *1* of a TQ144 or PQ208 chip of no > particular size (an XC2S50 would be underutilized and running at 48MHz) > as glue between a bunch of parts. Unless I can find a way to get a part > for this project, I'll be looking at other vendors. This particular > project *could* turn into a very large-scale production, and with Xilinx > recently dropping any sales of small quantity, plus the utter inability > to get the parts anywhere else, they could very easily fall out of > consideration in my design process. If I can find an appropriate Altera > part at their store that's actually in stock, or something that Digikey > carries, I'll be going with their parts. I like Quartus better than > ISE, but I prefer ISE running on Linux... > > It's also entertaining to try to find any of the Xilinx parts that > Digikey actually *does* carry on the Xilinx site. AFAICT every part > they actually have has been discontinued long ago. > > Really pathetic, IMO. Frequently I get asked as to why I use Altera instead of Xilinx, if there's any technical reason for it. I usually get to answer that the single reason for it is that Altera parts as considerably easier to buy. You can buy it at single quantities at local stores here for the most common parts, you can buy it at farnell for a large overprice, you can buy it at arrow in single quantities and now you can buy it also at Digikey. So I have at least four places to look at when I need a pair of them. I've already tried xilinx, liked it, but couldn't buy the pieces I needed afterwards. Ricardo.Article: 85357
Falk Brunner wrote: > "Paul Smith" <ptsmith@nospam.indiana.edu> schrieb im Newsbeitrag > news:d84q4e$uga$1@rainier.uits.indiana.edu... > > >>I need to add a pair of 8 bit (unsigned) integers to get a 9 bit >>(unsigned) result at 250 MHz, preferably in an XC3S50-4. >> >>Using the Coregen adder/subtractor V7 with maximum pipelining (9) and >>RPM on, the best cycle time I can get is 4.55 ns. At each pipeline >>level the critical path is a LUT, a MUXCY, and another LUT. > > > Hmm, strange. a 8 bit adder should fit into one level of logic. make sure > both inputs are registered and placed correctly (close to the carry chain). > The output should be registerd too, of course ;-) > > OK, I did a quick test using Webpack 7.1. > > A plain description reaches 3.995 ns, uhhh tight timing ;-) > Looking at the floorplanner (after P&R) I see the mess.The registers for my > inputs are placed inside the IOBs. Not bad in general, but bad here, where > we need every fraction of a ns. So I disable the option for placing the > registers into the IOBs and run again. > BINGO! 3.5ns. > or just place post and pre-registers. or par your design as a macro. Laurent www.amontec.comArticle: 85358
hehehe guys I think I have started a pretty good discussion here. However I am not complaining because I am a novice in this field (actually a week old) and its very enlightening to read everyones point of views. Thanks a lot for your inputs.Article: 85359
Try disabling "cross-clock analysis" option, i think this one gives you this kind of warnings/errors. Vladislav "Tin-Yau Fung" <tyf@soda.csua.berkeley.edu> wrote in message news:d867i5$1v48$1@agate.berkeley.edu... > Dear all: > > I am working on Virtex2 Pro on Xilinx. In the design, > I instantiated an asynchronous fifo from coregen. The two > clock domains are entirely unrelated. Simulation sems to run > fine. However, during place and route, I keep getting timing > error from one clock domain to the other clock domain. I was > under the impression that coregen would have implicitly decouple > the two clock domains for timing. Apparently not. So, I > attempted to cut off the asyn fifo from timing analysis by > > INST "a/b/c/rxfifo" TIG; > > which according to the manual, will ignore all timng path which > passes through the instance. But it doesn't quite work. The > timing violation is within the asyn fifo itself. I have even > turned on the cross-clock analysis. The timing wizard says > I just need to separate the signals to two timing groups. > > Perhaps anyone has any insigh I imagine an asyn. fifo > is so common people must have come ccross it. > > help appreciated. > > > -- > ----------------------------------- > Tin-Yau Fung, tyf@csua.berkeley.edu > -----------------------------------Article: 85360
Hello, I'm working on a project where we utilize 2 EP1S25 Stratix Evaluation board. We have directly connected +5V, +3.3V and +1.5V onto the board and we have problems at boot, sometimes there's a card where the fpga is not programmed (LED PROG OFF), only LED D8 ON (+3.3V) do you have this problem yet or not thanks...Article: 85361
I also noticed that the fitter for ISE 7.1 isn't as efficient. I had a legacy design for an XC9500, and I called Xilinx tech support on an unrelated issue. I was using 6.3, the tech support guy used 7.1, and he couldn't fit my design to the chip. He had to install 6.3 to be able to work on it. It really does seem that the new fitter isn't as efficient.Article: 85362
Methi, You cannot use any DLL outputs, such as CLK0 and CLK2x, as they limit your lowest CLKIN to 24 MHz. Use only CLKFX or CLKFX180 outputs, NOTHING ELSE. Try this and let's know how's going. Vladislav "methi" <gmethi@gmail.com> wrote in message news:1118095629.005516.101160@g43g2000cwa.googlegroups.com... > Hello Chuck, Gabor and Austin.. > > I used both the methods...and have a 27 Mhz for both of these methods.. > > Thankyou very much for helping me out.. > > I appreciate it very much, > > Methi > > methi wrote: >> Hi Austin and Chuck, >> >> Thankyou so much for helping me out... >> >> I am goin to try using the DCM core >> >> as well the XOR circuitry( by the way, I found the diagram in one of >> the google posts) >> >> Thank you so much for your time.. >> >> I really appreciate all the help.. >> >> Methi >> >> >> >> Chuck Bodgers wrote: >> > "methi" <gmethi@gmail.com> wrote in message >> > news:1118088247.690449.312480@g43g2000cwa.googlegroups.com... >> > > Hi Chuck, >> > > >> > > Thanks for replying.. >> > > >> > > Did I get this right: >> > > >> > > Take my 13.5 and give it as one input of an XOR >> > >> > Yes >> > >> > > >> > > Take the output of the XOR1 and give it as input clk to a D-FF1 >> > >> > Yes >> > >> > > >> > > Take the output of the D-FF1 and give it as input to an inverter. >> > >> > Yes >> > >> > > >> > > Take the output of the inverter and give it as input clk to another >> > > D-FF2 >> > >> > No, take it to the D input of the DFF1 - there is only one XOR and one >> > DFF >> > in design. >> > >> > > >> > > and also as the second input of the XOR1 >> > >> > Yes >> > >> > > >> > > And the output of the XOR1 gives 27mhz >> > >> > Yes, but it does rely on your 13.5MHz input being 50% duty cycle. The >> > output >> > will be a positive pulse produced on each edge of input, the pulse >> > width >> > being a function of the prop delays on XOR/DFF and inverter. >> > > >> > >> > > Am I understanding this right? >> > > >> > I hope the above makes it clearer - a picture is worth a thousand >> > words!!!! >> > >> > Ciao for now >> > >> > Chuck >Article: 85363
Hi all, I'm getting started with QuickLogic FPGAs, and I was wondering if anyone has experience programming the QuickRAM series in-circuit via JTAG. Is this even possible? The datasheet glosses over that. They talk a lot about using an external programmer though. Is there a JTAG programming capability similar to that of Xilinx devices? All advice is appreciated. -VadimArticle: 85364
Hi all, I am searching XC3s200 or XC3s100 in TQ144 package. Please let me know if you have any stock, 20-100 pces. Email me with laurent.gauch AT amontec.com Thank you in advance, LaurentArticle: 85365
>In 20 years, HDLs will fall out of fashion and we'll have a schematic renaissance. Do you mean that in 20 years Java will fall out of fashion and we'll have a assembly renaissance?Article: 85366
Hallo, I would buy a ip core. What does it means: "Available under the terms of the SignOnce IP License" ??? Thanks MarcoArticle: 85367
Marco, sorry, could not resist... i think it means something like "no 30 days returning policy" :) V "Marco" <marcotoschi_no_spam@email.it> wrote in message news:d87161$m79$1@news.ngi.it... > Hallo, > I would buy a ip core. What does it means: "Available under the terms of > the SignOnce IP License" ??? > > Thanks > Marco >Article: 85368
Erik, The parts are not discontinued. Digikey carries them, and we still sell them. And, we still make them, too. We use our website to showcase the new products, not the old ones. Austin Erik Walthinsen wrote: > Jim Granville wrote: > >> Try mentioning this link, might hurry them along a bit... >> http://www.altera.com/buy/devices/buy-devices.html > > Except that they have '0' stock of most chips themselves. ;-( > >> Xilinx only have CPLDs here : > > As of a month ago, they listed a reasonable selection of in-stock > Spartan3 parts for prototyping work. Apparently they decided they don't > like people actually *buying* their parts. > > I'm pretty much newbie to FPGAs, but I've got in mind a decent-sized > project that needs quantity *1* of a TQ144 or PQ208 chip of no > particular size (an XC2S50 would be underutilized and running at 48MHz) > as glue between a bunch of parts. Unless I can find a way to get a part > for this project, I'll be looking at other vendors. This particular > project *could* turn into a very large-scale production, and with Xilinx > recently dropping any sales of small quantity, plus the utter inability > to get the parts anywhere else, they could very easily fall out of > consideration in my design process. If I can find an appropriate Altera > part at their store that's actually in stock, or something that Digikey > carries, I'll be going with their parts. I like Quartus better than > ISE, but I prefer ISE running on Linux... > > It's also entertaining to try to find any of the Xilinx parts that > Digikey actually *does* carry on the Xilinx site. AFAICT every part > they actually have has been discontinued long ago. > > Really pathetic, IMO.Article: 85369
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:42a61f65$1@clear.net.nz... > Comment: The inductive nature of the cross talk, suggests some > controlled capacitive crosstalk could actually help counteract/null this > > Has anyone actually tried that ? Carefull. This only "works" in a small band of resonance. Any wideband signal (NRZ data etc.) won't work with this. Iam not sure if this will work with DC balanced stuff like 8B10 either, since the bandwidth ist still 2-3 decades. Regards FalkArticle: 85370
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:42a61f65$1@clear.net.nz... > > The Altera package suffers from two issues: > > > > 1.. . Excessively fast signal rise/fall time > > For dI/dT, yes, but slower rise times make poorer eye diagrams... Yes, but you dont really want the fastest edges known to man in ALL designs. Would you build a kitchen timer using ECL? Would youl like the FPGAs spitting out 5ps (yes PICOseconds) edges, no matter whats your clock speed? I would put it the other way around. If the Xilinx edges are slower, but STILL look good in the target application (which includes stuff like 800 Mbit/s SPI4.2, 400 Mbit/s DDR-RAM etc.) why asking for more speed which is likely to cause trouble? I think there is a reason why CPLD/FPGA outputs have adjustable drive/slew parameters. And this was also long before the newest Gbit stuff form A and X was on the market. Regards FalkArticle: 85371
hello all, I have some questions related to memory management in a microblaze system.I am collecting some data which get from uart into a bram on the opb bus.I have used a pointer in my code to do this.I want a section of bram in which i can write this data.In other words a section of memeory starting from a particular addr. and size of say 32kb.I dont want any other data to be written in this space.I am not sure of what changes i am supposed to make in my linker script.Should i increase the size of my heap?How do i make sure that the starting addr i.e the addr. to which my pointer is initialized is into a safe space so that no other data overwrites or comes in between.?? Please share some info. abt this. I am having tough time with this prob. thanx.Article: 85372
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3goktmFdhal3U1@individual.net... > > "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag > news:42a61f65$1@clear.net.nz... > > > > The Altera package suffers from two issues: > > > > > > 1.. . Excessively fast signal rise/fall time > > > > For dI/dT, yes, but slower rise times make poorer eye diagrams... > > Yes, but you dont really want the fastest edges known to man in ALL designs. > Would you build a kitchen timer using ECL? > Would youl like the FPGAs spitting out 5ps (yes PICOseconds) edges, no > matter whats your clock speed? > Frankly, yes. Because FPGAs are general purpose devices, your kitchen timer is my DDR RAM controller or ultra fast sampling circuit. The faster the edges, the greater the range of applications for a given FPGA. If this means kitchen timer designers have to learn about SI, well that's the price I'm willing for them to pay! ;-) > > I would put it the other way around. If the Xilinx edges are slower, but > STILL look good in the target application (which includes stuff like 800 > Mbit/s SPI4.2, 400 Mbit/s DDR-RAM etc.) why asking for more speed which is > likely to cause trouble? I think there is a reason why CPLD/FPGA outputs > have adjustable drive/slew parameters. And this was also long before the > newest Gbit stuff form A and X was on the market. > > Regards > Falk > But, again, Altera's parts have half(ish) the rise time, which means they can cope with more applications as RAMs go faster. My point is that fast edges don't preclude any applications; crap designers do. The point Dr. Johnson was trying to spin, I mean make, is, I think, that fast edges in combination with a bad package can be unusable. True, of course. That's why you can't get new FPGAs in PLCC packages. What I dispute is whether Altera's packages are that bad at today's rise times. That said, Xilinx's package is superior in terms of ground bounce. What we need is Stratix silicon in a Xilinx package! Cheers, Syms.Article: 85373
> That's what I had in mind for the problem statement. But once the > designer is made aware of the problem, he needs some help in dealing > with it. That's where a list of recommendations would come in handy. > OK, I'll bite. How about this? 1) Group sets of I/Os common to a clock domain together in I/O banks. Minimise sharing of I/O banks between clock domains. 2) Isolate the Vccos for each of these banks. Cheers, Syms.Article: 85374
"dima2882" <vadimv@ieee.org> schrieb im Newsbeitrag news:ee8ed07.-1@webx.sUN8CHnE... > Hi all, > > I'm getting started with QuickLogic FPGAs, and I was wondering if anyone has experience programming the QuickRAM series in-circuit via JTAG. Is this even possible? The datasheet glosses over that. They talk a lot about using an external programmer though. Is there a JTAG programming capability similar to that of Xilinx devices? All advice is appreciated. > > -Vadim NO Jtag programming possible, they are not RAM or Flash devices. You really need special programmer. Antti
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