Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Symon, you wrote: "Also, in the original demo, http://www.xilinx.com/products /virtex4/pdfs/BGA_Crosstalk.pd f , I would question whether the PCB was laid out optimally, or in such a way as to accentuate the problem. Long and adjacent traces far from a ground plane would do this. There's no picture of the stackup or layout in the demo document. " We have nothing to hide. I cannot post the files for the 24-layer pc-board (12 MB) and the schematic (another MB) here in the newsgroup, but we have no hesitation to provide them to somebody who needs to know. We did all this without any devious intents. No need for it. We knew that our parts are better (and also consume less power), so we built a board, totally symmetrical, to prove it to ourselves and to others. And it does proves better signal integrity as well as lower power. Some people may not like it. But that's their problem, not ours. Peter Alfke, Xilinx ApplicationsArticle: 85326
> ALWAYS use Verilog/VHDL > NEVER use schematic capture That's kind of like saying: ALWAYS code in Java NEVER use assembly I think better advice is to use the appropriate tool for the job. Schematics have their place. In 20 years, HDLs will fall out of fashion and we'll have a schematic renaissance. These things come and go in cycles. I see a lot of bell bottom trousers lately. And there seems to be an uptick in serial "expansion busses" in personal computers. It sounds like the 1970's have returned. EricArticle: 85327
> > Simon wrote: > > So, having had something of a forced absence from FPGA's for > > a few months, I've just been looking at upgrading to 7.1 for > > both ISE and EDK. > > > > My BaseX subscription seems to have allowed me to update ISE > > to 7.1, but I can't see any way of upgrading my EDK ? > > > > Questions: > > > > 1) Is it possible to do an upgrade, or is it a question of > > re-purchasing the EDK every time there's a release ? I > > bought it in March (just checked the order :-) and I thought > > you got upgrades for a year ? > > > > 2) Will the EDK 'service pack 7_1_01' (which I do seem to have > > access to) upgrade a 6.3 version of the EDK ? > > > > 3) Am I simply being stupid and missing the blinking neon lights > > somewhere on the site saying 'Oy, it's over here'... ? > > > > Tx for any help :-) > > > > Simon > > > > digi wrote: > The 'service pack 7_1_01' is a update for the EDK 7.1 I think. > But I'm sure when you want EDK 7.1 you must buy it. It not possible > update EDK 6.3 with EDK 7.1 without pay somethink. Could someone from Xilinx please comment on whether this is true ? Cheers, Simon.Article: 85328
Besides "How" there is always the question "why". 150 mA is a lot of current, and the voltage must stay below 3.3 V. What are you really doing that you think you need this much current? Peter Alfke, Xilinx ApplictionsArticle: 85329
Peter Alfke wrote: > Jim, we described Virtex-4, which is 100% flip-chip. > This was not a history lesson on the older families, nor on TQ144 > packages :-( Quite understood. Which other family(s) are also flip-chip ? -jgArticle: 85330
Peter, No need to post the entire thing, all I'd need to know is the stack up, the length and spacing of the traces from the balls to the destination, which layer(s) the traces are on. I agree your pinout is better, let's say 5 times better. The point I'm trying to make is that if the board is laid out so Virtex parts give 50-100mV crosstalk, the Altera parts are down the loo, but if the board is laid out so the Virtex parts give 10-20mV crosstalk, things aren't nearly so bad for the Altera parts. The simple fact that the first demo used a 110 mil thick, 24 layer board suggests to me the board may not have been designed by someone experienced in the art. I'd be sacked if I did that! ;-) Anyway, I'm off down the pub with my Spectrum Analyser designer mate armed with a printout of the last demo. He's already started talking about directional coupling, I imagine I'll learn something I can post tomorrow! Cheers, Syms. "Peter Alfke" <peter@xilinx.com> wrote in message news:1118189009.319083.266220@g44g2000cwa.googlegroups.com... > Symon, you wrote: > "Also, in the original demo, > http://www.xilinx.com/products /virtex4/pdfs/BGA_Crosstalk.pd f , I > would > question whether the PCB was laid out optimally, or in such a way as to > > accentuate the problem. Long and adjacent traces far from a ground > plane > would do this. There's no picture of the stackup or layout in the demo > document. " > > We have nothing to hide. I cannot post the files for the 24-layer > pc-board (12 MB) and the schematic (another MB) here in the newsgroup, > but we have no hesitation to provide them to somebody who needs to > know. > We did all this without any devious intents. No need for it. We knew > that our parts are better (and also consume less power), so we built a > board, totally symmetrical, to prove it to ourselves and to others. And > it does proves better signal integrity as well as lower power. Some > people may not like it. But that's their problem, not ours. > > Peter Alfke, Xilinx Applications >Article: 85331
The gcc version was updated in EDK 7.1. $ mb-gcc --version mb-gcc (GCC) 3.4.1 (Xilinx EDK 7.1.1 Build EDK_H.11.3) This e-mail is my own opinion, and not an official Xilinx e-mail. Revese domain and remove the NOSPAM from the address to respond by e-mail. "Zolee" <zoltan_csizmadia@yahoo.com> wrote in message news:1118187063.078830.84550@o13g2000cwo.googlegroups.com... > mb-gcc --version -> 2.95.3-4 Xilinx EDK 6.3 > Yes, it supports anonym structs. > > ZoleeArticle: 85332
Hi all, How to write a barrel shifter in Verilog? Any easy approaches will be appreciated! Best regards, DavyArticle: 85333
Davy wrote:
> Hi all,
>
> How to write a barrel shifter in Verilog?
>
> Any easy approaches will be appreciated!
> Best regards,
> Davy
What does a barrel shifter do?
What are the inputs and the outputs that are required of a barrel shifter.
What do the Verilog >> and << operators do?
What do you get when you use a construct like {a[7:0],a[7:0]}?
And last, what do you get when you assign a larger vector to a smaller
one like
always @(posedge clk) b[3:0] <= a[7:0];
If you can answer these questions, you can build a barrel shifter.
Article: 85334Mounard, > ...by not knowing VHDL you'll be stuck > doing simple designs and will need my consulting services to do anything > remotely complex. Would you consider the Alpha processor remotely complex, or a simple design? AustinArticle: 85335
Jim Granville wrote: > Try mentioning this link, might hurry them along a bit... > http://www.altera.com/buy/devices/buy-devices.html Except that they have '0' stock of most chips themselves. ;-( > Xilinx only have CPLDs here : As of a month ago, they listed a reasonable selection of in-stock Spartan3 parts for prototyping work. Apparently they decided they don't like people actually *buying* their parts. I'm pretty much newbie to FPGAs, but I've got in mind a decent-sized project that needs quantity *1* of a TQ144 or PQ208 chip of no particular size (an XC2S50 would be underutilized and running at 48MHz) as glue between a bunch of parts. Unless I can find a way to get a part for this project, I'll be looking at other vendors. This particular project *could* turn into a very large-scale production, and with Xilinx recently dropping any sales of small quantity, plus the utter inability to get the parts anywhere else, they could very easily fall out of consideration in my design process. If I can find an appropriate Altera part at their store that's actually in stock, or something that Digikey carries, I'll be going with their parts. I like Quartus better than ISE, but I prefer ISE running on Linux... It's also entertaining to try to find any of the Xilinx parts that Digikey actually *does* carry on the Xilinx site. AFAICT every part they actually have has been discontinued long ago. Really pathetic, IMO.Article: 85336
I am using iSE6 to test a opencores project. All the files are in good order, however, when the files were added to the project, there was a "eth_registers" module which can not merge into the tree in the top project, though the instantiation and other syntax are correct. ISE indicates a missing module for "eth_registers", however the file was included in un-used file section of the project. There were no `ifdef sattement to exclude this module. ThanksArticle: 85337
Bob, I once wrote: A single-clock synchronous system can tolerate a surprising amount of ground bounce and crosstalk, since its single clock is safely parked when the outputs change, and the outputs are still stable the moment the clock changes. But give me two (or more) unrelated clocks, and the chip becomes very sensitive to ground bounce and crosstalk, for one clock domain might (i.e. will, sooner or later) change just as the other domain is in its most sensitive state. That can generate uncontrolled clocking hick-ups and other non-repetitive nasty things. Bob, was this what you had in mind? Of course no news for an experienced guy like you, but might be a valuable warning for naive beginners... Peter Alfke, XilinxArticle: 85338
Paul, if you want to be fast, run lean. You want to add, so pick an adder, not an adder/subtractor. This design should only take 9 or 10 LUTs, and the carry chain should be just combinatorial. And you don't have an active carry input to the LSB. So eliminate that path from the speed analysis. Try to get the basic functionality (without the routing) as fast as possible. Then apply some floorplanning. Peter Alfke, Xilinx.Article: 85339
Hi, Currently I have verilog design files ready for a CPLD implementation and am planning to use a Atmel AT15xx series CPLD. But I am having difficulty in finding the right Atmel development software. As per the Atmel website, Prochip supports Verilog, but when installed I am not able to compile the Verilog design. Is there any other tool I can use to get the edif file from my Verilog design and then use the edif in Prochip for fitting? Thanks SrideviArticle: 85340
For such LCDs, is the display RAM usually implemented in the LCD panel or the camera manufacturer implements that in his camera's circuit board? Thanks "Art" <plotsligt@comcast.net> wrote in message news:RMGdnR2nZbGy8jjfRVn-uw@comcast.com... > Probably need to hack it a bit and see what results you experience. Maybe > post to a "Digital Camera" N/Gs? > "Krist Neot" <Krist_Neot@hotmail.com> wrote in message > news:42a5306c$1@news.starhub.net.sg... > > In my old Olympus C900Z, it has very brilliant color display, and a > > resonable > > 240*180 resolution. When I opened it, the connectors and everything are in > > good order. Now I need to find out the connection so that I can use it in > > my > > hobby projects. Is there a standard connection for such small LCD > > displays? > > > > Thanks. > > > > > >Article: 85341
> > Success will depend on the device errata, how solid the tools are, and > > their ability to ship - [as other FPGA vendors are finding...?] > > Correct me, if I'm wrong - I have in mind, that somebody just told me that ST wants to stop their FPGA-activities? JochenArticle: 85342
"Austin Lesea" <austin@xilinx.com> wrote in message news:d84b0o$p1b3@cliff.xsj.xilinx.com... > Vaugn, > > Page 3, lists a number of "in-rush" requirements. > > http://focus.ti.com/lit/ml/slyb113a/slyb113a.pdf And lists no In-rush for Stratix II, which makes sense given that there is none. This datasheet does not yet include Cyclone II, hence it has no statement about in-rush for it. As I said earlier, there is no in-rush for Cyclone II either. > And, XPower requires you have a test bench of transistions for your > design. I suppose you worked really hard to verify that your test bench > was accurate? No, I suspected not. Maybe you designed a single 16 bit > counter in an LX60 part? Easy ways to misuse all tools. Don't bore me. Yes, we worked hard to make good test benches, and no, we didn't use a single 16-bit counter. We measured 9 designs, and compared dynamic power prediction accuracy vs. silicon. XPower had >20% error on all but 1 design, overpredicted power by up to +190%, and underpredicted by up to -90%. We used the same circuits and test benches to test the PowerAnalyzer in Quartus II, and its predictions were always within +/-20% of silicon. Vaughn [v b e t z (at) alteara.com]Article: 85343
I have built a new project with two SDRAM(each 32M) in EDK7.1i,and used the original memory test program,i find the first SDRAM test is successful,BUT the second SDRAM test has failed,Why?What is wrong with it? Any advice is appreciated!!!Article: 85344
Dear all: I am working on Virtex2 Pro on Xilinx. In the design, I instantiated an asynchronous fifo from coregen. The two clock domains are entirely unrelated. Simulation sems to run fine. However, during place and route, I keep getting timing error from one clock domain to the other clock domain. I was under the impression that coregen would have implicitly decouple the two clock domains for timing. Apparently not. So, I attempted to cut off the asyn fifo from timing analysis by INST "a/b/c/rxfifo" TIG; which according to the manual, will ignore all timng path which passes through the instance. But it doesn't quite work. The timing violation is within the asyn fifo itself. I have even turned on the cross-clock analysis. The timing wizard says I just need to separate the signals to two timing groups. Perhaps anyone has any insigh I imagine an asyn. fifo is so common people must have come ccross it. help appreciated. -- ----------------------------------- Tin-Yau Fung, tyf@csua.berkeley.edu -----------------------------------Article: 85345
Peter - On 7 Jun 2005 20:48:38 -0700, "Peter Alfke" <alfke@sbcglobal.net> wrote: >Bob, I once wrote: > >A single-clock synchronous system can tolerate a surprising amount of >ground bounce and crosstalk, since its single clock is safely parked >when the outputs change, and the outputs are still stable the moment >the clock changes. >But give me two (or more) unrelated clocks, and the chip becomes very >sensitive to ground bounce and crosstalk, for one clock domain might >(i.e. will, sooner or later) change just as the other domain is in its >most sensitive state. That can generate uncontrolled clocking hick-ups >and other non-repetitive nasty things. > >Bob, was this what you had in mind? Of course no news for an >experienced guy like you, but might be a valuable warning for naive >beginners... That's what I had in mind for the problem statement. But once the designer is made aware of the problem, he needs some help in dealing with it. That's where a list of recommendations would come in handy. Bob Perlman Cambrian Design WorksArticle: 85346
What does multiplying by 10 do? 1000? 0.01? Cheers, Syms. "Davy" <zhushenli@gmail.com> wrote in message news:1118197939.765788.144340@g14g2000cwa.googlegroups.com... > Hi all, > > How to write a barrel shifter in Verilog? > > Any easy approaches will be appreciated! > Best regards, > Davy >Article: 85347
Jochen wrote: >>>Success will depend on the device errata, how solid the tools are, and >>>their ability to ship - [as other FPGA vendors are finding...?] >>> > > > Correct me, if I'm wrong - > I have in mind, that somebody just told me > that ST wants to stop their FPGA-activities? ST had a number of parallel efforts - they have licensed FPGA cores, and also were pushing a open-source path as well. It is the open-source effort that has been 'redeployed', and the winner was a licensed/stable/proven design which is what is used in these GreenField chips. In these, the FPGA does not need to be cutting edge, just mainstream. All the Ethernet/UARTS/HDLC/Timers/DSP/CPU/DRAM are hard coded, so the FPGA can be smaller, and covers all the IO/Datapump one may need. See http://www.us.design-reuse.com/news/news10239.html -jgArticle: 85348
john.deepu@gmail.com schrieb: > I wanted to sort 48 8bit unsigned numbers > As others suggested the big question is: How are you numbers presented? If you have 48 bit serial inputs that present the data MSB first you can build a systolic 48x6 array of units containing two LUTs and two registers . As each cell connects only to three neighbours it can run at extremely high clock rates. The throughput in your case is 7 words per clock. If your data arrives in words, one word at a time consider a systolic priority queue. (Similar to parallel heap sort). The simplest version has about 48x8 registers and can still run at fairly high speeds. The throughput is one word per clock. If your data is allready in RAM (on or of chip) sort as you would on a CPU. Counting sort comes to mind. In your case it uses a single BRAM and is guaranteed to complete in 256+2N clock cycles on a single BRAM port. If you use both ports the number of cycles is halved. 3.7 clock cycles per word is not much better than other sort algorithms for a small data set as yours, but the implementation of counting sort is very simple and the number of clock cycles per word will actually decrease if the number of words increases. Kolja SulimmaArticle: 85349
> Ben Joneswrote:
"vinch" <vincesusu@yahoo-dot-fr.no-spam.invalid> wrote in
message
> news:KvednQrWrplsyjjfRVn_vg@giganews.com...
> At the end of the first page, -9/4 is translated in binary in a
> strange way.
> First, 9 is 1001 in unsigned, but -9 doesn't exist in signd binary
as
> far as I can remember....
> in the datasheet :
> -9/4=9/-4=-(2 1/4)
> this corresponds to :
> (1)0111/0100 or 1001/1100
> isn't that wrong ?
>
Well, 10111 would be -9 in 5-bit binary, so it depends what you mean
by
"wrong". "Sloppy" might be a better word. I think it's a red herring
though.
The point it's illustrating is that if the result of a signed division
is
negative, the quotient will always be negative (or zero). However, if
you
choose an *integer* remainder then it may differ in sign from the
quotient;
if you choose a *fractional* remainder then it will always have the
same
sign as the quotient.
Cheers,
-Ben-[/quote:2e25e143ca]
Ok cheers mate !
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z