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Threads Starting Jan 2001
28215: 01/01/01: chsw: help
28220: 01/01/01: Ben Twijnstra: Re: help
28221: 01/01/02: <blueflyer@my-deja.com>: Re: help
28219: 01/01/01: <harveytwyman@my-deja.com>: How can I design FPGA based RISC processors?
28223: 01/01/02: <khatib@ieee.org>: Free Tools and Designs
28224: 01/01/02: Jon Schneider: Jedec to tms/tdi wiggles
28225: 01/01/02: Dave Vanden Bout: Re: Jedec to tms/tdi wiggles
28226: 01/01/02: Jon Schneider: Re: Jedec to tms/tdi wiggles
28249: 01/01/03: Neil Glenn Jacobson: Re: Jedec to tms/tdi wiggles
28260: 01/01/04: Leopold Faschalek: Re: Jedec to tms/tdi wiggles
28332: 01/01/08: Klaus Falser: Re: Jedec to tms/tdi wiggles
28230: 01/01/03: Hal Murray: More than 4 clocks on VirtexE
28236: 01/01/03: Bo Petersen: 2-D DCT implementation
28338: 01/01/08: Michael Unger: Re: 2-D DCT implementation
28237: 01/01/03: <mlms@fe.up.pt>: Partial reconfiguration using jbits
28243: 01/01/03: Phil James-Roxby: Re: Partial reconfiguration using jbits
28238: 01/01/03: OSFT Inc.: Hardware Eng IV : FPGA/ASIC Design Engineer/Arch, $80 to $110, Ottawa, Large Telecom
28239: 01/01/03: OSFT Inc.: Hardware Engineer/FPGA's for Ruggedized PC/Driver Design, Excellent $$$, Toronto
28240: 01/01/03: OSFT Inc.: ASICS Design, VoIP, FPGA, $70k to $100+relocation, Ottawa
28241: 01/01/03: OSFT Inc.: IC Hardware Design, Telecom company, Ottawa, $70k to $100k+great benefits, relocation
28242: 01/01/03: OSFT Inc.: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
28244: 01/01/03: Jon Schneider: Re: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
28251: 01/01/03: M. Simon: Re: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
28247: 01/01/03: Mikhail Matusov: Fixing pins on Spartan II
28252: 01/01/03: Ray Andraka: Re: Fixing pins on Spartan II
28254: 01/01/03: John Larkin: Re: Fixing pins on Spartan II
28295: 01/01/05: Jakab Tanko: Re: Fixing pins on Spartan II
28305: 01/01/05: Ray Andraka: Re: Fixing pins on Spartan II
28312: 01/01/05: Jakab Tanko: Re: Fixing pins on Spartan II
28313: 01/01/05: eteam: Re: Fixing pins on Spartan II
28535: 01/01/16: Rick Filipkiewicz: Re: Fixing pins on Spartan II
28773: 01/01/24: Jim Watts: Re: Fixing pins on Spartan II
28781: 01/01/24: Ray Andraka: Re: Fixing pins on Spartan II
28795: 01/01/24: Andy Peters: Re: Fixing pins on Spartan II
28250: 01/01/03: <eriks@avidyne.com>: NIOS Processor soft core
28257: 01/01/04: Wolfgang Loewer: Re: NIOS Processor soft core
28253: 01/01/04: yaohan: Serial interface (urgent)
28258: 01/01/04: Jaan Sirp: Re: Serial interface (urgent)
28255: 01/01/04: valeri: FPGA starter kit recommendations
28256: 01/01/04: Wolfgang Loewer: Re: FPGA starter kit recommendations
28262: 01/01/04: Dave Vanden Bout: Re: FPGA starter kit recommendations
28322: 01/01/07: Tony Burch: Re: FPGA starter kit recommendations
28354: 01/01/09: Steve Prokosch: Re: FPGA starter kit recommendations
28361: 01/01/10: Leon Heller: Re: FPGA starter kit recommendations
28259: 01/01/04: <hirsch_yoav@hotmail.com>: XILINX SRL16E - FIFO
28265: 01/01/04: Ray Andraka: Re: XILINX SRL16E - FIFO
28287: 01/01/05: <hirsch_yoav@my-deja.com>: Re: XILINX SRL16E - FIFO
28306: 01/01/05: Ray Andraka: Re: XILINX SRL16E - FIFO
28263: 01/01/04: <felix_bertram@my-deja.com>: Spartan-II DLL Usage
28266: 01/01/04: Austin Lesea: Re: Spartan-II DLL Usage
28292: 01/01/05: Hal Murray: Re: Spartan-II DLL Usage
28299: 01/01/05: <felix_bertram@my-deja.com>: Re: Spartan-II DLL Usage
28308: 01/01/05: Austin Lesea: Re: Spartan-II DLL Usage
28316: 01/01/06: Hal Murray: Re: Spartan-II DLL Usage
28333: 01/01/08: Nial Stewart: Re: Spartan-II DLL Usage
28307: 01/01/05: Austin Lesea: Re: Spartan-II DLL Usage
28425: 01/01/12: Hal Murray: Re: Spartan-II DLL Usage
28439: 01/01/12: Austin Lesea: Re: Spartan-II DLL Usage
28478: 01/01/15: Hal Murray: Re: Spartan-II DLL Usage
28301: 01/01/05: Jaan Sirp: Re: Spartan-II DLL Usage
28337: 01/01/08: <felix_bertram@my-deja.com>: Re: Spartan-II DLL Usage
28346: 01/01/08: Ray Andraka: Re: Spartan-II DLL Usage
28348: 01/01/08: Austin Lesea: Re: Spartan-II DLL Usage
28264: 01/01/04: Lee Weston: FPGA Compiler2 question
28289: 01/01/05: Petter Gustad: Re: FPGA Compiler2 question
28267: 01/01/04: DATE 2001 University Booth: CFP: DATE2001 University Booth
28268: 01/01/04: jon: how do you design with + compile separate entity +architecture files
28269: 01/01/04: Brian Philofsky: Re: how do you design with + compile separate entity +architecture files
28270: 01/01/04: Reetinder P. S. Sidhu: Nondeterministic FSMs in hardware?
28271: 01/01/04: Peter Alfke: Re: Nondeterministic FSMs in hardware?
28276: 01/01/05: Greg Neff: Re: Nondeterministic FSMs in hardware?
28272: 01/01/04: Eric C. Fromm: Re: Nondeterministic FSMs in hardware?
28273: 01/01/04: George Coulouris: Re: Nondeterministic FSMs in hardware?
28274: 01/01/04: Eric C. Fromm: Re: Nondeterministic FSMs in hardware?
28284: 01/01/04: Joe Pfeiffer: Re: Nondeterministic FSMs in hardware?
28286: 01/01/05: Terje Mathisen: Re: Nondeterministic FSMs in hardware?
28296: 01/01/05: Eric C. Fromm: Re: Nondeterministic FSMs in hardware?
28297: 01/01/05: Del Cecchi: Re: Nondeterministic FSMs in hardware?
28314: 01/01/06: Bernd Paysan: Re: Nondeterministic FSMs in hardware?
28275: 01/01/04: Pete Smoot: Re: Nondeterministic FSMs in hardware?
28277: 01/01/04: Paul DeMone: Re: Nondeterministic FSMs in hardware?
28283: 01/01/05: <amolitor-at@visi-dot-com.com>: Re: Nondeterministic FSMs in hardware?
28291: 01/01/05: Lars Henrik Mathiesen: Re: Nondeterministic FSMs in hardware?
28293: 01/01/05: Torben AEgidius Mogensen: Re: Nondeterministic FSMs in hardware?
28445: 01/01/12: Maynard Handley: Re: Nondeterministic FSMs in hardware?
28288: 01/01/05: Dennis O'Connor: Re: Nondeterministic FSMs in hardware?
28302: 01/01/05: Greg Neff: Re: Nondeterministic FSMs in hardware?
28304: 01/01/05: Greg Pfister: Re: Nondeterministic FSMs in hardware?
28315: 01/01/05: Kelly Hall: Re: Nondeterministic FSMs in hardware?
28318: 01/01/05: Joe Pfeiffer: Re: Nondeterministic FSMs in hardware?
28334: 01/01/08: Jonathan Thornburg: Re: Nondeterministic FSMs in hardware?
28309: 01/01/05: George Coulouris: Re: Nondeterministic FSMs in hardware?
28311: 01/01/05: Greg Neff: Re: Nondeterministic FSMs in hardware?
28319: 01/01/05: Joe Pfeiffer: Re: Nondeterministic FSMs in hardware?
28278: 01/01/05: Thomas Maslen: Re: Nondeterministic FSMs in hardware?
28279: 01/01/05: Mark W Brehob: Re: Nondeterministic FSMs in hardware?
28352: 01/01/09: Jan Vorbrueggen: Re: Nondeterministic FSMs in hardware?
28281: 01/01/04: del cecchi: Re: Nondeterministic FSMs in hardware?
28282: 01/01/04: Philip Freidin: Re: Nondeterministic FSMs in hardware?
28285: 01/01/05: Jan Gray: Re: Nondeterministic FSMs in hardware?
28294: 01/01/05: Jean-Marc Bourguet: Re: Nondeterministic FSMs in hardware?
28280: 01/01/05: Ashok Mahadevan: HELP: Problem with interfacing an Altera MAX7000 device to the ISA bus
28298: 01/01/05: Kenneth Porter: Re: HELP: Problem with interfacing an Altera MAX7000 device to the ISA bus
28300: 01/01/05: Ashok Mahadevan: Re: HELP: Problem with interfacing an Altera MAX7000 device to the ISA bus
28303: 01/01/05: Kenneth Porter: Re: HELP: Problem with interfacing an Altera MAX7000 device to the ISA bus
28470: 01/01/14: <pineji@my-deja.com>: Re: HELP: Problem with interfacing an Altera MAX7000 device to the ISA bus
28290: 01/01/05: Anthony Ellis - LogicWorks: WebPack-ISE .ucf problem?
28310: 01/01/05: Arthur: Re: WebPack-ISE .ucf problem?
28340: 01/01/08: Jennifer Jenkins: Re: WebPack-ISE .ucf problem?
28317: 01/01/05: Reetinder P. S. Sidhu: Update on nondeterministic FSMs in hardware
28324: 01/01/06: Jan Gray: Re: Update on nondeterministic FSMs in hardware
28320: 01/01/06: <chillihung@i-cable.com>: rt18139.c
28321: 01/01/06: Torbjörn Stabo: Timing loops
28323: 01/01/06: luigi funes: Altera free software
28325: 01/01/07: yaohan: Re: Altera free software
28328: 01/01/07: C.Schlehaus: Re: Altera free software
28326: 01/01/06: C.Schlehaus: Re: Altera free software
28327: 01/01/07: <rajesh52@hotmail.com>: FYI: chip-guru online chip design magazine
28329: 01/01/07: <kkdeep@my-deja.com>: which fpga architecture?
28330: 01/01/07: S. Ramirez: Re: which fpga architecture?
28331: 01/01/07: B. Joshua Rosen: Xilinx of Linux Howto Updated
28335: 01/01/08: Le Mer Michel: APEX
28362: 01/01/10: S.K. Sharma: Re: APEX
28437: 01/01/12: Le Mer Michel: Re: APEX
28469: 01/01/14: <pineji@my-deja.com>: Re: APEX
28480: 01/01/15: Le Mer Michel: Re: APEX
28772: 01/01/24: Jim Watts: Re: APEX
28796: 01/01/24: Andy Peters: Re: APEX
28336: 01/01/08: I. Purnhagen: Viewlogic to Eagle and vs.
28342: 01/01/08: Duane: Re: Viewlogic to Eagle and vs.
28339: 01/01/08: <tomderham@my-deja.com>: FPGA for radar digital downconversion
28347: 01/01/08: Ray Andraka: Re: FPGA for radar digital downconversion
28350: 01/01/08: Steve W.: Re: FPGA for radar digital downconversion
28617: 01/01/18: Ken Chapman: Re: FPGA for radar digital downconversion
28629: 01/01/18: Ray Andraka: Re: FPGA for radar digital downconversion
28654: 01/01/19: <tomderham@my-deja.com>: Re: FPGA for radar digital downconversion
28341: 01/01/08: Michael Boehnel: Foundation P&R + location constraint
28536: 01/01/16: Rick Filipkiewicz: Re: Foundation P&R + location constraint
28561: 01/01/17: Michael Boehnel: Re: Foundation P&R + location constraint
28343: 01/01/08: Petter Gustad: Alliance for Linux
28344: 01/01/08: B. Joshua Rosen: Re: Alliance for Linux
28349: 01/01/08: Eric Smith: Re: Alliance for Linux
28351: 01/01/09: Petter Gustad: Re: Alliance for Linux
28365: 01/01/10: Andy Peters: Re: Alliance for Linux
28373: 01/01/10: Dennis McCrohan: Re: Alliance for Linux
28382: 01/01/11: Hal Murray: Re: Alliance for Linux
28383: 01/01/10: Duane: Re: Alliance for Linux
28388: 01/01/11: bjrosen: Re: Alliance for Linux
28418: 01/01/11: Kenneth Porter: Re: Alliance for Linux
28427: 01/01/12: bjrosen: Re: Alliance for Linux
28450: 01/01/12: Kenneth Porter: Re: Alliance for Linux
28454: 01/01/13: Simon Gornall: Re: Alliance for Linux - not a technical issue
28505: 01/01/15: Kenneth Porter: Re: Alliance for Linux - not a technical issue
28429: 01/01/12: Thomas Reinemann: Re: Alliance for Linux
28392: 01/01/11: Thomas Reinemann: Re: Alliance for Linux
28394: 01/01/11: Petter Gustad: Re: Alliance for Linux
28399: 01/01/11: <eml@riverside-machines.com.NOSPAM>: Re: Alliance for Linux
28411: 01/01/11: Andy Peters: Re: Alliance for Linux
28413: 01/01/11: Petter Gustad: Re: Alliance for Linux
28435: 01/01/12: Jamie Lokier: Re: Alliance for Linux
28449: 01/01/12: Andy Peters: Re: Alliance for Linux
28521: 01/01/16: Jamie Lokier: Re: Alliance for Linux
28590: 01/01/17: Andy Peters: Re: Alliance for Linux
28657: 01/01/19: Duane: Re: Alliance for Linux
28661: 01/01/19: Eric Smith: Re: Alliance for Linux
28345: 01/01/08: B. Joshua Rosen: Hdlmaker updated
28353: 01/01/09: Markus Dobschall: Error in Logic Simulator
28355: 01/01/09: bjrosen: Hdlmaker Updated
28356: 01/01/10: bjrosen: Re: Alliance for Linux
28358: 01/01/10: Simon Bacon: Re: Alliance for Linux
28360: 01/01/10: Georg Acher: Re: Alliance for Linux
28398: 01/01/11: Petter Gustad: Re: Alliance for Linux
28364: 01/01/10: Peter Alfke: Re: Alliance for Linux
28379: 01/01/10: Simon Gornall: Re: Alliance for Linux
28381: 01/01/10: Peter Alfke: Re: Alliance for Linux
28422: 01/01/12: Hal Murray: Re: Alliance for Linux
28393: 01/01/11: Petter Gustad: Re: Alliance for Linux
28357: 01/01/10: Bill Lenihan: grey code counters
28359: 01/01/10: Jaan Sirp: Re: grey code counters
28368: 01/01/10: Kevin Neilson: Re: grey code counters
28369: 01/01/10: Peter Alfke: Re: grey code counters
28396: 01/01/11: Wolfgang Friedrich: Re: grey code counters
28405: 01/01/11: Utku Ozcan: Re: grey code counters
28412: 01/01/11: Peter Alfke: Re: grey code counters
28415: 01/01/11: Ray Andraka: Re: grey code counters
28374: 01/01/10: Eric Smith: Re: grey code counters
28375: 01/01/10: Peter Alfke: Re: grey code counters
28378: 01/01/10: Kevin Neilson: Re: grey code counters
28387: 01/01/10: John L. Smith: Re: grey code counters
28409: 01/01/11: Peter Alfke: Re: grey code counters
28366: 01/01/10: Peter Alfke: Re: grey code counters
28385: 01/01/11: Peter Alfke: Re: grey code counters
28370: 01/01/10: Arrigo Benedetti: Re: grey code counters
28371: 01/01/10: Peter Alfke: Re: grey code counters
28384: 01/01/11: Kevin Neilson: Re: grey code counters
28389: 01/01/11: Jaan Sirp: Re: grey code counters
28390: 01/01/11: Jaan Sirp: Re: grey code counters
28391: 01/01/11: Petter Gustad: Re: grey code counters
28421: 01/01/11: Andy Peters: Re: grey code counters
28460: 01/01/13: Bill Lenihan: Re: grey code counters
28461: 01/01/14: Peter Alfke: Re: grey code counters
28496: 01/01/15: <erika_uk@my-deja.com>: Re: grey code counters
28497: 01/01/15: Peter Alfke: Re: grey code counters
28504: 01/01/15: Theron Hicks: Re: grey code counters
28513: 01/01/16: Peter Alfke: Re: grey code counters
28750: 01/01/23: Nial Stewart: Re: grey code counters
28842: 01/01/25: Rick Collins: Re: grey code counters
28913: 01/01/29: Nial Stewart: Re: grey code counters
28588: 01/01/17: Andy Peters: Re: grey code counters
28428: 01/01/12: Kent Orthner: Re: grey code counters
28434: 01/01/12: seamus: Re: grey code counters
28462: 01/01/14: bob elkind: Re: grey code counters
28463: 01/01/14: bob elkind: Re: grey code counters
28508: 01/01/15: eteam: Re: grey code counters -- BUG FIX (OOPS!)
160324: 17/11/14: <aviralmittal@gmail.com>: Re: grey code counters
160325: 17/11/14: David Brown: Re: grey code counters
28363: 01/01/10: diei-unipg-it: VIRTEX : pad location
28372: 01/01/10: Ray Andraka: Re: VIRTEX : pad location
28395: 01/01/11: Michael Boehnel: Re: VIRTEX : pad location
28367: 01/01/10: Gil Golov: Xilinx Spartan II - PQ208 Orcad symbols
28380: 01/01/10: eteam: Re: Xilinx Spartan II - PQ208 Orcad symbols
28376: 01/01/10: <sharifs@psu.edu>: Simulation File
28377: 01/01/10: ed.mccauley: Xilinx XPERT Partner seeking Senior FPGA/ASIC & HDL Engineers
28386: 01/01/11: Ed Ngai: Need some help on beginning
28400: 01/01/11: <tusunov@my-deja.com>: Re: Which Group is focusing on IC design
28401: 01/01/11: Beyond Feng: How to do simulation on Synopsys FPGA Express
28402: 01/01/11: bjrosen: Re: How to do simulation on Synopsys FPGA Express
28416: 01/01/11: Ray Andraka: Re: How to do simulation on Synopsys FPGA Express
28403: 01/01/11: Ansgar Bambynek: Re: How to do simulation on Synopsys FPGA Express
28404: 01/01/11: Jerry English: Xilinx's XST hanging
28785: 01/01/24: Jerry English: Re: Xilinx's XST hanging
28406: 01/01/11: <erika_uk@my-deja.com>: address of ram using the clk net
28410: 01/01/11: Peter Alfke: Re: address of ram using the clk net
28423: 01/01/12: <erika_uk@my-deja.com>: Re: address of ram using the clk net
28426: 01/01/12: Peter Alfke: Re: address of ram using the clk net
28420: 01/01/11: Andy Peters: Re: address of ram using the clk net
28407: 01/01/11: Christian Wiencke: Problem with Simulation of VirtexE Block SelectRAM
28444: 01/01/12: Newsbrowser: Re: Problem with Simulation of VirtexE Block SelectRAM
28408: 01/01/11: Wade D. Peterson: Latest on: WISHBONE System-on-chip (SoC) Interconnection Architecture for Portable IP Cores
28414: 01/01/11: Jamie Sanderson: CRC - from long division to XOR, how?
28417: 01/01/11: Peter Alfke: Re: CRC - from long division to XOR, how?
28419: 01/01/12: x-guy: Re: CRC - from long division to XOR, how?
28436: 01/01/12: Jamie Sanderson: Re: CRC - from long division to XOR, how?
28448: 01/01/12: <eml@riverside-machines.com.NOSPAM>: Re: CRC - from long division to XOR, how?
28501: 01/01/15: Jamie Sanderson: Re: CRC - from long division to XOR, how?
28503: 01/01/15: Phil Short: Re: CRC - from long division to XOR, how?
28571: 01/01/17: <eml@riverside-machines.com.NOSPAM>: Re: CRC - from long division to XOR, how?
28591: 01/01/17: Phil Short: Re: CRC - from long division to XOR, how?
28624: 01/01/18: Jamie Sanderson: Re: CRC - from long division to XOR, how?
28452: 01/01/12: Duane: Re: CRC - from long division to XOR, how?
28433: 01/01/12: <eml@riverside-machines.com.NOSPAM>: Re: CRC - from long division to XOR, how?
28424: 01/01/12: Alex Rast: JTAG configuration fails with XC95144XL
28446: 01/01/12: Petter Gustad: Re: JTAG configuration fails with XC95144XL
28486: 01/01/15: David Hawke: Re: JTAG configuration fails with XC95144XL
28430: 01/01/12: Meta Fernando: APEX20K multi-device configuration
28443: 01/01/12: eteam: Re: APEX20K multi-device configuration
28431: 01/01/12: Martin.J Thompson: Re: Altera free software
28432: 01/01/12: Simon Fielder: SRAM fpga cell
28442: 01/01/12: Peter Alfke: Re: SRAM fpga cell
29725: 01/03/06: Bedrich Pola: Re: SRAM fpga cell
29727: 01/03/06: Tim Boescke: Re: SRAM fpga cell
29750: 01/03/07: Utku Ozcan: Re: SRAM fpga cell
29754: 01/03/07: Austin Lesea: Re: SRAM fpga cell
29763: 01/03/08: Keith R. Williams: Re: SRAM fpga cell
29767: 01/03/08: Austin Lesea: Re: SRAM fpga cell
29823: 01/03/12: Utku Ozcan: Re: SRAM fpga cell
29810: 01/03/12: Peter Alfke: Re: SRAM fpga cell
31110: 01/05/11: Vivek Sood: Re: SRAM fpga cell
31118: 01/05/12: Falk Brunner: Re: SRAM fpga cell
31120: 01/05/12: Rick Filipkiewicz: Re: SRAM fpga cell
31134: 01/05/12: Falk Brunner: Re: SRAM fpga cell
31200: 01/05/14: Peter Alfke: Re: SRAM fpga cell
31201: 01/05/15: Kolja Sulimma: Re: SRAM fpga cell
31228: 01/05/16: glen herrmannsfeldt: Re: SRAM fpga cell
31231: 01/05/16: Allan Herriman: Re: SRAM fpga cell
31240: 01/05/16: Rick Filipkiewicz: Re: SRAM fpga cell
31250: 01/05/16: Peter Alfke: Re: SRAM fpga cell
31265: 01/05/16: Rick Filipkiewicz: Re: SRAM fpga cell
31301: 01/05/17: glen herrmannsfeldt: Re: SRAM fpga cell
28438: 01/01/12: Sven Fleck: Stereo vision on Virtex
28440: 01/01/12: Steven Derrien: Re: Stereo vision on Virtex
28532: 01/01/16: Sven Fleck: Re: Stereo vision on Virtex
28568: 01/01/17: Steven Derrien: Re: Stereo vision on Virtex
28441: 01/01/12: Jan Gray: Re: Stereo vision on Virtex
28447: 01/01/12: Christof Paar: CHES 2001 --- 2nd CFP
28455: 01/01/13: A Al-Sabagh: Re: CHES 2001 --- 2nd CFP
28451: 01/01/12: Lawrence Peregrim: Virtex counter speed
28453: 01/01/13: Ray Andraka: Re: Virtex counter speed
28761: 01/01/23: Falk Brunner: Re: Virtex counter speed
28767: 01/01/24: Ray Andraka: Re: Virtex counter speed
28771: 01/01/24: Peter Alfke: Re: Virtex counter speed
28792: 01/01/24: Falk Brunner: Re: Virtex counter speed
28801: 01/01/24: Ray Andraka: Re: Virtex counter speed
28804: 01/01/24: Falk Brunner: Re: Virtex counter speed
28805: 01/01/24: Ray Andraka: Re: Virtex counter speed
28579: 01/01/17: Peter Alfke: Re: Virtex counter speed
28456: 01/01/13: Changeun: I wanna Model Sim cracked
28459: 01/01/13: Ray Andraka: Re: I wanna Model Sim cracked
28464: 01/01/14: Christoph Hauzeneder: Re: I wanna Model Sim cracked
28587: 01/01/17: Andy Peters: Re: I wanna Model Sim cracked
28465: 01/01/14: bjrosen: Re: I wanna Model Sim cracked
28457: 01/01/13: Malcolm Reeves: ANN: Test Bench tool V2.01 - powerful and cheap
28458: 01/01/13: an: Altera and LVDS
28466: 01/01/14: <ppetener@my-deja.com>: IDS 6.0 - FPGA Compiler Problem
28483: 01/01/15: Ulf Samuelsson: Re: IDS 6.0 - FPGA Compiler Problem
28467: 01/01/14: <strshn99@my-deja.com>: Please explain these terms
28474: 01/01/14: Eric Smith: Re: Please explain these terms
28516: 01/01/16: Extern: Re: Please explain these terms
28468: 01/01/14: <strshn99@my-deja.com>: revision control tools ??
28475: 01/01/14: Eric Smith: Re: revision control tools ??
28484: 01/01/15: Hamish Moffatt VK3SB: Re: revision control tools ??
28488: 01/01/15: Jan Vermaete: Re: revision control tools ??
28515: 01/01/16: Hamish Moffatt VK3SB: Re: revision control tools ??
28548: 01/01/16: Eric Smith: Re: revision control tools ??
28557: 01/01/17: Steve O'Hara-Smith: Re: revision control tools ??
28612: 01/01/18: Hamish Moffatt VK3SB: Re: revision control tools ??
28565: 01/01/17: Hamish Moffatt VK3SB: Re: revision control tools ??
28567: 01/01/17: Petter Gustad: Re: revision control tools ??
28502: 01/01/15: Petter Gustad: Re: revision control tools ??
28522: 01/01/16: Jamie Lokier: Re: revision control tools ??
28534: 01/01/16: Berni Joss: Re: revision control tools ??
28570: 01/01/17: <eml@riverside-machines.com.NOSPAM>: Re: revision control tools ??
28573: 01/01/17: Rick Filipkiewicz: Re: revision control tools ??
28574: 01/01/17: Petter Gustad: Re: revision control tools ??
28614: 01/01/18: Paul Campbell: Re: revision control tools ??
28615: 01/01/18: <eml@riverside-machines.com.NOSPAM>: Re: revision control tools ??
28626: 01/01/18: Jamie Sanderson: Re: revision control tools ??
28633: 01/01/18: <eml@riverside-machines.com.NOSPAM>: Re: revision control tools ??
28635: 01/01/18: Martin Darwin: Re: revision control tools ??
28645: 01/01/19: Jamie Sanderson: Re: revision control tools ??
28674: 01/01/20: Petter Gustad: Re: revision control tools ??
28602: 01/01/17: Eric Smith: Re: revision control tools ??
28625: 01/01/18: Christof Abt: Re: revision control tools ??
28627: 01/01/18: Doug Hillmer: Re: revision control tools ??
28655: 01/01/19: Doug Hillmer: Re: revision control tools ??
28634: 01/01/18: Chris G. Schneider: Re: revision control tools ??
28476: 01/01/14: chsw: Synplify Pro6.13
28479: 01/01/15: Arnd Sluiter: Re: Synplify Pro6.13
28585: 01/01/17: Andy Peters: Re: Synplify Pro6.13
28477: 01/01/14: William Andrew Publishing: Great New Electronics Book
28481: 01/01/15: chsw: fifo
28494: 01/01/15: Ray Andraka: Re: fifo
28482: 01/01/15: Juan Antonio =?iso-8859-1?Q?G=F3mez?= Pulido: Looking for prototyping board
28485: 01/01/15: =?iso-8859-1?Q?J=F6rg?= Ritter: Re: Looking for prototyping board
28493: 01/01/15: Ray Andraka: Re: Looking for prototyping board
28499: 01/01/15: David Dye: Re: Looking for prototyping board
28519: 01/01/16: Henry Styles: Re: Looking for prototyping board
28533: 01/01/16: Sven Fleck: Re: Looking for prototyping board
28547: 01/01/17: S. Ramirez: Re: Looking for prototyping board
28575: 01/01/17: Manfred Kraus: Re: Looking for prototyping board
28487: 01/01/15: Lee Weston: Certify 2.2.1 question
28489: 01/01/15: <bjorn_lindegren@my-deja.com>: Spartan programming error
28540: 01/01/16: Leon Heller: Re: Spartan programming error
28589: 01/01/17: <plogic1@my-deja.com>: Re: Spartan programming error
28490: 01/01/15: Rune Baeverrud: Virtex-II officially launched
28491: 01/01/15: <erika_uk@my-deja.com>: Re: Virtex-II officially launched
28492: 01/01/15: Austin Lesea: Re: Virtex-II officially launched
28584: 01/01/17: Andy Peters: Re: Virtex-II officially launched
28495: 01/01/15: Ray Andraka: Re: Virtex-II officially launched
28498: 01/01/15: Peter Alfke: Re: Virtex-II officially launched
28506: 01/01/16: Jim Granville: Re: Virtex-II officially launched
28510: 01/01/15: Peter Alfke: Re: Virtex-II officially launched
28511: 01/01/15: Austin Lesea: Re: Virtex-II officially launched
28509: 01/01/16: Allan Herriman: Re: Virtex-II officially launched
28703: 01/01/21: Austin Lesea: Re: Virtex-II officially launched
28714: 01/01/22: Ray Andraka: Re: Virtex-II officially launched
28715: 01/01/22: Austin Lesea: Re: Virtex-II officially launched
28737: 01/01/23: Allan Herriman: Re: Virtex-II officially launched
28738: 01/01/23: Ray Andraka: Re: Virtex-II officially launched
28779: 01/01/24: Ken Chapman: Re: Virtex-II officially launched
28783: 01/01/24: Ray Andraka: Re: Virtex-II officially launched
28512: 01/01/16: Bob Perlman: Re: Virtex-II officially launched
28577: 01/01/17: Austin Lesea: Re: Virtex-II officially launched
28605: 01/01/18: Bob Perlman: Re: Virtex-II officially launched
28621: 01/01/18: Peter Alfke: Re: Virtex-II officially launched
28623: 01/01/18: Bob Perlman: Re: Virtex-II officially launched
28631: 01/01/18: Andy Peters: Re: Virtex-II officially launched
28649: 01/01/19: Austin Lesea: Re: Virtex-II officially launched
28659: 01/01/20: Reinoud: Re: Virtex-II officially launched
28538: 01/01/16: Rick Filipkiewicz: Re: Virtex-II officially launched
28554: 01/01/16: Terry Hicks: Re: Virtex-II officially launched
28680: 01/01/20: Rick Collins: Re: Virtex-II officially launched
28683: 01/01/20: Peter Alfke: Re: Virtex-II officially launched
28684: 01/01/21: Rick Collins: Re: Virtex-II officially launched
28698: 01/01/21: Peter Alfke: Re: Virtex-II officially launched
28707: 01/01/22: Rick Collins: Re: Virtex-II officially launched
28723: 01/01/22: <kolja@prowokulta.org>: Re: Virtex-II officially launched
28729: 01/01/22: Austin Lesea: Re: Virtex-II officially launched
28745: 01/01/23: <kolja@prowokulta.org>: Re: Virtex-II officially launched
28746: 01/01/23: <kolja@prowokulta.org>: Re: Virtex-II officially launched
28760: 01/01/23: Lasse Langwadt Christensen: Re: Virtex-II officially launched
28766: 01/01/23: Austin Lesea: Re: Virtex-II officially launched
28776: 01/01/24: <sulimma@my-deja.com>: Re: Virtex-II officially launched
28581: 01/01/17: Newsbrowser: Re: Virtex-II officially launched
28582: 01/01/17: Peter Alfke: Re: Virtex-II officially launched
28569: 01/01/17: Gary Watson: Re: Virtex-II officially launched
28578: 01/01/17: Austin Lesea: Re: Virtex-II officially launched
28613: 01/01/18: Gary Watson: Re: Virtex-II officially launched
28618: 01/01/18: Gary Watson: Re: Virtex-II officially launched
28595: 01/01/17: Austin Lesea: Re: Virtex-II officially launched
28500: 01/01/15: Kenneth Porter: Re: Altera Jam player on SHARC
28566: 01/01/17: Steve Rencontre: Re: Altera Jam player on SHARC
28507: 01/01/15: NokioGL: http://www.datasheetlocator.com/nl
28523: 01/01/16: Jamie Lokier: Re: http://www.datasheetlocator.com/nl
28514: 01/01/16: chsw: answer
28517: 01/01/16: <karenwlead@my-deja.com>: negative borrow
28518: 01/01/16: jack: help
28520: 01/01/16: Nicolas Matringe: Xilinx UCF/ngdbuild problem
28524: 01/01/16: Utku Ozcan: Re: Xilinx UCF/ngdbuild problem
28525: 01/01/16: Nicolas Matringe: Re: Xilinx UCF/ngdbuild problem
28527: 01/01/16: Utku Ozcan: Re: Xilinx UCF/ngdbuild problem
28530: 01/01/16: Nicolas Matringe: Re: Xilinx UCF/ngdbuild problem
28539: 01/01/16: Rick Filipkiewicz: Re: Xilinx UCF/ngdbuild problem
28563: 01/01/17: Nicolas Matringe: Re: Xilinx UCF/ngdbuild problem
28576: 01/01/17: Brian Drummond: Re: Xilinx UCF/ngdbuild problem
28526: 01/01/16: Kwong Chan: How to implement a 5-variable function in a CLB?
28529: 01/01/16: Utku Ozcan: Re: How to implement a 5-variable function in a CLB?
28555: 01/01/17: Kwong Chan: Re: How to implement a 5-variable function in a CLB?
28559: 01/01/17: Utku Ozcan: Re: How to implement a 5-variable function in a CLB?
28528: 01/01/16: Utku Ozcan: Synplicity newsgroup?
28541: 01/01/16: Rick Filipkiewicz: Re: Synplicity newsgroup?
28550: 01/01/17: Muzaffer Kal: Re: Synplicity newsgroup?
28663: 01/01/19: Andrew Dauman: Re: Synplicity newsgroup?
28669: 01/01/20: Ray Andraka: Re: Synplicity newsgroup?
28670: 01/01/19: Andrew Dauman: Re: Synplicity newsgroup?
28677: 01/01/20: Jan Gray: Re: Synplicity newsgroup?
28679: 01/01/20: Muzaffer Kal: Re: Synplicity newsgroup?
28682: 01/01/20: Bill Lenihan: Re: Synplicity newsgroup?
28531: 01/01/16: Sven Fleck: testss
28537: 01/01/16: Mladen Veselic: Oscillator for FPGA - low cost
28542: 01/01/16: Peter Alfke: Re: Oscillator for FPGA - low cost
28549: 01/01/16: Eric Smith: Re: Oscillator for FPGA - low cost
28562: 01/01/17: Uwe Bonnes: Re: Oscillator for FPGA - low cost
28543: 01/01/17: Dean Armstrong: FPGA driving clock line
28544: 01/01/17: Dean Armstrong: Re: FPGA driving clock line
28545: 01/01/17: S. Ramirez: Re: FPGA driving clock line
28546: 01/01/17: Dean Armstrong: Re: FPGA driving clock line
28552: 01/01/16: Peter Alfke: Re: FPGA driving clock line
28639: 01/01/19: Hal Murray: Re: FPGA driving clock line
28553: 01/01/17: S. Ramirez: Re: FPGA driving clock line
28551: 01/01/16: Peter Alfke: Re: FPGA driving clock line
28556: 01/01/17: Hal Murray: Re: FPGA driving clock line
28593: 01/01/18: Dean Armstrong: Re: FPGA driving clock line
28558: 01/01/17: <elmoties@hotmail.com>: FSM encoding
28601: 01/01/18: Ray Andraka: Re: FSM encoding
28653: 01/01/19: Luis Yanes: Re: FSM encoding
28656: 01/01/19: Peter Alfke: Re: FSM encoding
28667: 01/01/20: Ray Andraka: Re: FSM encoding
28666: 01/01/20: Ray Andraka: Re: FSM encoding
28560: 01/01/17: <xgeorg@my-deja.com>: Rconfiguration of FPSLIC
28564: 01/01/17: Ulf Samuelsson: Re: Rconfiguration of FPSLIC
28572: 01/01/17: <erika_uk@my-deja.com>: CMOS or TTL
28580: 01/01/17: Steve Rencontre: Re: CMOS or TTL
28583: 01/01/17: <plogic1@my-deja.com>: Re: CMOS or TTL
28592: 01/01/17: Peter Alfke: Re: CMOS or TTL
28600: 01/01/18: Ray Andraka: Re: CMOS or TTL
28637: 01/01/18: rk: Re: CMOS or TTL
28638: 01/01/18: Peter Alfke: Re: CMOS or TTL
28643: 01/01/19: Keith R. Williams: Re: CMOS or TTL
28701: 01/01/21: Austin Franklin: Re: CMOS or TTL
28702: 01/01/21: Peter Alfke: Re: CMOS or TTL
28712: 01/01/22: rk: Re: CMOS or TTL
28713: 01/01/22: Austin Franklin: Re: CMOS or TTL
28586: 01/01/17: Andy Peters: Re: Computer Wizard!
28594: 01/01/17: Juan M. Rivas: About programming cables
28599: 01/01/17: John Grider: Re: About programming cables
28609: 01/01/18: Nial Stewart: Re: About programming cables
28662: 01/01/20: Rick Filipkiewicz: Re: About programming cables
28644: 01/01/19: Tomasz Nakielski: Re: About programming cables
28708: 01/01/22: Klaus Falser: Re: About programming cables
28774: 01/01/24: Jim Watts: Re: About programming cables
28681: 01/01/20: Bill Lenihan: Re: About programming cables
28596: 01/01/17: <karenwlead@my-deja.com>: back-annotation is not possible
28597: 01/01/18: Chuck Woodring: spartanII chip availability
28598: 01/01/17: Peter Alfke: Re: spartanII chip availability
28642: 01/01/19: Ulf Samuelsson: Re: spartanII chip availability
28664: 01/01/20: Ray Andraka: Re: spartanII chip availability
28726: 01/01/22: <sulimma@my-deja.com>: Re: spartanII chip availability
28603: 01/01/17: Terry Hicks: FAQ for this news group? (or What is an FPGA?)
28604: 01/01/18: Ray Andraka: Re: FAQ for this news group? (or What is an FPGA?)
28619: 01/01/18: Vikram Pasham: Re: FAQ for this news group? (or What is an FPGA?)
28606: 01/01/18: #ROBERTUS WAHENDRO ADI#: VHDL question
28632: 01/01/18: Andy Peters: Re: VHDL question
28775: 01/01/24: Jim Watts: Re: VHDL question
28607: 01/01/18: <bjorn_lindegren@my-deja.com>: DSP->FPGA development board
28610: 01/01/18: Dirk Kautz: Re: DSP->FPGA development board
28616: 01/01/18: <plogic1@my-deja.com>: Re: DSP->FPGA development board
28678: 01/01/20: Rick Collins: Re: DSP->FPGA development board
28608: 01/01/18: <bjorn_lindegren@my-deja.com>: Development board, DSP->FPGA
28611: 01/01/18: Chai Mee Joon: WTB: Virtex-based board
28895: 01/01/27: Edward L. Hepler: Leonardo -> Xilinx Alliance 3.1i
28896: 01/01/27: Edward L. Hepler: Re: Leonardo -> Xilinx Alliance 3.1i
28620: 01/01/18: <kkdeep@my-deja.com>: what placement and route tool?
28733: 01/01/22: Ashok Chotai: Re: what placement and route tool?
28622: 01/01/18: Paul Wiercienski: fpga-cpu-subscribe @egroups.com
28628: 01/01/18: Michael Boehnel: Tool to partially, dynamically reconfigure Virtex?
28630: 01/01/18: Chris G. Schneider: Best design for asyn. interface DSP <-> FPGA?
28636: 01/01/18: Peter Alfke: Re: Best design for asyn. interface DSP <-> FPGA?
28658: 01/01/19: Chris G. Schneider: Re: Best design for asyn. interface DSP <-> FPGA?
28660: 01/01/19: Peter Alfke: Re: Best design for asyn. interface DSP <-> FPGA?
28668: 01/01/20: Ray Andraka: Re: Best design for asyn. interface DSP <-> FPGA?
28675: 01/01/20: Chris G. Schneider: Re: Best design for asyn. interface DSP <-> FPGA?
28640: 01/01/19: Manfred Kraus: Re: Best design for asyn. interface DSP <-> FPGA?
28641: 01/01/19: <xgeorg@my-deja.com>: Reconfiguration of Armel fpga
28646: 01/01/19: Lars Rzymianowicz: problem with Xilinx CORE Generator
28647: 01/01/19: Juan M. Rivas: About JTAG
28685: 01/01/21: Alain Cloet: Re: About JTAG
28648: 01/01/19: <pawel5732@my-deja.com>: FPGAs with a partial reconfiguration
28650: 01/01/19: Phil James-Roxby: Re: FPGAs with a partial reconfiguration
28651: 01/01/19: Austin Lesea: Re: FPGAs with a partial reconfiguration
28665: 01/01/20: Ray Andraka: Re: FPGAs with a partial reconfiguration
28673: 01/01/20: Pawel: Re: FPGAs with a partial reconfiguration
28716: 01/01/22: Ulf Samuelsson: Re: FPGAs with a partial reconfiguration
28740: 01/01/23: Ray Andraka: Re: FPGAs with a partial reconfiguration
28652: 01/01/19: Pawel: info about FPGA market?
28732: 01/01/22: Ashok Chotai: Re: info about FPGA market?
28671: 01/01/20: Dan: How to be a more efficient productive FPGA designer ?
28672: 01/01/20: Geoffrey G. Rochat: Re: How to be a more efficient productive FPGA designer ?
28676: 01/01/20: Eugeny M. Zubok (Studio Sound, Ltd.): Clear Logic and ALTERA
28686: 01/01/21: <jms@geriatrix.circlesXXXXXquared.com>: UK parts
28690: 01/01/21: Mike H.: Re: UK parts
28692: 01/01/21: Gary Watson: Re: UK parts
28694: 01/01/21: Dan: Re: UK parts
28724: 01/01/22: <sulimma@my-deja.com>: Re: UK parts
28788: 01/01/24: Jon Schneider: Re: UK parts
28822: 01/01/25: Nial Stewart: Re: UK parts
28851: 01/01/26: Jon Schneider: Re: UK parts
28902: 01/01/28: <sulimma@my-deja.com>: Re: UK parts
28853: 01/01/26: <kolja@prowokulta.org>: Re: UK parts
28736: 01/01/22: Leon Heller: Re: UK parts
28687: 01/01/21: Ralf A. Eckhardt: xc95108 funny behaviour
28688: 01/01/21: Greg Neff: Re: xc95108 funny behaviour
28691: 01/01/21: Ralf A. Eckhardt: Re: xc95108 funny behaviour
28693: 01/01/21: Paul Taylor: Re: xc95108 funny behaviour
28705: 01/01/22: Jim Granville: Re: xc95108 funny behaviour
28717: 01/01/22: Ralf A. Eckhardt: Re: xc95108 funny behaviour
28725: 01/01/22: Greg Neff: Re: xc95108 funny behaviour
28730: 01/01/22: Ralf A. Eckhardt: Re: xc95108 funny behaviour
28689: 01/01/21: Austin Franklin: Is the Xilinx XCV200 in the FG456 package cavity UP or DOWN?
28704: 01/01/21: Austin Lesea: Re: Is the Xilinx XCV200 in the FG456 package cavity UP or DOWN?
28718: 01/01/22: Austin Lesea: Re: Is the Xilinx XCV200 in the FG456 package cavity UP or DOWN?
28735: 01/01/22: Austin Franklin: Re: Is the Xilinx XCV200 in the FG456 package cavity UP or DOWN?
28720: 01/01/22: Austin Lesea: Re: Is the Xilinx XCV200 in the FG456 package cavity UP or DOWN?
28695: 01/01/21: jam: Designing fractional counters?
28699: 01/01/21: Peter Alfke: Re: Designing fractional counters?
28709: 01/01/22: <felix_bertram@my-deja.com>: Re: Designing fractional counters?
28727: 01/01/22: <sulimma@my-deja.com>: Re: Designing fractional counters?
28752: 01/01/23: Jan Gray: Re: Designing fractional counters?
28696: 01/01/21: bjrosen: HDLmaker users guide updated
28697: 01/01/21: Dan: Firewire bus driven/received by Xilinx using LVDS
28700: 01/01/21: Peter Alfke: Re: Firewire bus driven/received by Xilinx using LVDS
28734: 01/01/22: Christoph Hauzeneder: Re: Firewire bus driven/received by Xilinx using LVDS
28706: 01/01/22: ccc: test
28710: 01/01/22: Lars Rzymianowicz: Inferring Virtex selectRAM with FC2?
28711: 01/01/22: <felix_bertram@my-deja.com>: Spartan-II CLKDLL Constraints
28719: 01/01/22: Reinoud: Re: VirtexII and high speed counter
28744: 01/01/23: Jaan Sirp: Re: VirtexII and high speed counter
28721: 01/01/22: Utku Ozcan: Verilog model of Xilinx macro in VHDL Testbench fails
28731: 01/01/22: Chris Dunlap: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28741: 01/01/23: Utku Ozcan: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28753: 01/01/23: Andy Peters: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28777: 01/01/24: Utku Ozcan: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28782: 01/01/24: Ray Andraka: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28787: 01/01/24: Utku Ozcan: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28722: 01/01/22: Theron Hicks: VirtexII and high speed counter
28843: 01/01/26: Phil Hays: Re: VirtexII and high speed counter
28728: 01/01/22: <sulimma@my-deja.com>: Low Cost Software for XC4013XL
28739: 01/01/23: Ray Andraka: Xilinx XCell is not on-line?
28754: 01/01/23: John L. Smith: Re: Xilinx XCell is not on-line?
28756: 01/01/23: Austin Lesea: Re: Xilinx XCell is not on-line?
28763: 01/01/23: Ray Andraka: Re: Xilinx XCell is not on-line?
28757: 01/01/23: Peter Alfke: Re: Xilinx XCell is not on-line?
28762: 01/01/23: Ray Andraka: Re: Xilinx XCell is not on-line?
29055: 01/02/04: <gazit@my-deja.com>: Re: Xilinx XCell is not on-line?
29333: 01/02/14: Paulo Dutra: Re: Xilinx XCell is not on-line?
28742: 01/01/23: <eric.levrault@mageos.com>: multiplier architecture
28768: 01/01/24: Ray Andraka: Re: multiplier architecture
28743: 01/01/23: bob elkind: minor bug in MAX+2 v10.0
28747: 01/01/23: <sulimma@my-deja.com>: Foundation FPGA Editor hard macros in VHDL
28847: 01/01/26: <mrandelzhofer@my-deja.com>: Re: Foundation FPGA Editor hard macros in VHDL
28852: 01/01/26: <kolja@prowokulta.org>: Re: Foundation FPGA Editor hard macros in VHDL
28879: 01/01/26: Neil Franklin: Re: Foundation FPGA Editor hard macros in VHDL
28748: 01/01/23: Filip Atanassov: Atmel ATSTK40 starter kit
28749: 01/01/23: Richard Dungan: Program Atmel CPLD with Xilinx JTAG Cable?
28751: 01/01/23: Juan M. Rivas: Can Virtex-II be programmed with MultiLINX?
28823: 01/01/25: Austin Lesea: Re: Can Virtex-II be programmed with MultiLINX?
28941: 01/01/30: Nial Stewart: Re: Can Virtex-II be programmed with MultiLINX?
28948: 01/01/30: Austin Lesea: Re: Can Virtex-II be programmed with MultiLINX?
28981: 01/02/01: Me: Re: Can Virtex-II be programmed with MultiLINX?
28985: 01/01/31: Austin Lesea: Re: Can Virtex-II be programmed with MultiLINX?
28996: 01/02/01: Rune Baeverrud: Re: Can Virtex-II be programmed with MultiLINX?
29036: 01/02/03: Me: Re: Can Virtex-II be programmed with MultiLINX?
29056: 01/02/04: Rick Filipkiewicz: Re: Can Virtex-II be programmed with MultiLINX?
29064: 01/02/04: Falk Brunner: Re: Can Virtex-II be programmed with MultiLINX?
28755: 01/01/23: Daniel Nilsson: xilinx cpld
28794: 01/01/24: Andy Peters: Re: xilinx cpld
28829: 01/01/25: Leon Heller: Re: xilinx cpld
28758: 01/01/23: Vasant Ram: Leonardo Spectrum or FPGA Express/Compiler II
28759: 01/01/23: <steve@sk-tech.com>: Foundation - Source Constraints
28793: 01/01/24: Andy Peters: Re: Foundation - Source Constraints
28918: 01/01/29: David Hawke: Re: Foundation - Source Constraints
28764: 01/01/23: cybin: Xilinx will NEVER support Linux
28769: 01/01/24: x-guy: Re: Xilinx will NEVER support Linux
28800: 01/01/24: cybin: Re: Xilinx will NEVER support Linux
28808: 01/01/24: Simon Gornall: Re: Xilinx will NEVER support Linux
28765: 01/01/23: <lkostov@my-deja.com>: Could I use IOPAD twince in the design?
28798: 01/01/24: PeteD: Re: Could I use IOPAD twince in the design?
28770: 01/01/23: M.Sivanandan: fpga: regarding startup virtex
28790: 01/01/24: Utku Ozcan: Re: fpga: regarding startup virtex
28778: 01/01/24: I. Purnhagen: ACTEL 54SX bidir IF Problem
29670: 01/03/04: Timothy R. Sloper: Re: ACTEL 54SX bidir IF Problem
28780: 01/01/24: Jens Popp: Hardware Debugger crashes with Xchecker Cable
28784: 01/01/24: <jimmy75@my-deja.com>: Advice on FPGA board.
28799: 01/01/24: Dan: Re: Advice on FPGA board.
28825: 01/01/25: Sylvia Tam: Re: Advice on FPGA board.
28828: 01/01/25: Dave Vanden Bout: Re: Advice on FPGA board.
28835: 01/01/25: <jimmy75@my-deja.com>: Re: Advice on FPGA board.
28839: 01/01/26: -ackNnak-: Re: Advice on FPGA board.
28868: 01/01/26: Ray Andraka: Re: Advice on FPGA board.
28841: 01/01/26: Pratip Mukherjee: Re: Advice on FPGA board.
28850: 01/01/26: Bill Blyth: Re: Advice on FPGA board.
28944: 01/01/30: <erika_uk@my-deja.com>: Re: Advice on FPGA board.
28945: 01/01/30: Phil James-Roxby: Re: Advice on FPGA board.
28951: 01/01/31: Pratip Mukherjee: Re: Advice on FPGA board.
28954: 01/01/31: Simon Bacon: Re: Advice on FPGA board.
28960: 01/01/31: Jamie Lokier: Re: Advice on FPGA board.
28861: 01/01/26: Dan: Re: Advice on FPGA board.
29065: 01/02/04: Dan: Re: Advice on FPGA board.
28867: 01/01/26: Chuck Woodring: Re: Advice on FPGA board.
28939: 01/01/30: Chuck Woodring: Re: Advice on FPGA board.
28786: 01/01/24: Dan: Encryption is supported in new Virtex II but.....
28789: 01/01/24: Jamie Sanderson: Re: Encryption is supported in new Virtex II but.....
28791: 01/01/24: Jon Schneider: Re: Encryption is supported in new Virtex II but.....
28802: 01/01/24: Eric Smith: Re: Encryption is supported in new Virtex II but.....
28810: 01/01/25: Dan: Re: Encryption is supported in new Virtex II but.....
28812: 01/01/24: Eric Smith: Re: Encryption is supported in new Virtex II but.....
28824: 01/01/25: Austin Lesea: Re: Encryption is supported in new Virtex II but.....
28833: 01/01/25: Andy Peters: Re: Encryption is supported in new Virtex II but.....
28905: 01/01/29: <widding@my-deja.com>: Re: Encryption is supported in new Virtex II but.....
28803: 01/01/24: Peter Alfke: Re: Encryption is supported in new Virtex II but.....
28813: 01/01/24: Ben Franchuk: Re: Encryption is supported in new Virtex II but.....
28831: 01/01/25: Simon Bacon: Re: Encryption is supported in new Virtex II but.....
28840: 01/01/26: -ackNnak-: Re: Encryption is supported in new Virtex II but.....
28826: 01/01/25: Falk Brunner: Re: Encryption is supported in new Virtex II but.....
28834: 01/01/25: Andy Peters: Re: Encryption is supported in new Virtex II but.....
29007: 01/02/01: Steve Rencontre: Re: Encryption is supported in new Virtex II but.....
28923: 01/01/29: Peter: Re: Encryption is supported in new Virtex II but.....
28928: 01/01/30: Peter Alfke: Re: Encryption is supported in new Virtex II but.....
28950: 01/01/31: Rick Filipkiewicz: Re: Encryption is supported in new Virtex II but.....
29006: 01/02/01: Steve Rencontre: Re: Encryption is supported in new Virtex II but.....
29018: 01/02/02: Peter Alfke: Re: Encryption is supported in new Virtex II but.....
29023: 01/02/02: Steve Rencontre: Re: Encryption is supported in new Virtex II but.....
29038: 01/02/02: Terry Hicks: Re: Encryption is supported in new Virtex II but.....
29039: 01/02/03: Peter Alfke: Re: Encryption is supported in new Virtex II but.....
29043: 01/02/03: Terry Hicks: sorry: Encryption is supported in new Virtex II but.....
29045: 01/02/03: Peter: Re: Encryption is supported in new Virtex II but.....
29050: 01/02/04: Jim Granville: Re: Encryption is supported in new Virtex II but.....
29054: 01/02/04: Peter Alfke: Re: Encryption is supported in new Virtex II but.....
29057: 01/02/04: Rick Collins: Re: Encryption is supported in new Virtex II but.....
29066: 01/02/04: Peter Alfke: Re: Encryption is supported in new Virtex II but.....
29067: 01/02/05: Dan: Re: Encryption is supported in new Virtex II but.....
29046: 01/02/03: David Gesswein: Re: Encryption is supported in new Virtex II but.....
28811: 01/01/24: Austin Lesea: Re: Encryption is supported in new Virtex II but.....
28818: 01/01/25: Dan: Re: Encryption is supported in new Virtex II but.....
28931: 01/01/30: Greg Neff: Re: Encryption is supported in new Virtex II but.....
28797: 01/01/24: Bob Bernatchez: Help with Boundary Scan / BSDL
28806: 01/01/24: JianyongNiu: can not start coregen
28807: 01/01/24: JianyongNiu: Re: can not start coregen
28815: 01/01/25: Rune Baeverrud: Re: can not start coregen
28855: 01/01/26: JianyongNiu: Re: can not start coregen
28897: 01/01/28: Rune Baeverrud: Re: can not start coregen
28809: 01/01/24: John Grider: Spartan-II serial vs. parallel configuration
28820: 01/01/25: Theron Hicks: Re: Spartan-II serial vs. parallel configuration
28814: 01/01/25: RDR: XC7272 vers XC9272.
28832: 01/01/25: Andy Peters: Re: XC7272 vers XC9272.
28849: 01/01/26: RDR: Re: XC7272 vers XC9272.
28816: 01/01/25: Iman SedehZadeh: how to reduce number of gates in xor reducing in crc computing?
28844: 01/01/26: Rick Collins: Re: how to reduce number of gates in xor reducing in crc computing?
28856: 01/01/26: <kolja@prowokulta.org>: Re: how to reduce number of gates in xor reducing in crc computing?
28817: 01/01/25: J.H.R. Schrader: Field Programmable Gate Array selection and task suitability
28854: 01/01/26: Cemal Coemert: Re: Field Programmable Gate Array selection and task suitability
28819: 01/01/25: Dan: How does a flip chip differ from a BGA ?
28821: 01/01/25: Jonas Thor: Re: How does a flip chip differ from a BGA ?
28830: 01/01/25: Newsbrowser: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
28846: 01/01/26: Phil Hays: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
28871: 01/01/26: Newsbrowser: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
28891: 01/01/27: Brian Drummond: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
28900: 01/01/28: Stuart Clubb: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
28917: 01/01/29: Newsbrowser: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
29159: 01/02/08: Brian Drummond: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
28836: 01/01/26: Paul Campbell: Re: looping and ranges
28860: 01/01/26: Rick Collins: Re: looping and ranges
28837: 01/01/26: yaohan: choose device
28845: 01/01/26: Saqib: CORDIC ALGORITHM
28859: 01/01/26: <frouatbi@my-deja.com>: Re: CORDIC ALGORITHM
28870: 01/01/26: Ray Andraka: Re: CORDIC ALGORITHM
28848: 01/01/26: Rick Collins: looping and ranges
28872: 01/01/26: Stephen Williams: Re: looping and ranges
28877: 01/01/26: Paul Campbell: Re: looping and ranges
28889: 01/01/27: Rick Collins: Re: looping and ranges
28887: 01/01/27: Rick Collins: Re: looping and ranges
28920: 01/01/29: Mark Curry: Re: looping and ranges
28857: 01/01/26: Seb C: mutiplier !!
28869: 01/01/26: Ray Andraka: Re: mutiplier !!
28862: 01/01/26: <net9147@yahoo.com>: 6845
28864: 01/01/26: Dan: Re: 6845
28878: 01/01/26: Reinoud: Re: 6845
28863: 01/01/26: Jamie Sanderson: RAM reset question - Xilinx Virtex
28865: 01/01/26: Philip Freidin: Re: RAM reset question - Xilinx Virtex
28881: 01/01/26: Peter Alfke: Re: RAM reset question - Xilinx Virtex
28882: 01/01/27: Jan Gray: Re: RAM reset question - Xilinx Virtex
28883: 01/01/27: Jan Gray: Re: RAM reset question - Xilinx Virtex
28873: 01/01/26: JianYong Niu: what is the best FPGA development toolkit?
28874: 01/01/26: Jan Gray: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
28875: 01/01/26: <erika_uk@my-deja.com>: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
28884: 01/01/27: Peter Alfke: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28876: 01/01/26: Ray Andraka: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28880: 01/01/26: Muzaffer Kal: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28885: 01/01/27: Ray Andraka: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28890: 01/01/27: Simon Bacon: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28892: 01/01/27: Ray Andraka: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28886: 01/01/27: Peter Alfke: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28888: 01/01/27: Ray Andraka: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28893: 01/01/27: EKC: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
28911: 01/01/29: <kolja@prowokulta.org>: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
28894: 01/01/28: <javidiaz@my-deja.com>: Standard Deviation Moving Window
28964: 01/01/31: Ray Andraka: Re: Standard Deviation Moving Window
28898: 01/01/28: Ben Franchuk: Re: Xilinx fast carry counter question
28974: 01/01/31: Ray Andraka: Re: Xilinx fast carry counter question
28899: 01/01/28: jean-francois hasson: Actel's FPGA : A54SX32A
28901: 01/01/28: Philip Freidin: Re: Actel's FPGA : A54SX32A
29669: 01/03/04: Timothy R. Sloper: Re: Actel's FPGA : A54SX32A
29678: 01/03/05: S. Ramirez: Re: Actel's FPGA : A54SX32A
29711: 01/03/06: Timothy R. Sloper: Re: Actel's FPGA : A54SX32A
29722: 01/03/06: Ray Andraka: Re: Actel's FPGA : A54SX32A
29739: 01/03/07: S. Ramirez: Re: Actel's FPGA : A54SX32A
28903: 01/01/29: <szolnoki@my-deja.com>: C2VHDL
28942: 01/01/30: Jan Kindt: Re: C2VHDL
28904: 01/01/29: Neo Wei Thiam: Is it a timing constraint problem?
28907: 01/01/29: Peter Alfke: Re: Is it a timing constraint problem?
28908: 01/01/29: Kang Liat Chuan: Re: Is it a timing constraint problem?
28916: 01/01/29: Ray Andraka: Re: Is it a timing constraint problem?
28927: 01/01/30: Kang Liat Chuan: Re: Is it a timing constraint problem?
28932: 01/01/30: Ray Andraka: Re: Is it a timing constraint problem?
28934: 01/01/30: Utku Ozcan: Re: Is it a timing constraint problem?
28906: 01/01/28: Alex Sherstuk: Q: VIRTEX experience, multipliers
28925: 01/01/29: Ray Andraka: Re: Q: VIRTEX experience, multipliers
28909: 01/01/29: Nelson Wang: compatible issue
28910: 01/01/29: Martin.J Thompson: Re: UK parts
28912: 01/01/29: noelia: set/reset
28919: 01/01/29: Andy Peters: Re: set/reset
28935: 01/01/30: noelia: Re: set/reset
28936: 01/01/30: =?iso-8859-1?Q?J=F6rg?= Ritter: Re: set/reset
28940: 01/01/30: Andy Peters: Re: set/reset
28914: 01/01/29: Jakab Tanko: Xilinx NODELAY attribute question
28915: 01/01/29: Brendan Lynskey: Re: Xilinx NODELAY attribute question
28921: 01/01/29: Mikko: Xilinx JEDEC files to SVF format
28922: 01/01/29: Rick Filipkiewicz: Re: Xilinx JEDEC files to SVF format
28924: 01/01/29: Greg Neff: Re: Xilinx JEDEC files to SVF format
28933: 01/01/30: Mikko: Re: Xilinx JEDEC files to SVF format
28957: 01/01/31: Mikko: Re: Xilinx JEDEC files to SVF format
29008: 01/02/01: Petter Gustad: Re: Xilinx JEDEC files to SVF format
28926: 01/01/30: <szoszo9@freemail.hu>: LavaLogic Forge Complier
28943: 01/01/30: David Dye: Re: LavaLogic Forge Complier
28929: 01/01/30: Marc: Clocking system with CPLD? - timing.JPG (0/1)
28938: 01/01/30: Peter Alfke: Re: Clocking system with CPLD? - timing.JPG (0/1)
28930: 01/01/30: Amy Vaughn: FPGA DESIGN ENGINEER - NORTHERN CALIFORNIA
28937: 01/01/30: Falk Brunner: Spartan 2 DLL
28946: 01/01/30: Chris G. Schneider: Re: Spartan 2 DLL
28962: 01/01/31: <felix_bertram@my-deja.com>: Re: Spartan 2 DLL
28972: 01/01/31: Simon Bacon: Re: Spartan 2 DLL
28975: 01/01/31: Falk Brunner: Re: Spartan 2 DLL
28977: 01/02/01: <serebr@my-deja.com>: Re: Spartan 2 DLL
28998: 01/02/01: Austin Lesea: Re: Spartan 2 DLL
29048: 01/02/03: Rick Collins: Re: Spartan 2 DLL
29076: 01/02/05: Austin Lesea: Re: Spartan 2 DLL
29207: 01/02/09: Austin Lesea: DLL jitter "bake-off" vs. PLL
29209: 01/02/09: Falk Brunner: Re: DLL jitter "bake-off" vs. PLL
29227: 01/02/10: Peter Alfke: Re: DLL jitter "bake-off" vs. PLL
29519: 01/02/24: Rick Collins: Re: DLL jitter "bake-off" vs. PLL
29577: 01/02/27: Ray Andraka: Re: DLL jitter "bake-off" vs. PLL
30059: 01/03/22: Rick Collins: Re: DLL jitter "bake-off" vs. PLL
30071: 01/03/22: Austin Lesea: Globals are plenty fast
30100: 01/03/23: BriMDavis: Re: Globals are plenty fast
30102: 01/03/23: Rick Collins: Re: Globals are plenty fast
29015: 01/02/01: Peter Alfke: Re: Spartan 2 DLL
28947: 01/01/30: <rajesh52@hotmail.com>: Verilog FAQ : Jan 2001
28949: 01/01/30: Pete Dudley: lvds and lvpecl differential I/O input termination on Virtex II - Whats Best?
28982: 01/02/01: Me: Re: lvds and lvpecl differential I/O input termination on Virtex II -
28953: 01/01/31: Amy Vaughn: Help Please
28955: 01/01/31: Allan Herriman: Virtex Engineering Samples timing problem
28958: 01/01/31: Philip Freidin: Re: Virtex Engineering Samples timing problem
28956: 01/01/31: Saqib: CORDI C PROCESSOR!
28963: 01/01/31: Ray Andraka: Re: CORDI C PROCESSOR!
28959: 01/01/31: <luca.haab@ascom.ch>: XILINX FPGA programming through JTAG
28967: 01/01/31: Jaan Sirp: Re: XILINX FPGA programming through JTAG
29334: 01/02/14: RADHIKA: Re: XILINX FPGA programming through JTAG
29336: 01/02/14: Chris Dunlap: Re: XILINX FPGA programming through JTAG
28961: 01/01/31: Dan K: Xilinx fast carry counter question
28965: 01/01/31: Ray Andraka: Re: Xilinx fast carry counter question
28971: 01/01/31: Peter Alfke: Re: Xilinx fast carry counter question
28966: 01/01/31: Jan Gray: Re: Xilinx fast carry counter question
28968: 01/01/31: Russell Tessier: FPGA'2001 Pre-registration deadline
28969: 01/01/31: Laurent Gauch: vector / edif format / LeonardoSpectrum
28973: 01/01/31: Simon Bacon: Re: vector / edif format / LeonardoSpectrum
29011: 01/02/01: Tim Jaynes: Re: vector / edif format / LeonardoSpectrum
28970: 01/01/31: mccarley: 64b/66b gearbox in an FPGA
28978: 01/02/01: Allan Herriman: Re: 64b/66b gearbox in an FPGA
28993: 01/02/01: <sulimma@my-deja.com>: Re: 64b/66b gearbox in an FPGA
29016: 01/02/02: Peter Alfke: Re: 64b/66b gearbox in an FPGA
29021: 01/02/02: <sulimma@my-deja.com>: Re: 64b/66b gearbox in an FPGA
28979: 01/01/31: Piggy: How to program FPGA with PROTEL? (ORCA OR2C06 serie)
29047: 01/02/03: Rick Collins: Re: How to program FPGA with PROTEL? (ORCA OR2C06 serie)
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