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"Rick Filipkiewicz" wrote in message: > Anyone know of a model of a I2C or SMB [System management bus] slave- > doesn't have to be synthesisable. > You may get a free evaluation version from DCD: DI2CM - Master I2C controller HDL IP core http://www.dcd.com.pl/english/di2cm.htm DI2CS - Slave I2C controller HDL IP core http://www.dcd.com.pl/english/di2cs.htm DI2CSB - Slave I2C controller HDL IP Core - standalone version http://www.dcd.com.pl/english/di2csb.htm Regards, Tomek.Article: 29151
Hi I guest that the Altera ByteBlaster utility can be used instead of the PROM. They use the same fpga pins. But, you should check. Michel Le Mer. STA. L.C. <cupido@mail.ua.pt> a écrit dans le message : 95t9fs$gnl$1@venus.telepac.pt... > Hello, > > I would like to find information on how to program the 7000's from > ALTERA (the old non JTAG versions) without having to buy > an expensive programmer. > I can apply a little development effort on this but I dont find the > programming > info on any of the datasheets. Does anybody > has info on this ? Or have a programming technique that doesn't require a > very $$$ programmer ? > > I would like to use a box of devices I have... if not... better get new > JTAG compliant devices rather than buying an expensive programmer. > > Please let me know to cupido@mail.ua.pt > L Cupido. > > > >Article: 29152
Chris Anderson schrieb: > > Hi, > I'm after a second hand programmer for PAL/GAL 22V10 (CE) type devices. > Anyone know where I might get one in the UK? did you ever think about ISP 22V10 ? needs no programmer (ISP) :-) but: only PLCC, higher price regards, bertram -- Bertram Geiger, bgeiger@aon.at HTL Bulme Graz-Goesting - AUSTRIAArticle: 29153
"S. Ramirez" wrote: > "Raymond Chow" <rchow@endpoints.com> wrote in message > news:arkg6.58416$9v2.1057309@quark.idirect.com... > > Hi, > > > > Has anyone done a comparison between Xilinx and Altera, especially > > on how well each do on route utilization and meeting timing requirements. > > > > I'd just tried routing a design that routed fine using XCV600E with 56% > LUT > > utilization > > and when I tried using XCV400E the router will stop with the following > > error: > > > > Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. > > > > Using target part "v400ebg432-6". > > > > Reading NGD file "u200.ngd"... > > > > Processing FMAPs... > > > > Removing unused or disabled logic... > > > > Running cover... > > > > Writing file u200.ngm... > > > > Running directed packing... > > > > Running delay-based packing... > > > > Running related packing... > > > > Running unrelated pack... > > > > EXEWRAP detected a return code of '-1073741819' from program 'map' > > > > Done: failed with exit code: 0005. > > > > -any help will be greatly appreciated > > > > -Raymond > > But the great thing about Brand X is that soon enough, a Brand X person > will pick off your error code and translate it into an answer for you. And the answer is: This is fixed in Service Pack 7, which will be available from http://www.xilinx.com/support/techsup/sw_updates/ in the next few days. Brian.Article: 29154
Hi Im working with Xilnix Virtex FPGAs and I have the following question, problem: In my design, I need to evaluate boolean functions of a large number of input signals. These signals are outputs of statemachines in the design. What I need, is a _fast_ boolean OR resp. AND operations on all of these output signals. Since there are quite a lot of output signals, say typically more than 40 signals, I need several levels of logic, when implementing this in the obivous tree-like structure with a tree of 4 Input AND/OR gates. I think this problem could also be solved by using a wired-or function, where - in the case of the OR operations - all signals either drive a line to logical '1' or go into high-impedance state 'Z'. The only additional thing I need is a pulldown resistor on this line. Does anybody know, whether a circuit like this will work and is realizable in Xilinx Virtex FPGAs? How could this be done? Im working with VHDL using Xilinx Foundation F3.1i. I would be glad for any hint. /ChrisArticle: 29155
I need a 4x multiplier and the duti cycle is i think (i'll have to check that when i receve a clock from my co worker but i think it is)Article: 29156
Hello, I would like to find information on how to program the 7000's from ALTERA (the old non JTAG versions) without having to buy an expensive programmer. I can apply a little development effort on this but I dont find the programming info on any of the datasheets. Does anybody has info on this ? Or have a programming technique that doesn't require a very $$$ programmer ? I would like to use a box of devices I have... if not... better get new JTAG compliant devices rather than buying an expensive programmer. Please let me know to cupido@mail.ua.pt L Cupido.Article: 29157
In article <9Rlg6.107958$8V6.15243012@typhoon.tampabay.rr.com>, "S. Ramirez" <sramirez@deletethis.cfl.rr.com> wrote: > "Raymond Chow" <rchow@endpoints.com> wrote in message > news:arkg6.58416$9v2.1057309@quark.idirect.com... > > Hi, > > > > Has anyone done a comparison between Xilinx and Altera, especially > > on how well each do on route utilization and meeting timing requirements. > > > > I'd just tried routing a design that routed fine using XCV600E with 56% > LUT > > utilization > > and when I tried using XCV400E the router will stop with the following > > error: > > > > Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. > > > > Using target part "v400ebg432-6". > > > > Reading NGD file "u200.ngd"... > > > > Processing FMAPs... > > > > Removing unused or disabled logic... > > > > Running cover... > > > > Writing file u200.ngm... > > > > Running directed packing... > > > > Running delay-based packing... > > > > Running related packing... > > > > Running unrelated pack... > > > > EXEWRAP detected a return code of '-1073741819' from program 'map' > > > > Done: failed with exit code: 0005. > > > > -any help will be greatly appreciated > > > > -Raymond > > Raymond, > In general and especially with certain types of functions such as > anything using carry chains, Brand X will win hands down. > But the great thing about Brand X is that soon enough, a Brand X person > will pick off your error code and translate it into an answer for you. > That's because this newsgroup is monitored by Brand X. It is even > advertised on their web site! Exactly! I didn't get the answer from support@altera on my last question even after month of waiting and second request with the reference to my first letter Service Request number (#10058499 if any). It's permanent trade-off: Xilinx provides instant and very high quality support but Altera's devices are mostly available in stock (I mean in comparison with the Spartan-II availability). > So kick back and wait for the answer. Some Brand X employee will go > research the answer by going into their code documentation and finding out > what the error means. > Would Brand A do that on this newsgroup? Yeah, I know. They dont have > access to the Xilinx code! > Simon Ramirez, Consultant > Synchronous Design, Inc. > Oviedo, FL USA > > Sent via Deja.com http://www.deja.com/Article: 29158
Hello, In a few weeks we will be starting our first PCI project, and we are going to use a Xilinx PCI core. We bought ourselfs an Insight evaluation board to get to know the PCI core, and do some testing. Since we've never done anything with the PCI bus and we don't have that much experience with FPGA desing, I'm asking for some starter-tips. We're using Ease/Eale, Leonardo Spectrum and Modelsim. Are there some "dos" and "don'ts", tips, guides... anything is welcome. Regards, H. Otten.Article: 29159
On Mon, 29 Jan 2001 16:18:59 GMT, Newsbrowser@Newsbrowser.com (Newsbrowser) wrote: >On Sun, 28 Jan 2001 16:41:45 GMT, s_clubb@NOSPAMnetcomuk.co.uk (Stuart >Clubb) wrote: > >>Memory inferencing speed has been improved hugely in release 2000.1b. I can now confirm that! Thanks, - BrianArticle: 29160
Hi! I have woked with Xilinx XC4010E and wish to get a development kit,
for prototyping, but i dont seem to find one at afair price! If you can
help-me ? thank you!
Article: 29161serebr@my-deja.com wrote: > > It's permanent trade-off: Xilinx provides instant and very high quality > support but Altera's devices are mostly available in stock > (I mean in comparison with the Spartan-II availability). > Thanks for the friendly words about Xilinx support. And regarding availability: Please don't give all of Xilinx a black eye for the very special situation with Spartan-II. We expect that to clear up very soon. Let me tell you, there is no lack of attention on this case ! Peter AlfkeArticle: 29162
Klaus Falser wrote: > Does anybody know where to find VHDL-Mode for Emacs? > > The official site should be http://www.emacs.org/hdl/vhdl-mode.html, > but www.emacs.org seams dead. It is available at a new site and I will soon announce it officially. http://opensource.ethz.ch/emacs/vhdl-mode.html RetoArticle: 29163
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Just a note on Xilinx support;- I had a problem recently with
an 4000xla type device NODELAY attribute for some critical
inputs on my design. The problem was (and still is) that the Alliance
tool refuses to implement this attribute; it is all good up to the mapper
but on the next step which is the PAR, the attribute is not there anymore.
Now, you would think that this is a pretty-strait-forward, specific problem
that should be a no-brainer for a Xilinx application engineer..
but not so fast;- after 4 days of trying to get the Xilinx support to
give me
an answer I simply gave up...It seems to me that they have a two-tier system
where you get the top-notch support if you pay for it, but if you just
"another
customer" then you get the co-op student to solve your problems and you
might as well
try to solve them yourself,
But again this is just my oppinion and I could be wrong,
jakab
Peter Alfke wrote:
>
> serebr@my-deja.com wrote:
>
>> It's permanent trade-off: Xilinx provides instant and very high quality
>> support but Altera's devices are mostly available in stock
>> (I mean in comparison with the Spartan-II availability).
>>
>
> Thanks for the friendly words about Xilinx support.
> And regarding availability:
> Please don't give all of Xilinx a black eye for the very special situation with
> Spartan-II. We expect that to clear up very soon. Let me tell you, there is no
> lack of attention on this case !
>
> Peter Alfke
>
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Content-Type: text/html; charset=us-ascii
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<html><head></head><body>Just a note on Xilinx support;- I had a problem recently with <br>
an 4000xla type device NODELAY attribute for some critical<br>
inputs on my design. The problem was (and still is) that the Alliance<br>
tool refuses to implement this attribute; it is all good up to the mapper<br>
but on the next step which is the PAR, the attribute is not there anymore.<br>
Now, you would think that this is a pretty-strait-forward, specific problem<br>
that should be a no-brainer for a Xilinx application engineer..<br>
but not so fast;- after 4 days of trying to get the Xilinx support to give me<br>
an answer I simply gave up...It seems to me that they have a two-tier system<br>
where you get the top-notch support if you pay for it, but if you just "another<br>
customer" then you get the co-op student to solve your problems and you might as well <br>
try to solve them yourself,<br>
But again this is just my oppinion and I could be wrong,<br>
jakab<br>
<br>
Peter Alfke wrote:<br>
<blockquote type="cite" cite="mid:3A82CB21.6808D98A@xilinx.com"><pre wrap=""><br><a class="moz-txt-link-abbreviated" href="mailto:serebr@my-deja.com">serebr@my-deja.com</a> wrote:<br><br></pre>
<blockquote type="cite"><pre wrap="">It's permanent trade-off: Xilinx provides instant and very high quality<br>support but Altera's devices are mostly available in stock<br>(I mean in comparison with the Spartan-II availability).<br><br></pre></blockquote>
<pre wrap=""><!----><br>Thanks for the friendly words about Xilinx support.<br>And regarding availability:<br>Please don't give all of Xilinx a black eye for the very special situation with<br>Spartan-II. We expect that to clear up very soon. Let me tell you, there is no<br>lack of attention on this case !<br><br>Peter Alfke<br><br></pre>
</blockquote>
<br>
</body></html>
--------------000001030406050801020701--
Article: 29164This is a multi-part message in MIME format. --------------DBDD0695A6AED7462FBFA48D Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You can create a wired-AND/OR funtion however I don't think you would realize the same speed as if you used the carry-chain instead. Although this is not the best method on all situations, I can sugest for you to use the Virtex carry chain to create lare AND or OR gate functions. Depending on exaclty how many inputs you have, the approximate delay will be 1 LUT delay + (inputs/4 * carry chain delay). The basic structure of and AND cate is to configure the LUT as a four input AND gate and tie the output to the MUXCY select. Tie the MUX 0 input to the MUX to the 1 input CIN and the other to ground. The initial CIN needs to be ties to VCC. OR is a similar structure except now create an OR gate in the LUT and reverse all VCC and ground connections I stated above. Obviousl6y other logical structures such as wide decoders can be made in a similar manner if you use your imagination. Most likely, you will have to hand create this structure as I am not sure if any synthesis tools currently infer this structure. Maybe in the near future though... -- Brian Hopefully this will have the speed and characteristics you desire. Christian Plessl wrote: > Hi > > Im working with Xilnix Virtex FPGAs and I have the following question, > problem: > > In my design, I need to evaluate boolean functions of a large number > of input signals. These signals are outputs of statemachines in the > design. > > What I need, is a _fast_ boolean OR resp. AND operations on all of > these output signals. Since there are quite a lot of output signals, > say typically more than 40 signals, I need several levels of logic, > when implementing this in the obivous tree-like structure with a tree > of 4 Input AND/OR gates. > > I think this problem could also be solved by using a wired-or > function, where - in the case of the OR operations - all signals > either drive a line to logical '1' or go into high-impedance state > 'Z'. The only additional thing I need is a pulldown resistor on this > line. > > Does anybody know, whether a circuit like this will work and is > realizable in Xilinx Virtex FPGAs? How could this be done? Im working > with VHDL using Xilinx Foundation F3.1i. > > I would be glad for any hint. > > /Chris --------------DBDD0695A6AED7462FBFA48D Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian tel;work:1-800-255-7778 x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx, Inc.;Software Marketing adr:;;2300 55th Street;Boulder;CO;80301;USA version:2.1 email;internet:brianp@xilinx.com title:Sr. Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------DBDD0695A6AED7462FBFA48D--Article: 29165
On Wed, 07 Feb 2001 17:35:44 GMT, p25486@my-deja.com wrote: >Hi, this is slightly off topic, sorry. > >I work for a big corporation that shall remain nameless (starts with >an "M" and ends with an "ola"). Anyway, some corporate type purchased >company wide licenses for the Mentor Graphics suite of tools (seems >like a suspiciously smart thing for a corporate type to do). My corp starts with Ray and ends with eon > >I'm an FPGA designer, and have been doing mostly VHDL designs aimed at >FPGAs/CPLDs. Having lived with Xilinx's foundation Express for the >last several years, this upgrade seems to be great. Saved us $60k or >so from buying Synplicity. > >The Mentor tools seem really good. However, their front-end tool is >something called Renoir. At first glance it looks like a really cool >tool, and I'm sure that there are people out there who love it. I am >not one of them. We have Mentor Tools here also. I think basically that any graphical entry tool is crap and is mainly for beginners at vhdl or too lazy to figure it out. I totally ignored Renoir and would call it mainly a time waster. > >Renoir, is a graphical environment. So the source files in which you >work are not all text, but contain some Mentor proprietary crap-o- >lium. I thought the whole point of VHDL and Verilog was that you could >use any dumb text editor to view or edit a design. This Renoir thing >seems to be taking that away. > >The Mentor people I've talked to say that is not so. True, that a VHDL >only version of the code is saved, but you can't directly edit it from >within Renoir. > >So here's the question. What's the best way to approach using this >tool (assuming that I have to stay Mentor because it's free to me)? > >Approaches: > >1. Use some other tool, emacs, or the foundation stuff for the HDL >entry, then import the design to Renoir. > >2. Use some other tool emacs, or the foundation stuff for the HDL, and >go directly to ModelSim and then on to Leonardo Spectrum (I haven't >attempted this, any pitfalls?). I use method number 2 with simple text editor. Modelsim has an OK editor that will let you know the location of the error in the VHDL Code when you do an compilation. Try to back annotate this error to Renoir would be just plain silly and waste of time. I haven't found any real pitfalls. I setup all sorts of script files that can be played back for both Leonardo and ModelSim. > >3. Use some nifty option in Renoir that I don't know about. > >4. Use your incredibly cool approach that hasn't occurred to me. > >Thanks, > >John > > >Sent via Deja.com >http://www.deja.com/ Ralph Watson Return Email Address is: ralphwat dot home at excite dot com just type the address in like it should look likeArticle: 29166
--------------91BCFD478929BAABECE22189 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Since I was the engineer working on this case I would like to clear things up. I apologize, Jakab, for not being able to find out what the issue with your software was, but after verifying that the constraint was accepted in your design on my machine, I can state for sure that the Alliance tool does not refuse to implement this attribute. You will see the NODELAY attribute for the register in your MAP report as you say you did. To verify it was indeed implemented, you can look into the IOB in FPGA Editor to see if the signal is routed through a delay element or not. I offered you the opportunity for me to guide you through the steps, and only closed the case upon your request. I can re-open it for you at any time if you are not satisfied with my service. Please do not let our miscommunication reflect on all of Xilinx Support. Thank you for your time. Jakab Tanko wrote: > Just a note on Xilinx support;- I had a problem recently with > an 4000xla type device NODELAY attribute for some critical > inputs on my design. The problem was (and still is) that the Alliance > tool refuses to implement this attribute; it is all good up to the > mapper > but on the next step which is the PAR, the attribute is not there > anymore. > Now, you would think that this is a pretty-strait-forward, specific > problem > that should be a no-brainer for a Xilinx application engineer.. > but not so fast;- after 4 days of trying to get the Xilinx support to > give me > an answer I simply gave up...It seems to me that they have a two-tier > system > where you get the top-notch support if you pay for it, but if you just > "another > customer" then you get the co-op student to solve your problems and > you might as well > try to solve them yourself, > But again this is just my oppinion and I could be wrong, > jakab > > Peter Alfke wrote: > >> serebr@my-deja.com wrote: >> >> >> > It's permanent trade-off: Xilinx provides instant and very high >> > quality >> > support but Altera's devices are mostly available in stock >> > (I mean in comparison with the Spartan-II availability). >> > >> > >> Thanks for the friendly words about Xilinx support. >> And regarding availability: >> Please don't give all of Xilinx a black eye for the very special >> situation with >> Spartan-II. We expect that to clear up very soon. Let me tell you, >> there is no >> lack of attention on this case ! >> >> Peter Alfke >> >> --------------91BCFD478929BAABECE22189 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Since I was the engineer working on this case I would like to <br>clear things up. I apologize, Jakab, for not being able to find <br>out what the issue with your software was, but after verifying <br>that the constraint was accepted in your design on my machine, <br>I can state for sure that the Alliance tool does not refuse to <br>implement this attribute. You will see the NODELAY attribute <br>for the register in your MAP report as you say you did. To verify <br>it was indeed implemented, you can look into the IOB in FPGA <br>Editor to see if the signal is routed through a delay element or not. <p>I offered you the opportunity for me to guide you through the steps, <br>and only closed the case upon your request. I can re-open it for <br>you at any time if you are not satisfied with my service. Please <br>do not let our miscommunication reflect on all of Xilinx Support. <p>Thank you for your time. <p>Jakab Tanko wrote: <blockquote TYPE=CITE>Just a note on Xilinx support;- I had a problem recently with <br>an 4000xla type device NODELAY attribute for some critical <br>inputs on my design. The problem was (and still is) that the Alliance <br>tool refuses to implement this attribute; it is all good up to the mapper <br>but on the next step which is the PAR, the attribute is not there anymore. <br>Now, you would think that this is a pretty-strait-forward, specific problem <br>that should be a no-brainer for a Xilinx application engineer.. <br>but not so fast;- after 4 days of trying to get the Xilinx support to give me <br>an answer I simply gave up...It seems to me that they have a two-tier system <br>where you get the top-notch support if you pay for it, but if you just "another <br>customer" then you get the co-op student to solve your problems and you might as well <br>try to solve them yourself, <br>But again this is just my oppinion and I could be wrong, <br>jakab <p>Peter Alfke wrote: <blockquote type="cite" cite="mid:3A82CB21.6808D98A@xilinx.com"> <pre wrap=""><a href="mailto:serebr@my-deja.com" class="moz-txt-link-abbreviated">serebr@my-deja.com</a> wrote: </pre> <blockquote type="cite"> <pre wrap="">It's permanent trade-off: Xilinx provides instant and very high quality support but Altera's devices are mostly available in stock (I mean in comparison with the Spartan-II availability). </pre> </blockquote> <pre wrap=""><!----> Thanks for the friendly words about Xilinx support. And regarding availability: Please don't give all of Xilinx a black eye for the very special situation with Spartan-II. We expect that to clear up very soon. Let me tell you, there is no lack of attention on this case ! Peter Alfke </pre> </blockquote> </blockquote> </html> --------------91BCFD478929BAABECE22189--Article: 29167
On Wed, 7 Feb 2001 07:23:09 -0800, "Jason Daughenbaugh" <jad_NOSPAM@aedinc.net> wrote: >The Cypress Hotlink series has great documentation. The Xilinx 8b/10b cores have ok documentation as well. > >I have a question - IBM Patented it. How does this limit its use? >Xilinx has a Notice on their core saying that use of it may infringe on IBM's patent. But it seems like everyone is using 8b/10b codes. > >Thanks! >Jason Daughenbaugh >http://www.aedinc.net What date is on IBM's patent and what does it cover? Oh, filed June 1982. There is a large family of possible 8B/10B codes, I worked with one in about April/May 1982. It is possible that IBM's patent covers only one member of the family or only one aspect of 8B/10B coding, but that wouldn't prevent the use of others in the family. Of course this depends whether both ends of the process are under your control, or if you have to be compatible with an existing standard. - BrianArticle: 29168
"james.rowland1" <james.rowland1@ntlworld.com> wrote in message news:T6Dg6.24551$Ee3.617420@news6-win.server.ntlworld.com... > Hi, > > I want to make a single cycle low pulse as a global reset in VHDL: > > signal start : std_logic; > > begin > > p: process(reset, clk) begin > if(reset = '1') then > start <= '0'; > else if(rising_edge(clk) and clk = '1') then > start <= '1'; > end if; > end process p; > This will give you a runt pulse. Synchronise 'reset' before generating 'start'.Article: 29169
Hello, I would like to find information on how to program the 7000's from ALTERA (the old non JTAG versions) without having to buy an expensive programmer. I'm willing to apply a little development effort on this but I don't find the programming info on any of the datasheets. Does anybody has info on this ? Or have already a "build yourself" programmer or know where is info on such a thing ? I would like to use a box of devices I have (EPM7064 and EPM7256) ... if not... better get new JTAG compliant devices rather than buying an expensive programmer. Please let me know to cupido@mail.ua.pt L Cupido.Article: 29170
On Thu, 08 Feb 2001 10:56:10 +0100, Christian Plessl <cplessl@ee.ethz.ch> wrote: >Hi > >Im working with Xilnix Virtex FPGAs and I have the following question, >problem: > >In my design, I need to evaluate boolean functions of a large number >of input signals. These signals are outputs of statemachines in the >design. > >What I need, is a _fast_ boolean OR resp. AND operations on all of >these output signals. Since there are quite a lot of output signals, >say typically more than 40 signals, I need several levels of logic, >when implementing this in the obivous tree-like structure with a tree >of 4 Input AND/OR gates. > >I think this problem could also be solved by using a wired-or >function, where - in the case of the OR operations - all signals >either drive a line to logical '1' or go into high-impedance state >'Z'. The only additional thing I need is a pulldown resistor on this >line. > >Does anybody know, whether a circuit like this will work and is >realizable in Xilinx Virtex FPGAs? How could this be done? Im working >with VHDL using Xilinx Foundation F3.1i. > >I would be glad for any hint. > >/Chris The best way to do this is to use a carry chain to combine the outputs of multiple 4-in LUTs - look up an OR16 in the online docs. This gives you a 1-level delay, plus the carry chain delay. You can't directly extend the OR16 primitive, but you'll be able to code up a wider version by instantiating the primitives in the diagram. EvanArticle: 29171
Hi Harjo, One thing I would recommend is going through the Ping Design example that is provided with the Xilinx PCI core. Using the Implementation Guide, it will demonstrate functional simulation, synthesis, implementation, and verification of the Xilinx PCI LogicCore. This example also includes a test bench to help you get an idea of how to write a test bench for your design. Also you have probably already been to this site, but just in case, you can find information on our PCI core at: http://support.xilinx.com/pci/ Hope this helps, Regards, John Harjo Otten wrote: > Hello, > > In a few weeks we will be starting our first PCI project, and we are going > to use a Xilinx PCI core. We bought ourselfs an Insight evaluation board to > get to know the PCI core, and do some testing. Since we've never done > anything with the PCI bus and we don't have that much experience with FPGA > desing, I'm asking for some starter-tips. > We're using Ease/Eale, Leonardo Spectrum and Modelsim. Are there some "dos" > and "don'ts", tips, guides... anything is welcome. > > Regards, > > H. Otten.Article: 29172
hi, I need to generate a PRBS. I know how to do this using a LFSR one bit at a time. But my output speed is 10x faster than my system clock. IOW, there is a deserializer which takes 10 bits at a time using a slow clock. Has anyone worked the boolean equations which would generate N bits of PRBS at a time ? Any quick ways of generating the equations ? thanks, Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 29173
Synplicity users do not have to use the slightly awkward implementation strategy documented by Xilinx. Since you are using Leonardo, check in case there is an implementation update from Exemplar. "John Ayer" <john.ayer@xilinx.com> wrote in message news:3A831C9D.B5F4DF2@xilinx.com... > Hi Harjo, > > One thing I would recommend is going through the Ping Design example that is > provided with the Xilinx PCI core. Using the Implementation Guide, it will > demonstrate functional simulation, synthesis, implementation, and verification > of the Xilinx PCI LogicCore. This example also includes a test bench to help > you get an idea of how to write a test bench for your design. > > Also you have probably already been to this site, but just in case, you can > find information on our PCI core at: > > http://support.xilinx.com/pci/ > > > Hope this helps, > Regards, > John > > Harjo Otten wrote: > > > Hello, > > > > In a few weeks we will be starting our first PCI project, and we are going > > to use a Xilinx PCI core. We bought ourselfs an Insight evaluation board to > > get to know the PCI core, and do some testing. Since we've never done > > anything with the PCI bus and we don't have that much experience with FPGA > > desing, I'm asking for some starter-tips. > > We're using Ease/Eale, Leonardo Spectrum and Modelsim. Are there some "dos" > > and "don'ts", tips, guides... anything is welcome. > > > > Regards, > > > > H. Otten. >Article: 29174
For Peter Alfke and his colleagues that produce the fine Xilinx documentation, Here's a request in the "you can't please all the people all the time department": The v1.2 of the Virtex-II data sheet was in one convenient PDF file, and the data book itself was spread across some half dozen or so separate PDF files. Now the v1.3 data sheet update has been posted to the web site, unfortunately it too has been broken into multiple PDFs. These are inconvenient to navigate around, search, etc. Request: For those of us with fast net connections, it would be nice if there were an optional set of "monster PDFs", to download the entire data sheet, and the entire user's handbook, in one or two files. I have Adobe Acrobat (writer) so I suppose I could glue all the pieces back together myself... Also, are printed copies of the Handbook with revision v1.2 or v1.3 data sheet available? Thanks, Jan Gray, Gray Research LLC
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