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Threads Starting Dec 1995
2412: 95/12/01: Scott Evans: Atmel Web Site
2421: 95/12/03: Kirk Hobart: Re: Atmel Web Site
2417: 95/12/02: Christian Iseli: Free C hardware synthesizer available
2418: 95/12/02: Manoj Chaubal: New ALDEC tools for XACT 6.0
2425: 95/12/04: Charles Y. Hitchcock: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
2426: 95/12/04: George Noten: Re: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
2435: 95/12/05: Richard Russell: Re: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
2459: 95/12/08: Tom Biggs: Re: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
2451: 95/12/06: Jonathan Griffitts: Re: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
2427: 95/12/04: Jean-Paul Smeets: Xilinx vs Altera with Verilog/VHDL
2439: 95/12/05: Tom Dillon: Re: Xilinx vs Altera with Verilog/VHDL
2446: 95/12/06: Erik Jessen: Re: Xilinx vs Altera with Verilog/VHDL
2448: 95/12/06: Paul S Secinaro: Re: Xilinx vs Altera with Verilog/VHDL
2466: 95/12/08: Tony Goodloe: Re: Xilinx vs Altera with Verilog/VHDL
2429: 95/12/05: Knut Tvete: Median filter
2464: 95/12/08: Ralph Watson: Re: Median filter
2430: 95/12/05: Knut Tvete: Median filter
2431: 95/12/05: Knut Tvete: Median filter
2432: 95/12/05: Knut Tvete: Median filter
2433: 95/12/05: Knut Tvete: Median filter
2438: 95/12/05: Philip Freidin: Re: Median filter
2440: 95/12/05: Russell Petersen: Re: Median filter
2455: 95/12/07: Tim Sheen: Re: Median filter
2475: 95/12/13: Steve Knapp: Re: Median filter
2434: 95/12/05: Erik Jessen: Re: Search for programs implementing Finite State Machine
2436: 95/12/05: Joe Troxel: Altera Verilog Problems
2449: 95/12/06: W. Scott Cranston: Re: Altera Verilog Problems
2437: 95/12/05: Raja Neogi: final call for paper (ICSE'96)
2441: 95/12/05: Pietro Carratu': Search for programs implementing Finite State Machine
2442: 95/12/05: Dave: FPGA => ASIC (Summary)
2483: 95/12/15: Lllapides: Re: FPGA => ASIC (Summary)
2444: 95/12/06: Коротких Юрий Николаевич: Where to obtain the FPGA group FAQ?
2447: 95/12/06: Mattias Onils: Problems with Autologic using Altera FPGA...
2450: 95/12/06: John Cooley: FBI Raids "Avant!" ("ArcSys") For Alleged Cadence Source Code Theft
2453: 95/12/07: Larry Ryan: VHDL Editor for Windows PC, Suggestions?
2559: 96/01/02: Jeremy Sonander: Re: VHDL Editor for Windows PC, Suggestions?
2563: 96/01/03: Rynier van der Watt: Re: VHDL Editor for Windows PC, Suggestions?
2454: 95/12/07: Cristian P. Masgras: Synario and 22V10 problems
2462: 95/12/08: Tom Bowns: Re: Synario and 22V10 problems
2474: 95/12/12: Cristian P. Masgras: Re: Synario and 22V10 problems
2457: 95/12/08: <gburnore@databasix.com>: subscribe
2458: 95/12/08: <gburnore@netcom.com>: subscribe
2460: 95/12/08: Gary Miller: Help on boards using FPGA devices for hareware realisation
2470: 95/12/11: Mark Cartlidge: Re: Help on boards using FPGA devices for hareware realisation
2461: 95/12/08: Erik Jessen: Where is the FAQ?
2463: 95/12/08: Scott Kroeger: FPGA Synthesis/Simulation
2465: 95/12/08: Erik Jessen: Re: FPGA Synthesis/Simulation
2469: 95/12/11: Brian Drummond: Lattice ISP download cable?
2472: 95/12/12: <david@opq.se>: PALASM under OS/2???
2473: 95/12/12: John Cooley: **** YIKES! Need Help On Synopsys Report Card! ****
2476: 95/12/13: Hank Wallace: Your PLD/FPGA Experiences Needed for Article
2477: 95/12/14: Jose'Pedro Abreu: Looking for OpenABEL
2506: 95/12/21: Hiroshi Miyauchi: Re: Looking for OpenABEL
2478: 95/12/14: Chih-Ching Chen: Gated Clock Problem in Xilinx FPGA Implementation
2479: 95/12/14: Scott Kroeger: Re: Gated Clock Problem in Xilinx FPGA Implementation
2480: 95/12/14: Yuce Beser: Re: Gated Clock Problem in Xilinx FPGA Implementation
2482: 95/12/15: Pete Becker: Re: Gated Clock Problem in Xilinx FPGA Implementation
2489: 95/12/17: Tom Dillon: Re: Gated Clock Problem in Xilinx FPGA Implementation
2486: 95/12/15: Paul S Secinaro: Re: Gated Clock Problem in Xilinx FPGA Implementation
2490: 95/12/18: Ray Andraka: Re: Gated Clock Problem in Xilinx FPGA Implementation
2488: 95/12/16: Peter Alfke: Re: Gated Clock Problem in Xilinx FPGA Implementation
2516: 95/12/22: <joebird>: Re: Gated Clock Problem in Xilinx FPGA Implementation
2481: 95/12/15: Lutz Buettner: problem with statemachine
2484: 95/12/15: <javier@world>: WAnted: correlator!!!!!
2485: 95/12/15: <javier@world>: WAnted: correlator!!!!!
2491: 95/12/18: Ray Andraka: Re: WAnted: correlator!!!!!
2492: 95/12/18: Ray Andraka: Re: WAnted: correlator!!!!!
2487: 95/12/15: David Pellerin: Free VHDL Simulator (demo version)
2493: 95/12/18: Maya Reuveni: Floor Planning for Xilinx
2496: 95/12/18: Bill Clark: Re: Floor Planning for Xilinx
2497: 95/12/18: Jack Greenbaum: Re: Floor Planning for Xilinx
2500: 95/12/19: Phil Sailer: Re: Floor Planning for Xilinx
2514: 95/12/22: mush: Re: Floor Planning for Xilinx
2494: 95/12/18: Charles P. Ohrbom: UART in PLD
2495: 95/12/18: David Van den Bout: Re: UART in PLD
2502: 95/12/20: Eric Pearson: Re: UART in PLD
2508: 95/12/21: Ken Goldman: Re: UART in PLD
2507: 95/12/21: Holger Petersen: Re: UART in PLD
2498: 95/12/18: Udi Finkelstein: Synplicity vs. Exemplar for ORCA - Which is better?
2499: 95/12/19: <mc4519@mclink.it>: CYPRESS WARP 2+ VHDL DEVELOPMENT SYSTEM
2501: 95/12/20: S.G. Wood, Jr.: Bit Stream Parser
2503: 95/12/20: Greg Stenzoski: VLSI DESIGN AND TEST Short Course at Georgia Tech
2504: 95/12/20: Jan Maris: Altera related Qs.
2505: 95/12/21: Eric Edwards: Career value: VHDL or Verilog?
2513: 95/12/21: Michael McNamara: Re: Career value: VHDL or Verilog?
2517: 95/12/22: Steve Weigand: Re: Career value: VHDL or Verilog?
2534: 95/12/28: Stephen A. Bailey -- SRBailey Consulting: Re: Career value: VHDL or Verilog?
2536: 95/12/28: Steve Weigand: Re: Career value: VHDL or Verilog?
2537: 95/12/29: Russell Petersen: Re: Career value: VHDL or Verilog?
2547: 95/12/30: Michael Lodman: Re: Career value: VHDL or Verilog?
2549: 95/12/31: suzanne M southworth: Re: Career value: VHDL or Verilog?
2554: 96/01/02: Michael Lodman: Re: Career value: VHDL or Verilog?
2562: 96/01/02: Michael M.Y. Hui: Re: Career value: VHDL or Verilog?
2600: 96/01/10: Simon J Davidmann: Re: Career value: VHDL or Verilog?
2605: 96/01/10: Tony Goodloe: Re: Career value: VHDL or Verilog?
2551: 96/01/02: peter cnudde sh146 8218: Re: Career value: VHDL or Verilog?
2555: 96/01/02: Carl Wuebker: Re: Career value: VHDL or Verilog?
2557: 96/01/02: Russell Petersen: Re: Career value: VHDL or Verilog?
2560: 96/01/02: Holger Veit: Re: Career value: VHDL or Verilog?
2564: 96/01/03: Bernd Paysan: Re: Career value: VHDL or Verilog?
2568: 96/01/04: Ken Wood: Re: Career value: VHDL or Verilog?
2569: 96/01/04: Ken Wood: Re: Career value: VHDL or Verilog?
2586: 96/01/07: Jan Decaluwe: Re: Career value: VHDL or Verilog?
2601: 96/01/10: Holger Veit: Re: Career value: VHDL or Verilog?
2588: 96/01/09: Tom Biggs: Re: Career value: VHDL or Verilog?
2595: 96/01/10: Ken Wood: Re: Career value: VHDL or Verilog?
2606: 96/01/10: GNEEC: Re: Career value: VHDL or Verilog?
2546: 95/12/30: Tom Drabenstott: Re: Career value: VHDL or Verilog?
2509: 95/12/21: Dave Daurelio: Re: Altera related Qs.
2510: 95/12/21: Dr. Jason Cong: FPGA'96 Adv. Program
2511: 95/12/21: <gwise@ibm.net>: Lattice Products
2512: 95/12/21: Dan Blow: Re-progromable VXI module
2521: 95/12/26: Ewan D. Milne: Xiling 4025E routing info
2522: 95/12/27: Philip Freidin: Re: Xiling 4025E routing info
2527: 95/12/28: Steve Knapp (Xilinx, Inc.): Re: Xiling 4025E routing info (Multiplier Arrays)
2532: 95/12/28: Bob Myers: Need help: Actel "bibuf" working with Quicksim II (Men 8.4)
2548: 95/12/30: Tim Schneider: Re: Need help: Actel "bibuf" working with Quicksim II (Men 8.4)
2553: 96/01/02: Michael L. Bates: Re: Need help: Actel "bibuf" working with Quicksim II (Men 8.4)
2558: 96/01/02: Mark L. Hampton: Re: Need help: Actel "bibuf" working with Quicksim II (Men 8.4)
2566: 96/01/03: <Todd>: Re: Need help: Actel "bibuf" working with Q
2575: 96/01/04: Bob Myers: Solved -> Re: Need help: Actel "bibuf" working with Q
2535: 95/12/28: FSI HUNTER: JOB> Sr. Digital Design Engineer
2538: 95/12/29: Jeff Wilkinson: Programmable Interconnect ICs
2539: 95/12/29: Jeff Wilkinson: Programmable Interconnect ICs - Repost
2541: 95/12/29: Joe G. Thompson: Re: Programmable Interconnect ICs - Repost
2544: 95/12/30: Steve Knapp (Xilinx, Inc.): Re: Programmable Interconnect ICs
2542: 95/12/29: Robert F. Calderwood: Gate-level description of 8051 to become available
2545: 95/12/30: Larry Cameron: Re: Gate-level description of 8051 to become available
2552: 96/01/02: L.L. Frederiks: Re: Gate-level description of 8051 to become available
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Compare FPGA features and resources
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