Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Threads Starting Mar 2000
20956: 00/03/01: <javidiaz@my-deja.com>: AMS board simple questions
20962: 00/03/01: Simon: Re: AMS board simple questions
20969: 00/03/01: Andy Peters: Re: AMS board simple questions
20972: 00/03/01: Simon: Re: AMS board simple questions
20965: 00/03/01: Ray Andraka: Re: AMS board simple questions
20959: 00/03/01: YEUNG-CHUEL: help me!...please...
21151: 00/03/09: Wilson TAN: Re: help me!...please...
20964: 00/03/01: Mark: Re: Materials on PCI
20966: 00/03/01: Mark: Re: Materials on PCI
20967: 00/03/01: Steve Charlwood: Error in Xilinx application note XAPP131?
20970: 00/03/01: Bob Perlman: Re: Error in Xilinx application note XAPP131?
21013: 00/03/02: Manfred Kuhland: Re: Error in Xilinx application note XAPP131?
20975: 00/03/01: Tom Leacock: Virtex loading question
20980: 00/03/02: Peter Alfke: Re: Virtex loading question
20979: 00/03/02: <javidiaz@my-deja.com>: AMS board design advice asked
20991: 00/03/02: Ray Andraka: Re: AMS board design advice asked
20986: 00/03/02: Ulf Samuelsson: Re: Comment on Atmel AT40K ?
20993: 00/03/02: Harald Simmler: ORCA 3T - input/output delay reduction?
20996: 00/03/02: Peter Alfke: Re: ORCA 3T - input/output delay reduction?
21004: 00/03/02: Rickman: Re: ORCA 3T - input/output delay reduction?
21148: 00/03/08: Harald Simmler: Re: ORCA 3T - input/output delay reduction?
21027: 00/03/03: pmueller: Re: ORCA 3T - input/output delay reduction?
21033: 00/03/03: Andy Peters: Re: ORCA 3T - input/output delay reduction?
20998: 00/03/02: George: restrictions due to signal types of Global Clock inputs for Virtex
21010: 00/03/03: Keith R. Williams: Re: restrictions due to signal types of Global Clock inputs for Virtex
21026: 00/03/03: Ed Mcgettigan: Re: restrictions due to signal types of Global Clock inputs for Virtex
21000: 00/03/02: Björn Lindegren: xilinx synthesis tool
21003: 00/03/02: Andy Peters: Re: xilinx synthesis tool
21020: 00/03/03: Sherdyn: Re: xilinx synthesis tool
21032: 00/03/03: Andy Peters: Re: xilinx synthesis tool
21002: 00/03/02: Nestor: DLL Details of Xilinx Virtex FPGAs
21006: 00/03/02: Tom Burgess: Re: DLL Details of Xilinx Virtex FPGAs
21024: 00/03/03: Nestor: Re: DLL Details of Xilinx Virtex FPGAs
21008: 00/03/02: Peter Fenn: Comment on Atmel AT40K ?
21009: 00/03/03: Ray Andraka: Re: Comment on Atmel AT40K ?
21016: 00/03/02: Rickman: Re: Comment on Atmel AT40K ?
21036: 00/03/03: Ray Andraka: Re: Comment on Atmel AT40K ?
21045: 00/03/03: Rickman: Re: Comment on Atmel AT40K ?
21046: 00/03/04: Ray Andraka: Re: Comment on Atmel AT40K ?
21050: 00/03/04: Rickman: Re: Comment on Atmel AT40K ?
21052: 00/03/04: Ray Andraka: Re: Comment on Atmel AT40K ?
21054: 00/03/04: Tim Tyler: Re: Comment on Atmel AT40K ?
21055: 00/03/04: Tim Tyler: Re: Comment on Atmel AT40K ?
21057: 00/03/04: Ray Andraka: Re: Comment on Atmel AT40K ?
21085: 00/03/06: Joseph H Allen: Re: Comment on Atmel AT40K ?
21088: 00/03/06: Ray Andraka: Re: Comment on Atmel AT40K ?
21093: 00/03/06: Joseph H Allen: Re: Comment on Atmel AT40K ?
21011: 00/03/03: Keith R. Williams: SpartanXL route and place
21015: 00/03/02: Phil Hays: Re: SpartanXL route and place
21096: 00/03/07: Keith R. Williams: Re: SpartanXL route and place
21018: 00/03/03: Utku Ozcan: Re: SpartanXL route and place
21039: 00/03/03: Ray Andraka: Re: SpartanXL route and place
21097: 00/03/07: Keith R. Williams: Re: SpartanXL route and place
21105: 00/03/06: Phil Hays: Re: SpartanXL route and place
21136: 00/03/08: Keith R. Williams: Re: SpartanXL route and place
21109: 00/03/07: Ray Andraka: Re: SpartanXL route and place
21023: 00/03/03: Monte Dalrymple: Re: SpartanXL route and place
21098: 00/03/07: Keith R. Williams: Re: SpartanXL route and place
21137: 00/03/08: Keith R. Williams: Re: SpartanXL route and place
21144: 00/03/08: Utku Ozcan: Re: SpartanXL route and place
21165: 00/03/09: Keith R. Williams: Re: SpartanXL route and place
21184: 00/03/09: Jonathan Bromley: Re: SpartanXL route and place
21227: 00/03/11: Keith R. Williams: Re: SpartanXL route and place
21031: 00/03/03: Andy Peters: Re: SpartanXL route and place
21073: 00/03/06: Rick Filipkiewicz: Re: SpartanXL route and place
21083: 00/03/06: Andy Peters: Re: SpartanXL route and place
21099: 00/03/07: Keith R. Williams: Re: SpartanXL route and place
21034: 00/03/03: John Janusson: Re: SpartanXL route and place
21100: 00/03/07: Keith R. Williams: Re: SpartanXL route and place
21156: 00/03/08: <rotemg@mysticom.com>: Re: SpartanXL route and place
21166: 00/03/09: Keith R. Williams: Re: SpartanXL route and place
21037: 00/03/03: Ray Andraka: Re: SpartanXL route and place
21102: 00/03/07: Keith R. Williams: Re: SpartanXL route and place
21110: 00/03/07: Ray Andraka: Re: SpartanXL route and place
21112: 00/03/07: Hal Murray: Re: SpartanXL route and place
21113: 00/03/07: Ray Andraka: Re: SpartanXL route and place
21138: 00/03/07: Phil Hays: Re: SpartanXL route and place
21146: 00/03/08: Ray Andraka: Re: SpartanXL route and place
21152: 00/03/08: Andy Peters: Re: SpartanXL route and place
21169: 00/03/09: Ray Andraka: Re: SpartanXL route and place
21191: 00/03/09: Andy Peters: Re: SpartanXL route and place
21172: 00/03/09: Allan Herriman: Re: SpartanXL route and place
21185: 00/03/09: Ray Andraka: Re: SpartanXL route and place
21199: 00/03/09: Rickman: Re: SpartanXL route and place
21205: 00/03/10: Ray Andraka: Re: SpartanXL route and place
21206: 00/03/10: Rickman: Re: SpartanXL route and place
21213: 00/03/10: Ray Andraka: Re: SpartanXL route and place
21190: 00/03/09: Andy Peters: Re: SpartanXL route and place
21196: 00/03/09: Peter Alfke: Re: SpartanXL route & place, Corrected
21202: 00/03/09: Phil Hays: Re: SpartanXL route & place, Corrected
21194: 00/03/09: Peter Alfke: Re: SpartanXL route and place
21203: 00/03/10: Ray Andraka: Re: SpartanXL route and place
21220: 00/03/10: Carl Rohrer: Re: SpartanXL route and place
21207: 00/03/10: <eml@riverside-machines.com.NOSPAM>: Re: SpartanXL route and place
21210: 00/03/10: <eml@riverside-machines.com.NOSPAM>: Re: SpartanXL route and place
21214: 00/03/10: Ray Andraka: Re: SpartanXL route and place
21224: 00/03/10: Rickman: Re: SpartanXL route and place
21219: 00/03/10: David Hawke: Re: SpartanXL route and place
21115: 00/03/07: Rick Filipkiewicz: Re: SpartanXL route and place
21125: 00/03/07: Utku Ozcan: Re: SpartanXL route and place
21181: 00/03/09: Rick Filipkiewicz: Re: SpartanXL route and place
21014: 00/03/03: Matt Billenstein: Virtex decoupling cap considerations...
21017: 00/03/02: Rickman: Re: Virtex decoupling cap considerations...
21021: 00/03/03: Jerry English: Re:
21029: 00/03/03: <1209@my-deja.com>: Synplicity for sale
21074: 00/03/06: Rick Filipkiewicz: Re: Synplicity for sale
21130: 00/03/07: Stuart Clubb: Re: Synplicity for sale
21179: 00/03/09: Rick Filipkiewicz: Re: Synplicity for sale
21232: 00/03/11: Stuart Clubb: Re: Synplicity for sale
21035: 00/03/03: Stan Ramsden: EDA tools
21038: 00/03/03: muzo: Re: EDA tools
21042: 00/03/04: Ray Andraka: Re: EDA tools
21041: 00/03/03: SPG: BOOKS ON FPGA
21043: 00/03/04: <gweinreb@gwinst.com>: Need help w/ Dual Port Ram
21049: 00/03/04: Erez Mozes: I need an advice here pls!
23454: 00/06/26: Pini: Re: I need an advice here pls!
21051: 00/03/04: Stan Ramsden: Long Island Consultant Available
21058: 00/03/04: Adam J. Elbirt: Xilinx Tools Question
21059: 00/03/05: Ray Andraka: Re: Xilinx Tools Question
21060: 00/03/05: Adam J. Elbirt: Re: Xilinx Tools Question
21061: 00/03/05: Ray Andraka: Re: Xilinx Tools Question
21065: 00/03/05: Jesse Newcomb: QuickLogic programmers for sale
21068: 00/03/06: Hans Holm: Re: QuickLogic programmers for sale
21066: 00/03/06: Songhyun Yun: To use synplify in command mode
21075: 00/03/06: Rick Filipkiewicz: Re: To use synplify in command mode
21069: 00/03/06: qfwfq: about multipliers
21080: 00/03/06: Ray Andraka: Re: about multipliers
21071: 00/03/06: Klaus Falser: Xilinx Parallel Cable III and 3.3V
21072: 00/03/06: Daryl Bradley: Re: Xilinx Parallel Cable III and 3.3V
21076: 00/03/06: Mark W.: Re: An optical allusion that will astound you, works on all spec pc's:) 9523
21077: 00/03/06: Kang Liat Chuan: From Xilinx Coregen 2.1 to Mentor EDDM
21078: 00/03/06: <alexlamba@my-deja.com>: 300 Xilinx Xa7272a wanted, we'll pay up to 45$ each
21084: 00/03/06: Björn Lindegren: Problem with vector copy
21086: 00/03/06: Stuart J Adams: PCI reflected wave switching spec ???
21094: 00/03/06: Jim McManus: Re: PCI reflected wave switching spec ???
21089: 00/03/06: Jim Stewart: Stupid Foundation question
21118: 00/03/07: Holger Kleinert: Re: Stupid Foundation question
21123: 00/03/07: Andy Peters: Re: Stupid Foundation question
21126: 00/03/07: Tom Burgess: Re: Stupid Foundation question
21090: 00/03/06: <pirger@astrosun.tn.cornell.edu>: Apex vs. 10K
21103: 00/03/07: MarvL: Newbie asks: prototype done, now what?
21104: 00/03/07: wannarat: Xilinx software
21106: 00/03/07: Jason Lohn: REMINDER: CFP: The Second NASA/DoD Workshop on Evolvable Hardware
21108: 00/03/07: Tobin Fricke: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
21117: 00/03/07: Trent Worthington: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
21128: 00/03/07: Lee Webb: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86,
21132: 00/03/07: Ivar: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
21139: 00/03/07: Code Mangler: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
21149: 00/03/08: Paul DeMone: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86,
21145: 00/03/08: Norm Ebsary: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
21173: 00/03/09: Volker Urban: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
21183: 00/03/09: Jerry English: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86,
21192: 00/03/09: Joseph H Allen: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86,
21157: 00/03/08: <blackhole@rtd.com>: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
21161: 00/03/08: <eml@riverside-machines.com.NOSPAM>: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
156954: 14/08/04: <johngreer2003@yahoo.com>: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
21114: 00/03/07: Hans Holm: antifuse fpga's replacing xilinx
21119: 00/03/07: rk: Re: antifuse fpga's replacing xilinx
21122: 00/03/07: Kate Atkins: Re: antifuse fpga's replacing xilinx
21127: 00/03/07: rk: Re: antifuse fpga's replacing xilinx
21140: 00/03/08: Hal Murray: Re: antifuse fpga's replacing xilinx
21143: 00/03/08: Kate Atkins: Re: antifuse fpga's replacing xilinx
21154: 00/03/08: Peter Alfke: Re: antifuse fpga's replacing xilinx
21160: 00/03/08: Magnus Homann: Re: antifuse fpga's replacing xilinx
21163: 00/03/08: Peter Alfke: Re: antifuse fpga's replacing xilinx
21175: 00/03/09: Magnus Homann: Re: antifuse fpga's replacing xilinx
21170: 00/03/08: Rickman: Re: antifuse fpga's replacing xilinx
21174: 00/03/09: Magnus Homann: Re: antifuse fpga's replacing xilinx
21200: 00/03/09: Rickman: Re: antifuse fpga's replacing xilinx
21211: 00/03/10: Magnus Homann: Re: antifuse fpga's replacing xilinx
21176: 00/03/09: <eml@riverside-machines.com.NOSPAM>: Re: antifuse fpga's replacing xilinx
21182: 00/03/09: Magnus Homann: Re: antifuse fpga's replacing xilinx
21209: 00/03/10: <eml@riverside-machines.com.NOSPAM>: Re: antifuse fpga's replacing xilinx
21168: 00/03/08: rk: Re: antifuse fpga's replacing xilinx
21141: 00/03/08: Hans Holm: Re: antifuse fpga's replacing xilinx
21124: 00/03/07: Keith Jasinski, Jr.: Re: antifuse fpga's replacing xilinx
21129: 00/03/07: Uwe Bonnes: Re: antifuse fpga's replacing xilinx
21142: 00/03/08: Hans Holm: Re: antifuse fpga's replacing xilinx
21116: 00/03/07: <usenet201@hotmail.com>: setup and hold times for data during configuration (Xilinx Virtex 4000E select-map)
21131: 00/03/07: Mike Peattie: Re: setup and hold times for data during configuration (Xilinx Virtex
21134: 00/03/07: Peter Alfke: Re: setup and hold times for data during configuration (Xilinx Virtex
21121: 00/03/07: Ron: Quartus for APEX
21133: 00/03/07: Zhibin Dai: Quick questions for Xilinx tools
21147: 00/03/08: Rémi SEGLIE: Re: Quick questions for Xilinx tools
21167: 00/03/08: Stan Ramsden: Re: Quick questions for Xilinx tools
21150: 00/03/08: Jan Stumps: Q: Hitachi FPGA HD61J215P: Searching Infos!!!
21155: 00/03/08: John L. Smith: Re: Q: Hitachi FPGA HD61J215P: Searching Infos!!!
21153: 00/03/08: <boniolopez@my-deja.com>: links about design verification
21158: 00/03/08: Abednego: ModelSim 2.1i ?
21164: 00/03/08: Andy Peters: Re: ModelSim 2.1i ?
21171: 00/03/09: Ray Andraka: Re: ModelSim 2.1i ?
21180: 00/03/09: Rick Filipkiewicz: Re: ModelSim 2.1i ?
21189: 00/03/09: Ray Andraka: Re: ModelSim 2.1i ?
21216: 00/03/10: Ray Andraka: Re: ModelSim 2.1i ?
21159: 00/03/08: test: Logiblox from ABEL?
21162: 00/03/08: steve wenner: pal design using GAL22V10 and PROTEL
21195: 00/03/10: Mikeandmax: Re: pal design using GAL22V10 and PROTEL
21208: 00/03/10: Jim Granville: Re: pal design using GAL22V10 and PROTEL
21177: 00/03/09: Juan Antonio =?iso-8859-1?Q?G=F3mez?= Pulido: I need parallel processor SIMULATOR
21187: 00/03/09: Utku Ozcan: Re: I need parallel processor SIMULATOR
21259: 00/03/14: Tim Tyler: Re: I need parallel processor SIMULATOR
21178: 00/03/09: Steven Sanders: Xilinx Foundation 2.1:Functional simulation
21188: 00/03/09: <channing-wen@usa.net>: Re: Xilinx Foundation 2.1:Functional simulation
21186: 00/03/09: Don McCarley: Virtex and Virtex E package availability
21201: 00/03/09: Joel Kolstad: Re: Virtex and Virtex E package availability
21225: 00/03/10: John L. Smith: Re: Virtex and Virtex E package availability
21193: 00/03/09: Yvon Hache: FPGA board
21197: 00/03/09: Dave Vanden Bout: Re: FPGA board
21204: 00/03/10: Ray Andraka: Re: FPGA board
21212: 00/03/10: Mark Wyman: Re: **NEW VERSION** MindBender v1.2 814
21215: 00/03/10: Allan Herriman: Spartan 2 Industrial temp range versions
21217: 00/03/10: Ray Andraka: Re: Spartan 2 Industrial temp range versions
22741: 00/05/22: Mark Harvey: Re: Spartan 2 Industrial temp range versions
21218: 00/03/10: <alaincloet@hotmail.com>: Checksum CPLD with Foundation Series
21223: 00/03/10: <recruiterm2@my-deja.com>: Digital Design Engineer Job
21228: 00/03/11: yang_li1: Synthesis question ( PCI based ASIC )
21229: 00/03/11: peter dudley: Xilinx IP Protection
21233: 00/03/11: Ray Andraka: Re: Xilinx IP Protection
21230: 00/03/11: Enrico Migliore: Xilinx Foundation Series and FSM designs
21231: 00/03/11: Dave Vanden Bout: Re: Xilinx Foundation Series and FSM designs
21238: 00/03/12: Rickman: Re: Xilinx Foundation Series and FSM designs
21239: 00/03/12: Ray Andraka: Re: Xilinx Foundation Series and FSM designs
21234: 00/03/12: NTM: Freeware Newsreader
21235: 00/03/12: yang_li1: Synthesis question ( PCI based ASIC )
21236: 00/03/12: Tobin Fricke: Altera LPM from VHDL
21237: 00/03/12: Pai H Chou: SIGDA Ph.D. Forum at DAC'2000 -- new deadline Fri Mar.17
21240: 00/03/12: Steven K. Knapp: FPGA Prototype Boards/System Listing Updated
21242: 00/03/13: Jean-Réginald Louis: DSP with FPGA
21244: 00/03/13: Jonas Thor: Re: DSP with FPGA
21247: 00/03/13: Jean-Réginald Louis: Re: DSP with FPGA
21250: 00/03/14: Ray Andraka: Re: DSP with FPGA
21246: 00/03/13: Ray Andraka: Re: DSP with FPGA
21243: 00/03/12: dnardi: Standalone EEPROM memories
21245: 00/03/13: Steven Derrien: Xilinx FPGA densities
21248: 00/03/13: Björn Lindegren: Testbench for a modulator and a demodulator
21249: 00/03/14: raja: Re: Testbench for a modulator and a demodulator
21251: 00/03/14: <editor@mail.booksonline.com>: Survey on computer/electrical engineering – free book
21252: 00/03/14: <bfredc@my-deja.com>: Virtex IOB T register
21261: 00/03/14: Peter Alfke: Re: Virtex IOB T register
21262: 00/03/14: Peter Alfke: Re: Virtex IOB T register
21265: 00/03/14: Ray Andraka: Re: Virtex IOB T register
21266: 00/03/14: Rickman: Re: Virtex IOB T register
21274: 00/03/14: Andy Peters: Re: Virtex IOB T register
21279: 00/03/15: Ray Andraka: Re: Virtex IOB T register
21281: 00/03/15: Rick Filipkiewicz: Re: Virtex IOB T register
21282: 00/03/15: <eml@riverside-machines.com.NOSPAM>: Re: Virtex IOB T register
21288: 00/03/15: Rick Filipkiewicz: Re: Virtex IOB T register
21291: 00/03/15: <bfredc@my-deja.com>: Re: Virtex IOB T register
21253: 00/03/14: Guido Pohl: Is there a chance to synthesize that?
21283: 00/03/15: <eml@riverside-machines.com.NOSPAM>: Re: Is there a chance to synthesize that?
21254: 00/03/14: Steven Derrien: Pb with Coregen in F2.1i
21294: 00/03/15: Louis Caron: Re: Pb with Coregen in F2.1i
21255: 00/03/14: Sprow: Where've Xilinx hidden it then?
21256: 00/03/14: <mark_harvey@my-deja.com>: JTAG by parallel port
21258: 00/03/14: Dave Vanden Bout: Re: JTAG by parallel port
21379: 00/03/21: Larry Doolittle: Re: JTAG by parallel port
21257: 00/03/14: Avinash Maddy: Can we read bits from a file in PCc using Altera or Xilinx ?
21264: 00/03/14: Rickman: Re: Can we read bits from a file in PCc using Altera or Xilinx ?
21299: 00/03/15: Navaneethan Sundaramoorthy: Re: Can we read bits from a file in PCc using Altera or Xilinx ?
21260: 00/03/14: Seb C: DCT using FPGA
21263: 00/03/14: Tom McLaughlin: Programming FPGAs via backplane (Xilinx)
21267: 00/03/14: Rickman: Re: Programming FPGAs via backplane (Xilinx)
21269: 00/03/15: Mark Summerfield: Re: Programming FPGAs via backplane (Xilinx)
21270: 00/03/14: Peter Alfke: Re: Programming FPGAs via backplane (Xilinx)
21268: 00/03/14: Peter Alfke: Atmel censors web access
21271: 00/03/14: Scott Campbell: Re: Atmel censors web access
21278: 00/03/15: Ray Andraka: Re: Atmel censors web access
21272: 00/03/14: Larry Doolittle: Re: Atmel censors web access
21275: 00/03/14: Peter Alfke: Re: Atmel censors web access
21343: 00/03/17: Ulf Samuelsson: SV: Atmel censors web access
21347: 00/03/17: Peter Alfke: Re: SV: Atmel censors web access
21293: 00/03/15: John Kortink: Re: Atmel censors web access
21659: 00/03/28: Hyun-Taek Chang: Re: Atmel censors web access
21273: 00/03/14: Andy Peters: Today's Unexplained Phenomena, Xilinx Department
21276: 00/03/15: Sherdyn: Need help on VHDL testbench
21277: 00/03/15: JaeYong Kim: Difference between FPGA, PLD, CPLD ?
21280: 00/03/15: Ray Andraka: Re: Difference between FPGA, PLD, CPLD ?
21284: 00/03/15: <eml@riverside-machines.com.NOSPAM>: Re: Difference between FPGA, PLD, CPLD ?
21286: 00/03/15: David Frith: Re: Difference between FPGA, PLD, CPLD ?
21287: 00/03/15: David Frith: Re: Difference between FPGA, PLD, CPLD ?
21296: 00/03/15: Richard Erlacher: Re: Difference between FPGA, PLD, CPLD ?
21298: 00/03/15: Peter Alfke: Re: Difference between FPGA, PLD, CPLD ?
21304: 00/03/16: Kevin Dale Kirmse: Re: Difference between FPGA, PLD, CPLD ?
21307: 00/03/16: Peter Alfke: Re: Difference between FPGA, PLD, CPLD ?
21311: 00/03/16: rk: Re: Difference between FPGA, PLD, CPLD ?
21319: 00/03/16: Kevin Dale Kirmse: Re: Difference between FPGA, PLD, CPLD ?
21321: 00/03/16: Peter Alfke: Re: Difference between FPGA, PLD, CPLD ?
21290: 00/03/15: rk: Re: Difference between FPGA, PLD, CPLD ?
21300: 00/03/16: Jared Church: Re: Difference between FPGA, PLD, CPLD ?
21303: 00/03/16: Peter Alfke: Re: Difference between FPGA, PLD, CPLD ?
21335: 00/03/17: Steve Rencontre: Re: Difference between FPGA, PLD, CPLD ?
21322: 00/03/16: Ray Andraka: Re: Difference between FPGA, PLD, CPLD ?
21328: 00/03/16: Peter Alfke: Re: Difference between FPGA, PLD, CPLD ?
21333: 00/03/16: rk: Re: Difference between FPGA, PLD, CPLD ?
21645: 00/03/27: Michael Lee: Re: Difference between FPGA, PLD, CPLD ?
21309: 00/03/16: Alasdair MacLean: Re: Difference between FPGA, PLD, CPLD ?
21323: 00/03/16: gerald coe: Re: Difference between FPGA, PLD, CPLD ?
21285: 00/03/15: Bingfeng Mei: About atmel's FPGA and JBit
21289: 00/03/15: Riad BOURGUIBA: Re: About atmel's FPGA and JBit
21292: 00/03/15: <dulik@dcse.fee.vutbr.cz>: SystemC vs. VHDL
21310: 00/03/16: Bingfeng Mei: Re: SystemC vs. VHDL
21297: 00/03/15: Christof Paar: CHES 2000 --- 3rd CFP
21301: 00/03/16: Keith R. Williams: SpartanXL Express mode configuration
21344: 00/03/17: Stewart, Nial [HAL02:HH00:EXCH]: Re: SpartanXL Express mode configuration
21355: 00/03/18: Brian Drummond: Re: SpartanXL Express mode configuration
21359: 00/03/20: Keith R. Williams: Re: SpartanXL Express mode configuration
21302: 00/03/16: Yang Li: PCI Synthesis Question
21305: 00/03/16: =?EUC-KR?B?wNPA58iv?=: question for virtex
21306: 00/03/16: Peter Sutton: Xilinx 6200 devices?
21308: 00/03/16: Peter Alfke: Re: Xilinx 6200 devices?
21312: 00/03/16: Daryl Bradley: Re: Xilinx 6200 devices?
21315: 00/03/16: Bingfeng Mei: Re: Xilinx 6200 devices?
21394: 00/03/21: Prasanna Sundararajan: Re: Xilinx 6200 devices?
21314: 00/03/16: Andrew batchelor: Actel Design with A42MX36 Help
21334: 00/03/16: rk: Re: Actel Design with A42MX36 Help
21337: 00/03/17: Alasdair MacLean: Re: Actel Design with A42MX36 Help
21342: 00/03/17: rk: Re: Actel Design with A42MX36 Help
21346: 00/03/17: Richard I. Guerin: Re: Actel Design with A42MX36 Help
21384: 00/03/21: Holger Venus: Re: Actel Design with A42MX36 Help
21420: 00/03/22: Andrew batchelor: Re: Actel Design with A42MX36 Help
21424: 00/03/22: Rickman: Re: Actel Design with A42MX36 Help
21316: 00/03/16: <jodoan@my-deja.com>: Atmel A29 Series Software Erase
21317: 00/03/16: Peter: Xilinx configuration current
21320: 00/03/16: Rickman: Re: Xilinx configuration current
21324: 00/03/16: Greg Neff: Re: Xilinx configuration current
21329: 00/03/16: Peter Alfke: Re: Xilinx configuration current
21339: 00/03/17: Peter: Re: Xilinx configuration current
21330: 00/03/16: Greg Neff: Re: Xilinx configuration current
21318: 00/03/16: Gary Watson: Is there a Xilink PCI or ISA demo board with external connector?
21816: 00/04/02: Rozelle Schwarz: Re: Is there a Xilink PCI or ISA demo board with external connector?
21325: 00/03/16: HR: Employment
21327: 00/03/16: HR: Re: Employment
21326: 00/03/16: Steve Dewey: Altera literature misleading
21336: 00/03/17: JPC: Re: Altera literature misleading
21331: 00/03/16: HH: Re: ,,..SAY A PRAYER FOR THE INNOCENT VICTIMS OF BLACK VIOLENCE AND LAWLESSNESS!!..
21332: 00/03/17: Zoltan Kocsi: Re: ,,..SAY A PRAYER FOR THE INNOCENT VICTIMS OF BLACK VIOLENCE AND LAWLESSNESS!!..
21338: 00/03/17: Dennis Krupp: Is there a cheaper alternative to ByteblasterMV?
21340: 00/03/17: John Renvar: Re: Is there a cheaper alternative to ByteblasterMV?
21341: 00/03/17: Leon Heller: Re: Is there a cheaper alternative to ByteblasterMV?
21351: 00/03/17: Joel Kolstad: Re: Is there a cheaper alternative to ByteblasterMV?
21353: 00/03/18: John Kortink: Re: Is there a cheaper alternative to ByteblasterMV?
21348: 00/03/17: Riad BOURGUIBA: Looking for informations about VCC's EVC1 architecture.
21349: 00/03/17: Nick: Xilinx Foundation 1.5 Question
21350: 00/03/18: Nick: Re: Xilinx Problem Found
21352: 00/03/18: Scott Paul Johnston: UPDATED ENGINEERING PAGE: Please Visit
21354: 00/03/18: hamilton: Re: UPDATED ENGINEERING PAGE: Please Visit
21356: 00/03/18: Max: Actel fpgas
22035: 00/04/14: Alex Flitwick: Re: Actel fpgas
22043: 00/04/14: Simon Ramirez: Re: Actel fpgas
22044: 00/04/14: rk: Re: Actel fpgas
21357: 00/03/20: Jan Gray: "Building a RISC System in an FPGA" magazine series, and XSOC/xr16 RISC SoC
21358: 00/03/20: Lorcan Mc Donagh: Question about Atmel AT40k FPGA: mode4 configuration download details ? ( not in the datasheets )
21360: 00/03/20: Sherdyn: Weak Pull up
21363: 00/03/20: Rémi SEGLIE: Re: Weak Pull up
21361: 00/03/19: Pawel Chodowiec: How to eliminate high fan-out in Xilinx FPGA's?
21362: 00/03/20: <bfredc@my-deja.com>: Re: How to eliminate high fan-out in Xilinx FPGA's?
21368: 00/03/20: Ed McCauley: Re: How to eliminate high fan-out in Xilinx FPGA's?
21364: 00/03/20: Nick: Re: Beginner's Guide
21365: 00/03/20: Nick: Re: Beginner's Guide
21369: 00/03/20: Hans Holm: Re: Beginner's Guide
21366: 00/03/20: Nicolas Matringe: Clock disabling
21375: 00/03/21: Jared Church: Re: Clock disabling
21393: 00/03/21: Peter Alfke: Re: Clock disabling
21431: 00/03/22: <boniolopez@my-deja.com>: Re: Clock disabling
21453: 00/03/23: Jared Church: Re: Clock disabling
21464: 00/03/23: Rickman: Re: Clock disabling
21495: 00/03/23: bob elkind: Re: Clock disabling
21540: 00/03/24: Andrew Brown: Re: Clock disabling
21547: 00/03/24: Nicholas C. Weaver: Re: Clock disabling
21576: 00/03/25: Peter: Re: Clock disabling
21367: 00/03/20: <boniolopez@my-deja.com>: relationship of gates quantity for the same design in FPGA (Virtex) and ASIC.
21370: 00/03/20: <boniolopez@my-deja.com>: Clock nets using non-dedicated resources
21382: 00/03/21: Rémi SEGLIE: Re: Clock nets using non-dedicated resources
21385: 00/03/21: <boniolopez@my-deja.com>: Re: Clock nets using non-dedicated resources
21387: 00/03/21: <a@z.com>: Re: Clock nets using non-dedicated resources
21388: 00/03/21: Rickman: Re: Clock nets using non-dedicated resources
21390: 00/03/21: <boniolopez@my-deja.com>: Re: Clock nets using non-dedicated resources
21395: 00/03/21: Nicolas Matringe: Re: Clock nets using non-dedicated resources
21416: 00/03/22: <boniolopez@my-deja.com>: Re: Clock nets using non-dedicated resources
21389: 00/03/21: <boniolopez@my-deja.com>: Re: Clock nets using non-dedicated resources
21407: 00/03/22: =?iso-2022-jp?B?GyRCMEIwZhsoQiAbJEI3chsoQg==?=: Re: Clock nets using non-dedicated resources
21418: 00/03/22: <boniolopez@my-deja.com>: Re: Clock nets using non-dedicated resources
21425: 00/03/22: Rickman: Re: Clock nets using non-dedicated resources
21392: 00/03/21: Andy Peters: Re: Clock nets using non-dedicated resources
21419: 00/03/22: <boniolopez@my-deja.com>: Re: Clock nets using non-dedicated resources
21427: 00/03/22: Rickman: Re: Clock nets using non-dedicated resources
21443: 00/03/22: Andy Peters: Re: Clock nets using non-dedicated resources
21401: 00/03/21: Tim: Re: Clock nets using non-dedicated resources
21429: 00/03/22: <boniolopez@my-deja.com>: Re: Clock nets using non-dedicated resources
21444: 00/03/22: Andy Peters: Re: Clock nets using non-dedicated resources
21466: 00/03/23: =?iso-2022-jp?B?GyRCMEIwZhsoQiAbJEI3chsoQg==?=: Re: Clock nets using non-dedicated resources
21614: 00/03/26: James C. LaLone: Re: Clock nets using non-dedicated resources
21430: 00/03/22: <boniolopez@my-deja.com>: Re: Clock nets using non-dedicated resources
21463: 00/03/22: Gerard Auclair: Re: Clock nets using non-dedicated resources
21782: 00/03/31: <boniolopez@my-deja.com>: Re: Clock nets using non-dedicated resources
21372: 00/03/20: Márcio Longaray: Re: Beginner's Guide
21373: 00/03/20: MegaBolt: Beginner's Guide
21380: 00/03/21: Keith R. Williams: Re: Beginner's Guide
21386: 00/03/21: Edwin Naroska: Re: Beginner's Guide
22247: 00/05/03: erica: Re: Beginner's Guide
22256: 00/05/03: Xanatos: Re: Beginner's Guide
22391: 00/05/08: <vsundaram@my-deja.com>: Re: Beginner's Guide
22268: 00/05/03: Steve Dewey: Re: Beginner's Guide
22271: 00/05/03: erica: Re: Beginner's Guide
21374: 00/03/20: Andy Krumel: Synthesis error
21376: 00/03/20: Rickman: Re: Synthesis error
21381: 00/03/21: <boniolopez@my-deja.com>: Re: Synthesis error
21377: 00/03/21: =?EUC-KR?B?wNPA58iv?=: How I can DLL function unsing VHDL in Virtex?
21378: 00/03/21: Ray Andraka: Re: How I can DLL function unsing VHDL in Virtex?
21383: 00/03/21: Sherdyn: Open Drain and tristate buffer
21391: 00/03/21: Andy Peters: Re: Open Drain and tristate buffer
21396: 00/03/21: Vincent Mooney: CASES 2000 Call for Papers
21397: 00/03/21: Anshuman Sharma: FPGA related projects
21398: 00/03/22: =?EUC-KR?B?wNPA58iv?=: qestion for Vref pin of Virtex chip
21399: 00/03/22: À念Áø: Looking for Xilinx Spartan Synthesis library for Synopsys.
21400: 00/03/22: Edward: How to solder FPGA in BGA package ?
21405: 00/03/22: Rickman: Re: How to solder FPGA in BGA package ?
21411: 00/03/22: <rob_dickinson@my-deja.com>: Re: How to solder FPGA in BGA package ?
21515: 00/03/24: Steve Rencontre: Re: How to solder FPGA in BGA package ?
21410: 00/03/22: Holger Kleinert: Re: How to solder FPGA in BGA package ?
21414: 00/03/22: Sherdyn: Re: How to solder FPGA in BGA package ?
21415: 00/03/22: Keith Wootten: Re: How to solder FPGA in BGA package ?
21402: 00/03/22: Pratip Mukherjee: Good book on learning FPGA/VHDL/Verilog programming
21488: 00/03/23: <iglasner@my-deja.com>: Re: Good book on learning FPGA/VHDL/Verilog programming
21634: 00/03/27: Holger Kleinert: Re: Good book on learning FPGA/VHDL/Verilog programming
21792: 00/03/31: Steven K. Knapp: Re: Good book on learning FPGA/VHDL/Verilog programming
21406: 00/03/22: Greg Alexander: FPGA openness
21409: 00/03/21: Hobson Frater: Re: FPGA openness
21428: 00/03/22: Greg Alexander: Re: FPGA openness
21432: 00/03/22: Gordon Brebner: Re: FPGA openness
21439: 00/03/22: Greg Alexander: Re: FPGA openness
21441: 00/03/22: Andy Peters: Re: FPGA openness
21446: 00/03/22: Ben Franchuk: Re: FPGA openness
21548: 00/03/24: Theron Hicks: Re: FPGA openness
21552: 00/03/24: Jason T. Wright: Re: FPGA openness
21553: 00/03/24: Jason T. Wright: Re: FPGA openness
21450: 00/03/22: Peter Alfke: Re: FPGA openness
21459: 00/03/23: Greg Alexander: Re: FPGA openness
21454: 00/03/22: Larry Doolittle: Re: FPGA openness
21465: 00/03/23: Rickman: Re: FPGA openness
21476: 00/03/23: <eml@riverside-machines.com.NOSPAM>: Re: FPGA openness
21478: 00/03/23: Greg Alexander: Re: FPGA openness
21482: 00/03/23: Ray Andraka: Re: FPGA openness
21489: 00/03/23: Greg Alexander: Re: FPGA openness
21493: 00/03/23: Ray Andraka: Re: FPGA openness
21501: 00/03/23: Greg Alexander: Re: FPGA openness
21519: 00/03/24: Andreas Doering: Re: FPGA openness
21524: 00/03/24: Greg Alexander: Re: FPGA openness
21538: 00/03/24: Don Husby: Re: FPGA openness
21539: 00/03/24: Greg Alexander: Re: FPGA openness
21545: 00/03/24: Nicholas C. Weaver: Re: FPGA openness
21586: 00/03/26: Greg Alexander: Re: FPGA openness
21591: 00/03/26: Greg Alexander: Re: FPGA openness
21593: 00/03/26: Nicholas C. Weaver: Re: FPGA openness
21550: 00/03/24: Don Husby: Re: FPGA openness
21562: 00/03/24: Rickman: Re: FPGA openness
21587: 00/03/26: Greg Alexander: Re: FPGA openness
21729: 00/03/30: Andreas Doering: Re: FPGA openness
21534: 00/03/24: Brian Drummond: Re: FPGA openness
21484: 00/03/23: Ruben Leote Mendes: Re: FPGA openness
21500: 00/03/23: Greg Alexander: Re: FPGA openness
21455: 00/03/22: Greg Alexander: Re: FPGA openness
21462: 00/03/23: Ray Andraka: Re: FPGA openness
21467: 00/03/23: Greg Alexander: Re: FPGA openness
21480: 00/03/23: Gary Watson: Re: FPGA openness
21563: 00/03/24: Rickman: Re: FPGA openness
21574: 00/03/25: Gary Watson: Re: FPGA openness
21588: 00/03/25: Rickman: Re: FPGA openness
21597: 00/03/26: Ray Andraka: Re: FPGA openness
21603: 00/03/26: Peter Alfke: Re: FPGA openness
21607: 00/03/26: Greg Alexander: Re: FPGA openness
21609: 00/03/26: Tom Burgess: Re: FPGA openness
21611: 00/03/26: Greg Alexander: Re: FPGA openness
21619: 00/03/26: Larry Doolittle: Re: FPGA openness
21620: 00/03/26: Ben Franchuk: FPGA open source
21624: 00/03/26: Rickman: Re: FPGA open source
21596: 00/03/26: Greg Alexander: Re: FPGA openness
21598: 00/03/26: Ray Andraka: Re: FPGA openness
21608: 00/03/26: Greg Alexander: Re: FPGA openness
21599: 00/03/26: Rickman: Re: FPGA openness
21626: 00/03/27: Ray Andraka: Re: FPGA openness
21655: 00/03/28: Michael J. Ferrador: Re: FPGA openness
21487: 00/03/23: Nicholas C. Weaver: Re: FPGA openness
21498: 00/03/23: Greg Alexander: Re: FPGA openness
21504: 00/03/23: Nicholas C. Weaver: Re: FPGA openness
21506: 00/03/23: Greg Alexander: Re: FPGA openness
21483: 00/03/23: Brian Drummond: Re: FPGA openness
21485: 00/03/23: Ben Franchuk: Re: FPGA openness
21513: 00/03/24: Brian Drummond: Re: FPGA openness
21491: 00/03/23: Greg Alexander: Re: FPGA openness
21509: 00/03/23: Ray Andraka: Re: FPGA openness
21521: 00/03/24: Greg Alexander: Re: FPGA openness
21529: 00/03/24: Ray Andraka: Re: FPGA openness
21533: 00/03/24: Greg Alexander: Re: FPGA openness
21544: 00/03/24: Andrew Brown: Re: FPGA openness
21592: 00/03/26: Greg Alexander: Re: FPGA openness
21543: 00/03/24: Dave Vanden Bout: Re: FPGA openness
21555: 00/03/24: Gary Watson: Re: FPGA openness
21557: 00/03/24: Don Husby: Re: FPGA openness
21558: 00/03/24: Peter Alfke: Re: FPGA openness
21564: 00/03/24: Rickman: Re: FPGA openness
21583: 00/03/26: Robert Carney: Re: FPGA openness
21590: 00/03/25: Rickman: Re: FPGA openness
21602: 00/03/26: Ray Andraka: Re: FPGA openness
21605: 00/03/26: Peter Alfke: Re: FPGA openness
21613: 00/03/26: Rickman: Re: FPGA openness
21617: 00/03/26: Greg Alexander: Re: FPGA openness
21625: 00/03/26: Rickman: Re: FPGA openness
21627: 00/03/27: Ray Andraka: Re: FPGA openness
21630: 00/03/27: Rickman: Re: FPGA openness
21651: 00/03/28: Zoltan Kocsi: Re: FPGA openness
21681: 00/03/29: Ray Andraka: Re: FPGA openness
21685: 00/03/29: Keith R. Williams: Re: FPGA openness
21691: 00/03/29: Ray Andraka: Re: FPGA openness
21697: 00/03/29: Andrew Brown: Re: FPGA openness
21702: 00/03/29: Ray Andraka: Re: FPGA openness
21693: 00/03/29: Greg Alexander: Re: FPGA openness
21698: 00/03/29: Andrew Brown: Re: FPGA openness
21703: 00/03/29: Ray Andraka: Re: FPGA openness
21717: 00/03/29: Greg Alexander: Re: FPGA openness
21725: 00/03/30: Keith R. Williams: Re: FPGA openness
21724: 00/03/30: Keith R. Williams: Re: FPGA openness
21694: 00/03/29: Rickman: Re: FPGA openness
21704: 00/03/29: Ray Andraka: Re: FPGA openness
21723: 00/03/30: Zoltan Kocsi: Re: FPGA openness
21806: 00/04/01: Gary Watson: Re: FPGA openness
21809: 00/04/01: Zoltan Kocsi: Re: FPGA openness
21818: 00/04/02: Keith R. Williams: Re: FPGA openness
21827: 00/04/03: Zoltan Kocsi: Re: FPGA openness
21844: 00/04/04: Keith R. Williams: Re: FPGA openness
21811: 00/04/01: Peter Alfke: Re: FPGA openness
21813: 00/04/01: Gary Watson: Re: FPGA openness
21812: 00/04/01: Ray Andraka: Re: FPGA openness
21867: 00/04/04: Steve Casselman: Re: FPGA openness (JBits)
21536: 00/03/24: Brian Drummond: Re: FPGA openness
21508: 00/03/23: glen herrmannsfeldt: Re: FPGA openness
21511: 00/03/23: Ben Franchuk: Re: FPGA openness
21530: 00/03/24: Ray Andraka: Re: FPGA openness
21546: 00/03/24: Ben Franchuk: Re: FPGA openness
21514: 00/03/24: Jim Granville: SPLD Usage ?
21520: 00/03/24: <eml@riverside-machines.com.NOSPAM>: Re: FPGA openness
21541: 00/03/24: Ben Franchuk: Gate logic
21549: 00/03/24: Theron Hicks: Re: FPGA openness
21551: 00/03/24: Theron Hicks: Re: FPGA openness
21556: 00/03/24: <eml@riverside-machines.com.NOSPAM>: Re: FPGA openness
21579: 00/03/25: Stuart Clubb: Re: FPGA openness
21560: 00/03/24: muzo: Re: FPGA openness
21567: 00/03/25: Ray Andraka: Re: FPGA openness
21615: 00/03/26: muzo: Re: FPGA openness
21628: 00/03/27: Ray Andraka: Re: FPGA openness
21569: 00/03/25: <eml@riverside-machines.com.NOSPAM>: Re: FPGA openness
21616: 00/03/26: muzo: Re: FPGA openness
21535: 00/03/24: Brian Drummond: Re: FPGA openness
21505: 00/03/23: glen herrmannsfeldt: Re: FPGA openness
21507: 00/03/23: Greg Alexander: Re: FPGA openness
21436: 00/03/22: Ben Franchuk: No- FPGA openness
21449: 00/03/22: Rickman: Re: No- FPGA openness
21456: 00/03/22: Ben Franchuk: Re: No- FPGA openness
21460: 00/03/23: Greg Alexander: Re: No- FPGA openness
21468: 00/03/23: Rickman: Re: No- FPGA openness
21486: 00/03/23: Andy Peters: Re: No- FPGA openness
21492: 00/03/23: Greg Alexander: Re: No- FPGA openness
21494: 00/03/23: Andy Peters: Re: No- FPGA openness
21496: 00/03/23: Ben Franchuk: FPGA - CPU's
21503: 00/03/23: Greg Alexander: Re: FPGA - CPU's
21502: 00/03/23: Greg Alexander: Re: No- FPGA openness
21516: 00/03/24: Catalin Baetoniu: Re: No- FPGA openness
21522: 00/03/24: Greg Alexander: Re: No- FPGA openness
21559: 00/03/24: muzo: Re: No- FPGA openness
21518: 00/03/24: <eml@riverside-machines.com.NOSPAM>: Re: No- FPGA openness
21523: 00/03/24: Greg Alexander: Re: No- FPGA openness
21526: 00/03/24: <a@z.com>: Re: No- FPGA openness
21531: 00/03/24: Greg Alexander: Re: No- FPGA openness
21542: 00/03/24: Don Husby: Re: No- FPGA openness
21573: 00/03/25: Zoltan Kocsi: Re: No- FPGA openness
21601: 00/03/26: Larry Doolittle: Re: No- FPGA openness
21589: 00/03/26: Greg Alexander: Re: No- FPGA openness
21528: 00/03/24: Ray Andraka: Re: No- FPGA openness
21532: 00/03/24: Greg Alexander: Re: No- FPGA openness
21584: 00/03/25: Kelly Hall: Re: No- FPGA openness
21594: 00/03/25: Rickman: Re: No- FPGA openness
21595: 00/03/26: Greg Alexander: Re: No- FPGA openness
21527: 00/03/24: Ray Andraka: Re: No- FPGA openness
21472: 00/03/22: Kelly Hall: Re: No- FPGA openness
21457: 00/03/22: Greg Alexander: Re: No- FPGA openness
21452: 00/03/22: Ray Andraka: Re: No- FPGA openness
21701: 00/03/29: <rob_dickinson@my-deja.com>: Re: FPGA openness
21714: 00/03/29: Greg Alexander: Re: FPGA openness
21734: 00/03/30: <rob_dickinson@my-deja.com>: Re: FPGA openness
21745: 00/03/30: Greg Alexander: Re: FPGA openness
21754: 00/03/30: Ray Andraka: Re: FPGA openness
21761: 00/03/30: Greg Alexander: Re: FPGA openness
21755: 00/03/30: Ray Andraka: Re: FPGA openness
21762: 00/03/30: Greg Alexander: Re: FPGA openness
21768: 00/03/31: Ray Andraka: Re: FPGA openness
21770: 00/03/31: Greg Alexander: Re: FPGA openness
21775: 00/03/31: <rob_dickinson@my-deja.com>: Re: FPGA openness
21786: 00/03/31: Ray Andraka: Re: FPGA openness
21800: 00/03/31: Greg Alexander: Re: FPGA openness
21808: 00/04/01: Zoltan Kocsi: Re: FPGA openness
21408: 00/03/21: Tim: Virtex Secondary Clock Nets
21843: 00/04/03: Paul Gigliotti: Re: Virtex Secondary Clock Nets
21412: 00/03/22: Holger Kleinert: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
21413: 00/03/22: Nicolas Matringe: Re: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
21417: 00/03/22: Holger Kleinert: Re: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
21433: 00/03/22: John Larkin: Re: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
21440: 00/03/22: Tim: Re: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
21422: 00/03/22: Holger Kleinert: How to implement STARTBUF / GSR with SpartanXL and VHDL on FNDTN 2.1i ?
21437: 00/03/22: Jaroslaw Kubica: Re: How to implement STARTBUF / GSR with SpartanXL and VHDL on FNDTN
21438: 00/03/22: Andy Peters: Re: How to implement STARTBUF / GSR with SpartanXL and VHDL on FNDTN 2.1i ?
21426: 00/03/22: <e97bjli@thn.htu.se>: constant error in VHDL code
21435: 00/03/22: Andy Peters: Re: constant error in VHDL code
21434: 00/03/22: David Neely: FPGA Part Selection Advice
21451: 00/03/22: Rickman: Re: FPGA Part Selection Advice
21442: 00/03/22: James Horn: Windowed Altera 1810s?
21447: 00/03/22: Tom Burgess: 4000XLA bitgen problem?
21458: 00/03/22: Greg Alexander: Re: 4000XLA bitgen problem?
21554: 00/03/24: Tom Burgess: Re: 4000XLA bitgen problem?
21461: 00/03/23: <kgbee@my-deja.com>: Giving fpga's unique id
21469: 00/03/23: Rickman: Re: Giving fpga's unique id
21470: 00/03/22: Joel Kolstad: Re: Giving fpga's unique id
21471: 00/03/23: Andreas Doering: Re: Giving fpga's unique id
21473: 00/03/23: EDM: FPGA & single point failure
21571: 00/03/25: Tom Burgess: Re: FPGA & single point failure
21575: 00/03/25: John Larkin: Re: FPGA & single point failure
21585: 00/03/26: Greg Alexander: Re: FPGA & single point failure
21610: 00/03/26: Tom Burgess: Re: FPGA & single point failure
21635: 00/03/27: Kate Atkins: Re: FPGA & single point failure
21637: 00/03/27: Ray Andraka: Re: FPGA & single point failure
21641: 00/03/27: Kate Atkins: Re: FPGA & single point failure
21647: 00/03/28: Ray Andraka: Re: FPGA & single point failure
21648: 00/03/28: Jim Granville: Re: FPGA & single point failure
21649: 00/03/27: Tom Burgess: Re: FPGA & single point failure
21653: 00/03/27: rk: Re: FPGA & single point failure
21668: 00/03/28: Joe Hass: Re: FPGA & single point failure
21670: 00/03/28: Tom Burgess: Re: FPGA & single point failure
21672: 00/03/28: rk: Re: FPGA & single point failure
21708: 00/03/29: Austin Lesea: Re: FPGA & single point failure
21679: 00/03/29: Craig Taniguchi: Re: FPGA & single point failure
21683: 00/03/28: rk: Re: FPGA & single point failure
21657: 00/03/27: rk: Re: FPGA & single point failure
21658: 00/03/27: Ben Franchuk: Re: FPGA & single point failure
21631: 00/03/27: EDM: Re: FPGA & single point failure
21639: 00/03/27: Greg Neff: Re: FPGA & single point failure
21640: 00/03/27: Ben Franchuk: Re: FPGA & single point failure
21643: 00/03/27: Greg Neff: Re: FPGA & single point failure
21656: 00/03/27: rk: Re: FPGA & single point failure
21673: 00/03/28: Magnus Homann: Re: FPGA & single point failure
21675: 00/03/28: rk: Re: FPGA & single point failure
21676: 00/03/28: Greg Neff: Re: FPGA & single point failure
21687: 00/03/29: Keith R. Williams: Re: FPGA & single point failure
21700: 00/03/29: Gary Watson: Re: FPGA & single point failure
21686: 00/03/29: Keith R. Williams: Re: FPGA & single point failure
21689: 00/03/28: rk: Re: FPGA & single point failure
21726: 00/03/30: Keith R. Williams: Re: FPGA & single point failure
21730: 00/03/30: rk: Re: FPGA & single point failure
21654: 00/03/27: rk: Re: FPGA & single point failure
21677: 00/03/29: Craig Taniguchi: Re: FPGA & single point failure
21727: 00/03/29: Jonathan Feifarek: Re: FPGA & single point failure
21618: 00/03/26: Greg Neff: Re: FPGA & single point failure
21749: 00/03/30: Tom Burgess: Re: FPGA & single point failure
21474: 00/03/23: Chih-Zong Lin: [REQ] download function of Xilinx CPLD
21525: 00/03/24: Thomas Hellerforth: Re: [REQ] download function of Xilinx CPLD
21475: 00/03/23: Holger Azenhofer: DCF 77
21479: 00/03/23: Karl Olsen: Re: DCF 77
21477: 00/03/23: <apunte@apunte.es>: AUTOVITRINA.COM
21481: 00/03/23: md: IC Designers, validation engineers--Portland, OR
21490: 00/03/23: Bruce Oakley: FPGA Design Productivity Metrics
21499: 00/03/23: Gary Spivey: Re: FPGA Design Productivity Metrics
21497: 00/03/23: Steve: Preferred Configuration Approach
21667: 00/03/28: <chadlamb@my-deja.com>: Re: Preferred Configuration Approach
21510: 00/03/24: Domagoj: StateCAD
21512: 00/03/23: Anurag Tiwari: debugger
21517: 00/03/24: J.R.: ERROR:NgdHelpers:312
21537: 00/03/24: Jamie Sanderson: Altering Xilinx FPGA version/ID after PAR
21565: 00/03/24: Rickman: Re: Altering Xilinx FPGA version/ID after PAR
21570: 00/03/25: <eml@riverside-machines.com.NOSPAM>: Re: Altering Xilinx FPGA version/ID after PAR
21663: 00/03/28: Jamie Sanderson: Re: Altering Xilinx FPGA version/ID after PAR
21919: 00/04/06: Robert Binkley: Re: Altering Xilinx FPGA version/ID after PAR
21985: 00/04/11: Rick Filipkiewicz: Re: Altering Xilinx FPGA version/ID after PAR
21662: 00/03/28: Joe Linoff: Re: Altering Xilinx FPGA version/ID after PAR
21561: 00/03/24: Don Husby: Chip-to-Chip benchmarks?
21568: 00/03/25: <stefanludwig@my-deja.com>: Re: Chip-to-Chip benchmarks?
21566: 00/03/25: <spyng@my-deja.com>: Clock on non-dedicate pin
21572: 00/03/25: Jaroslaw Kubica: Re: Clock on non-dedicate pin
21622: 00/03/27: <spyng@my-deja.com>: Re: Clock on non-dedicate pin
21633: 00/03/27: Jaroslaw Kubica: Re: Clock on non-dedicate pin
21650: 00/03/28: <spyng@my-deja.com>: Re: Clock on non-dedicate pin
21660: 00/03/28: Jaroslaw Kubica: Re: Clock on non-dedicate pin
21678: 00/03/29: =?iso-2022-jp?B?GyRCMEIwZhsoQiAbJEI3chsoQg==?=: Re: Clock on non-dedicate pin
21692: 00/03/29: <spyng@my-deja.com>: Re: Clock on non-dedicate pin
21577: 00/03/25: Peter: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21578: 00/03/25: david garnett: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21600: 00/03/26: Peter: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21604: 00/03/26: Peter Alfke: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21642: 00/03/27: Peter Alfke: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21629: 00/03/27: Jim Granville: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21732: 00/03/30: Peter: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21612: 00/03/26: gerald coe: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21580: 00/03/25: Anurag Tiwari: DLL
21581: 00/03/25: Peter Alfke: Re: DLL
21582: 00/03/26: Oliver King-Smith: FPGA chip for PalmPilot
21606: 00/03/25: Taras Zima: RTL vs. gate level simulation
21646: 00/03/27: Richard Iachetta: Re: RTL vs. gate level simulation
21674: 00/03/28: Richard Iachetta: Re: RTL vs. gate level simulation
21696: 00/03/28: Taras Zima: Re: RTL vs. gate level simulation
21682: 00/03/28: Paulo Dutra: Re: RTL vs. gate level simulation
21621: 00/03/27: jeffrey j cook: Virtex DLL Spread-spectrum clock sensitivity
21835: 00/04/03: Austin Lesea: Re: Virtex DLL Spread-spectrum clock sensitivity
21860: 00/04/04: Paul Walker: Re: Virtex DLL Spread-spectrum clock sensitivity
21873: 00/04/04: Austin Lesea: Re: Virtex DLL Spread-spectrum clock sensitivity
21623: 00/03/27: tasi: [co-design] HW/SW co-design
21632: 00/03/27: Jamil Khatib: Stimulus generator
21636: 00/03/27: Gerhard Griessnig: Communication FPGA & MII
21638: 00/03/27: <sramsden@my-deja.com>: Digital Filters
21652: 00/03/28: Domagoj: FATAL_ERROR
21661: 00/03/28: <sramsden@my-deja.com>: Digital Filters - Help me!!
21665: 00/03/28: Ray Andraka: Re: Digital Filters - Help me!!
21664: 00/03/28: Mark Harvey: Xilinx DLL properties
21666: 00/03/28: <chadlamb@my-deja.com>: Re: Xilinx DLL properties
21669: 00/03/28: Ravi Bhat: Test: Please ignore...
21671: 00/03/28: Steve: CoreGen incompatible with NT SP6 and Win2K?
21911: 00/04/06: Amal Khailtash: Re: CoreGen incompatible with NT SP6 and Win2K?
21680: 00/03/29: George: VHDL at RTL level vs. floorplanning.
21688: 00/03/29: Ray Andraka: Re: VHDL at RTL level vs. floorplanning.
21712: 00/03/29: George: Re: VHDL at RTL level vs. floorplanning.
21684: 00/03/29: Allan Herriman: Virtex bitstreams wanted for compression study
21742: 00/03/30: Tim Tyler: Re: Virtex bitstreams wanted for compression study
21822: 00/04/02: Allan Herriman: Re: Virtex bitstreams wanted for compression study
21842: 00/04/03: aeeaee.com.br: Re: Virtex bitstreams wanted for compression study
21845: 00/04/04: Allan Herriman: Re: Virtex bitstreams wanted for compression study
22124: 00/04/26: Allan Herriman: Re: Virtex bitstreams wanted for compression study
21690: 00/03/29: Vaughn Betz: New Place and Route Software for Non-Commercial Research (Academic VPR
21710: 00/03/29: Tom Burgess: Re: New Place and Route Software for Non-Commercial Research (Academic
21715: 00/03/29: Steve: Re: New Place and Route Software for Non-Commercial Research (Academic VPR 4.30 Available)
21731: 00/03/30: <gnippiks@my-deja.com>: Re: New Place and Route Software for Non-Commercial Research (Academic VPR 4.30 Available)
21866: 00/04/04: Vaughn Betz: Re: New Place and Route Software for Non-Commercial Research (Academic
21865: 00/04/04: Vaughn Betz: Re: New Place and Route Software for Non-Commercial Research (Academic
21695: 00/03/29: MK Yap: tristate /driving a bidirectional port
21737: 00/03/30: Jonas Rangell: Re: tristate /driving a bidirectional port
21803: 00/04/01: MK Yap: Re: tristate /driving a bidirectional port
21699: 00/03/29: Jens Hildebrandt: LUT components in Synopsys/Xilinx design flow
21705: 00/03/29: Anshuman Sharma: VGA interface and VHDL
21736: 00/03/30: Leon Heller: Re: VGA interface and VHDL
21750: 00/03/30: Jan Gray: Re: VGA interface and VHDL
21783: 00/03/31: <gnippiks@my-deja.com>: Re: VGA interface and VHDL
22086: 00/04/20: Jim Hamblen: Re: VGA interface and VHDL
21706: 00/03/29: Kate Atkins: APS V240 board
21797: 00/03/31: Richard Schwarz: Re: APS V240 board
21829: 00/04/03: Kate Atkins: Re: APS V240 board
21707: 00/03/29: Gary Watson: Hardware TCP/IP stack?
22500: 00/05/10: Jamil Khatib: Re: Hardware TCP/IP stack?
22509: 00/05/10: <cyrilw@my-deja.com>: Re: Hardware TCP/IP stack?
21711: 00/03/29: John Lockwood: I/O characteristics of Xilinx 1804 PROM
21716: 00/03/29: Peter Alfke: Re: I/O characteristics of Xilinx 1804 PROM
21713: 00/03/29: Joe Peniston: redundant multiplier
21718: 00/03/29: Tom McLaughlin: Global clock nets. Can I use it for signal other than clock.
21719: 00/03/30: <spyng@my-deja.com>: Re: Global clock nets. Can I use it for signal other than clock.
21720: 00/03/29: Peter Alfke: Re: Global clock nets. Can I use it for signal other than clock.
21739: 00/03/30: Tom McLaughlin: Re: Global clock nets. Can I use it for signal other than clock.
21744: 00/03/30: Tim: Re: Global clock nets. Can I use it for signal other than clock.
21748: 00/03/30: Peter Alfke: Re: Global clock nets. Can I use it for signal other than clock.
21756: 00/03/30: Ray Andraka: Re: Global clock nets. Can I use it for signal other than clock.
21721: 00/03/30: M R Wheeler: MaxPlus9.5 License and Fitter problems
21735: 00/03/30: <rob_dickinson@my-deja.com>: Re: MaxPlus9.5 License and Fitter problems
21765: 00/03/31: M R Wheeler: Re: MaxPlus9.5 License and Fitter problems
21856: 00/04/04: Tim: Re: MaxPlus9.5 License and Fitter problems
21870: 00/04/04: Vaughn Betz: Re: MaxPlus9.5 License and Fitter problems
21875: 00/04/05: Ray Andraka: Re: MaxPlus9.5 License and Fitter problems
21881: 00/04/05: Tim: Re: MaxPlus9.5 License and Fitter problems
21888: 00/04/05: Ray Andraka: Re: MaxPlus9.5 License and Fitter problems
21879: 00/04/05: Tim: Re: MaxPlus9.5 License and Fitter problems
21883: 00/04/05: Vaughn Betz: Re: MaxPlus9.5 License and Fitter problems
22095: 00/04/21: Jim Hamblen: Re: MaxPlus9.5 License and Fitter problems
21722: 00/03/30: Anoop Nannra: 10 gbit/s input
21733: 00/03/30: Tom Burgess: Re: 10 gbit/s input
21753: 00/03/30: Ray Andraka: Re: 10 gbit/s input
21728: 00/03/30: Chuck Carlson: Foundation 2.1 Macro HIZ outputs
21738: 00/03/30: Jamil Khatib: Memory cores
21741: 00/03/30: Eric Friedrichs: Re: Memory cores
21743: 00/03/30: David Kessner: Re: Memory cores
21757: 00/03/30: Ray Andraka: Re: Memory cores
21886: 00/04/05: Janos Ero: Re: Memory cores
21892: 00/04/05: Ray Andraka: Re: Memory cores
21895: 00/04/06: Janos Ero: Re: Memory cores
21907: 00/04/06: Ray Andraka: Re: Memory cores
21740: 00/03/30: Nestor Caouras: Pipelined ALTERA LPMs - where are the registers introduced?
21772: 00/03/31: Psycho333221: Re: Pipelined ALTERA LPMs - where are the registers introduced?
21840: 00/04/03: Nestor: Re: Pipelined ALTERA LPMs - where are the registers introduced?
21852: 00/04/04: <rob_dickinson@my-deja.com>: Re: Pipelined ALTERA LPMs - where are the registers introduced?
21746: 00/03/30: <fulvs@my-deja.com>: What's so good about antifuse???
21747: 00/03/30: HH: Re: What's so good about antifuse???
21752: 00/03/30: Peter Alfke: Re: What's so good about antifuse???
21759: 00/03/30: Ray Andraka: Re: What's so good about antifuse???
21751: 00/03/30: Peter Alfke: Re: What's so good about antifuse???
21794: 00/03/31: Andrew M. Dyer: Re: What's so good about antifuse???
21869: 00/04/04: rk: Re: What's so good about antifuse???
21758: 00/03/30: Ray Andraka: Re: What's so good about antifuse???
21763: 00/03/30: John Larkin: Re: What's so good about antifuse???
21774: 00/03/31: David Miller: Actel ProASIC
21781: 00/03/31: Hans Holm: RE: ANTIFUSE AND XILINX
21787: 00/03/31: Ray Andraka: Re: ANTIFUSE AND XILINX
21799: 00/04/01: Luigi Funes: Re: What's so good about antifuse???
21821: 00/04/02: Assaf Sarfati: Re: What's so good about antifuse???
21760: 00/03/30: Anshuman Sharma: Adrian Thompson's and GA work on Xilinx
21766: 00/03/30: Rickman: Re: Adrian Thompson's and GA work on Xilinx
21767: 00/03/31: Dave Vanden Bout: Re: Adrian Thompson's and GA work on Xilinx
21769: 00/03/31: Greg Alexander: Re: Adrian Thompson's and GA work on Xilinx
21773: 00/03/31: Andreas Doering: Re: Adrian Thompson's and GA work on Xilinx
21790: 00/03/31: Steven K. Knapp: Re: Adrian Thompson's and GA work on Xilinx
21804: 00/03/31: Rickman: Re: Adrian Thompson's and GA work on Xilinx
21807: 00/04/01: Dave Vanden Bout: Re: Adrian Thompson's and GA work on Xilinx
21810: 00/04/01: Rickman: Re: Adrian Thompson's and GA work on Xilinx
21780: 00/03/31: <gnippiks@my-deja.com>: Re: Adrian Thompson's and GA work on Xilinx
21789: 00/03/31: Craig Slorach: Re: Adrian Thompson's and GA work on Xilinx
21831: 00/04/03: Graham Seaman: Re: Adrian Thompson's and GA work on Xilinx
21848: 00/04/04: Craig Slorach: Re: Adrian Thompson's and GA work on Xilinx
21801: 00/03/31: Delon Levi: Re: Adrian Thompson's and GA work on Xilinx
21764: 00/03/30: Andy Peters: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21777: 00/03/31: Tom Burgess: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21791: 00/03/31: Andy Peters: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21796: 00/03/31: Etienne Racine: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21798: 00/03/31: Tom Burgess: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21784: 00/03/31: Etienne Racine: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21793: 00/03/31: Andy Peters: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21858: 00/04/04: John Chambers: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21863: 00/04/04: Andy Peters: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21771: 00/03/31: TeikMing Goh: Synthesize components within a block using FPGA compiler
21776: 00/03/31: Tomasz Brychcy: 82C54
21785: 00/03/31: Jens Hildebrandt: Re: 82C54
21788: 00/03/31: Ray Andraka: Re: 82C54
21819: 00/04/02: Marc Elpel: Re: 82C54
21778: 00/03/31: Tomasz Brychcy: Warning during synthesis
21779: 00/03/31: <spyng@my-deja.com>: physical macro (Xilinx)
21795: 00/03/31: Hartono: Modem Pooling using Fpga
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
