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Messages from 21850

Article: 21850
Subject: Re: Tired of paying your ISP?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 04 Apr 2000 05:33:43 -0400
Links: << >>  << T >>  << A >>
CrADEEkC@cWbEARxg.com wrote:
> 
> Thats right, Totally Free Internet Access, Just log on to
> 
> http://reallyfreeinternet.com and sign up. Instant access, No waiting. And best of all, No Ads Or Banners to spoil your surfing.


It may be free, but you get what you pay for. I signed up a few days ago
and have had trouble with email ever since. They claim they are
"upgrading" their servers. I guess that takes some time.


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21851
Subject: JTAG programming
From: "Grzegorz" <g_lis@microtech.com.pl>
Date: Tue, 04 Apr 2000 09:40:43 GMT
Links: << >>  << T >>  << A >>
Hi there,

Perhaps it's obvious for some of You...
I've got six devices in JTAG chain. 3 x Xilinx XLA 4000 series, AMD DSP
proc, 2x Xilinx 9500 series.
Everything looks OK, init is low, bsd files are correct and I get such an
error:

JTAG Programmer Started 2000/03/30 10:04:12
Loading Boundary-Scan Description Language (BSDL) file
'c:\xilinx\xc4000xla\data\xc4085xla_hq240.bsd'.....completed successfully.
Loading Boundary-Scan Description Language (BSDL) file
'c:\xilinx\xc4000xla\data\xc4044xla_bg352.bsd'.....completed successfully.
Loading Boundary-Scan Description Language (BSDL) file
'd:\dsp\bsdl_21160_pbga.bsd'.....completed successfully.
Loading Boundary-Scan Description Language (BSDL) file
'c:\xilinx\xc9500\data\xc95108.bsd'.....completed successfully.
Checking boundary-scan chain integrity...done.
Verifying device positions in boundary-scan chain...
Instance '(Device1)' at position '1'...ERROR:JTag - The IDCODE returned
(00000000001000111000000010010000) indicates that the
instance '(Device1)' in the boundary-scan chain is not a Xilinx part.
failed.
Instance '(Device2)' at position '2'...ERROR:JTag - The IDCODE returned
(00000000001000111000000010010000) indicates that the
instance '(Device2)' in the boundary-scan chain is not a Xilinx part.
failed.
Instance '(Device3)' at position '3'...ERROR:JTag - The IDCODE returned
(00000000001000101000000010010000) indicates that the
instance '(Device3)' in the boundary-scan chain is not a Xilinx part.
failed.
Instance '(Device5)' at position '5'...verified.
Instance '(Device6)' at position '6'...verified.
Verification completed.
ERROR:JTag - Boundary scan chain has been improperly specified. Please check
your configuration and re-enter the boundary-scan
chain information.
Boundary-scan chain validated unsuccessfully.
ERROR:JTag - : The boundary-scan chain has not been declared correctly.
Verify the syntax and correctness of the device BSDL files, correct the
files,
reset the cable and retry this command.

Note that programmer ignores processor. Returned IDCODE is almost correct.
The diferecce is on two bits: manufacturer and IEEE1149.1 compliance
Did anyone see such a problem? What it could be ?
Another thing is:  what else could I do to narrow the problem down ?
Thanks for any help.

Grzegorz.


Article: 21852
Subject: Re: Pipelined ALTERA LPMs - where are the registers introduced?
From: rob_dickinson@my-deja.com
Date: Tue, 04 Apr 2000 10:03:54 GMT
Links: << >>  << T >>  << A >>
In article <38e37f7d.181595150@News21.qc.aira.com>,
nestor@stansync.com (Nestor Caouras) wrote:
> Hi everyone.
>
> I have a very simple question regarding the ALTERA LPMs. I am
> currently using the ALTERA FLEX10K100 series for a project at work and
> I would like to use some of ALTERA's LPMs in pipelined form in order
> to speed up my design.
>
> My question:
> Assuming I want only one PIPELINE stage, where is it introduced in the
> macro? At the output stage, so that the macro is composed of a
> combinational circuit followed by a register? Is this general for all
> of ALTERA's macros?
>

> Your help is greatly appreciated.
>
> Thanks in advance.
>
> Nestor Caouras
> Tel.: (514) 356-0634 Fax.: (514) 356-0165
> email: nestor@stansync.com
>
I've never pipelined an LPM but have used LPM's a lot.  They are
allways poorly documented and the best way to work it out is to compile
the macro.  It's not rocket science, your macro just becomes some AHDL
which you can find with the design hierarchy view.  Reverse engineering
is allways a pain but it will get you there.


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 21853
Subject: No net is connected....... ( xilinx)
From: e97bjli@thn.htu.se
Date: Tue, 04 Apr 2000 10:24:01 GMT
Links: << >>  << T >>  << A >>
Hi

I recived an error message:

"No net is connected to the set/reset pin of Cell........"

Using Spartan s10.

This error message occured then i synthesis then code.

What's worng?

I leve my code at the bottom of this mail:

Thankful for help

Björn

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

library SYNOPSYS;						--
integer deklaration
use SYNOPSYS.attributes.all;

entity vhld0311 is
    port (
			clk:        in       STD_LOGIC;

			q0:        	inout       STD_LOGIC;
			read:       in
STD_LOGIC;
			INFYR:      in       STD_LOGIC_VECTOR(2 DOWNTO
0);
			ad_signal:  in       STD_LOGIC_VECTOR(7 DOWNTO
0);
			b1_c:  		inout          STD_LOGIC_VECTOR
(7 DOWNTO 0);
			b0_c:  		inout          STD_LOGIC_VECTOR
(7 DOWNTO 0);
			OUTFYR:     out      STD_LOGIC_VECTOR(2 DOWNTO
0);

			bw     :    inout    STD_LOGIC;
			mt     :    inout
STD_LOGIC;
			klocka:     inout    STD_LOGIC_VECTOR(15 DOWNTO
0); --20??
			korsvector:   inout    STD_LOGIC_VECTOR(14
DOWNTO 0);
			ad1_signal: inout    STD_LOGIC_VECTOR(7 DOWNTO
0);
			write:       out       STD_LOGIC

         );
end vhld0311;

--******************************************************
--*                                                    *
--*        ARCHITECTURE VHDL2000.03.11.                *
--*                                                    *
--******************************************************

architecture vhld0311_arch of vhld0311 is

	signal summa,s1,s2,korssumma: integer range -20 to 20;
	signal klocka1: std_logic_vector(15 downto 0);


	constant testvector: std_logic_vector(14 downto
0):="111101011001000";
	constant mt_limit: std_logic_vector(7 downto 0):="10000000";
	constant bw_limit: std_logic_vector(7 downto 0):="10010000";
	constant ad_limit: std_logic_vector(7 downto 0):="00000110";


begin
--******************************************************
--*
								 *
--*							FYR
							 *
--*
								 *
--******************************************************
fyr: process(clk)

begin

	if clk='1' and clk'event then

		if read='1' then     --read skall vara ett tills korr
klar

			OUTFYR  <=INFYR;
			--switch satser????
		else

 			OUTFYR  <=(others=>'0');

      end if; --start='1'

   end if; --clk='1'

end process; --fyr

--******************************************************
--*
								 *
--*							CLOCK
							 *
--*
								 *
--******************************************************
clock: process(clk)

begin

	if clk='1' and clk'event then

		if read='1' then     --read skall vara ett tills korr
klar

			klocka<=klocka+1;
		else

 			klocka  <=(others=>'0');

      end if; --start='1'

   end if; --clk='1'

end process; --clock

--******************************************************
--*
								 *
--*							AGC
							 *
--*
								 *
--******************************************************
--agc: process(clk)

--begin

--	if (clk='1' and clk'event) then

--		if read='1' then

--			if	ad_signal>=ad_limit and agc_val='0' then
--			agc_val<='1';
	--		agc_adress<=ad_adress;
--			end if;

--			ad_adress<=ad_adress+1;
--
--			if ad_signal>=ad_limit and agc_val='0'  then
--			agc_val<='1';
--			agc_adress<=ad_adress;

--			end if;

--			ad_adress<=ad_adress+1;
--			if ad_signal>=ad_limit and agc_val='0'  then
--			agc_val<='1';
--			agc_adress<=ad_adress;

--			end if;

--			if ad_adress="011" then
--				ad_adress<="001";
--			end if; --ad_adress

--		else
--			agc_val<='0';
--			agc_adress<=(others=>'0');
--			ad_adress<="001";
--

--		end if; --read='0'

--
--	end if; --if clk'event
--end process; --agc

--processen helvagslikriktar och tar ut barvagen.
--******************************************************
--*
								 *
--*					bw_process
						 *
--*
								 *
--******************************************************
bw_process: process(clk)

begin

	if clk='1' and clk'event then

		--if agc_val='1' then

			if (ad_signal /= ad1_signal) and (ad_signal /=
not ad1_signal) then

				if ad1_signal<bw_limit and
ad_signal>=bw_limit then

					bw<= not bw;

				elsif ad1_signal<bw_limit and not
ad_signal>=bw_limit then

					bw<= not bw;

				end if; --ad1 and ad

				if ad_signal>mt_limit then

					mt<='1';
				else		--if not
ad_signal>"bw_limit" then

					mt<='0';

				end if; --ad<<<<<mt

				if ad_signal(7)='0' then

					ad1_signal<= not ad_signal;

				else

					ad1_signal<=ad_signal;

				end if; -- ad(7)

				if bw='1' and q0='0' then

					if mt=bw then

						b1_c<=b1_c+1;

						if b1_c=10 or b1_c=30
or b1_c=50 or b1_c=70 then

							korsvector(14
downto 1)<=korsvector(13 downto 0);
							korsvector(0)
<='1';

						end if; --b0_c=10 or
b0_c=30 or b0_c=50 or b0_c=70
						b0_c<=(others=>'0');

					end if; --mt=bw


					if mt/=bw then

						b0_c<=b0_c+1;




						if b0_c=10 or b0_c=30
or b0_c=50 or b0_c=70 then

							korsvector(14
downto 1)<=korsvector(13 downto 0);
							korsvector(0)
<='0';

						end if; --b1_c=10 or
b1_c=30 or b1_c=50 or b1_c=70

						b1_c<=(others=>'0');


					end if; --mt/=bw


				end if; --bw='1'

				if bw /= q0 then

				q0<=bw;

				end if; --bw/=q0

			end if; --ad /=ad1


		--end if; --agc_val='1'

	end if; --clk='1''event

end process; --bw_process

--******************************************************
--*
								 *
--*				Korskorrelation
				 *
--*
								 *
--******************************************************

korskorrelation: process(clk)

begin

	if clk='1' and clk'event then

		summa<=0;

	  for i in 0 to 14 loop

	  	if korsvector(i)/=testvector(i) then

	  		summa<=summa-1;

	  	elsif korsvector(i)=testvector(i) then

	  		summa<=summa+1;

	  	end if; --korsvector=0

	  	if summa/=s1 then

	  		if s1>summa and s1>s2 then

				if abs(summa)>abs(korssumma) then

					klocka1<=klocka;
					korssumma<=summa;

				end if; --abs(summa)

	  		end if; -- s1>summa and s1>s2
			--s1=summa osv
	  	end if; --summa/=s1
	  end loop; --for i 0 to 14

	end if; --clk='1'

end process; --korskorrelation

end vhld0311_arch;


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Before you buy.
Article: 21854
Subject: Re: Xilinx student edition, version 1.5
From: myself@magma.ca (myself)
Date: Tue, 04 Apr 2000 12:05:38 GMT
Links: << >>  << T >>  << A >>
Thanks for the help.
I contacted xilinx and they confermed that
" it does allow VHDL and Verilog as input. The devices include all of
the Spartan and XC9500 families as well as the XC4000 and XC4000XL
families up to 10,000 gates."

also that
"Version 2.1i of the student edition will be available from Prentice
Hall in the
July timeframe."

thanks again I think I will get v2.1 in July.


On Mon, 3 Apr 2000 15:10:51 -0400, Luke Roth <roth@spaten.cse.psu.edu>
wrote:

>	Yes, I've used it a bit.  The student package comes with a limited
>version of the Foundation tools, v1.5.  It is several steps behing the
>current version (v2.1i, IIRC) but is perfecty functional.  It is limited
>to devices no larger that the XC4010, but it does handle both VHDL
>synthesis and schematic entry.
>	The book that comes with it is well written for a beginner, and
>most of its example designs are shown using VHDL, ABEL, and schematic
>entry.  It's not a comprehensive reference, but the examples are well
>written (if a bit basic).  I have heard that Xilinx will be upgrading the
>package to use the v2.1 foundation tools (which support the newer
>SpartanII/Virtex architecture, probably with the same gate count
>limitation) for the fall semester.
>	Luke
>
>On Mon, 3 Apr 2000, myself wrote:
>
>> Hi 
>> has Anyone used the
>> Xilinx student edition, version 1.5
>> 
>> I am unclear on the software that comes with this book!
>> I want to write VHDL code for  FPGA's. 
>> I am not interested in schematic entry.
>> 
>> 
>> Does this book cover VHDL? 
>> Does this book include the "Foundation" series of software?
>> What series and version is it? (Does it support VHDL)?
>> 
>> Any other books that come with vhdl software and practical examples? 
>> 
>> Martin Brown
>> 
>> 
>

Article: 21855
Subject: Re: JTAG programming
From: "Jean-Paul GOGLIO" <goglio@getris.com>
Date: Tue, 4 Apr 2000 14:05:59 +0200
Links: << >>  << T >>  << A >>

Grzegorz wrote

>Hi there,
>
>Perhaps it's obvious for some of You...
>I've got six devices in JTAG chain. 3 x Xilinx XLA 4000 series, AMD DSP
>proc, 2x Xilinx 9500 series.
>Everything looks OK, init is low, bsd files are correct and I get such an
>error:
>
>JTAG Programmer Started 2000/03/30 10:04:12
>Loading Boundary-Scan Description Language (BSDL) file
>'c:\xilinx\xc4000xla\data\xc4085xla_hq240.bsd'.....completed successfully.
>Loading Boundary-Scan Description Language (BSDL) file
>'c:\xilinx\xc4000xla\data\xc4044xla_bg352.bsd'.....completed successfully.
>Loading Boundary-Scan Description Language (BSDL) file
>'d:\dsp\bsdl_21160_pbga.bsd'.....completed successfully.
>Loading Boundary-Scan Description Language (BSDL) file
>'c:\xilinx\xc9500\data\xc95108.bsd'.....completed successfully.
>Checking boundary-scan chain integrity...done.
>Verifying device positions in boundary-scan chain...
>Instance '(Device1)' at position '1'...ERROR:JTag - The IDCODE returned
>(00000000001000111000000010010000) indicates that the
>instance '(Device1)' in the boundary-scan chain is not a Xilinx part.
>failed.
>Instance '(Device2)' at position '2'...ERROR:JTag - The IDCODE returned
>(00000000001000111000000010010000) indicates that the
>instance '(Device2)' in the boundary-scan chain is not a Xilinx part.
>failed.
>Instance '(Device3)' at position '3'...ERROR:JTag - The IDCODE returned
>(00000000001000101000000010010000) indicates that the
>instance '(Device3)' in the boundary-scan chain is not a Xilinx part.
>failed.
>Instance '(Device5)' at position '5'...verified.
>Instance '(Device6)' at position '6'...verified.
>Verification completed.
>ERROR:JTag - Boundary scan chain has been improperly specified. Please
check
>your configuration and re-enter the boundary-scan
>chain information.
>Boundary-scan chain validated unsuccessfully.
>ERROR:JTag - : The boundary-scan chain has not been declared correctly.
>Verify the syntax and correctness of the device BSDL files, correct the
>files,
>reset the cable and retry this command.
>
>Note that programmer ignores processor. Returned IDCODE is almost correct.
>The diferecce is on two bits: manufacturer and IEEE1149.1 compliance
>Did anyone see such a problem? What it could be ?
>Another thing is:  what else could I do to narrow the problem down ?
>Thanks for any help.
>
>Grzegorz.
>
>

We got a similar problem with a board including about 12 Xilinx FPGA and 7
Sharc DSP in a single JTAG Chain.
The Xilinx JTAG programmer didn't see the FPGA that were after a DSP in the
chain and the DSP emulator didn't work if the DSP were not first in the
chain. (We checked that BSDL files for DSP were OK, but we found no
solution)

So we had to split the JTAG chain in 2 chains, one for xilinx chips, and one
other for DSP. After that, it worked fine.

If someone knows a best solution...

J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
Tel : (33) 4 76 18 52 10
E-mail : goglio@getris.com
Fax : (33) 4 76 18 52 01



Article: 21856
Subject: Re: MaxPlus9.5 License and Fitter problems
From: timjeno@visto.com (Tim )
Date: Tue, 04 Apr 2000 12:44:03 GMT
Links: << >>  << T >>  << A >>
On Thu, 30 Mar 2000 02:14:26 GMT, "M R Wheeler"
<intell-a-sys@iquest.net> wrote:

>I am evaluating MaxPlus 9.5 and am finding that often the software can not
>seem to locate the dongle during the build process on larger designs.  The
>software give me a license error message.  Also, when selecting the Quartus
>fitter, I am getting internal errors (contact Altera, who never has a
>clue).  Both problems occur on two different computers.  Just wonder if
>anyone else is using this version yet.  
>

I haven't had any problems using our floating network license.  I also
haven't had any crashes yet.  Still, each new version fixes a thousand
bugs and adds a thousand more so we'll see.

Oh, I did have to turn off the Quartus fitter to make the timing
requirement in a design that easily makes the timing requirements in
9.3.

Up to 25xs faster compile....the gods of marketing are feeling playful
today.

                            Tim.

Article: 21857
Subject: XCS05XL de Xilinx
From: "Vicente Marti" <lavhek@teleline.es>
Date: Tue, 4 Apr 2000 17:21:16 +0200
Links: << >>  << T >>  << A >>
Desearia poder conseguir informacion en castellano sobre la FPGA
XCS05XL de Xilinx


Article: 21858
Subject: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
From: John Chambers <JohnC@ihr.mrc.ac.uk>
Date: Tue, 04 Apr 2000 16:30:38 +0100
Links: << >>  << T >>  << A >>
My local Lattice rep told me today that they have available code to
program all major FPGA manufactures hardware (including Xilinx) from a
Lattice programming cable.  Might be worth a look.

Article: 21859
Subject: Replication control in Xilinx P&R
From: Thomas Ekberg <thomas.ekberg@netinsight.net>
Date: Tue, 04 Apr 2000 15:39:54 GMT
Links: << >>  << T >>  << A >>
I'm trying to implement an asynchronous fifo in Xilinx Virtex,
according to Xilinx App note XAPP131.

I'm concerned about replication of the fifo flags, empty and
full, which must not be replicated. If they are, there is a
risk that a replicated flipflop gets the wrong value compared
to the flop it is replicating. This is due a comparison
between two pointers in different clock domains is made, and the
result is placed in the flag flop.

Is there a way to ensure that the Xilinx P&R tool does not replicate
these flops?

-- 
Thomas Ekberg              Net Insight AB
Article: 21860
Subject: Re: Virtex DLL Spread-spectrum clock sensitivity
From: Paul Walker <paul@4Links.co.uk>
Date: Tue, 4 Apr 2000 17:15:06 +0100
Links: << >>  << T >>  << A >>
In article <38E8C167.9FB3FAD0@xilinx.com>, Austin Lesea
<austin.lesea@xilinx.com> writes
>Are you intending to apply a spread spectrum clock to the input of the DLL?

I'd like to. This looks like a useful piece of apps work that you are
doing, and I'd be very interested in hearing which spread-spectrum clock
the tests are done with and how it behaves.

Once the results are reported, an even better follow-up would be for
Xilinx and IMI to get together and specify the parameters in such a way
that it is obvious to a user just what can be done. At present it looks
promising, but the parameters are expressed differently and so the users
can not tell exactly what is possible and what will give problems.
>
>If this is the case, the absolute, edge to edge change in delay (frequency) can
>not be any greater than that stated in the data sheet.  The reason for this is
>that the loop will not be able to track and lock if the edge to edge change
>prevents the detectors from figuring out when a complete cycle is in the delay
>line.
>
>As long as the edge to edge change is not exceeded, the DLL is designed to track
>over voltage and temperature variations, so that even though FM'ing or PM'ing
>modulation will be of greater deviation and faster than a voltage or temperature
>variation, the loop should track it just fine.
>
>We are doing some measurements now, and should have results in a week or so.
>
>I would also expect that if the change (however slow) was too great, the delay
>line would eventually lose the edge by stepping off the end.  I am trying to
>quantify "too great".

-- 
Paul Walker                            Chair of the 1355 Association
                                                        www.1355.org
4Links: 
Boards, chips, IP and consultancy ... for links 
                                                           phone/fax
paul@4Links.co.uk             P O Box 816, Two Mile Ash     +44 1908
http://www.4Links.co.uk       Milton Keynes MK8 8NS, UK       566253

Article: 21861
Subject: Curso gratuito de VHDL
From: "Michael García Lorenz" <lorenz@ing.uc3m.es>
Date: Tue, 4 Apr 2000 18:39:36 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

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Curso gratuito de VHDL Financiado por la Unión Europea.
Fechas 7 de Abril a 28 abril, horario de tarde. Ver Diapositiva adjunta de
PowerPoint.
Para más información e inscripciones:

"Diseño Electrónico Asistido por Ordenador II: Lenguajes de Descripción de
Hardware" (Curso 38)

Fundación Universidad Carlos III de Madrid
Avda. de la Universidad, 30
28911 Leganés (Madrid)
Tfno. 91 624 59 69

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Content-Disposition: attachment;
	filename="vhdl2000.ppt"

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Article: 21862
Subject: Re: No net is connected....... ( xilinx)
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Tue, 4 Apr 2000 09:46:24 -0700
Links: << >>  << T >>  << A >>
e97bjli@thn.htu.se wrote in message <8ccfrp$fch$1@nnrp1.deja.com>...
>Hi
>
>I recived an error message:
>
>"No net is connected to the set/reset pin of Cell........"
>
>Using Spartan s10.
>
>This error message occured then i synthesis then code.
>
>What's worng?


None of your flip-flops have reset clauses...

for instance, if you add/modify the lines without the '>', you're adding a
reset net.

>fyr: process(clk, reset)
>begin
    if reset = '1' then
        OUTFYR <= '0';
    elsif clk='1' and clk'event then
>         if read='1' then     --read skall vara ett tills korr
>            OUTFYR  <=INFYR;
>         --switch satser????
>         else
>             OUTFYR  <=(others=>'0');
>      end if; --start='1'
>   end if; --clk='1'
>end process; --fyr


--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens



Article: 21863
Subject: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Tue, 4 Apr 2000 09:50:31 -0700
Links: << >>  << T >>  << A >>
John Chambers wrote in message <38EA0A9E.568D66BA@ihr.mrc.ac.uk>...
>My local Lattice rep told me today that they have available code to
>program all major FPGA manufactures hardware (including Xilinx) from a
>Lattice programming cable.  Might be worth a look.

It's backwards - I have the Xilinx cable and want to program the Lattice
part!

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens



Article: 21864
Subject: Re: Replication control in Xilinx P&R
From: "Dan" <dan@kvdco.com>
Date: Tue, 4 Apr 2000 10:38:08 -0700
Links: << >>  << T >>  << A >>
Thomas

There is an environment variable called CM_EXCLUDE_XQYQ that you can set to
turn off register replication.  The problem is that it turns register
replication off for the entire design.  It would be nice if there were an
attribute that you could attach to the instance, but I do not know of any
such option.

Check you Xilinx technical document 3818

http://support.xilinx.com/techdocs/3813.htm


Dan Hicks
KVD


"Thomas Ekberg" <thomas.ekberg@netinsight.net> wrote in message
news:38EA0CCA.6F369D87@netinsight.net...
> I'm trying to implement an asynchronous fifo in Xilinx Virtex,
> according to Xilinx App note XAPP131.
>
> I'm concerned about replication of the fifo flags, empty and
> full, which must not be replicated. If they are, there is a
> risk that a replicated flipflop gets the wrong value compared
> to the flop it is replicating. This is due a comparison
> between two pointers in different clock domains is made, and the
> result is placed in the flag flop.
>
> Is there a way to ensure that the Xilinx P&R tool does not replicate
> these flops?
>
> --
> Thomas Ekberg              Net Insight AB


Article: 21865
Subject: Re: New Place and Route Software for Non-Commercial Research (Academic
From: Vaughn Betz <vaughn@rtrack.com>
Date: Tue, 04 Apr 2000 18:24:30 GMT
Links: << >>  << T >>  << A >>
I've fixed the link to that paper now.  Sorry about that.

Vaughn

Tom Burgess wrote:
> 
> Is the software usable with any real FPGAs or it is just an academic exercise?
> Tried to download paper, but it was
> 
> >Not Found
> >
> >The requested URL /~vaughn/papers/fpl97.ps.gz was not found on this server.
> 
> Vaughn Betz wrote:
> >
> > A new version of the "academic" VPR and T-VPack packing, placement and routing
> > CAD tool set for research is available on my web site.  This latest version
> > includes the enhancements Alexander (Sandy) Marquardt made to VPR during his
> > M. S. degree -- timing-driven logic block packing and timing-driven placement.
> > It can be freely used for non-commercial research, and can be downloaded
> > from:
> >
> > http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html
> >
> > Just for clarity, this code is the "academic" (i.e. code written at the
> > Univerity of Toronto during various students' grad degrees) VPR -- it is not
> > the code for the more recent, commercial version of VPR.
> >
> > Vaughn Betz
> 
> regards,
> Tom Burgess
> --
> Digital Engineer
> Dominion Radio Astrophysical Observatory
> P.O. Box 248, Penticton, B.C.
> Canada V2A 6K3
> Email:        tom.burgess@hia.nrc.ca

Article: 21866
Subject: Re: New Place and Route Software for Non-Commercial Research (Academic
From: Vaughn Betz <vaughn@rtrack.com>
Date: Tue, 04 Apr 2000 18:36:43 GMT
Links: << >>  << T >>  << A >>
The synopsis in the previous posting was correct.   The code I've
posted on my web site is not what went into MaxPlus2 9.5.  It is code
that was written at the University of Toronto to do research into FPGAs.
As such, it does not target any commercial FPGA architecture, 
but is instead intended to get results on architectures that researchers 
come up with and describe to the tool.  It is not an easy job to 
make the academic VPR target a commercial FPGA, as doing a precise
architecture capture is quite a lot of work, and the academic VPR does
not support things like carry chains that are in pretty much all commercial
architectures.

As the previous poster said, several of the authors of the academic VPR
started a company to commercialize it, and that commercial code is in 
MaxPlus2 9.5.  This commercial VPR is a totally separate (and much enhanced)
code base, and is not on my web site.

Vaughn

gnippiks@my-deja.com wrote:
> 
> In article <lauE4.42019$pA.130208@typhoon.mbnet.mb.ca>,
> "Steve" <reply.through.newsgroup@paranoid.com> wrote:
> >
> > Tom Burgess <tom.burgess@hia.nrc.ca> wrote in message
> > news:38E245D1.B020618E@hia.nrc.ca...
> > > Is the software usable with any real FPGAs or it is just an academic
> > exercise?
> >
> > Isn't this the stuff Altera is picking up?
> >
> > Steve
> >
> >
> 
> Well the technology in VPR has been commercialized by Right Track CAD
> (see http://www.rtrack.com/ and http://www.rtrack.com/technology.html )
> and incorporated in version 9.5 of MAX+PLUS II.
> 
> See this press release: http://www.altera.com/html/new/pressrel/pr-mp9.5.html
> VPR's timing-driven packing, placement, and routing algorithms have been
> incorporated in MAX+PLUS II.
> 
> The "academic non-commercial research" version just released also
> incorporates timing-driven algorithms, but they are probably more
> generic (i.e. not tuned to Altera's architecture).
> 
> The academic VPR allows to define your own FPGA architectural parameters
> so you could target it to Xilinx- or Altera-like architectures, but
> you won't be able to generate a bitstream from it and I don't think you can
> even pass a placed and routed netlist to the Xilinx or Altera tools.
> 
> The academic VPR is mainly a tool for research into FPGA architectures
> and CAD algorithms.  (The founders of Right Track CAD have written
> a book on these topics: http://www.wkap.nl/book.htm/0-7923-8460-1 )
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

Article: 21867
Subject: Re: FPGA openness (JBits)
From: "Steve Casselman" <sc@vcc.com>
Date: Tue, 4 Apr 2000 14:16:47 -0700
Links: << >>  << T >>  << A >>
You can manipulate all the bits and you can write all the tools you want by
using JBits. It is as close as you really want to get and it can be used to
reverse engineer the bit stream if you want.

Steve Casselman, President
Virtual Computer Corporation


Article: 21868
Subject: Initialization of Ram in a marco
From: "Steve Casselman" <sc@vcc.com>
Date: Tue, 4 Apr 2000 14:42:04 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_0064_01BF9E43.F1DB45E0
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	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

I reported a bug 2 service packs ago and I'm wondering if anyone has the =
same problem or a fix.

I desgned a controler using viewlogic which has hierarchical ram control =
store. I also have a C compiler that generates (what was at that time a =
ucf and is now a ncf) file initializes the ram. Works great with 1.5. =
Now however all ram is supposed to be initulized in the NCF file. The =
problem is that the NCF file is read BEFORE the design is resolved. In =
other words the software tries to find the ram before it reads in the =
entire design. So design "alpha" calls out macro "beta" I have a =
alpha.ngo and a beta.ngo. The ram is in beta and the software reads =
alpha reads the NCF file and bombs because it can't find "beta". The =
fact that the NCF file is read in the translator and the design is =
resolved in the mapper doesn't make sense to me.=20

The Hotline put in a notice to the software group 6 months ago I think =
that is a little too long to fix something so trivial. =20



Steve Casselman, President

Virtual Computer Corporation


------=_NextPart_000_0064_01BF9E43.F1DB45E0
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2920.0" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY>
<DIV>
<P><FONT face=3DArial size=3D2>I reported a bug 2 service packs ago and =
I'm=20
wondering if anyone has the same problem or a fix.</FONT></P>
<P><FONT face=3DArial size=3D2>I desgned a controler using viewlogic =
which has=20
hierarchical ram control store. I also have a C compiler that generates =
(what=20
was at that time a ucf and is now a ncf) file initializes the ram. Works =
great=20
with 1.5. Now however all ram is supposed to be initulized in the NCF =
file. The=20
problem is that the NCF file is read BEFORE the design is resolved. In =
other=20
words the software tries to find the ram before it&nbsp;reads in the =
entire=20
design. So design "alpha" calls out macro "beta" I have a alpha.ngo and =
a=20
beta.ngo. The ram is in beta and the software reads alpha reads the NCF =
file and=20
bombs because it can't find "beta". The fact that the NCF file is read =
in the=20
translator and the design is resolved in the mapper doesn't make sense =
to me.=20
</FONT></P>
<P><FONT face=3DArial><FONT size=3D2>The Hotline put in a notice to the =
software=20
group 6 months ago I think that is a little too long&nbsp;to fix =
something so=20
trivial.  </FONT></FONT></P>
<P><FONT face=3DArial></FONT>&nbsp;</P>
<P><FONT face=3DArial><FONT size=3D2>Steve Casselman, =
President</FONT></FONT></P>
<P><FONT face=3DArial><FONT size=3D2>Virtual Computer=20
Corporation</FONT></P></FONT></DIV></BODY></HTML>

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Article: 21869
Subject: Re: What's so good about antifuse???
From: rk <stellare@nospam.erols.com>
Date: Tue, 04 Apr 2000 18:10:32 -0400
Links: << >>  << T >>  << A >>
Hi Peter,

Peter Alfke wrote:

> You may get different answers from different people, and definitely
> from different companies. But since there is hardly anybody else
> here representing the vendors, and since Xilinx at one time designed
> and even made antifuse devices, here is my answer:

< snip >

> Remaining advantages: Instant-on, single-chip, and a certain degree
> of radiation-resistance.
>
> There are only two manufacturers: Actel ( the larger and older one
> ), and Quicklogic (the younger and smaller one ).
>
> I think this was a reasonably unbiased and fair explanation. Let the
> flames start!

Well, I would like to avoid flames and here's a comment or two.

First, from the various manufacturers who make antifuse devices, it's
not clear that any of them have "instant-on" at this time.  From
www.dictionary.com, instant (adj):

     Occurring at once; immediate

The amount of time it might take an antifuse device to start depends on
a number of factors including it's design and the ramp rate of the power
supply.  This can be important for critical systems; for example, those
that control explosives, critical relays, etc.  It's also not an
academic point or hair-splitting - there are examples of system failures
when engineers did not take the start up time/characteristics into
account.

Secondly, there are two other companies that make antifuse-based logic
devices.  UTMC makes a 22VP10 and two models of PROM (amorphous silicon
antifuse) while Lockheed-Martin also makes PROMs, using an ONO type
antifuse.

Have a good evening,

rk


Article: 21870
Subject: Re: MaxPlus9.5 License and Fitter problems
From: Vaughn Betz <vaughn@rtrack.com>
Date: Tue, 04 Apr 2000 22:17:10 GMT
Links: << >>  << T >>  << A >>
Hmmm ... it is very unusual for the Quartus fitter in MaxPlus2 9.5 to make a slower
circuit than MaxPlus2 9.3.  Here are some MaxPlus2 settings that, if set improperly, 
will hurt your speed, so you may want to check them.

1.  You should make sure you've turned on timing-driven compilation (by default
it is turned off).

Go to Assign->Global Project Timing Requirements and set an Fmax, 
Tsu, Tpd, or Tco constraint (depending on what kind of timing you're interested
in) *and* turn off the check-box in "Ignore Timing Requirements During Fitting."

2.  Also make sure that your logic optimization settings 
(Assign->Global Project Logic Synthesis) allow carry and cascade chains.
By default, the Normal synthesis style is used, which turns them off.
Use WYSIWYG instead (or Fast, but I haven't tried this setting).  Turning
off carry and cascade chains usually slows circuits down by about 20%.
The new fitter in 9.5 is very good at handling carry chains, so there's 
rarely a reason to turn them off due to fitting issues.

3.  Also make sure you have the Quartus fitter selected.

The 25x faster compile time is for timing-driven compiles.  The new fitter
in MaxPlus2 9.5 was really intended to be run in timing-driven mode unless
the user truly does not care at all about timing.  It usually takes this fitter
little extra CPU time to do a timing-driven compile, and the resulting circuit
speed averages about 30% better than the results of a non-timing-driven
compile (more than 30% better for large, 10K100 or above designs, less than
30% for smaller designs, typically).  What size of design are you compiling?

Vaughn Betz
Right Track CAD Corp.

Tim wrote:
> 
> On Thu, 30 Mar 2000 02:14:26 GMT, "M R Wheeler"
> <intell-a-sys@iquest.net> wrote:
> 
> >I am evaluating MaxPlus 9.5 and am finding that often the software can not
> >seem to locate the dongle during the build process on larger designs.  The
> >software give me a license error message.  Also, when selecting the Quartus
> >fitter, I am getting internal errors (contact Altera, who never has a
> >clue).  Both problems occur on two different computers.  Just wonder if
> >anyone else is using this version yet.
> >
> 
> I haven't had any problems using our floating network license.  I also
> haven't had any crashes yet.  Still, each new version fixes a thousand
> bugs and adds a thousand more so we'll see.
> 
> Oh, I did have to turn off the Quartus fitter to make the timing
> requirement in a design that easily makes the timing requirements in
> 9.3.
> 
> Up to 25xs faster compile....the gods of marketing are feeling playful
> today.
> 
>                             Tim.
Article: 21871
Subject: Clocks and BUFGP
From: Chuck Carlson <sanna@wco.com>
Date: Tue, 04 Apr 2000 22:56:13 GMT
Links: << >>  << T >>  << A >>
I'm using BUFGP to drive a clock and the docs seem to indicate it
can be connected to K and F3 pins of a CLB only.  I've been trying
to find such a CLB in the library and cannot.  Does anyone know
of CLB's that BUFGP can drive?

Thanks

Chuck


Article: 21872
Subject: Re: Clocks and BUFGP
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Tue, 4 Apr 2000 16:06:45 -0700
Links: << >>  << T >>  << A >>
Chuck Carlson wrote in message ...
>I'm using BUFGP to drive a clock and the docs seem to indicate it
>can be connected to K and F3 pins of a CLB only.  I've been trying
>to find such a CLB in the library and cannot.  Does anyone know
>of CLB's that BUFGP can drive?

K is the clock input to the flops in the CLB.


--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens



Article: 21873
Subject: Re: Virtex DLL Spread-spectrum clock sensitivity
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 04 Apr 2000 16:24:30 -0700
Links: << >>  << T >>  << A >>
Paul,

So far, I am unable to cause the DLL to lose lock by sinewave FM modulation of a
clock source (operating at 25 MHz).  Modulation spreading of ~10% of the clock's
frequency at a modulation frequency of up to 200 KHz results in the DLL just loafing
along, re-adjusting its taps to keep one entire cycle of the clock period in the
delay line at all times.

I believe the SS clock chips use less than 2% of a spread in the frequency.

I am in the process of getting equipment that can modulate up to 1/10 of the clock
rate, at deviations of a few cycles (not an easy task).

I will keep everyone posted on results when I can finally cause the DLL to lose lock,
or prevent it from locking on startup.  So far, I can not cause either to happen with
the equipment on hand.

Remember that the FCC is examining the "loophole" of the use of SS clocks in
equipment to get by with less shielding.  The idea that the FCC could change the
rules, and obsolete the entire SS clock chip business means that we are unlikely to
spend much effort on this other than to characterize the jitter tolerance of the DLL.

Austin

Paul Walker wrote:

> In article <38E8C167.9FB3FAD0@xilinx.com>, Austin Lesea
> <austin.lesea@xilinx.com> writes
> >Are you intending to apply a spread spectrum clock to the input of the DLL?
>
> I'd like to. This looks like a useful piece of apps work that you are
> doing, and I'd be very interested in hearing which spread-spectrum clock
> the tests are done with and how it behaves.
>
> Once the results are reported, an even better follow-up would be for
> Xilinx and IMI to get together and specify the parameters in such a way
> that it is obvious to a user just what can be done. At present it looks
> promising, but the parameters are expressed differently and so the users
> can not tell exactly what is possible and what will give problems.
> >
> >If this is the case, the absolute, edge to edge change in delay (frequency) can
> >not be any greater than that stated in the data sheet.  The reason for this is
> >that the loop will not be able to track and lock if the edge to edge change
> >prevents the detectors from figuring out when a complete cycle is in the delay
> >line.
> >
> >As long as the edge to edge change is not exceeded, the DLL is designed to track
> >over voltage and temperature variations, so that even though FM'ing or PM'ing
> >modulation will be of greater deviation and faster than a voltage or temperature
> >variation, the loop should track it just fine.
> >
> >We are doing some measurements now, and should have results in a week or so.
> >
> >I would also expect that if the change (however slow) was too great, the delay
> >line would eventually lose the edge by stepping off the end.  I am trying to
> >quantify "too great".
>
> --
> Paul Walker                            Chair of the 1355 Association
>                                                         www.1355.org
> 4Links:
> Boards, chips, IP and consultancy ... for links
>                                                            phone/fax
> paul@4Links.co.uk             P O Box 816, Two Mile Ash     +44 1908
> http://www.4Links.co.uk       Milton Keynes MK8 8NS, UK       566253

Article: 21874
Subject: Re: Replication control in Xilinx P&R
From: Bret Wade <bret.wade@xilinx.com>
Date: Tue, 04 Apr 2000 17:37:08 -0600
Links: << >>  << T >>  << A >>
Hello Thomas and Dan,

The CM_EXCLUDE_XQYQ variable only applies to the 4K architectures. The Virtex
router doesn't do any register replication, so this isn't an issue there. And
no, there isn't any way to disable the replication individually for the 4K
devices except to ensure that the register involved is combined into a CLB with
another register (using RLOC or BLKNM attributes) so that the replication won't
be necessary.

Regards,
Bret Wade
Xilinx Product Applications

Dan wrote:

> Thomas
>
> There is an environment variable called CM_EXCLUDE_XQYQ that you can set to
> turn off register replication.  The problem is that it turns register
> replication off for the entire design.  It would be nice if there were an
> attribute that you could attach to the instance, but I do not know of any
> such option.
>
> Check you Xilinx technical document 3818
>
> http://support.xilinx.com/techdocs/3813.htm
>
> Dan Hicks
> KVD
>
> "Thomas Ekberg" <thomas.ekberg@netinsight.net> wrote in message
> news:38EA0CCA.6F369D87@netinsight.net...
> > I'm trying to implement an asynchronous fifo in Xilinx Virtex,
> > according to Xilinx App note XAPP131.
> >
> > I'm concerned about replication of the fifo flags, empty and
> > full, which must not be replicated. If they are, there is a
> > risk that a replicated flipflop gets the wrong value compared
> > to the flop it is replicating. This is due a comparison
> > between two pointers in different clock domains is made, and the
> > result is placed in the flag flop.
> >
> > Is there a way to ensure that the Xilinx P&R tool does not replicate
> > these flops?
> >
> > --
> > Thomas Ekberg              Net Insight AB



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