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Nope, I installed it the day after they posted it on the website. Everything is running fine. Mine's NT4.0 SP 4 on a dual pentium pro 200 w/ 256MB RAM. It took forever to download (About 16 hours). Is it possible your download wasn't complete? Xilinx: It would be nice if you mailed the SP to your customers when it is that big! Andy Peters wrote: > Anyone else have problems installing this on an NT box? A bunch of DLLs > were forgotten and things just wouldn't work. > > -a > > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "Creation Science" is oxymoronic. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18651
In article <3821e21a.163120114@nntp.best.com>, bob@nospam.thanks (Bob Perlman) wrote: <snip> > The excess setup time Rick is referring to here is for the > flip-flop(s) being driven by the synchronizing flip-flop. <snip> Yup, I misread Rick's post. My apologies to Rick. The only danger with eliminating the second register prior to fanout, is that a metastable event can end up having much more unpredictable effects on the system. Some of the destination registers might settle one way, and the rest settle the other way. This can be hard to analyze and account for in the system design. In a fanout situation, I like to see the probability in the order of tens of millions of years between events. To achieve this we often still use a two stage register, prior to fanout to the other (third stage) flip flops. Every clock edge is a roll of the dice. I don't know about you, but I'm not much of a gambling man. I like to keep things as close to deterministic as possible. Even if the design is not safety/mission critical, it is not good for customers to have to deal with unreproduceable system glitches or failures. Sometimes I wonder if Microsoft was trying to simulate metastable flip-flops when they wrote Windows ;) -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18652
In article <7vt105$1v5f$1@noao.edu>, "Andy Peters" <apeters.nospam@nospam.noao.edu.nospam> wrote: > Anyone else have problems installing this on an NT box? A bunch of DLLs > were forgotten and things just wouldn't work. > > -a > > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "Creation Science" is oxymoronic. > > We loaded ours as a networked installation on a Windows NT V4.5 Back Office Server. I am running it on a Windows 98 Release 2 client, and everything is OK so far. I have not tried to run right on the server. The sys admin would probably shoot me if I did :) <flame on> BTW, You would think that Xilinx would mail out some CD's, instead of expecting us to download almost 90MB of stuff from the web site. Unfortunately, not all of us have high speed internet service available in our areas. <flame off> Good luck. You might want to try downloading SP2 again, in case it got corrupted during download. We installed both the programs patch and the speed files patch at the same time. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18653
Kwong Chan wrote: > > Peter C <peterc@hmgcc.gov.uk> wrote in message > news:38200B8D.5DF@hmgcc.gov.uk... > > > Yes (at least for those families that have 5-input CLBs). > > But when I compile some 5-input functions such as the > following sample code, the FPGA compiler maps the function into > 2 or 3 CLBs. > > Do I need to convert the true-table into Boolean function first? > > --sample code > entity FIVE_INPUT is > port (DIN: in std_logic_vector(4 downto 0); > DOUT: out std_logic); > end FIVE_INPUT; > > architecture BEHAV of FIVE_INPUT is > begin > process (DIN) > begin > case DIN is > when "00000"=> DOUT <='1'; > ....... > when "11111"=>DOUT<'1'; > when others=>DOUT<='X'; > end case; > end process; > end BEHAV; Is it the VHDL compiler output that is causing more CLBs to be used? Analysing the result in FPGA Editor would allow you to see exactly what the resulting logic is. Once you can see why it's using 2 or 3 CLBs then you may be able to re-code the design to use less. I'm not familiar enough with VHDL to be sure what will be produced from your code (much more with ABEL and schematics), but VHDL written in different ways (to acheive the same result) can cause more or less CLBs to be used. -- Peter CrightonArticle: 18654
Hi Alexander, > Hi All, > > Has anybody experience with TRAC020 chip from > http://www.fas.co.uk/silicon.htm? > Their data sheet does not mention possibility of any programming for > resistors > and capacitors in the matrix. Is that just specification omission? The internal resistors and capacitors are not programmable. JörgArticle: 18655
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Article: 18656I am administrator for the engineering tools here and have installed this service pack on half a dozen NT machines with no problems like you describe. The only problem I encountered, which produced an error message, was due to an background process unexpectedly still running and locking the file so the installer could not overwrite it. I now make sure that I reboot the PC before running the installer. Donald F. Frevele Senior Engineer, Technical Services MARCONI Aerospace Systems Inc. (formerly GEC-Marconi Hazeltine Corp) In article <7vt105$1v5f$1@noao.edu>, "Andy Peters" <apeters.nospam@nospam.noao.edu.nospam> wrote: > Anyone else have problems installing this on an NT box? A bunch of DLLs > were forgotten and things just wouldn't work. > > -a > > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "Creation Science" is oxymoronic. > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18657
I'm trying to make a bus master PCI interface with an AMCC5933 and a Coolrunner PLD, and I'm having real problems getting dma transfers to work for more than a few words - specifically, transfers of greater than about 16 words usually hang the pci bus after a few (or many) transfers. Any help, information or suggestions of a suitable ng would be very welcome ! regards, Dave Garnett And yes, I know that the internal fifo is 16 words long, but I also know that it is emptied as fast as stuff comes in, so the obvious problem is not occuring ...Article: 18658
Greg Neff wrote: > > In article <3821e21a.163120114@nntp.best.com>, > bob@nospam.thanks (Bob Perlman) wrote: > > <snip> > > The excess setup time Rick is referring to here is for the > > flip-flop(s) being driven by the synchronizing flip-flop. > <snip> > > Yup, I misread Rick's post. My apologies to Rick. > > The only danger with eliminating the second register prior to fanout, > is that a metastable event can end up having much more unpredictable > effects on the system. Some of the destination registers might settle > one way, and the rest settle the other way. This can be hard to > analyze and account for in the system design. In a fanout situation, I > like to see the probability in the order of tens of millions of years > between events. To achieve this we often still use a two stage > register, prior to fanout to the other (third stage) flip flops. > > Every clock edge is a roll of the dice. I don't know about you, but > I'm not much of a gambling man. I like to keep things as close to > deterministic as possible. Even if the design is not safety/mission > critical, it is not good for customers to have to deal with > unreproduceable system glitches or failures. Sometimes I wonder if > Microsoft was trying to simulate metastable flip-flops when they wrote > Windows ;) Perhaps my post was not clear. I did make one mistatement, but it made my view more conservative than I intended. I said that a precondition to removing one FF in the metastability resolution circuit was if there was sufficient set up time to the next FF AND the following FF was a single FF. That is the situation you are saying you would like to see. In reality I don't think this is needed. Peter Alfke and the others who have analyzed metastability have shown that it is exponentially related to the extra settling time provided. So 4 nS is much more than twice as good as 2 nS. In fact the current generation of Xilinx devices will settle with near certainty in about just a few nS. Of course you can never completely eliminate the possibility of getting a wrong result. But you can reduce it to say... once in a thousand years. So even if your input signal is feeding multiple FFs, providing one extra clock cycle with minimal routing delays will provide enough protection against metastability issues that it is extremely unlikely that your system will fail in your lifetime. The problem with adding an extra FF is the clock cycle delay it can cause. In many applications this is transparent. But is some, every clock cycle counts. As others have posted, if you remove the extra FF (or even if you don't) you need to use timing constraints to assure that you have enough excess setup time in your metastability resolution path. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 18659
Ray Andraka wrote: > > Nope, I installed it the day after they posted it on the website. > Everything is running fine. Mine's NT4.0 SP 4 on a dual pentium pro 200 w/ > 256MB RAM. It took forever to download (About 16 hours). Is it possible > your download wasn't complete? Xilinx: It would be nice if you mailed the > SP to your customers when it is that big! I have suggested this on one of the previous SPs that took a day to download on my machine. It seems that everybody thinks in terms of theoretical bestcase download times. Unfortunately my phone company (or ISP) has made some changes lately that only allow me to achive sub 20KBPS connection speed most of the time. Even downloading overnight gets into a problem where I need to try 4 or 5 times to get a complete download without being cut off by line conditions. This also blocks fax reception since I share the phone line with the fax machine and some people send faxes overnight. The response I got from Xlinx on this problem was something along the line of "you should look into a higher speed connection to the internet". I will when they offer something in my area, but in the meantime it is a little bit absurd to ask people to download files of 45 MB and up. I believe that they told me the service packs are on the next Applinx CDROM they send out. But they don't time the CD release with SP releases. How 'bout it Xilinx? You send out CDROMs with other info on them. Instead of letting Marketing decide when to release them, why not ship them when you have a new SP release? In their defence, when I made enough noise about it, they did send me a CD with the info on it, IIRC. But I think it took an extra couple/three weeks after I asked for them to finallize the CD. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 18660
project wrote: > > Where can I find an address with FPGA prices? Or what is > aproximately the prize of an FPGA? > Thanks > > * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is Beautiful You can get pricing from several distributor's web sites, but it won't be very accurate. They then to list the highest prices they charge. I have found that FPGA prices are a bit like car prices. If you take the first price you are given, you paid too much. It is best to call and get a quote based on your quantity, even if that quantity is small. As long as you do some volume with that disti, they will discount FPGA prices. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 18661
I had the same problem.
I downloaded Xilinx M2.1i SP2 using a high speed connection to the internet
but when I tried to install it on my NT machine I had the DLL problems that
you mention.
After that I copied the service pack to a zip drive and took it home. It
installed great on my MSW98 machine so there was not a problem with the
download. I never got it to work on my NT machine.
I hate the whole way MS uses DLL's. All the sharing and overwriting leads to
these kinds of problems.
Pete Dudley
Andy Peters <apeters.nospam@nospam.noao.edu.nospam> wrote in message
news:7vt105$1v5f$1@noao.edu...
> Anyone else have problems installing this on an NT box? A bunch of DLLs
> were forgotten and things just wouldn't work.
>
> -a
>
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
>
> "Creation Science" is oxymoronic.
>
>
Article: 18662In article <3822DBF7.96730D2C@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: <snip> > The problem with adding an extra FF is the clock cycle delay it can > cause. In many applications this is transparent. But is some, every > clock cycle counts. As others have posted, if you remove the extra FF > (or even if you don't) you need to use timing constraints to assure that > you have enough excess setup time in your metastability resolution path. > <snip> Agreed. The bottom line is that this is an area requiring some work on the part of the engineer. For each asynchronous input, the engineer has to make a tradeoff between probability of metatstability, and increased flip-flop count and signal delay. As you have pointed out, the new FPGAs with much shorter routing delays make this a much easier problem to contend with, except for very high frequency clocks. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18663
I recently did a similar design, but with a XC4000XLA part instead. The only time I ever saw the PCI bus hang, was when using the pass though interface. If the PCI bus did a read or write to the AMCC part, and my state machine never completed the transfer, the PCI bus would stall forever. It is possible to do standard PCI read/write transfers at the same time the AMCC part is doing its DMA transfer but the state machine is tricky. Also, double check that your AMCC fifo is set correctly. The two modes are syncronous and asyncronous depending on your PLD implenetaion. I never have seen the PCI bus hang during a bus master transfer. So you might look at where you are transfering your data to. Good luck Dan david garnett <dave.garnett@metapurple.co.uk> wrote in message news:7vum2f$lji$1@lure.pipex.net... > I'm trying to make a bus master PCI interface with an AMCC5933 and a > Coolrunner PLD, and I'm having real problems getting dma transfers to work > for more than a few words - specifically, transfers of greater than about 16 > words usually hang the pci bus after a few (or many) transfers. Any help, > information or suggestions of a suitable ng would be very welcome ! > > regards, Dave Garnett > > And yes, I know that the internal fifo is 16 words long, but I also know > that it is emptied as fast as stuff comes in, so the obvious problem is not > occuring ... > >Article: 18664
Ray Andraka wrote in message <382236A0.BA6BF6F0@ids.net>... >Nope, I installed it the day after they posted it on the website. >Everything is running fine. Mine's NT4.0 SP 4 on a dual pentium pro 200 w/ >256MB RAM. It took forever to download (About 16 hours). Is it possible >your download wasn't complete? Xilinx: It would be nice if you mailed the >SP to your customers when it is that big! We have a reasonably high-speed connection here; took about half an hour to download it all. I'll download it again. Perhaps something got corrupted in transit, but I really doubt it because a Xilinx tech support guy e-mailed every DLL in his bin directory and that seemed to solve the problem. harrumph. send me the CD and I'll install it. -- a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu "Creation Science" is oxymoronic.Article: 18665
Alexander Sherstuk schrieb in Nachricht <7vt13m$8su$1@bull.east.ru>... >Hi All, > > Has anybody experience with TRAC020 chip from >http://www.fas.co.uk/silicon.htm? >Their data sheet does not mention possibility of any programming for >resistors >and capacitors in the matrix. Is that just specification omission? Just studying the data sheet I came to the following conclusion (I don't know if I am right). The chip consists of 20 operational amplifiers which are organized in two signal pathes (1,3,5,..19 and 2,4,...,20). The function of these are programmable with 3 bits (ADD,NEGATE,PASS,AUX,RECTIFIER,ANTI-LOG,LOG,OFF). Normally, the two pathes form a chain, that means, that the output of OP1 goes to OP3 a. s. o. The connection signals are also availabe at pins IO3..IO22. The internal resistors for all OPs have the same value (ADD can only add). If you want amplification, differentiation or integration, you have to set one OP to OFF (000) and the following to AUX. You can then add *external* resistors/capacitors on the appropriate pins. For example you can set OP1 to OFF and OP3 to AUX and add a 2K and 4K resistor between IO1,IO3 and IO5. Then you get an amplifier which doubles the input voltage on IO1 at IO5. So the conclusion is - routing is not programmable - internal resistors/capacitors are not programmable - no internal capacitors Nevertheless I find the design rather interesting Reiner huober@vs.dasa.deArticle: 18666
fixed! xilinx tech support said that I should try putting the downloaded archive into C:\TEMP and install from there. that worked. of course, I had to clean up enough free space on C: to do that, which is why I didn't install it from there in the first place! -a Andy Peters wrote in message <7vt105$1v5f$1@noao.edu>... >Anyone else have problems installing this on an NT box? A bunch of DLLs >were forgotten and things just wouldn't work. > >-a > -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu "Creation Science" is oxymoronic.Article: 18667
Brian Philofsky wrote: > > > > If you wish to simulate the design with logic level delays but not > wire delays, this is possible if you run the synthesized netlist > through the Xilinx M1 tools to the Map stage. Run the ncd file that > Map outputs through ngdanno and then run the nga file from ngdanno > through ngd2vhdl. The command sequence will look like: > > ngdbuild <design_netlist> > map -o logic_sim.ncd <design>.ngd > ngdanno logic_sim.ncd > ngd2vhdl logic_sim.nga > > > The output of ngd2vhdl will be a structual VHDL file and an SDF file > containing only logic delays. > > > >> Hi, >> >> we would like to simulate an FPGA design after logic synthesis (for >> Xilinx XC4036) but before doing any place and route. I.e. we want to >> >> simulate the delays of the logic, but not of the wires. >> >> Is there a way to do this (with design compiler and vss)? >> >> I understand that we can write a vhdl netlist from design compiler >> after >> synthesis. But this netlist is not simulatable, e.g. it contains >> iob_4000 components for which we do not have simulation models. >> >> Any help on this would be appreciated, >> >> Joe >> > If you want to go via the MAP route you will have to compile & use the Xilinx simulation primitive library ``simprims''. I don't know the state of the VHDL one but I've found a fair number of problems with the Verilog ones. At least in 2.1i the Verilog LUT models work but there are still errors & issues in some of the others. For the other alternative of going via an FPGA Express netlist might mean using the ``unisims'' library which, as far as I can see from my Verilog experiance, is much cruder than the simprims one.Article: 18668
Ray Andraka <randraka@ids.net> wrote in message news:3820ED00.3C346516@ids.net... > Yes this is correct. You can put any 5 input boolean function into one > Xilinx 4K CLB. The tools don't always do that (in fact there is a switch > that will disable 5 input functions). If you know what you want, then you > can specify it using Fmaps and Hmaps. How to do this? >The 4K structure is a pair of 4 input > look-up tables (LUTs) followed by a 3 input LUT. Each LUT can be programmed > for any boolean function of the number of inputs to that LUT. For a 5 input > function, the 3 LUT is programmed as a multiplexer to select from one of the > two 4-LUTs. 4 bits of your input go to both 4 LUTs and the 5th bit controls > the 3LUT mux. I have tried this before but not always successful. I divided a 5-input function into two 4-bit input functions, say f1 and f2, and used the remaining bit as a selection to select the output from f1 or f2. When the two functions f1 and f2 were compiled seperately, they all fitted into the F-generator of the CLB. However, when I combined f1 and f2 and the selection bit in one process, two or more CLBs were required for some functions. Why and how to solve this?Article: 18669
It is a bit painful to do in using an HDL. If you were working with schematics, you just label the signals going into and out of the logic in question. Then put an FMAP (for the 4LUT) or HMAP (for the 3 LUT) symbol on the schematic with the same signals attached to it and you are done (you can also specify placement then by putting an RLOC= attribute on the F or Hmap). With synthesis, there is no easy or standard way to do this. There are several ways to go about it, not all work with all tools. The first option is to do a black box instantiation of the LUT primitives. For each, you will need to put an initial value in HEx which corresponds to the program for that LUT (see the Xilinx library guide for details). This is a pain to do, and is very hard to read. I've heard that you can create and instantiate an FMAP primitive and put it in parallel with the logic you wish to contain. I haven't gotten that to work in Synplicity because of problems with the port directions (causes a multiple driver error in synplicity). Last time I checked FPGA express, it ate the FMAPs, so they weren't there in when the mapper needed them. Evan Shattock at riverside-machines has some floorplanning info on his website that deals with how to do it with exemplar. (http://www.riverside-machines.com/pub2/xilinx/vhdl_rpm/top.htm) With synplicity, you can create a component and put the synplicity xc_fmap attribute on the component's architecture. That works fine, and is probably the most readable. It does create extra levels of hierarchy and is still a lot harder to read than RTL level code. This is the method I've had the most luck with. All of these wind up using the synthesis tool as a textual netlister - not really what synthesis is for. For this low level stuff, it is much much faster to do it as a schematic. Where the VHDL buys you something in these cases is the ability to make parameterized macros if the structure is more or less regular. For example, you can put together a generic FIR filter whose input width, coefficient width, coefficient values, number of taps, etc is provided at compile time. It takes a lot longer to make the parameterized code, but then next time you need that piece you just plug in the numbers an run it. With schematics, it means replacing pieces and relabeling busses to change bit widths. Kwong Chan wrote: > Ray Andraka <randraka@ids.net> wrote in message > news:3820ED00.3C346516@ids.net... > > Yes this is correct. You can put any 5 input boolean function into one > > Xilinx 4K CLB. The tools don't always do that (in fact there is a switch > > that will disable 5 input functions). If you know what you want, then you > > can specify it using Fmaps and Hmaps. > > How to do this? > > >The 4K structure is a pair of 4 input > > look-up tables (LUTs) followed by a 3 input LUT. Each LUT can be > programmed > > for any boolean function of the number of inputs to that LUT. For a 5 > input > > function, the 3 LUT is programmed as a multiplexer to select from one of > the > > two 4-LUTs. 4 bits of your input go to both 4 LUTs and the 5th bit > controls > > the 3LUT mux. > > I have tried this before but not always successful. I divided a 5-input > function into > two 4-bit input functions, say f1 and f2, and used the remaining bit as a > selection to > select the output from f1 or f2. When the two functions f1 and f2 were > compiled > seperately, they all fitted into the F-generator of the CLB. However, when I > combined f1 and f2 and the selection bit in one process, two or more CLBs > were > required for some functions. Why and how to solve this? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18670
Greg Neff wrote: > > In article <3822DBF7.96730D2C@yahoo.com>, > Rickman <spamgoeshere4@yahoo.com> wrote: > <snip> > > The problem with adding an extra FF is the clock cycle delay it can > > cause. In many applications this is transparent. But is some, every > > clock cycle counts. As others have posted, if you remove the extra FF > > (or even if you don't) you need to use timing constraints to assure > that > > you have enough excess setup time in your metastability resolution > path. > > > <snip> > > Agreed. The bottom line is that this is an area requiring some work on > the part of the engineer. For each asynchronous input, the engineer > has to make a tradeoff between probability of metatstability, and > increased flip-flop count and signal delay. As you have pointed out, > the new FPGAs with much shorter routing delays make this a much easier > problem to contend with, except for very high frequency clocks. I would agree with that 100%! -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 18671
Hi, I am trying to get a 16MHz Frequency from a 24MHz Clock on a Altera EPM7128. The 24MHz Clock is connected to one of the global clock inputs. Can anyone help me in doing this in AHDL ? Regards Anton ErasmusArticle: 18672
Hi Ray, What do you think of the idea of building special FPGA for DSP. I mean new FPGA that has more powerful Processing Elements (PE) that are capable of for example 16-bit arithmetic operations. Is it a good idea (worth of investigation), and do you expect to get huge performance out of it? My regards, Ahmad. ---------------------------------------------------------------------------- ------------------ Ray Andraka Wrote: Ray Andraka schrieb in Nachricht <3820377F.AA64DEE@ids.net>... >FPGAs allow you build a processing pipeline customized to the process you need to do. Using low level parallelism, you get potentially huge processing gains >over a microprocessor based DSP system. If for example you needed to add a list of numbers you need to do at least log2(n)-1 additions. In an FPGA you can >construct a tree of adders so all the additions are performed at the same time. In a microprocessor, there is usually only one adder so you need to do the >additions one at a time. > >As an example of the FPGA's processing power, look at the "FPGAs make a radar signal processor on a chip a reality" paper on my website. In that case, the >FPGA is performing over 10 billion multiplies per second on a 130 MHz clock (that's more than 80 multiplies per clock cycle). The processor is a pair of 256 >tap complex matched filters, a pair of quadrature phase detect demodulators and doppler pulse pair averagers. Thats about than 2 orders of magnitude more >performance than you will get out of the fastest DSP microprocessors today. > >An ASIC solution can outperform an FPGA, but involves a significant NRE cost and any flexibility has to be in the design. The FPGA solution can approach the >performance of an ASIC based system without giving up the flexibility and low volume economy. > >project wrote: > >> Why implement a DSP in a FPGA? Advantages of FPGA versus >> another systems. >> >> * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is Beautiful > > > >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email randraka@ids.net >http://users.ids.net/~randraka > >Article: 18673
There is much in the literature in that regard already. Many try to include multipliers and such. Problem is, as you get more complicated blocks, the harder it is to generalize to get the ideal block and the harder it is to fit your algorithm to the block. If you take that to the extreme, you wind up with a DSP microprocessor. When you have bigger blocks, you will have less of them for a given silicon area, and if they are function specific, then you run into a limited resource problem. The real power of using FPGAs is the ability to break the algorithms down into component parts and recombine the algorithm computation in a clever way to take advantage of the architecture. I think the current crop of FPGAs are pretty well suited to DSP, although (as I have mentioned here before) some are better suited than others. Ahmad A. wrote: > Hi Ray, > What do you think of the idea of building special FPGA for DSP. I mean new > FPGA that has more powerful Processing Elements (PE) that are capable of for > example 16-bit arithmetic operations. Is it a good idea (worth of > investigation), and do you expect to get huge performance out of it? > > My regards, > Ahmad. > > ---------------------------------------------------------------------------- > ------------------ > > Ray Andraka Wrote: > Ray Andraka schrieb in Nachricht <3820377F.AA64DEE@ids.net>... > >FPGAs allow you build a processing pipeline customized to the process you > need to do. Using low level parallelism, you get potentially huge > processing gains > >over a microprocessor based DSP system. If for example you needed to add a > list of numbers you need to do at least log2(n)-1 additions. In an FPGA you > can > >construct a tree of adders so all the additions are performed at the same > time. In a microprocessor, there is usually only one adder so you need to > do the > >additions one at a time. > > > >As an example of the FPGA's processing power, look at the "FPGAs make a > radar signal processor on a chip a reality" paper on my website. In that > case, the > >FPGA is performing over 10 billion multiplies per second on a 130 MHz clock > (that's more than 80 multiplies per clock cycle). The processor is a pair > of 256 > >tap complex matched filters, a pair of quadrature phase detect demodulators > and doppler pulse pair averagers. Thats about than 2 orders of magnitude > more > >performance than you will get out of the fastest DSP microprocessors today. > > > >An ASIC solution can outperform an FPGA, but involves a significant NRE > cost and any flexibility has to be in the design. The FPGA solution can > approach the > >performance of an ASIC based system without giving up the flexibility and > low volume economy. > > > >project wrote: > > > >> Why implement a DSP in a FPGA? Advantages of FPGA versus > >> another systems. > >> > >> * Sent from AltaVista http://www.altavista.com Where you can also find > related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is > Beautiful > > > > > > > >-- > >-Ray Andraka, P.E. > >President, the Andraka Consulting Group, Inc. > >401/884-7930 Fax 401/884-7950 > >email randraka@ids.net > >http://users.ids.net/~randraka > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18674
In article <3823BBB6.97D9D980@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > Greg Neff wrote: > > > > In article <3822DBF7.96730D2C@yahoo.com>, > > Rickman <spamgoeshere4@yahoo.com> wrote: > > <snip> > > > The problem with adding an extra FF is the clock cycle delay it can > > > cause. In many applications this is transparent. But is some, every > > > clock cycle counts. As others have posted, if you remove the extra FF > > > (or even if you don't) you need to use timing constraints to assure > > that > > > you have enough excess setup time in your metastability resolution > > path. > > > > > <snip> > > > > Agreed. The bottom line is that this is an area requiring some work on > > the part of the engineer. For each asynchronous input, the engineer > > has to make a tradeoff between probability of metatstability, and > > increased flip-flop count and signal delay. As you have pointed out, > > the new FPGAs with much shorter routing delays make this a much easier > > problem to contend with, except for very high frequency clocks. > > I would agree with that 100%! > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.
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