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Threads Starting Jul 1996
3582: 96/07/01: Ray Andraka: Re: REQ:Old Picture of Bus
3595: 96/07/02: William Stallings: Re: REQ:Old Picture of Bus
3583: 96/07/01: Ben Stuyts: Re: REQ:Old Picture of Bus
3585: 96/07/01: Douglas W. Jones,201H MLH,3193350740,3193382879: Re: REQ:Old Picture of Bus
3584: 96/07/01: Technisource: WANTED: SOME HELP PLEASE
3587: 96/07/02: alain arnaud: XUMA Digest #9
3591: 96/07/02: Trevor Hall: Re: XUMA Digest #9
3588: 96/07/02: Abdelhak Zoubir: ISSPA 96
3590: 96/07/02: Andre Klindworth: Using MAX+plusII under UNIX
3604: 96/07/03: Andreas Hofmann: Re: Using MAX+plusII under UNIX
3660: 96/07/10: Rob Pfile: Re: Using MAX+plusII under UNIX
3661: 96/07/10: Andreas Hofmann: Re: Using MAX+plusII under UNIX
3592: 96/07/02: Topjob: Advanced Network Products, Top UK Co., to c55k, Southern England - ECM
3593: 96/07/02: Michael D. Scott: LCA to Schematic
3602: 96/07/02: Brad L Taylor: Re: LCA to Schematic
3610: 96/07/03: Peter: Re: LCA to Schematic
3623: 96/07/04: David Pashley: Re: LCA to Schematic
3628: 96/07/05: Peter: Re: LCA to Schematic
3632: 96/07/05: David Pashley: Re: LCA to Schematic
3605: 96/07/03: Raghavendra G Jorapur: Re: LCA to Schematic
3599: 96/07/02: Rob Hurley: ANNOUNCE: New Tip of the Month - Deferred constants
3600: 96/07/02: Rob Hurley: ANNOUNCE: New Model of the Month - 16 bit ADC
3611: 96/07/03: Peter: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3629: 96/07/05: Stephen Baynes: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3638: 96/07/06: Peter: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3650: 96/07/09: Mark Sitkowski: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3659: 96/07/10: Mark Sitkowski: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3663: 96/07/10: Peter: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3606: 96/07/03: Andre Klindworth: FSM encoding in VHDL with MAX+plusII
3618: 96/07/03: J. Scott Dickson: Re: FSM encoding in VHDL with MAX+plusII
3622: 96/07/03: Lance Gin: Re: FSM encoding in VHDL with MAX+plusII
3624: 96/07/04: Oliver Weber: Re: FSM encoding in VHDL with MAX+plusII
3607: 96/07/03: Luis Sanchez Fernandez: CHDL '97
3612: 96/07/03: Tom Biggs: FPGA job
3613: 96/07/03: John Cooley: Their Own Words: Cadence vs. Avant! (Cadence's Side Part 1)
3614: 96/07/03: John Cooley: Their Own Words: Cadence vs. Avant! (Cadence's Side Part 2)
3615: 96/07/03: John Cooley: Their Own Words: Cadence vs. Avant! (Avant!'s Side)
3616: 96/07/03: Kevin Harney: Problems with ORCA c40 FPGAs
3625: 96/07/04: Wen-King Su: Re: Problems with ORCA c40 FPGAs
3620: 96/07/04: Felix K.C. CHEN: Re: FSM encoding in VHDL with MAX+plusII
3621: 96/07/04: Jack Ogawa: RE: Sanity check for 100K gate DSP FPGA project
3626: 96/07/05: Achim Gratz: RE: Sanity check for 100K gate DSP FPGA project
3633: 96/07/05: David Pashley: RE: Sanity check for 100K gate DSP FPGA project
3630: 96/07/05: Tom Brown: Needed: Hardware Design Engineer
3631: 96/07/05: Marc Palmarini: FPGA vs CPLD
3708: 96/07/18: Bryan Bushart: Re: FPGA vs CPLD
3712: 96/07/19: Andy Gulliver: Re: FPGA vs CPLD
3725: 96/07/22: Mark Christensen: Re: FPGA vs CPLD
3634: 96/07/05: Mann`y: Looking for a PCI bus model
3635: 96/07/05: ploog: size of fpga
3636: 96/07/05: ESPSys: Re: size of fpga
3639: 96/07/06: bob elkind: Re: size of fpga
3637: 96/07/05: ins: Motorola 68000 Chips
3640: 96/07/07: Felix K.C. CHEN: why? internal error in VSS when simulting
3651: 96/07/09: John Cooley: Re: why? internal error in VSS when simulting
3704: 96/07/18: Abhijeet A Chachad: Re: why? internal error in VSS when simulting
3641: 96/07/07: STUART CLUBB: RE: 100k gate DSP
3642: 96/07/07: STUART CLUBB: RE: Best HDL lang.
3643: 96/07/07: STUART CLUBB: Re: PCI compliance
3644: 96/07/07: STUART CLUBB: Re: FPGA Companies
3646: 96/07/07: Eric Edwards: Re: FPGA Companies
3647: 96/07/08: Ray Andraka: Re: FPGA Companies
3645: 96/07/07: Robyn Cheyne: emulation software
3666: 96/07/10: Oliver Paray: Re: emulation software
3679: 96/07/11: George Mills: Re: emulation software
3648: 96/07/08: Tony Hirst: online w/s - evolutionary electronics
3649: 96/07/08: David McKenna: Consultant$$Work$$Xilinx
3652: 96/07/09: Topjob: ASIC/VHDL, Graphics Chips Development, to 35k, Cambridge - ECM
3653: 96/07/09: Topjob: Advanced Network Products, Top UK Co., to c55k, Southern England - ECM
3654: 96/07/09: Aage Farstad: jul9-test
3655: 96/07/09: David J. Matthews: Xilinx Xc4000E Questions
3672: 96/07/10: Tom Burgess: Re: Xilinx Xc4000E Questions
3656: 96/07/09: Jack Ogawa: RE: Sanity check for 100K gate DSP FPGA project
3657: 96/07/09: Joey Y. Chen: Xilinx XC4000E Availability
3658: 96/07/09: Joey Y. Chen: FPGA capacity comparison
3671: 96/07/10: J. Scott Dickson: Re: FPGA capacity comparison
3662: 96/07/10: Per Bjureus: Q:Veribest and Xilinx netlist.
3664: 96/07/10: Scott A. Hauck: FPGA'97: Call for Papers
3665: 96/07/10: S.J.B.Acock: FPGA - RAM interfacing
3667: 96/07/10: Georg Acher: Re: FPGA - RAM interfacing
3718: 96/07/21: Raghavendra G Jorapur: Re: FPGA - RAM interfacing
3668: 96/07/10: John Cooley: Their Own Words: Cadence vs. Avant! (Avant!'s Court Filings 1/3)
3669: 96/07/10: John Cooley: Their Own Words: Cadence vs. Avant! (Avant!'s Court Filings 2/3)
3670: 96/07/10: John Cooley: Their Own Words: Cadence vs. Avant! (Avant!'s Court Filing 3/3)
3673: 96/07/11: GABBY SHPIRER: WANTED:: Altera second source
3682: 96/07/12: Thomas Ebert: Re: WANTED:: Altera second source
3674: 96/07/11: GAMRAT Christian: What about the XC6200 ?
3681: 96/07/12: William J. Wolf: Xilinx reconfigurable logic strategy
3684: 96/07/13: Andrew Morley: Re: What about the XC6200 ?
3723: 96/07/22: <jonathan@dcs.gla.ac.uk>: Re: What about the XC6200 ?
3749: 96/07/25: Gordon McGregor: Re: What about the XC6200 ?
3770: 96/07/29: Bill Wilkie: Re: What about the XC6200 ?
3776: 96/07/30: Hajimowlana-Hossain: Question: FPGA versus ASIC design.
3779: 96/07/30: bob elkind: new thread, was: Question: FPGA versus ASIC design.
3780: 96/07/30: Peter Alfke: Re: Question: FPGA versus ASIC design.
3785: 96/07/31: Peter: Re: Question: FPGA versus ASIC design.
3675: 96/07/11: Bob or Diana Lowell: Free Altera Simulator
3676: 96/07/11: Scott Kroeger: Re: wireless loader for (Xilinx) FPGAs ?
3677: 96/07/11: HLD PUBLISHING: Is your computer being bugged????
3678: 96/07/11: Ingo Cyliax: wireless loader for (Xilinx) FPGAs ?
3683: 96/07/12: Peter: Re: wireless loader for (Xilinx) FPGAs ?
3680: 96/07/11: George Mills: Check out this Logic Design/Simulator (Free Alpha)
3685: 96/07/13: Austin O'Hara: PCI Information Disk.
3686: 96/07/15: Rainer Scharnow: Atmel EEPROMs 17C65: again
3687: 96/07/15: Rainer Scharnow: Re: Atmel EEPROMs 17C65: again
3689: 96/07/16: Rainer Scharnow: Re: Atmel EEPROMs 17C65: again
3711: 96/07/19: Klaus-Guenter Leiss: Re: Atmel EEPROMs 17C65: again
3688: 96/07/16: Jochen Karrer: XC3195 serial-EEPROM dissassembler ?
3695: 96/07/17: Peter: Re: XC3195 serial-EEPROM dissassembler ?
3690: 96/07/16: Michael Johnson: Radiation resistance
3691: 96/07/16: <course@garnet.berkeley.edu>: Fall IC Technology courses at UC Berkeley Extension
3692: 96/07/16: Steve Casselman: Re: What about the XC6200 ?
3696: 96/07/17: Tom Burgess: Re: What about the XC6200 ?
3698: 96/07/17: Ray Andraka: Re: What about the XC6200 ?
3699: 96/07/17: Ray Andraka: Re: What about the XC6200 ?
3713: 96/07/19: Richard Wieler: Re: What about the XC6200 ?
3693: 96/07/16: Christof Paar: q
3694: 96/07/17: John Perry: Cheap/free fpga/cpld programming software
3697: 96/07/17: Fernando Pardo: Xilinx library for autologic
3727: 96/07/22: Lance Gin: Re: Xilinx library for autologic
3700: 96/07/17: Ray Andraka: Hardware sort?
3702: 96/07/17: Dennis Yelle: Re: Hardware sort?
3706: 96/07/18: Peter: Re: Hardware sort?
3716: 96/07/20: Safiri Hamidriza,13310,1100,g: Re: Hardware sort?
3726: 96/07/22: Peter: Re: Hardware sort?
3746: 96/07/24: Peter Alfke: Re: Hardware sort?
3720: 96/07/21: Henry Spencer: Re: Hardware sort?
3707: 96/07/18: John Hagerman: Re: Hardware sort?
3701: 96/07/17: Anne Greene: request for inclusion
3703: 96/07/17: Gavin Melville: (Another) XILINX XDE problem
3705: 96/07/18: Hardy Pottinger: MUG'96 Call for Papers
3709: 96/07/18: Mike Lottridge: Opinions on Graphical/Schematic capture vs HDL-text only design
3710: 96/07/19: Steve Casselman: Re: What about the XC6200 ?
3714: 96/07/19: Rainer Scharnow: IMPORTANT! ATMEL 17C65
3715: 96/07/19: Tim Forcer: CPLD Failure
3724: 96/07/22: Andy Gulliver: Re: CPLD Failure
3717: 96/07/21: Felix K.C. CHEN: What does the timing report from Synthesizer mean?
3721: 96/07/22: Brian "Cheebie" Merchant: Re: What does the timing report from Synthesizer mean?
3734: 96/07/22: Lllapides: Re: What does the timing report from Synthesizer mean?
3719: 96/07/21: Nadeem Sarwar: Information on Actel
3722: 96/07/21: Nadeem Sarwar: Actel information
3728: 96/07/22: Raj Patel: Xilinx XC6200 Information
3729: 96/07/22: * Atmel FPGA Apps *: Atmel AT17Cxxx EEPROMs
3730: 96/07/22: Technisource: I NEED HELP!!!!
3731: 96/07/22: Wilwert Marc: Daisychain or SPROM?
3735: 96/07/23: Philip Freidin: Re: Daisychain or SPROM?
3756: 96/07/25: David McKenna: Re: Daisychain or SPROM?
3732: 96/07/22: John Cooley: ### 7 Quick Multiple Choice Questions ###
3768: 96/07/29: Pete Peterson: Re: ### 7 Quick Multiple Choice Questions ###
3870: 96/08/12: John Cooley: Re: ### 7 Quick Multiple Choice Questions ###
3733: 96/07/22: Hajimowlana Sayed: Designing Dual Port RAM with 4000 series.
3742: 96/07/23: Peter Alfke: Re: Designing Dual Port RAM with 4000 series.
3809: 96/08/05: Gerhard Wiesinger: Re: Designing Dual Port RAM with 4000 series.
3744: 96/07/24: Philip Freidin: Re: Designing Dual Port RAM with 4000 series.
3736: 96/07/23: John Perry: Cheap/free fpga/cpld software
3737: 96/07/23: Anton Scherer: altera -> xilinx
3760: 96/07/26: Dave Matthews: Re: altera -> xilinx
3738: 96/07/23: Dipl.-Ing. D. Lenz: Information on Actel
3739: 96/07/23: Wilwert Marc: Mentor->XC3064
3743: 96/07/24: Philip Freidin: Re: Mentor->XC3064
3740: 96/07/23: Tony Hirst: CFP: Evolutionary Electronics (resend)
3741: 96/07/23: Daniel Payne: Job posting
3754: 96/07/25: HighTech: Re: Job posting
3784: 96/07/31: John Cooley: Re: Job posting
3803: 96/08/05: Jerry McGoveran: Re: Job posting
3810: 96/08/05: George Patrick: Re: Job posting
3865: 96/08/12: Jim Lewis, ASIC and HDL Consultant: Technical Job posting ( and ads) not related to the newsgroup.
3867: 96/08/12: Steve Pope: Re: Technical Job posting ( and ads) not related to the newsgroup.
3886: 96/08/14: Otto's CAD Auction: Re: Technical Job posting ( and ads) not related to the newsgroup.
3891: 96/08/15: Don Husby: Re: Technical Job posting ( and ads) not related to the newsgroup.
3892: 96/08/15: John Cooley: Re: Technical Job posting ( and ads) not related to the newsgroup.
3897: 96/08/15: David Clark: Re: Technical Job posting ( and ads) not related to the newsgroup.
3900: 96/08/16: Celia C.: Re: Technical Job posting ( and ads) not related to the newsgroup.
3745: 96/07/23: Bryan Harstad: Looking for an Eval Board for XILINX
3747: 96/07/24: Hajimowlana Sayed: Does XACT(ver5.2) support 4000E series?
3748: 96/07/24: Scott Kroeger: Re: Does XACT(ver5.2) support 4000E series?
3750: 96/07/25: Cyber Millionair: A New " America Online"......$19.96\month Unlimited access!!!
3751: 96/07/25: Arrigo Benedetti: Signed digit arithmetic on FPGA's
3757: 96/07/25: Janet Ellsworth: Question about books for FPGA
3767: 96/07/29: Rainer Scharnow: Re: Question about books for FPGA
3799: 96/08/03: Peter Alfke: Re: Question about books for FPGA
3804: 96/08/05: Rainer Scharnow: Re: Question about books for FPGA
3816: 96/08/06: Peter Alfke: Re: Question about books for FPGA
3773: 96/07/29: Pasquale Corsonello: Re: Signed digit arithmetic on FPGA's
3752: 96/07/25: regis robart: MACH AMD Serie Programing
3753: 96/07/25: LATAWIEC Regis: VME Hardware Interface using CPLD
3755: 96/07/25: Walter Lang (Operator): ATT serial EEPROMs
3758: 96/07/25: David McKenna: Re: ATT serial EEPROMs
3763: 96/07/26: Lawrence Butcher: Re: ATT serial EEPROMs
3778: 96/07/30: Tom Burgess: Re: ATT serial EEPROMs
3759: 96/07/26: Jeremy Sonander: Re: ATT serial EEPROMs
3766: 96/07/27: Kirsten and Thomas Rounds: Re: ATT serial EEPROMs
3761: 96/07/26: Edward Leventhal: Fault Tolerance With Programmable Logic
3762: 96/07/26: Matt Cross: Clearing security fuse on Lattice ispLSI2032?
3765: 96/07/27: Nigel Burrows: Re: Clearing security fuse on Lattice ispLSI2032?
3774: 96/07/29: Leon Heller: Re: Clearing security fuse on Lattice ispLSI2032?
3781: 96/07/31: Trevor Hall: Re: Clearing security fuse on Lattice ispLSI2032?
3795: 96/08/02: Matt Cross: Re: Clearing security fuse on Lattice ispLSI2032?
3764: 96/07/27: gary crothers: ANNOUNCE HDL Editor
3769: 96/07/29: M. Movahedin: A Survey on Design Errors
3771: 96/07/29: Dan Alley: Programmer for Cypress 7C382A - how to speed up production?
3772: 96/07/29: Larry Getzin: 35K gates into 1 device...doable?
3775: 96/07/30: Alex Krynew: BIDIR Buses
3777: 96/07/30: Mark Webster: Re: BIDIR Buses
3782: 96/07/31: J. A. Herrera Camacho: Multi-FPGA Partitioners?
3783: 96/07/31: Rafiki Kim Hofmans: assigning LOC in XACT
3786: 96/08/01: Andy Gulliver: Re: assigning LOC in XACT
3793: 96/08/02: Raghavendra G Jorapur: Re: assigning LOC in XACT
3805: 96/08/05: Charles Manning: Re: assigning LOC in XACT
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
