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Threads Starting Jun 2011
151889: 11/06/01: RSGUPTA: Random Reset calls
151891: 11/06/01: johnp: Re: Random Reset calls
151890: 11/06/01: moindsp: FFT using logic gates only
151892: 11/06/02: Joel Williams: Re: FFT using logic gates only
151893: 11/06/02: glen herrmannsfeldt: Re: FFT using logic gates only
151906: 11/06/02: Jon Elson: Re: FFT using logic gates only
151912: 11/06/03: RCIngham: Re: FFT using logic gates only
151930: 11/06/08: RCIngham: Re: FFT using logic gates only
151983: 11/06/17: Mr.CRC: Re: FFT using logic gates only
151894: 11/06/02: Martin Thompson: Re: FFT using logic gates only
151895: 11/06/02: Christopher Felton: Re: FFT using logic gates only
151928: 11/06/07: moindsp: Re: FFT using logic gates only
151896: 11/06/02: am85: Microblaze and PowerPC
151897: 11/06/02: Rob Gaddi: Re: Microblaze and PowerPC
151904: 11/06/02: glen herrmannsfeldt: Re: Microblaze and PowerPC
151910: 11/06/03: Martin Thompson: Re: Microblaze and PowerPC
151898: 11/06/02: chifalcon: How could I get LUT-level netlist in Xilinx ISE?
151899: 11/06/02: Tim Wescott: Re: How could I get LUT-level netlist in Xilinx ISE?
151905: 11/06/02: glen herrmannsfeldt: Re: How could I get LUT-level netlist in Xilinx ISE?
151908: 11/06/02: chifalcon: Re: How could I get LUT-level netlist in Xilinx ISE?
151907: 11/06/02: OutputLogic: Re: How could I get LUT-level netlist in Xilinx ISE?
151909: 11/06/02: chifalcon: Re: How could I get LUT-level netlist in Xilinx ISE?
151911: 11/06/03: Martin Thompson: Re: How could I get LUT-level netlist in Xilinx ISE?
151916: 11/06/03: chifalcon: Re: How could I get LUT-level netlist in Xilinx ISE?
151900: 11/06/02: Wojciech M. Zabolotny: Connecting of IP core simulated in GHDL to pseudoterminal via
151902: 11/06/02: wzab: Re: Connecting of IP core simulated in GHDL to pseudoterminal via
151903: 11/06/02: Mike Treseler: Re: Connecting of IP core simulated in GHDL to pseudoterminal via
151913: 11/06/03: carlob: verilog task and vhdl
151914: 11/06/03: RCIngham: Re: verilog task and vhdl
151915: 11/06/03: carlob: Re: verilog task and vhdl
151917: 11/06/03: Mike Treseler: Re: verilog task and vhdl
151921: 11/06/03: carlob: Re: verilog task and vhdl
151922: 11/06/04: Mike Treseler: Re: verilog task and vhdl
151923: 11/06/04: carlob: Re: verilog task and vhdl
151925: 11/06/05: Alan Fitch: Re: verilog task and vhdl
151926: 11/06/05: Mike Treseler: Re: verilog task and vhdl
151927: 11/06/06: carlob: Re: verilog task and vhdl
152080: 11/07/01: Alessandro Basili: Re: verilog task and vhdl
151918: 11/06/03: Neil Steiner: Looking for bitgen Virtex7 and Kintex7 support
151919: 11/06/03: maxascent: Re: Looking for bitgen Virtex7 and Kintex7 support
151924: 11/06/04: Neil Steiner: Re: Looking for bitgen Virtex7 and Kintex7 support
151920: 11/06/03: Ed McGettigan: Re: Looking for bitgen Virtex7 and Kintex7 support
151931: 11/06/08: kclo4: multiplication in indexation
151932: 11/06/08: RCIngham: Re: multiplication in indexation
151938: 11/06/10: jc: Re: multiplication in indexation
151942: 11/06/11: kclo4: Re: multiplication in indexation
151933: 11/06/09: Calvin Ball: Variable Optimized Away
151934: 11/06/09: Gabor: Re: Variable Optimized Away
151937: 11/06/10: Arlet Ottens: Re: Variable Optimized Away
151939: 11/06/10: Gabor: Re: Variable Optimized Away
151935: 11/06/09: Calvin Ball: Re: Variable Optimized Away
151936: 11/06/09: Calvin Ball: Re: Variable Optimized Away
151940: 11/06/10: Christopher Head: Area Optimization
151941: 11/06/11: glen herrmannsfeldt: Re: Area Optimization
151943: 11/06/11: John Adair: Re: Area Optimization
151944: 11/06/11: rickman: Re: Area Optimization
151945: 11/06/12: jt_eaton: Re: Area Optimization
151947: 11/06/13: rickman: Re: Area Optimization
151948: 11/06/13: jt_eaton: Re: Area Optimization
151951: 11/06/14: jt_eaton: Re: Area Optimization
151954: 11/06/14: glen herrmannsfeldt: Re: Area Optimization
151973: 11/06/15: jt_eaton: Re: Area Optimization
151975: 11/06/16: glen herrmannsfeldt: Re: Area Optimization
151950: 11/06/14: ARSDMTHE: Re: Area Optimization
151953: 11/06/14: ARSDMTHE: Re: Area Optimization
151955: 11/06/14: rickman: Re: Area Optimization
151956: 11/06/14: rickman: Re: Area Optimization
151986: 11/06/17: rickman: Re: Area Optimization
151946: 11/06/13: Martin Thompson: Re: Area Optimization
151957: 11/06/14: Christopher Head: Re: Area Optimization
151959: 11/06/15: RCIngham: Re: Area Optimization
151971: 11/06/15: jt_eaton: Re: Area Optimization
151961: 11/06/15: AMDyer@gmail.com: Re: Area Optimization
151970: 11/06/15: glen herrmannsfeldt: Re: Area Optimization
151972: 11/06/15: rickman: Re: Area Optimization
151979: 11/06/16: Christopher Head: Re: Area Optimization
151980: 11/06/17: Brian Drummond: Re: Area Optimization
151949: 11/06/14: valtih1978: What is the advantage of source-syncronization (in SDRAMs)?
151958: 11/06/15: RCIngham: Re: What is the advantage of source-syncronization (in SDRAMs)?
151960: 11/06/15: Morten Leikvoll: Re: What is the advantage of source-syncronization (in SDRAMs)?
151963: 11/06/15: valtih1978: Re: What is the advantage of source-syncronization (in SDRAMs)?
151964: 11/06/15: maxascent: Re: What is the advantage of source-syncronization (in SDRAMs)?
151967: 11/06/15: valtih1978: Re: What is the advantage of source-syncronization (in SDRAMs)?
151968: 11/06/15: valtih1978: Re: What is the advantage of source-syncronization (in SDRAMs)?
152411: 11/08/20: valtih1978: Re: What is the advantage of source-syncronization (in SDRAMs)?
152454: 11/08/25: valtih1978: Re: What is the advantage of source-syncronization (in SDRAMs)?
152524: 11/09/01: valtih1978: Re: What is the advantage of source-syncronization (in SDRAMs)?
152516: 11/08/30: valtih1978: Re: What is the advantage of source-syncronization (in SDRAMs)?
152523: 11/09/01: valtih1978: Re: What is the advantage of source-syncronization (in SDRAMs)?
151969: 11/06/15: valtih1978: Re: What is the advantage of source-syncronization (in SDRAMs)?
151966: 11/06/15: RCIngham: Re: What is the advantage of source-syncronization (in SDRAMs)?
152291: 11/08/03: trag: Re: What is the advantage of source-syncronization (in SDRAMs)?
152416: 11/08/20: Ed McGettigan: Re: What is the advantage of source-syncronization (in SDRAMs)?
152456: 11/08/25: Ed McGettigan: Re: What is the advantage of source-syncronization (in SDRAMs)?
152461: 11/08/26: Mawa_fugo: Re: What is the advantage of source-syncronization (in SDRAMs)?
152519: 11/08/30: Mawa_fugo: Re: What is the advantage of source-syncronization (in SDRAMs)?
152525: 11/09/02: Mawa_fugo: Re: What is the advantage of source-syncronization (in SDRAMs)?
151952: 11/06/14: Vivek Menon: Area optimization (optimizing DSP48E usage)
151962: 11/06/15: Vivek Menon: Determine latency of GTX links vs Aurora+LVDS
151965: 11/06/15: RCIngham: Re: Determine latency of GTX links vs Aurora+LVDS
151974: 11/06/15: OutputLogic: Re: Determine latency of GTX links vs Aurora+LVDS
152038: 11/06/24: John Adair: Re: Determine latency of GTX links vs Aurora+LVDS
151976: 11/06/16: scrts: Choosing a scope
151984: 11/06/17: Mr.CRC: Re: Choosing a scope
151988: 11/06/19: scrts: Re: Choosing a scope
151985: 11/06/18: Symon: Re: Choosing a scope
151989: 11/06/19: scrts: Re: Choosing a scope
151977: 11/06/16: Simon: Xilinx or Altera
151978: 11/06/16: Gabor: Re: Xilinx or Altera
151981: 11/06/17: Michael: Re: Xilinx or Altera
151982: 11/06/17: Ed McGettigan: Re: Xilinx or Altera
151987: 11/06/18: Simon: Re: Xilinx or Altera
151990: 11/06/19: Chopper: Re: Xilinx or Altera
151991: 11/06/20: scrts: Re: Xilinx or Altera
151997: 11/06/20: Chopper: Re: Xilinx or Altera
151998: 11/06/20: scrts: Re: Xilinx or Altera
151995: 11/06/20: Simon: Re: Xilinx or Altera
152005: 11/06/21: Tom Johnson: Re: Xilinx or Altera
152007: 11/06/21: Simon: Re: Xilinx or Altera
152015: 11/06/21: John Miles: Re: Xilinx or Altera
152016: 11/06/21: John Adair: Re: Xilinx or Altera
152019: 11/06/22: Simon: Re: Xilinx or Altera
152021: 11/06/22: John Adair: Re: Xilinx or Altera
151992: 11/06/20: JB: Sporadic simulation result with modelsim
151993: 11/06/20: Thomas Stanka: Re: Sporadic simulation result with modelsim
151994: 11/06/20: JB: Re: Sporadic simulation result with modelsim
151996: 11/06/20: KJ: Re: Sporadic simulation result with modelsim
151999: 11/06/21: jc: Re: Sporadic simulation result with modelsim
152000: 11/06/21: shyam: Re: Sporadic simulation result with modelsim
152013: 11/06/21: JB: Re: Sporadic simulation result with modelsim
152012: 11/06/21: JB: Re: Sporadic simulation result with modelsim
152014: 11/06/21: KJ: Re: Sporadic simulation result with modelsim
152017: 11/06/22: JB: Re: Sporadic simulation result with modelsim
152018: 11/06/22: Thomas Stanka: Re: Sporadic simulation result with modelsim
152020: 11/06/22: KJ: Re: Sporadic simulation result with modelsim
152023: 11/06/23: Nial Stewart: Re: Sporadic simulation result with modelsim
152028: 11/06/23: jc: Re: Sporadic simulation result with modelsim
152031: 11/06/23: Nial Stewart: Re: Sporadic simulation result with modelsim
152035: 11/06/23: JB: Re: Sporadic simulation result with modelsim
152034: 11/06/23: jc: Re: Sporadic simulation result with modelsim
152039: 11/06/24: Martin Thompson: Re: Sporadic simulation result with modelsim
152040: 11/06/24: Mike Treseler: Re: Sporadic simulation result with modelsim
152043: 11/06/27: Martin Thompson: Re: Sporadic simulation result with modelsim
152044: 11/06/27: Thomas Stanka: Re: Sporadic simulation result with modelsim
152001: 11/06/21: moudud: ucf file for 32 bit counter spartan 3e S500E -4
152006: 11/06/21: Ed McGettigan: Re: ucf file for 32 bit counter spartan 3e S500E -4
152008: 11/06/21: salimbaba: Re: ucf file for 32 bit counter spartan 3e S500E -4
152002: 11/06/21: submachine: Xilinx ISE ignores Max Fanout
152003: 11/06/21: aibk01: Verilog Custom Core To Read and Write From RAM
152026: 11/06/23: maxascent: Re: Verilog Custom Core To Read and Write From RAM
152098: 11/07/06: maxascent: Re: Verilog Custom Core To Read and Write From RAM
152102: 11/07/07: aibk01: Re: Verilog Custom Core To Read and Write From RAM
152103: 11/07/07: RCIngham: Re: Verilog Custom Core To Read and Write From RAM
152104: 11/07/07: maxascent: Re: Verilog Custom Core To Read and Write From RAM
152106: 11/07/07: aibk01: Re: Verilog Custom Core To Read and Write From RAM
152105: 11/07/07: aibk01: Re: Verilog Custom Core To Read and Write From RAM
152004: 11/06/21: Amy_jing: How to open the interface GUI of ChipScope Pro Analyzer on linux
152010: 11/06/21: OutputLogic: Re: How to open the interface GUI of ChipScope Pro Analyzer on linux
152011: 11/06/21: OutputLogic: Re: How to open the interface GUI of ChipScope Pro Analyzer on linux
152022: 11/06/22: chifalcon: P&R based on the post-map simulation model?
152024: 11/06/23: RCIngham: Re: P&R based on the post-map simulation model?
152032: 11/06/23: NeedCleverHandle: Re: P&R based on the post-map simulation model?
152154: 11/07/14: Andreas Ehliar: Re: P&R based on the post-map simulation model?
152025: 11/06/23: Richard: Depth of logical Circuit
152027: 11/06/23: Brian Drummond: Re: Depth of logical Circuit
152029: 11/06/23: Richard: Re: Depth of logical Circuit
152030: 11/06/23: Richard: Re: Depth of logical Circuit
152033: 11/06/23: Ed McGettigan: Re: Depth of logical Circuit
152036: 11/06/23: Brian Drummond: Re: Depth of logical Circuit
152037: 11/06/23: OutputLogic: Re: Depth of logical Circuit
152041: 11/06/24: Brad Smallridge: Re: Depth of logical Circuit
152042: 11/06/26: bhatti: digitization of sensor array
152046: 11/06/27: RCIngham: Re: digitization of sensor array
152078: 11/06/30: Kolja Sulimma: Re: digitization of sensor array
152084: 11/07/03: bhatti: Re: digitization of sensor array
152047: 11/06/27: Jonathan Bromley: XST 13.1 explodes with generic of enum type with only one member
152048: 11/06/28: Alan Fitch: Re: XST 13.1 explodes with generic of enum type with only one member
152055: 11/06/28: Jonathan Bromley: Re: XST 13.1 explodes with generic of enum type with only one member
152065: 11/06/29: Alan Fitch: Re: XST 13.1 explodes with generic of enum type with only one member
152066: 11/06/29: Jonathan Bromley: Re: XST 13.1 explodes with generic of enum type with only one member
152049: 11/06/28: RCIngham: Re: XST 13.1 explodes with generic of enum type with only one member
152054: 11/06/28: Jonathan Bromley: Re: XST 13.1 explodes with generic of enum type with only one member
152052: 11/06/28: Tim Wescott: Re: XST 13.1 explodes with generic of enum type with only one member
152057: 11/06/29: Jonathan Bromley: Re: XST 13.1 explodes with generic of enum type with only one member
152058: 11/06/29: Jonathan Bromley: Re: XST 13.1 explodes with generic of enum type with only one member
152072: 11/06/30: Brian Drummond: Re: XST 13.1 explodes with generic of enum type with only one
152081: 11/07/01: Martin Thompson: Re: XST 13.1 explodes with generic of enum type with only one member
152201: 11/07/19: Christopher Head: Re: XST 13.1 explodes with generic of enum type with only one
152290: 11/08/03: Brian Drummond: Re: XST 13.1 explodes with generic of enum type with only one
152050: 11/06/28: Rob Gaddi: Delta-Sigma in an FPGA
152051: 11/06/28: Tim Wescott: Re: Delta-Sigma in an FPGA
152053: 11/06/28: Andrew Holme: Re: Delta-Sigma in an FPGA
152056: 11/06/29: Tim: Re: Delta-Sigma in an FPGA
152062: 11/06/29: Rob Gaddi: Re: Delta-Sigma in an FPGA
152063: 11/06/29: Tim Wescott: Re: Delta-Sigma in an FPGA
152082: 11/07/02: Frank Buss: Re: Delta-Sigma in an FPGA
152094: 11/07/05: Rob Gaddi: Re: Delta-Sigma in an FPGA
152096: 11/07/05: Jim Granville: Re: Delta-Sigma in an FPGA
152059: 11/06/29: YH: JESD204A and Spartan-6 GTPs
152060: 11/06/29: jgk2004: Virtex 5 Rocket IO design for reading in ADC data.
152064: 11/06/29: maxascent: Re: Virtex 5 Rocket IO design for reading in ADC data.
152067: 11/06/30: jgk2004: Re: Virtex 5 Rocket IO design for reading in ADC data.
152068: 11/06/30: maxascent: Re: Virtex 5 Rocket IO design for reading in ADC data.
152069: 11/06/30: jgk2004: Re: Virtex 5 Rocket IO design for reading in ADC data.
152070: 11/06/30: maxascent: Re: Virtex 5 Rocket IO design for reading in ADC data.
152071: 11/06/30: jgk2004: Re: Virtex 5 Rocket IO design for reading in ADC data.
152073: 11/06/30: maxascent: Re: Virtex 5 Rocket IO design for reading in ADC data.
152075: 11/06/30: jgk2004: Re: Virtex 5 Rocket IO design for reading in ADC data.
152076: 11/06/30: maxascent: Re: Virtex 5 Rocket IO design for reading in ADC data.
152079: 11/07/01: vasu: Re: Virtex 5 Rocket IO design for reading in ADC data.
152107: 11/07/07: Kolja Sulimma: Re: Virtex 5 Rocket IO design for reading in ADC data.
152061: 11/06/29: chifalcon: What's the black and while round on FPGA slice?
152099: 11/07/06: mike: Re: What's the black and while round on FPGA slice?
152074: 11/06/30: DSPtronics: [ANNOUNCE] DSP-FPGA Programming Contest
152077: 11/06/30: salimbaba: Ericsson Eurocom D1
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Compare FPGA features and resources
Threads starting:
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