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On 04/06/11 21:23, carlob wrote: >> I the instanced task can only be called from inside the module. >> A test task would have to be declared in the testbench. >> >> -- Mike Treseler >> >> > > On the internet I read about writing a verilog wrapper that trigger tasks > using its input signals....then instanciate that wrapper into vhdl > testbench and move tasks by triggering signals.... > > Otherwise...I should write the testbench in verilog.... > > Another question is...I use modelsim...is there any issue related to mixed > language (vhdl-verilog) simulation that must be considered.... > It should be useful to know it before starting.... > > Thank you for help... > Carlo > The first thing I would do is read the chapter "Mixed Language Simulation" in the Modelsim User Guide. For instance, Modelsim 10.0a supports VHDL external names (hierarchical names), but only from VHDL to VHDL, not from VHDL to Verilog. So I suspect some kind of triggering would be required. The other practical issue is whether you have a mixed-language license. regards Alan -- Alan FitchArticle: 151926
On 6/4/2011 1:23 PM, carlob wrote:
> On the internet I read about writing a verilog wrapper that trigger tasks
> using its input signals....then instanciate that wrapper into vhdl
> testbench and move tasks by triggering signals....
> Otherwise...I should write the testbench in verilog....
That "wrapper" is a verilog testbench.
> Another question is...I use modelsim...is there any issue related to mixed
> language (vhdl-verilog) simulation that must be considered....
> It should be useful to know it before starting....
Modelsim requires two licenses for mixed vhdl and verilog.
Your choices are:
1. Buy a license and write vhdl procedures for the verilog uut.
2. Learn verilog and write a verilog testbench.
3. Write your own phy model in vhdl.
-- Mike Treseler
Article: 151927>That "wrapper" is a verilog testbench. Yes you are right... > >> Another question is...I use modelsim...is there any issue related to mixed >> language (vhdl-verilog) simulation that must be considered.... >> It should be useful to know it before starting.... > >Modelsim requires two licenses for mixed vhdl and verilog. >Your choices are: >1. Buy a license and write vhdl procedures for the verilog uut. >2. Learn verilog and write a verilog testbench. >3. Write your own phy model in vhdl. > > -- Mike Treseler > I think I will write my own phy model in vhdl taking inspiration from the verilog one...it seems cleaner...in my opinion... Thanks all for help Carlo --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151928
I am thankful to you guys especially Martin and glen , I used Xilinx
schematic editor to build the 2d 8*8 DCT using Look up table with
adders and few multipliers. It is synthesized and it performs
accurately on lena.jpg and results are pretty good as compared to
matlab.
this is our first step and using IC fabs technolgy we are set
to implement the same thing on MTJ's by the way RCIngham when you
invent new technology you have to go to basics. e.g CAN YOU EXPLAIN
ME THE MULTIPLIER ,FF and other stuff in magnetic gate MTJ's . if
still clueless here is a paper which i am using
A High-Reliability, Low-Power Magnetic Full Adder
Yi Gang1, 2, Weisheng Zhao1, 2, Jacques-Olivier Klein1, 2, Claude
Chappert1, 2, Pascale Mazoyer3
1IEF, Univ. Paris-Sud, Orsay, 91405, France
2CNRS, UMR 8622, Orsay, 91405, France
3STMicroelectronics, 850, Rue Jean Monnet, 38926, Crolles, France
.
Article: 151929On May 30, 2:03=A0pm, Michael <michael_laaja...@yahoo.com> wrote: > Hi, > > On 05/29/11 08:37 AM, Guy Eschemann wrote:> Michael, > > > as others have said, don't expect too much from a third-party synthesis= tool. XST is a really good synthesis tool now, and I'm using it in all of = my Xilinx projects. > > > There are lots of strategies for improving logic utilization and/or tim= ing, the most effective usually being optimizations of the RTL code such as= reducing the number of logic levels, leveraging built-in hard-macros, remo= ving resets etc. > > > The best advice I can give you is to show your design to a qualified co= nsultant near you. It will cost you some money, but you'll learn a lot and = he may catch other issues in the process. Another option is of course to sw= itch to a device with a faster speed grade. > > > Hope this helps, > > > Guy Eschemann > >http://guy-eschemann.de > > I agree with you, but as the FPGA gets more filled routing tends to be a > critical issue in my experience so timing constraints as you wrote is vit= al. > > It is not so easy to find someone that is really good and can pinpoint > the weekness in a design in a relative short period of time IMHO. > > So as I wrote, if a tool can fix 5-10% then that is very well invested > money usually, xst has improved alot and works great but how much has > the other vendors(read Synopsys) improved their tools is the question! > > xst is catching up but are they ahead or on par with tools like Synopsys? > > /michael Michael, I don't have any comparison data between XST and Synplify. However I saw many times, that another synthesis tool can give you 10-15% improvement in timing, or even more, it is very design dependent. I'd suggest to contact Synopsys/Synplify and ask for a trial. They definitely will give you a ~15 days license to try for free ... and possibly they might be even willing to help (advise how) to get your target timing. -- AlexyArticle: 151930
So, this wasn't targetting any FPGA technology at all, and therefore the thread is completely off-topic for the newsgroup... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151931
Hello everyone
I want to do a for loop in order to repeat the same construction and
use the number of the loop to create the index to take the desirated
part of the bus , the problem is that i don't know how to do it and i
don't know what to look for in google , i would like to do this
enable_reg(2*i+1 downto 2*i)
my code:
for i in 0 to 11 loop
case enable_reg(2*i+1 downto 2*i) is
when "00" =>
enable_output(i) <= '1';
when "01" =>
enable_output(i) <= (disc_enable(0));
when others =>
enable_output(i) <= '0';
end case;
end for;
thank you for your help
Article: 151932>Hello everyone > >I want to do a for loop in order to repeat the same construction and >use the number of the loop to create the index to take the desirated >part of the bus , the problem is that i don't know how to do it and i >don't know what to look for in google , i would like to do this >enable_reg(2*i+1 downto 2*i) > >my code: > >for i in 0 to 11 loop > case enable_reg(2*i+1 downto 2*i) is > when "00" => > enable_output(i) <= '1'; > when "01" => > enable_output(i) <= (disc_enable(0)); > when others => > enable_output(i) <= '0'; > end case; > end for; > >thank you for your help > In VHDL it is "end loop" rather than "end for". Apart from that, it's difficult to work out what you are trying to achieve - and your level of expertise - from so little information... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151933
Hello, I am having a problem where Xilinx ISE is trimming away a variable that I need, tempShifts. I can still implement the module but I am not sure what it is doing with my variable. This says to me that tempShifts isn't being trimmed... Explanations? Also this module uses the shift and add 3 algorithm to convert binary to BCD format. Specifically this converts a 16 bit binary number into 5 BCD digits. module binaryBCD( input [15:0] binaryIn, //input 16bit number output reg [19:0] bcdOut //5 display BCD output ); reg [35:0] tempShifts; //temporary storage while computing always @(binaryIn) begin tempShifts = 0; //the method used is shift and add 3 //this requires 16 total shifts, first three are done here tempShifts[18:3] = binaryIn; repeat(13) begin //for the method if any BCD digit is over 4 add three then shift if (tempShifts[19:16] > 4) tempShifts[19:16] = tempShifts[19:16] + 3; if (tempShifts[23:20] > 4) tempShifts[23:20] = tempShifts[23:20]+ 3; if (tempShifts[27:24] > 4) tempShifts[27:24] = tempShifts[27:24] + 3; if (tempShifts[31:28] > 4) tempShifts[31:28] = tempShifts[31:28] + 3; if (tempShifts[35:32] > 4) tempShifts[35:32] = tempShifts[35:32] + 3; tempShifts = tempShifts << 1; end //save the final output bcdOut = tempShifts[35:16]; end endmodule The warning I get is below: WARNING:Xst:646 - Signal <tempShifts> is assigned but never used. This unconnected signal will be trimmed during the optimization process.Article: 151934
Calvin Ball wrote: > Hello, > I am having a problem where Xilinx ISE is trimming away a variable > that I need, tempShifts. I can still implement the module but I am not > sure what it is doing with my variable. This says to me that > tempShifts isn't being trimmed... Explanations? > > Also this module uses the shift and add 3 algorithm to convert binary > to BCD format. Specifically this converts a 16 bit binary number into > 5 BCD digits. > > module binaryBCD( > input [15:0] binaryIn, //input 16bit number > output reg [19:0] bcdOut //5 display BCD output > ); > > reg [35:0] tempShifts; //temporary storage while computing > > always @(binaryIn) > begin > tempShifts = 0; > //the method used is shift and add 3 > //this requires 16 total shifts, first three are done here > tempShifts[18:3] = binaryIn; > > repeat(13) > begin //for the method if any BCD digit is over 4 add three then > shift > if (tempShifts[19:16] > 4) > tempShifts[19:16] = tempShifts[19:16] + 3; > if (tempShifts[23:20] > 4) > tempShifts[23:20] = tempShifts[23:20]+ 3; > if (tempShifts[27:24] > 4) > tempShifts[27:24] = tempShifts[27:24] + 3; > if (tempShifts[31:28] > 4) > tempShifts[31:28] = tempShifts[31:28] + 3; > if (tempShifts[35:32] > 4) > tempShifts[35:32] = tempShifts[35:32] + 3; > > tempShifts = tempShifts << 1; > end > //save the final output > bcdOut = tempShifts[35:16]; > end > endmodule > > The warning I get is below: > WARNING:Xst:646 - Signal <tempShifts> is assigned but never used. This > unconnected signal will be trimmed during the optimization process. XST has a brain-dead way of giving warnings about intermediate results. Basically the only bits of tempShifts that are used are effectively renamed to bcdOut. By the way I was under the impression that the repeat operator was not synthesizable. Does this code actually work in the hardware? -- GaborArticle: 151935
On Jun 9, 2:34=A0pm, Gabor <ga...@szakacs.invalid> wrote: > Calvin Ball wrote: > > Hello, > > I am having a problem where Xilinx ISE is trimming away a variable > > that I need, tempShifts. I can still implement the module but I am not > > sure what it is doing with my variable. This says to me that > > tempShifts isn't being trimmed... Explanations? > > > Also this module uses the shift and add 3 algorithm to convert binary > > to BCD format. Specifically this converts a 16 bit binary number into > > 5 BCD digits. > > > module binaryBCD( > > =A0 =A0input [15:0] binaryIn, =A0 =A0 =A0 =A0 =A0//input 16bit number > > =A0 =A0output reg [19:0] bcdOut =A0 =A0 =A0 =A0//5 display BCD output > > =A0 =A0); > > > =A0 =A0reg [35:0] tempShifts; =A0//temporary storage while computing > > > =A0 =A0always @(binaryIn) > > =A0 =A0 =A0 =A0 =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tempShifts =3D 0; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0//the method used is shift and a= dd 3 > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0//this requires 16 total shifts,= first three are done here > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tempShifts[18:3] =3D binaryIn; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0repeat(13) > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0begin =A0 //for the method if an= y BCD digit is over 4 add three then > > shift > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (tempShifts[1= 9:16] > 4) > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= tempShifts[19:16] =3D tempShifts[19:16] + 3; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (tempShifts[2= 3:20] > 4) > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= tempShifts[23:20] =3D tempShifts[23:20]+ 3; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (tempShifts[2= 7:24] > 4) > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= tempShifts[27:24] =3D tempShifts[27:24] + 3; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (tempShifts[3= 1:28] > 4) > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= tempShifts[31:28] =3D tempShifts[31:28] + 3; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (tempShifts[3= 5:32] > 4) > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= tempShifts[35:32] =3D tempShifts[35:32] + 3; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tempShifts =3D t= empShifts << 1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0end > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0//save the final output > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bcdOut =3D tempShifts[35:16]; > > =A0 =A0 =A0 =A0 =A0 =A0end > > endmodule > > > The warning I get is below: > > WARNING:Xst:646 - Signal <tempShifts> is assigned but never used. This > > unconnected signal will be trimmed during the optimization process. > > XST has a brain-dead way of giving warnings about intermediate results. > Basically the only bits of tempShifts that are used are effectively > renamed to bcdOut. =A0By the way I was under the impression that the > repeat operator was not synthesizable. =A0Does this code actually work > in the hardware? > > -- Gabor Yea I have successfully implemented this code on a Nexys 2 development board, XCS3500E FPGA.Article: 151936
On Jun 9, 3:16=A0pm, Calvin Ball <ballcal...@gmail.com> wrote: > On Jun 9, 2:34=A0pm, Gabor <ga...@szakacs.invalid> wrote: > > > > > > > > > > > Calvin Ball wrote: > > > Hello, > > > I am having a problem where Xilinx ISE is trimming away a variable > > > that I need, tempShifts. I can still implement the module but I am no= t > > > sure what it is doing with my variable. This says to me that > > > tempShifts isn't being trimmed... Explanations? > > > > Also this module uses the shift and add 3 algorithm to convert binary > > > to BCD format. Specifically this converts a 16 bit binary number into > > > 5 BCD digits. > > > > module binaryBCD( > > > =A0 =A0input [15:0] binaryIn, =A0 =A0 =A0 =A0 =A0//input 16bit number > > > =A0 =A0output reg [19:0] bcdOut =A0 =A0 =A0 =A0//5 display BCD output > > > =A0 =A0); > > > > =A0 =A0reg [35:0] tempShifts; =A0//temporary storage while computing > > > > =A0 =A0always @(binaryIn) > > > =A0 =A0 =A0 =A0 =A0 =A0begin > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tempShifts =3D 0; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0//the method used is shift and= add 3 > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0//this requires 16 total shift= s, first three are done here > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tempShifts[18:3] =3D binaryIn; > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0repeat(13) > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0begin =A0 //for the method if = any BCD digit is over 4 add three then > > > shift > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (tempShifts= [19:16] > 4) > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0tempShifts[19:16] =3D tempShifts[19:16] + 3; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (tempShifts= [23:20] > 4) > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0tempShifts[23:20] =3D tempShifts[23:20]+ 3; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (tempShifts= [27:24] > 4) > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0tempShifts[27:24] =3D tempShifts[27:24] + 3; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (tempShifts= [31:28] > 4) > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0tempShifts[31:28] =3D tempShifts[31:28] + 3; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (tempShifts= [35:32] > 4) > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0tempShifts[35:32] =3D tempShifts[35:32] + 3; > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tempShifts =3D= tempShifts << 1; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0end > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0//save the final output > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bcdOut =3D tempShifts[35:16]; > > > =A0 =A0 =A0 =A0 =A0 =A0end > > > endmodule > > > > The warning I get is below: > > > WARNING:Xst:646 - Signal <tempShifts> is assigned but never used. Thi= s > > > unconnected signal will be trimmed during the optimization process. > > > XST has a brain-dead way of giving warnings about intermediate results. > > Basically the only bits of tempShifts that are used are effectively > > renamed to bcdOut. =A0By the way I was under the impression that the > > repeat operator was not synthesizable. =A0Does this code actually work > > in the hardware? > > > -- Gabor > > Yea I have successfully implemented this code on a Nexys 2 development > board, XCS3500E FPGA. To implement this wouldn't it just copy the structure as many times as needed, in this case 13 times?Article: 151937
On 06/10/2011 12:19 AM, Calvin Ball wrote: > On Jun 9, 3:16 pm, Calvin Ball<ballcal...@gmail.com> wrote: >> On Jun 9, 2:34 pm, Gabor<ga...@szakacs.invalid> wrote: >> >> >> >> >> >> >> >> >> >>> Calvin Ball wrote: >>>> Hello, >>>> I am having a problem where Xilinx ISE is trimming away a variable >>>> that I need, tempShifts. I can still implement the module but I am not >>>> sure what it is doing with my variable. This says to me that >>>> tempShifts isn't being trimmed... Explanations? >> >>>> Also this module uses the shift and add 3 algorithm to convert binary >>>> to BCD format. Specifically this converts a 16 bit binary number into >>>> 5 BCD digits. >> >>>> module binaryBCD( >>>> input [15:0] binaryIn, //input 16bit number >>>> output reg [19:0] bcdOut //5 display BCD output >>>> ); >> >>>> reg [35:0] tempShifts; //temporary storage while computing >> >>>> always @(binaryIn) >>>> begin >>>> tempShifts = 0; >>>> //the method used is shift and add 3 >>>> //this requires 16 total shifts, first three are done here >>>> tempShifts[18:3] = binaryIn; >> >>>> repeat(13) >>>> begin //for the method if any BCD digit is over 4 add three then >>>> shift >>>> if (tempShifts[19:16]> 4) >>>> tempShifts[19:16] = tempShifts[19:16] + 3; >>>> if (tempShifts[23:20]> 4) >>>> tempShifts[23:20] = tempShifts[23:20]+ 3; >>>> if (tempShifts[27:24]> 4) >>>> tempShifts[27:24] = tempShifts[27:24] + 3; >>>> if (tempShifts[31:28]> 4) >>>> tempShifts[31:28] = tempShifts[31:28] + 3; >>>> if (tempShifts[35:32]> 4) >>>> tempShifts[35:32] = tempShifts[35:32] + 3; >> >>>> tempShifts = tempShifts<< 1; >>>> end >>>> //save the final output >>>> bcdOut = tempShifts[35:16]; >>>> end >>>> endmodule >> >>>> The warning I get is below: >>>> WARNING:Xst:646 - Signal<tempShifts> is assigned but never used. This >>>> unconnected signal will be trimmed during the optimization process. >> >>> XST has a brain-dead way of giving warnings about intermediate results. >>> Basically the only bits of tempShifts that are used are effectively >>> renamed to bcdOut. By the way I was under the impression that the >>> repeat operator was not synthesizable. Does this code actually work >>> in the hardware? >> >>> -- Gabor >> >> Yea I have successfully implemented this code on a Nexys 2 development >> board, XCS3500E FPGA. > > To implement this wouldn't it just copy the structure as many times as > needed, in this case 13 times? Doesn't this take an awful amount of logic resources ? If this is for a display, or other human interface, there's generally no requirement to update it faster than people can read. In that case, a version with a state machine that requires N clocks would probably work just as well, and be much more compact.Article: 151938
On Jun 8, 3:01=A0pm, kclo4 <alexis.ga...@gmail.com> wrote: > Hello everyone > > I want to do a for loop in order to repeat the same construction and > use the number of the loop to create the index to take the desirated > part of the bus , the problem is that i don't know how to do it and i > don't know what to look for in google , i would like to do this > enable_reg(2*i+1 downto 2*i) > > my code: > > for i in =A00 to 11 loop > =A0 =A0case enable_reg(2*i+1 downto 2*i) is > =A0 =A0 =A0 =A0 when "00" =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0enable_output(i) <=3D '1'; > =A0 =A0 =A0 =A0 when "01" =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0enable_output(i) <=3D (disc_enable= (0)); > =A0 =A0 =A0 =A0 =A0when others =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0enable_output(i) <=3D '0'; > =A0 =A0 =A0 =A0 end case; > =A0end for; > > thank you for your help It appears you are taking a 24-bit bus and splitting up into pairs to derive 12 individual output enable signals, each which can go 0, 1, or a single enable called disc_enable(0). I'm not sure why you are using 24-bit bus to gate the passing of a single driving enable signal--it seems like an additional of complexity perhaps not necessary but I could be wrong--but a generate statement would work. Google "VHDL generate."Article: 151939
Calvin Ball wrote: > On Jun 9, 3:16 pm, Calvin Ball <ballcal...@gmail.com> wrote: >> On Jun 9, 2:34 pm, Gabor <ga...@szakacs.invalid> wrote: >> >> >> >> >> >> >> >> >> >>> Calvin Ball wrote: >>>> Hello, >>>> I am having a problem where Xilinx ISE is trimming away a variable >>>> that I need, tempShifts. I can still implement the module but I am not >>>> sure what it is doing with my variable. This says to me that >>>> tempShifts isn't being trimmed... Explanations? >>>> Also this module uses the shift and add 3 algorithm to convert binary >>>> to BCD format. Specifically this converts a 16 bit binary number into >>>> 5 BCD digits. >>>> module binaryBCD( >>>> input [15:0] binaryIn, //input 16bit number >>>> output reg [19:0] bcdOut //5 display BCD output >>>> ); >>>> reg [35:0] tempShifts; //temporary storage while computing >>>> always @(binaryIn) >>>> begin >>>> tempShifts = 0; >>>> //the method used is shift and add 3 >>>> //this requires 16 total shifts, first three are done here >>>> tempShifts[18:3] = binaryIn; >>>> repeat(13) >>>> begin //for the method if any BCD digit is over 4 add three then >>>> shift >>>> if (tempShifts[19:16] > 4) >>>> tempShifts[19:16] = tempShifts[19:16] + 3; >>>> if (tempShifts[23:20] > 4) >>>> tempShifts[23:20] = tempShifts[23:20]+ 3; >>>> if (tempShifts[27:24] > 4) >>>> tempShifts[27:24] = tempShifts[27:24] + 3; >>>> if (tempShifts[31:28] > 4) >>>> tempShifts[31:28] = tempShifts[31:28] + 3; >>>> if (tempShifts[35:32] > 4) >>>> tempShifts[35:32] = tempShifts[35:32] + 3; >>>> tempShifts = tempShifts << 1; >>>> end >>>> //save the final output >>>> bcdOut = tempShifts[35:16]; >>>> end >>>> endmodule >>>> The warning I get is below: >>>> WARNING:Xst:646 - Signal <tempShifts> is assigned but never used. This >>>> unconnected signal will be trimmed during the optimization process. >>> XST has a brain-dead way of giving warnings about intermediate results. >>> Basically the only bits of tempShifts that are used are effectively >>> renamed to bcdOut. By the way I was under the impression that the >>> repeat operator was not synthesizable. Does this code actually work >>> in the hardware? >>> -- Gabor >> Yea I have successfully implemented this code on a Nexys 2 development >> board, XCS3500E FPGA. > > To implement this wouldn't it just copy the structure as many times as > needed, in this case 13 times? I presume it should be the same as: for (i = 0;i < 13; i = i + 1) However in the past I have never tried "repeat" other than in test benches. My "Verilog Golden Reference Guide" has this to say about repeat for synthesis: "Only synthesizable with some tools, and only then if the loop is 'broken' by a clock event..." Apparently tools have advanced a bit since this book was written. -- GaborArticle: 151940
Hi all, I have a design (written in VHDL) targetting the Spartan 6 series, and it's oversubscribed for LUTs. Can anyone recommend good resources to read? I've already spent a little time looking around the design in ISE's schematic viewer, but with tens of thousands of LUTs it's not exactly a fast process going from that angle, and if possible I'd rather avoid getting into a lot of explicit instantiation of primitives. I've already read the ISE documentation on how to write expressions that the synthesizer can recognize as particular patterns, but unfortunately most of my design is just brute-force combinational logic (a lot of basic boolean operations and additions on fairly wide values) arranged into a pipeline, so the special patterns don't really apply (I don't have counters, or RAMs, or shift registers, or what have you). This is with ISE 13.1, in case it matters, the most recent AFAIK. I do have the option of moving to a larger chip if necessary, but would strongly prefer not to as the one I'm using is the largest supported by WebPack. I've looked at chips in other families, and WebPack seems to top out at similar LUT counts in all the families. Thanks! ChrisArticle: 151941
Christopher Head <chead@is.invalid> wrote: > I have a design (written in VHDL) targetting the Spartan 6 series, and > it's oversubscribed for LUTs. Can anyone recommend good resources to > read? I've already spent a little time looking around the design in > ISE's schematic viewer, but with tens of thousands of LUTs it's not > exactly a fast process going from that angle, and if possible I'd > rather avoid getting into a lot of explicit instantiation of primitives. > I've already read the ISE documentation on how to write expressions > that the synthesizer can recognize as particular patterns, but > unfortunately most of my design is just brute-force combinational logic > (a lot of basic boolean operations and additions on fairly wide values) > arranged into a pipeline, so the special patterns don't really apply (I > don't have counters, or RAMs, or shift registers, or what have you). One of the tricks, which I don't believe the the tools will do automatically, is use the BRAMs in place of logic. That is, use a BRAM as a big look-up table. Since BRAMs are synchronous, you have to fit it in with your pipeline logic, but that shouldn't be so hard to do. -- glenArticle: 151942
On Jun 10, 2:05=A0pm, jc <jcappe...@optimal-design.com> wrote: > On Jun 8, 3:01=A0pm, kclo4 <alexis.ga...@gmail.com> wrote: > > > > > Hello everyone > > > I want to do a for loop in order to repeat the same construction and > > use the number of the loop to create the index to take the desirated > > part of the bus , the problem is that i don't know how to do it and i > > don't know what to look for in google , i would like to do this > > enable_reg(2*i+1 downto 2*i) > > > my code: > > > for i in =A00 to 11 loop > > =A0 =A0case enable_reg(2*i+1 downto 2*i) is > > =A0 =A0 =A0 =A0 when "00" =3D> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0enable_output(i) <=3D '1'; > > =A0 =A0 =A0 =A0 when "01" =3D> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0enable_output(i) <=3D (disc_enab= le(0)); > > =A0 =A0 =A0 =A0 =A0when others =3D> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0enable_output(i) <=3D '0'; > > =A0 =A0 =A0 =A0 end case; > > =A0end for; > > > thank you for your help > > It appears you are taking a 24-bit bus and splitting up into pairs to > derive 12 individual output enable signals, each which can go 0, 1, or > a single enable called disc_enable(0). I'm not sure why you are using > 24-bit bus to gate the passing of a single driving enable signal--it > seems like an additional of complexity perhaps not necessary but I > could be wrong--but a generate statement would work. Google "VHDL > generate." I found out how to do what I want by using variable in which I compute my index and then use this computed variable for my index in the vector extraction so it gives something like that > > for i in 0 to 11 loop index_i :=3D 2*i; index_j :=3D 2*i+1; temp :=3D enable_reg(index_j downto index_i); > > case temp is > > when "00" =3D> > > enable_output(i) <=3D '1'; > > when "01" =3D> > > enable_output(i) <=3D (disc_enable(0)); > > when others =3D> > > enable_output(i) <=3D '0'; > > end case; > > end for; and what that does: In my systeme i have 3 discrete inputs for enable of outputs I have 12 outputs and 1 register of 24bits wich defines which configure the enable to use for the outputs, like this each output has 2 bit to define the output enable that is active on the ouput. enable reg is a register and for rc >> and your level of expertise I think VHDL is the same for dummies and expert just one would know better and go faster anyway thanks for looking at my problem even i fixed by myself (maybe should i 've asked it in vhdl group not fpga)Article: 151943
Chris Are a pile of techniques that can reduce size and a lot depends on the original HDL design and coding style. We do this as one of our services and I have seen designs reduced to 40% of the original design in some extreme cases. Obtaining a 20% reduction to 80% of the original is more typical. As with any engineering prpblem the first thing to do is to identify where your problem might be. I would typically use Floorplanner to identify which modules in your design are the largest. The largest is probably got the most chance of giving you most. On the simple level try speed and area driven synthesis. Area mode does not always give the smallest result. You can also use choice of sythesisers to get different results if you have those available to you. Typically you might get 5-10% out of these techniques but I have seen some extreme sythesiser results giving a X3 variation on some logic. One other thing on synthesis that can make a reasonable difference is the setting for you state machine encoding. Try playing with different settings. If the XST switch isn't broken again try anything but One Hot encoding. XST programmers have a fixation for One Hot encoding and it one gives the best results in less than 25% of designs. Moving to the next level and much more extreme is to look at your HDL. Here you can look for shift registers that can go to SRL16/32 technology in Xilinx parts. That can save a lot. Old techniques like using illegial states in a state machine to reduce logic decoded can also be beneficial. Other techniques like using RAM for multiple related registers may also get you a reduction. John Adair Enterpoint Ltd. - Home of Drigmorn4. The Spartan-6 FPGA Embedded processor Board. On Jun 11, 6:54=A0am, Christopher Head <ch...@is.invalid> wrote: > Hi all, > I have a design (written in VHDL) targetting the Spartan 6 series, and > it's oversubscribed for LUTs. Can anyone recommend good resources to > read? I've already spent a little time looking around the design in > ISE's schematic viewer, but with tens of thousands of LUTs it's not > exactly a fast process going from that angle, and if possible I'd > rather avoid getting into a lot of explicit instantiation of primitives. > > I've already read the ISE documentation on how to write expressions > that the synthesizer can recognize as particular patterns, but > unfortunately most of my design is just brute-force combinational logic > (a lot of basic boolean operations and additions on fairly wide values) > arranged into a pipeline, so the special patterns don't really apply (I > don't have counters, or RAMs, or shift registers, or what have you). > > This is with ISE 13.1, in case it matters, the most recent AFAIK. > > I do have the option of moving to a larger chip if necessary, but would > strongly prefer not to as the one I'm using is the largest supported by > WebPack. I've looked at chips in other families, and WebPack seems to > top out at similar LUT counts in all the families. > > Thanks! > ChrisArticle: 151944
On Jun 11, 1:54=A0am, Christopher Head <ch...@is.invalid> wrote: > Hi all, > I have a design (written in VHDL) targetting the Spartan 6 series, and > it's oversubscribed for LUTs. Can anyone recommend good resources to > read? I've already spent a little time looking around the design in > ISE's schematic viewer, but with tens of thousands of LUTs it's not > exactly a fast process going from that angle, and if possible I'd > rather avoid getting into a lot of explicit instantiation of primitives. > > I've already read the ISE documentation on how to write expressions > that the synthesizer can recognize as particular patterns, but > unfortunately most of my design is just brute-force combinational logic > (a lot of basic boolean operations and additions on fairly wide values) > arranged into a pipeline, so the special patterns don't really apply (I > don't have counters, or RAMs, or shift registers, or what have you). > > This is with ISE 13.1, in case it matters, the most recent AFAIK. > > I do have the option of moving to a larger chip if necessary, but would > strongly prefer not to as the one I'm using is the largest supported by > WebPack. I've looked at chips in other families, and WebPack seems to > top out at similar LUT counts in all the families. > > Thanks! > Chris Have you turned on the area optimization control? Most synthesizers have a trade off between speed and area. Most of the time they seem to default to optimizing for speed. That can easily get you 10% in most designs. As to techniques, first you need to find out where your LUTs are being used. Rather than using tools for that, compile your code one module at a time or in smaller groups of modules. I usually code from the bottom up and test every module in the simulator. So it is not hard to also do a compile and see how large each one is. Then you might be able to see which ones are larger than you expect and can look at how to improve them. RickArticle: 151945
>Hi all, >I have a design (written in VHDL) targetting the Spartan 6 series, and >it's oversubscribed for LUTs. Can anyone recommend good resources to >read? Xilinx white paper WP231 is a good read. It is mainly for speed but shows why doing things like using an asynchronous reset is a really bad plan for both speed and area. If you really don't care about speed then have you considered converting your parallel data paths into serial? Serial adders are really really small. John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151946
Christopher Head <chead@is.invalid> writes: > Hi all, > I have a design (written in VHDL) targetting the Spartan 6 series, and > it's oversubscribed for LUTs. Can anyone recommend good resources to > read? I've already spent a little time looking around the design in > ISE's schematic viewer, but with tens of thousands of LUTs it's not > exactly a fast process going from that angle, and if possible I'd > rather avoid getting into a lot of explicit instantiation of primitives. Have you first established which parts of you design are responsible for the most LUT usage? If not, I wrote FPGAOptim when I was in a similar situation to help with just that: http://www.conekt.co.uk/capabilities/49-fpga-optim Drop me an email via that webpage and I'll get a download link to you. Alternatively, these days Planahead can provide a view on LUT usage, and the logfiles also have some information. Once you know which blocks to optimise, you've had good answers from others already. In my most recent case (a video processing application) there's sections of code which only have to update once per video line - they are prime targets for resource sharing. As John Adair said, reducing by 20% is usually easily doable. With deep knowledge of what's going on and the tradeoffs that are acceptable, I've achieved 40-50% in the past. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 151947
On Jun 12, 7:22=A0pm, "jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >Hi all, > >I have a design (written in VHDL) targetting the Spartan 6 series, and > >it's oversubscribed for LUTs. Can anyone recommend good resources to > >read? > > Xilinx white paper WP231 is a good read. It is mainly for speed but shows > why doing things like using an asynchronous reset is a really bad plan fo= r > both =A0speed and area. > > If you really don't care about speed then have you considered converting > your parallel data paths into serial? Serial adders are really really > small. > > John Eaton Hi John, Thanks for that pointer. I have always been a believer in using the async reset and now I see that this may not always be the best way to reset a design. But the devil is in the details. I wonder if this still applies to non-Xilinx designs? RickArticle: 151948
>On Jun 12, 7:22=A0pm, "jt_eaton" ><z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >Thanks for that pointer. I have always been a believer in using the >async reset and now I see that this may not always be the best way to >reset a design. But the devil is in the details. I wonder if this >still applies to non-Xilinx designs? > >Rick > It applies it all designs. Designers who started their careers with asynchronous logic carried it with them when Design for Synthesis and synchronous design became a requirement but it has never been the best choice. Many designers make the mistake of thinking that because they need an asynchronous reset system that they must design it using asynchronous logic. That is simply not true. We design synchronous systems that are black box equivalent to asynchronous systems all the time. The main thing that you need to realize about reset system design is that the purpose of the reset system is not to reset the system when a trigger event occurs. It's purpose is to NOT reset the system when a trigger event is NOT occuring. The same is true for airbag controllers.The job of an airbag controller is not to deploy the bag when the car is in a accident, it's job is to not deploy the bag when the car is not having an accident. Any system where the expected number of uses is small and the effects of the usage is large will follow this rule. Remember the 1st StarWars movie? They built DeathStar with an emergency exhaust port that provided a direct path from the reactor core to the surface. It was ray shielded but could not be particle shielded. Bad plan. An asynchronous reset has a direct path from a pad into every flip-flop in the entire chip. It is analog shielded but not digitally shielded. Bad plan. Resets in a real product (not a simulation) are really rare events. If a reset is delayed by 20 microseconds then nobody will notice. If a product that you are using suddenly resets itself then you will likely notice. Spend a few hundred cycles on a digital filter before you do something drastic. John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151949
The data arrives with some unknown phase shift relatively to system (synchronized to SDRAM) clock. DQ can be captured more reliably if we route the data clock, DQS, along the data. They suggest that it is easy to transport the received data bursts into the system clock domain using a FIFO afterwards. This is great. I just see a one small problem: How do you know that the read operation takes place so that the captured data are valid for submission into FIFO? A READ_EN signal must be delivered from the SDRAM write/command part (CLK domain) into asynchronously running receiver in DQS domain (the period is the same but phase is unknown) with one DQS clock precision. Remember that we run away from strobing DQ by CLK phases because we do not know the data arriving phase relatively to CLK. That is why we introduced the DQS. But now, we still must figure out the phase shift. It looks like our attempt to do without the phase difference has failed. Why people still use DQS for strobing data instead of some CLK-derived phase?
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