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Authors (C)
c:
4744: 96/12/10: FPGA JOB OFFER
C:
71617: 04/07/25: Re: VHDL
c d saunter:
76718: 04/12/09: Re: Open source FPGA EDA Tools
77681: 05/01/14: Re: Programming and copyright
77683: 05/01/14: Re: Programming and copyright
81704: 05/03/30: Re: Dividing a 24 bit std_logic_vector by a decimal number
81705: 05/03/30: Re: Multi-FPGA PCB data aggregation?
82612: 05/04/14: Re: CCD and Graphics - which FPGA?
82970: 05/04/20: Re: Perl Preprocessor for HDL
84176: 05/05/13: Re: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
85179: 05/06/06: Hope for OS X tools...
85298: 05/06/07: Re: Fast/low area Sorting hardware.
85319: 05/06/07: Re: Fast/low area Sorting hardware.
85666: 05/06/13: Re: Synplify vs XST...
85763: 05/06/15: Re: Auto pipeline logic??
86321: 05/06/25: Re: Need help for Xilinx FPGA
86648: 05/07/01: Re: Direct audio output from FPGA pins
88071: 05/08/08: Re: Xilinx Impact order
88491: 05/08/19: Re: Best FPGA for floating point performance
88646: 05/08/24: Re: FPGA Development Board Wish List
89465: 05/09/15: Re: Starbridge Hypercomputer & Viva
90666: 05/10/18: Re: using i2c core
91313: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
92673: 05/12/04: Tip: Spotlight (OS X) indexing of VHDL files
92721: 05/12/05: Re: Tip: Spotlight (OS X) indexing of VHDL files
92724: 05/12/05: Re: Quick question, how do I supply +-5V?
92730: 05/12/05: Re: Quick question, how do I supply +-5V?
96092: 06/01/30: Re: Digilent FPGA & Handel-C
96188: 06/01/31: Re: Digilent FPGA & Handel-C
96202: 06/01/31: Re: Digilent FPGA & Handel-C
98441: 06/03/10: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
101098: 06/04/25: Re: Opinions on Viva
101203: 06/04/27: Re: How are constants stored ?
101205: 06/04/27: Re: How are constants stored ?
101307: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
101311: 06/04/28: Re: Opteron HT coprocessors
101316: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
101356: 06/04/29: Re: Opteron HT coprocessors
101660: 06/05/04: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101731: 06/05/05: Re: Xilinx 3s8000?
101810: 06/05/07: Re: Opteron HT coprocessors
101822: 06/05/07: Re: Spartan 3e starter kit & Multimedia
101872: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101980: 06/05/09: Re: Crossing clock domains
102084: 06/05/10: Re: Xilinx 3s8000?
102749: 06/05/19: Re: "disappointing" performance
103012: 06/05/24: Re: I2C on Xilinx V4
103289: 06/05/30: Re: Personalization of Xilinx ISE
103429: 06/06/01: Re: Virtex4 FX12 - maximum frequency for Picoblaze
103612: 06/06/06: Re: Who's dying?
104217: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104398: 06/06/26: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
104437: 06/06/27: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
105816: 06/08/01: Re: 100m JTAG cable
107196: 06/08/25: Re: Why No Process Shrink On Prior FPGA Devices ?
111918: 06/11/13: Re: Xilinx USB cable - can't install driver
117775: 07/04/10: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
119356: 07/05/17: Re: Avnet Virtex-4 LX Evaluation Kit USB FX2 Issue
120030: 07/05/31: Re: Nexys by Digilen xbd file
120035: 07/05/31: Re: Nexys by Digilen xbd file
121804: 07/07/13: Re: Counter ?
133151: 08/06/19: VHDL refactoring tools
133266: 08/06/23: Re: NVIDIA’s Tesla T10P Blurs Some Lines
134872: 08/09/04: Re: FPGA on a DIMM module, performing encryption
142666: 09/08/25: Xilinx at LLVM developers meeting
C Kuethe:
14203: 99/01/19: help w/ broken xilinx dongle
<c-d-symes@worldnet.att.net>:
5790: 97/03/15: Re: Accolade
C-M, Chang:
129032: 08/02/13: setup time not met in Quartus
129047: 08/02/13: Re: setup time not met in Quartus
C. C. Lin:
828: 95/03/08: XNF translator
C. F. Fung:
9217: 98/03/03: Questions about creating personal package
9303: 98/03/06: Pricing info for OTP FPGA
C. G.:
92366: 05/11/29: Re: async fifo design
C. Gyselinck:
32902: 01/07/11: emergency consumption reduction for Spartan II
C. Michele Rogers:
15956: 99/04/23: Timing Constraint
16029: 99/04/28: Counters
C. Mueller:
16036: 99/04/29: IRQ Controller
C. Peter:
49432: 02/11/12: FPGA PCMCIA-card?
82318: 05/04/11: CCD and Graphics - which FPGA?
82790: 05/04/18: Re: CCD and Graphics - which FPGA?
C. R. Johnson:
10935: 98/07/05: FPGA Programming Bitstream Compression
C...T:
64525: 04/01/06: [newbie] How to get the value of active pins through JTAG
C.Amendola:
62042: 03/10/17: microblaze data transfer
C.Hermine:
35726: 01/10/15: ask for ispLSI 1016
35730: 01/10/15: ask for ispLSI 1016
<c.j.w@telia.com>:
111177: 06/10/30: How stable is the internal clock of a Xilinx CPLD?
111206: 06/10/31: Re: How stable is the internal clock of a Xilinx CPLD?
C.Jesko:
81706: 05/03/30: FPGA programming via Slave-Serial-Mode
82194: 05/04/08: Re: FPGA programming via Slave-Serial-Mode
82195: 05/04/08: Re: FPGA programming via Slave-Serial-Mode
C.Schlehaus:
27578: 00/11/29: Re: ACEX1K vs FLEX10K
27608: 00/11/29: S: Exaclibur Kit
28205: 00/12/29: Re: MAX+Plus II Output. to HEX
28326: 01/01/06: Re: Altera free software
28328: 01/01/07: Re: Altera free software
29319: 01/02/14: Integrated Conf.EPROM / smaller Footprints?
29448: 01/02/21: Re: Integrated Conf.EPROM / smaller Footprints?
29555: 01/02/26: Re: VHDL:case
29968: 01/03/19: Re: Altera Flex10K config
29978: 01/03/20: Re: Altera Flex10K config
30230: 01/03/29: Problems with NIC and FlexLM / W2K
30262: 01/03/30: Re: Problems with NIC and FlexLM / W2K
30288: 01/03/31: Quartus in W2K System
30514: 01/04/12: Problems Software Build ALTERA Quartus II
30572: 01/04/17: Re: inout pin of DAC
31368: 01/05/21: JTAG and Debugging
31386: 01/05/21: Re: JTAG and Debugging
31388: 01/05/21: Re: JTAG and Debugging
31635: 01/06/01: Re: Second source for Altera EPC1 or EPC2 configuration devices
33008: 01/07/15: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
33376: 01/07/25: Re: Flex 10K10 prototyping system
35261: 01/09/27: Re: Maxplus waveform simulations
36034: 01/10/26: Re: Bi directional pin
36241: 01/11/03: Re: Implementing NIOS softcore in ACEX
36249: 01/11/03: Re: Implementing NIOS softcore in ACEX
36467: 01/11/09: Re: Maxplus error
37578: 01/12/16: Leonardo Spectrum Editor Configuration
38366: 02/01/12: Re: FPGA : Configurtion
39779: 02/02/19: Re: Multipliers in Altera FPGAs
C.W. THomas:
41858: 02/04/09: Re: 32 bit accumulator/comparator PWM?
41862: 02/04/09: Tying Virtex II unused pins to GND???
41896: 02/04/10: DLC4 Download cable question
43149: 02/05/14: Please help me figure out serial prom problem
43202: 02/05/16: Re: SPARTAN II - Master serial mode configuration problem
47962: 02/10/08: HELP !!! IOB wire or errors in ise ver 5.01i
48119: 02/10/11: where can I find the FAQs for this news group???
48121: 02/10/11: HELP !/ How to mark (find) signals in VHDL simulation.
48140: 02/10/11: How to keep components from being optimized out of VHDL
48225: 02/10/14: Re: How to keep components from being optimized out of VHDL
49079: 02/10/31: UCF files how to use???
57189: 03/06/25: Re: Interfacing IDE
C3:
76637: 04/12/08: "Hello World" project for an FPGA (on a Spartan3 board)
78681: 05/02/06: Digilent JTAG cable parallel port pinout (Spartan 3)
78691: 05/02/06: Re: Digilent JTAG cable parallel port pinout (Spartan 3)
78721: 05/02/07: Re: Digilent JTAG cable parallel port pinout (Spartan 3)
c4cheema:
149369: 10/10/19: problem while adding externa MIG IP in design
149370: 10/10/19: How keep OPEN single bit in ucf
C:COMMSDISWIN32KA9QSPOOLMAIL:
1297: 95/05/30: Display EDIF (EDIF -> ORCAD)
cabaret:
52534: 03/02/12: Card developpement
Cable And Computer Tech:
3855: 96/08/09: Job Offering In Orange County, CA
3894: 96/08/15: Job Offering In Orange County, CA
cacosta:
92176: 05/11/23: Support for runtime reconfiguration
<cadamson@horizon.hit.net>:
7235: 97/08/17: Help!!!!
7236: 97/08/17: FPGA Express...
<cadmanager@my-deja.com>:
27189: 00/11/14: Re: Leonardo for Altera
27208: 00/11/15: Re: Leonardo for Altera
27294: 00/11/17: Re: Conversion of Altera POF file for a new config device
27299: 00/11/17: Re: Using FPGA as PCI target
27301: 00/11/17: Re: Basic question on PLD & FPGA
Caeliferum:
150740: 11/02/08: Good FPGA dev kit for a student who is not a complete newbie?
150785: 11/02/10: Re: Good FPGA dev kit for a student who is not a complete newbie?
Cagatay Kalelioglu:
127214: 07/12/14: Chrontel 7010A
127215: 07/12/14: Re: Chrontel 7010A
Cahill schmitz Cahill:
1989: 95/09/29: Re: FPGA for a 20k gates micro-controller.
caihong:
32215: 01/06/19: Spartan
Caillet:
47906: 02/10/07: Re: Low power design
49213: 02/11/05: Re: Anyone has VHDL code for decimator and interpolater?
calaf:
85436: 05/06/09: pcb layers on BGAs Spartan-3
85535: 05/06/10: re:pcb layers on BGAs Spartan-3
91875: 05/11/15: 3 devices on the same external bus
91902: 05/11/16: re:3 devices on the same external bus
91943: 05/11/17: re:Data recovery (XAPP224)
93030: 05/12/12: FPGA in industrial environment
Caleb Hess:
26351: 00/10/12: Long filenames in Express schematic editor
32607: 01/07/02: Re: Xilink WebPACK keeps removing a pin I want to keep.
41365: 02/03/26: Re: Xilinx JTAG Cables
43686: 02/05/29: Re: Xilinx Foundation schematic multi-sheet problem.
46342: 02/08/26: Re: Downloading bit streams in Xilinx
51249: 03/01/08: Re: USB OPENCORE IP usage
51278: 03/01/09: Re: USB OPENCORE IP usage
51311: 03/01/10: Re: USB OPENCORE IP usage
51411: 03/01/13: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
51412: 03/01/13: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
51774: 03/01/21: Re: New Language Generates Verilog, VHDL, and C
51812: 03/01/22: Re: Conditional signal assignment
51849: 03/01/23: Re: VHDL or Verilog?
52305: 03/02/06: Re: Clock Enables
54350: 03/04/08: Re: Reset problem
Caleb Leak:
96398: 06/02/03: FPGA growth vs. ASIC growth
96526: 06/02/06: Re: FPGA growth vs. ASIC growth
<Caleb@audiologic.com>:
3065: 96/03/26: XACT X? on NT
<caleb@audiologic.com>:
2242: 95/11/09: Can X30xx Reset itself?
caliskan:
48849: 02/10/25: Re: DLL and PLL in Xilinx and Altera
<calkins@millenworks.com>:
124141: 07/09/12: Ethernet Code Problem with Xilinx Spartan3E
Callisto:
121521: 07/07/06: ML501 Constraints file problems
122152: 07/07/20: Re: ML501 Constraints file problems
Calum MacGregor:
4516: 96/11/08: Re: PCB Handling of chip packages greater than 100 pins?
Calvin Ball:
151933: 11/06/09: Variable Optimized Away
151935: 11/06/09: Re: Variable Optimized Away
151936: 11/06/09: Re: Variable Optimized Away
Calvin Klein:
48562: 02/10/21: Ms-DOS formatting in an CompactFlash card?
48619: 02/10/22: Re: Ms-DOS formatting in an CompactFlash card?
48620: 02/10/22: Re: Ms-DOS formatting in an CompactFlash card?
48625: 02/10/22: Re: Beginner question
Calvin Lee:
12785: 98/10/30: Re: ahdl to vhdl or verilog
13376: 98/12/01: Re: Help] Altera FloorPlan Editor
<camel_1213@yahoo.com>:
114026: 07/01/02: Wishbone I2C Application
Camelot:
79903: 05/02/25: SD Card question?
Cameron McNairy:
753: 95/02/23: Getting Synopsys to use LCA information
Cameron Watt:
14193: 99/01/19: Re: Intellectual Property
14827: 99/02/19: Re: Xilinx Foundation V1.5
14871: 99/02/22: Re: Eval Activ-VHDL only for 30 day :(
14900: 99/02/24: Re: Xilinx de-compiler
27338: 00/11/19: Re: Using FPGA as PCI target
27339: 00/11/19: Re: manchester decoder
32689: 01/07/05: Xilinx J Drive
Cameron, Charles B.:
65600: 04/02/03: Re: ByteBlaster fails on Windows 98
65935: 04/02/10: Re: Synchronization of signals
Cameron, Gary (EXCHANGE:WDLN2:2Y86):
16081: 99/04/30: Re: High speed reconfigurability
<camil.matiska@gmail.com>:
161404: 19/07/08: Re: Field update
161405: 19/07/08: New uses of FPGAs
<camillo79@gmail.com>:
93672: 05/12/28: Handel-C & DK3
Candida Ferreira:
84230: 05/05/15: Universal logic modules vs NAND-like modules
84247: 05/05/16: Re: Universal logic modules vs NAND-like modules
84260: 05/05/16: Re: Universal logic modules vs NAND-like modules
84313: 05/05/17: Re: Universal logic modules vs NAND-like modules
84555: 05/05/20: Re: Universal logic modules vs NAND-like modules
Candy:
<canest>:
114955: 07/01/28: Minimal design for xilinx?
114965: 07/01/28: Re: Minimal design for xilinx?
114982: 07/01/28: Re: Minimal design for xilinx?
114986: 07/01/28: Problem with verilog program
114992: 07/01/29: Re: Problem with verilog program
cans:
77866: 05/01/18: Re: Time constraints in ISE, help required
Cant Tell You:
16364: 99/05/18: Re: 4062XL problems and solutions
capnx01:
44156: 02/06/12: Re: How to estimate the cost of writing EMBEDDED software ?
captain:
127679: 08/01/05: =?GB2312?Q?about_"tri-states_data_bus"_problem_=D1=A1=CF=EE?=
Captain Bly:
72167: 04/08/10: Re: Altera winner?
72201: 04/08/11: Re: Altera winner?
Captain Charlene Shapiro:
Captain Rick:
78034: 05/01/23: Re: Microscope examination of a PLD
captset.vrn.ru:
30966: 01/05/05: Re: FPGA based PCI cards
carel harmsen:
57106: 03/06/23: Re: regarding I2C protocols
cargopatch:
71856: 04/08/02: Any advice on programming XSA-50 w/ programming header pins
Carl:
57065: 03/06/23: Re: Implementing standard DDR module with Cyclone 1C6 (240PQFP)
57296: 03/06/27: Re: Implementing standard DDR module with Cyclone 1C6 (240PQFP)
62173: 03/10/21: 74 logic to CPLD. how easy for a Newbie?
62202: 03/10/22: Re: 74 logic to CPLD. how easy for a Newbie?
63405: 03/11/21: Re: Altera Max 7000 cpld's
153754: 12/05/13: Re: Best way to get an array of vectors into a vector?
154257: 12/09/18: Re: Global Reset using Global Buffer
156374: 14/03/20: Xilinx ISERDESE2 deserializer primitive behaviour
156397: 14/03/28: Re: Xilinx ISERDESE2 deserializer primitive behaviour
156405: 14/03/29: Re: Xilinx ISERDESE2 deserializer primitive behaviour
156417: 14/04/03: Simulation deltas
156419: 14/04/03: Re: Simulation deltas
156447: 14/04/07: Re: Simulation deltas
156448: 14/04/07: Re: Simulation deltas
156449: 14/04/07: Re: Simulation deltas
156453: 14/04/08: Re: Simulation deltas
Carl Brannen:
37579: 01/12/16: Efficient multiplication using block SRAM...
37580: 01/12/16: Multiplying by squaring using Block RAM.
37592: 01/12/17: Re: Certicom challenge and FPGA based modular math
37597: 01/12/17: Re: Certicom challenge and FPGA based modular math
37598: 01/12/17: Re: Certicom challenge and FPGA based modular math
37600: 01/12/17: Re: Certicom challenge and FPGA based modular math
37656: 01/12/18: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37671: 01/12/18: Divide by 3, with remainder, efficient and fast, for Altera or Xilinx
37681: 01/12/19: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37684: 01/12/19: Re: Kindergarten Stuff
37686: 01/12/19: Re: Divide by 3, with remainder, efficient and fast, for Altera or Xilinx
37697: 01/12/19: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37698: 01/12/19: Low area barrel shift puts 3 to 1 mux in a Xilinx LUT:
37699: 01/12/19: Re: Low area barrel shift puts 3 to 1 mux in a Xilinx LUT:
37700: 01/12/19: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37729: 01/12/19: Efficient new multiplier for Spartan2, Virtex &c.
37748: 01/12/19: How to route a segment at a time with FPGA Editor
37749: 01/12/19: Re: Kindergarten Stuff
37750: 01/12/19: Re: Kindergarten Stuff
37816: 01/12/20: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37825: 01/12/21: An algorithm improvement...
37834: 01/12/21: Re: Clock pins in Virtex-E
37839: 01/12/21: 16x5 multiplier uses new multiply algorithm
37844: 01/12/21: Re: Michelangelo's Counter
37846: 01/12/21: Re: How to make an implementable big counter?
37866: 01/12/21: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37868: 01/12/22: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37869: 01/12/22: Re: Kindergarten Stuff
37870: 01/12/22: Re: Initialization of RAM
37912: 01/12/24: Re: Kindergarten Stuff
37942: 01/12/26: Re: Virtex-2 maximum clock speed
38021: 01/12/31: Re: Stupid Foundation Question (Hey Peter, some Kindergarden stuff for you)
38022: 01/12/31: Re: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
38739: 02/01/23: Re: I2C multiplexer
Carl Christensen:
8281: 97/12/05: Re: VHDL -> XNF via Synopsys
10000: 98/04/21: Re: Xilinx RPMs for DSP (16-tap 8-bit FIR)
10036: 98/04/23: Re: Synopsys FPGA compiler
10537: 98/05/28: Re: Partitioning an a large design in Altera's Max+Plus II
10714: 98/06/11: Re: floorplanning in xilinx
11069: 98/07/16: Re: Floorplanning Intro?
Carl Daniel:
43013: 02/05/09: Re: Have you designed a PCI/Ethernet Adapter using a HDL?
Carl De Far:
51044: 02/12/28: How suppress Xilinx XCT complier warnings: WARNING:HDLCompilers?
51046: 02/12/28: Re: How suppress Xilinx XCT complier warnings: WARNING:HDLCompilers?
Carl H. Scheuermann:
5555: 97/02/24: Re: State Diagram Tools
Carl Hage:
665: 95/02/01: Re: Seeking Info on LPM
Carl Horton:
12753: 98/10/27: Re: Wed. Night: "How To BS Your Way To Fame & Fortune In Consulting"
150690: 11/02/03: FPGA pin re-configuration
150701: 11/02/04: Re: FPGA pin re-configuration
150709: 11/02/04: Re: FPGA pin re-configuration
Carl Ingemarsson:
149020: 10/09/21: CLB relative RLOC constraint in Virtex 4?
Carl L. Meert:
5653: 97/03/04: Re: Serial Communication Controller Design
5656: 97/03/04: Re: 2nd try: What kind of functions mostly implemented using FPGAs?
Carl Langlois:
8738: 98/01/23: DSP vs FPGA
Carl Martin:
16217: 99/05/10: Need Altera 10k Prototype bd
Carl Perkins:
730: 95/02/18: Re: Real-time fractal gen in h/w
Carl R. Poirier:
13667: 98/12/17: Xilinx XC4000 cinfigured from EPC2?
13729: 98/12/21: Re: Xilinx XC4000 cinfigured from EPC2?
13730: 98/12/21: Re: Xilinx XC4000 cinfigured from EPC2?
13731: 98/12/21: Re: Xilinx XC4000 cinfigured from EPC2?
13868: 98/12/30: Re: Xilinx XC4000 cinfigured from EPC2?
Carl Rohrer:
21220: 00/03/10: Re: SpartanXL route and place
25818: 00/09/21: Re: Xilinx Web Pack
25837: 00/09/22: Re: Pack I/O Reg/Latches into IOBs
25838: 00/09/22: Re: Virtex: partial reconfiguration
25840: 00/09/22: Re: A Question on Virtex Configuration
25978: 00/09/28: Re: Difference between Foundation Base and Foundation ISE Base Express?
26544: 00/10/19: Re: PCI Core : Clock Problem
27431: 00/11/21: Re: Xilinx coregen problems
Carl Rouse:
25410: 00/09/11: Xilinx Student Edition 2.1 where?
Carl Smith:
94889: 06/01/19: How much do you trust your CAD Program?
96823: 06/02/11: Re: Altera EPLD
99004: 06/03/18: Re: Urgent Help Needed!!!!!
99019: 06/03/19: Re: Urgent Help Needed!!!!!
Carl Stern:
156: 94/09/02: Re: PLDshell/Intel ftp site
14909: 99/02/25: Re: Place and Route Times question
30756: 01/04/27: Re: PAR single pass vs multi-pass differences
30953: 01/05/04: Re: Internal Error of routing in iSE3.3i
Carl W.:
83066: 05/04/22: Re: Some signals became ? and missing on the simvision, why?
Carl Wuebker:
2555: 96/01/02: Re: Career value: VHDL or Verilog?
3597: 96/07/02: Re: INDUSTRY GADFLY "Why I Hate Wally"
<carl.horton08@gmail.com>:
136718: 08/12/02: Hold Time Requirement
136760: 08/12/04: Re: Hold Time Requirement
136761: 08/12/04: Which terms include the setup time and hold time in Xilinx ISE timing
153891: 12/06/23: What are differences between IBUF and IBUFDS inferred and implemented
CARLA:
143493: 09/10/13: difference between virtex 5 and old versin(virtex3,2)
Carla Sewell:
13338: 98/11/26: Exciting Job Opportunities
Carlhermann Schlehaus:
12365: 98/10/10: Re: VHDL'93 in MaxPlus
12583: 98/10/17: Re: What's wrong at this Address decoder?
14689: 99/02/11: JTAG Test fuer FPGA
14801: 99/02/17: Re: "Altera FreeCore Library" back on the web
14802: 99/02/17: Re: Flex6016 config. problem.
15007: 99/03/03: Re: ALTERA pin assignment
15207: 99/03/13: Re: Power Estimiation
15410: 99/03/23: Re: FLEX 10K question
16122: 99/05/05: Re: Compiler ignores clock input??
16123: 99/05/05: Re: flex10k 1 gate change
16726: 99/06/04: Re: Altera EPC1 PROM + Data IO ChipWriter
16763: 99/06/07: Re: Altera EPC1 PROM + Data IO ChipWriter
17066: 99/06/28: Re: Altera EPC1 replacement?
17254: 99/07/15: Re: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
17468: 99/07/30: Re: Problem with Max+PlusII / Flex10k
17755: 99/08/31: Re: Problem with VHDL in MAX+Plus II / Flex10k
18814: 99/11/17: Re: COM1-FPGA communication
20336: 00/02/06: Re: Alternate to Altera Flex family
20494: 00/02/11: Re: Altera vs Cypress?
20869: 00/02/24: Re: PWM implementation in Flex 10K.
22867: 00/05/29: Re: STD_LOGIC_VECTOR problem.....
23343: 00/06/22: Re: Looking for 'FREE' FPGA software
23470: 00/06/26: Re: FPGA and ASIC
23789: 00/07/08: Re: Where can I get Altera MAX+Plus2 9.x software?
25845: 00/09/22: memory interface trouble...
25868: 00/09/23: Re: memory interface trouble...
25869: 00/09/23: Re: memory interface trouble...
25877: 00/09/24: Re: memory interface trouble...
25882: 00/09/24: Re: memory interface trouble...
26947: 00/11/04: Re: ACEX1K vs FLEX10K
26956: 00/11/05: Re: ACEX1K vs FLEX10K
71802: 04/07/30: Re: Altera Configuration Device
116375: 07/03/08: Re: Spartan3AN - Roadmap
<carlmorada@gmail.com>:
124245: 07/09/16: sounds
Carlo Kovacec:
32004: 01/06/10: Re: FPGA based STN LCD Controller/Driver
Carlo Reinhart:
8237: 97/12/02: Consultant for Image Compression wanted
carlob:
149926: 10/12/02: FSM single process...BIG question
149941: 10/12/02: Re: FSM single process...BIG question
149952: 10/12/03: Re: FSM single process...BIG question
149953: 10/12/03: Re: FSM single process...BIG question
149966: 10/12/03: Re: FSM single process...BIG question
149968: 10/12/03: Re: FSM single process...BIG question
149983: 10/12/05: Re: FSM single process...BIG question
149987: 10/12/05: Re: FSM single process...BIG question
149993: 10/12/06: Re: FSM single process...BIG question
149995: 10/12/06: Re: FSM single process...BIG question
150006: 10/12/06: Re: FSM single process...BIG question
150039: 10/12/07: Re: FSM single process...BIG question
151566: 11/04/20: Free Model Foundry USB3300
151569: 11/04/20: Re: Free Model Foundry USB3300
151576: 11/04/21: Re: Free Model Foundry USB3300
151580: 11/04/21: more precise info
151582: 11/04/21: Re: more precise info
151588: 11/04/22: Re: more precise info
151589: 11/04/22: Re: more precise info
151593: 11/04/22: SOLVED
151662: 11/05/03: Re: help with a power pc processor based software
151852: 11/05/24: Re: Verify failed between address 0x80000 and 0x8FFFF
151860: 11/05/25: Re: Verify failed between address 0x80000 and 0x8FFFF
151913: 11/06/03: verilog task and vhdl
151915: 11/06/03: Re: verilog task and vhdl
151921: 11/06/03: Re: verilog task and vhdl
151923: 11/06/04: Re: verilog task and vhdl
151927: 11/06/06: Re: verilog task and vhdl
Carlos:
64304: 03/12/26: FPGA SRAM
Carlos Correa Goncalves:
6105: 97/04/12: FAQ
Carlos Murillo:
74415: 04/10/11: CORDIC NCO Frequency resolution?
74472: 04/10/12: CORDIC NCO Frequency resolution?
Carlos Stahr:
6669: 97/06/11: Re: PCI how to
16606: 99/05/30: Application Consulting Engineer (ACE)
Carlos Villalpando:
66518: 04/02/20: EDK 6.1 vs 3.2 and OPB Bus resets
66595: 04/02/23: Re: EDK 6.1 vs 3.2 and OPB Bus resets
<carlos.asmat@gmail.com>:
117101: 07/03/22: Re: Xilinx Platform cable USB and impact on linux without windrvr
117169: 07/03/25: Re: Xilinx Platform cable USB and impact on linux without windrvr
Carlton:
73017: 04/09/10: Re: delivering VHDL (RTL) IP core to my customer: how ?
Carlton Blow:
42083: 02/04/15: Re: Using SRL16E Xilinx primitive.
42085: 02/04/15: Re: DLL property control in UCF
42094: 02/04/15: Re: FPGA parameters
<carltonnbd@gmail.com>:
153866: 12/06/14: Re: Virtex 4 Cameralink DCM Limitation
153872: 12/06/18: Re: Virtex 4 Cameralink DCM Limitation
153881: 12/06/20: Re: Virtex 4 Cameralink DCM Limitation
153882: 12/06/20: Re: Data transfers between MicroBlaze and VHDL
153895: 12/06/25: Re: Virtex 4 Cameralink DCM Limitation
153896: 12/06/25: Re: What are differences between IBUF and IBUFDS inferred and
Carmen Baena Oliva:
8355: 97/12/10: combinational multipliers
carmen lee:
58179: 03/07/16: Re: Xilinx ECS Schematic Entry
Carol Perkins:
2230: 95/11/06: IMPORTANT WORLD COMMUNITY PUBLIC ANNOUNCEMENT
Carolyn:
<carshie>:
115110: 07/01/31: cpld version?
115119: 07/01/31: Re: cpld version?
115120: 07/01/31: Where is help for schematic entry?
115121: 07/01/31: Re: Where is help for schematic entry?
115126: 07/01/31: Re: cpld version?
115127: 07/01/31: Question about simple design
115134: 07/01/31: Re: Question about simple design
115135: 07/01/31: Re: cpld version?
115145: 07/02/01: Re: cpld version?
115156: 07/02/01: Re: cpld version?
115157: 07/02/01: Re: cpld version?
Carson He:
123178: 07/08/18: Re: Xilinx MIG DDR2 initialization problems
Carson Pun:
77160: 04/12/27: newbie in fpga, sincerely look for guidance
Carsten:
39851: 02/02/21: Re: Orca FPSC synthesizing issue
40031: 02/02/25: EDIF netlist in FPGA Express
40093: 02/02/27: Re: Orca FPSC synthesizing issue
75977: 04/11/21: Re: Altera chip identification
76053: 04/11/23: Re: Low cost million gate Spartan 3 board?
76054: 04/11/23: Re: Low cost million gate Spartan 3 board?
76055: 04/11/23: Re: Spartan 3 output voltage level
78410: 05/01/31: Re: spartan3 starter kit now comes with eval version of edk
78968: 05/02/10: Re: Spartan-3 Starter Kit supplier in the UK?
79813: 05/02/24: Re: Spartan-3 Starter Kit supplier in the UK?
80318: 05/03/03: Re: spartan3 development board in Europe?
80380: 05/03/04: Re: spartan3 development board in Europe?
81250: 05/03/20: Re: ISE 7.1 WebPack + EDK 6.3
86858: 05/07/07: Re: Small FPGA
92413: 05/11/29: Re: boot from flah
92934: 05/12/09: Re: How to connect 2 FPGA?
100745: 06/04/17: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
100777: 06/04/18: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
100778: 06/04/18: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
138308: 09/02/14: Re: Logic Analyzer
Carsten =?iso-8859-1?Q?N=F6ding?=:
22448: 00/05/09: virtex e lvds clock recovery
Carsten Heise:
39760: 02/02/19: Orca FPSC synthesizing issue
Carsten Nöding:
30708: 01/04/25: Pin A1 on Spartan2 chips
30714: 01/04/25: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
31095: 01/05/11: Re: SpartanII: non clock pad drives clock net ?
Carsten Trinitis:
15921: 99/04/21: Cadence Europractice System Package
carstenherr:
158465: 15/12/01: Re: Found: an FPGA with internal tri-states
158466: 15/12/01: Re: Sum of 8 numbers in FPGA
carter:
74171: 04/10/05: How to use Xilinx Virtex-II Pro to read and write NAND FLASH.
74173: 04/10/05: HOw to use Xilinx Virtex-II Pro to read and write FLASH
Carter Buck:
54111: 03/04/02: Re: [Question] FPGA/PLX9054
Carter De Leo:
119625: 07/05/24: fit_timer: trouble connecting interrupt
<cartman_sspi@my-deja.com>:
19324: 99/12/14: Re: Virtex boards
<cartoffice@mail3.clio.it>:
13401: 98/12/01: Re: Which parts are fastest for 3-state enables?
Cary Goltermann:
21938: 00/04/07: Re: Any free design of 8051 in the net?
Cary McCormick:
33719: 01/08/02: Clock skew with Xilinx DLLs...
Cary Snyder:
7984: 97/11/05: Re: Help with 64 bit, 33MHz PCI bridge in FPGA...
7995: 97/11/05: Re: Help with 64 bit, 33MHz PCI bridge in FPGA...
cas7406@yahoo.com:
77749: 05/01/15: Re: Lattice DDR Interface
81184: 05/03/18: Re: Spartan 3E vs. Cyclone2
81452: 05/03/23: Re: LogicAnalyzer ispTracy
81459: 05/03/23: Re: Lattic ECP/EC -- Partial Run-time Reconfiguration??
83096: 05/04/23: Re: Bug in DDR template in Lattice FPGAs ?
83269: 05/04/26: Re: Bug in DDR template in Lattice FPGAs ?
86009: 05/06/20: Re: Lattice LFEC
CASES:
Casey:
47859: 02/10/05: FIFO Simulation problem
47905: 02/10/07: Re: FIFO Simulation problem
Casey Lang:
9284: 98/03/05: Re: ++ TMS320C6x DSP info website ++
Casey Smith:
9519: 98/03/20: Linux Xchecker Downloads?
9975: 98/04/20: Help! Writing to IDE hard drive
148329: 10/07/07: Controlling Path Delay with Constraints?
148346: 10/07/09: Re: Controlling Path Delay with Constraints?
cash:
10149: 98/04/29: $$$Show me the money!!!
Cash Cow:
Casio:
93896: 06/01/03: My design to big for the FPGA or not?
93908: 06/01/03: Re: My design to big for the FPGA or not?
Caspar Steineke:
9601: 98/03/25: Re: USB bus interface (12 mbit/sec) in an FPGA - how difficult?
9602: 98/03/25: Re: Partially reconfigurable FPGA
Casper K. Chen:
7003: 97/07/22: Altera and Synopsys
Cassie15:
Catalin:
11416: 98/08/11: Re: Combinatoric Divide-by-3 Algorithm
11464: 98/08/17: Re: Combinatoric Divide-by-3 Algorithm
11463: 98/08/17: Re: Combinatoric Divide-by-3 Algorithm
11623: 98/08/27: Re: How to design a PLL
11782: 98/09/09: Re: Altera 10K20 Register File Implementation??
11799: 98/09/10: Re: Design Security Question
11804: 98/09/10: Re: Design Security Question
11891: 98/09/17: Re: Xilinx Spartan and 4K speed grades
15038: 99/03/03: Re: Clock divider: 100MHz->40MHz
15056: 99/03/04: Re: Clock divider: 100MHz->40MHz
15060: 99/03/04: Re: Clock divider: 100MHz->40MHz
15119: 99/03/08: Re: Getting started in programmable logic
15941: 99/04/22: Re: How to use TDO pin of Xilinx4000 in Exemplar ?
27190: 00/11/14: Re: CRC, LFSR and scramblers
49290: 02/11/07: Wrong speed specs for Spartan II ??
50027: 02/11/28: Spartan-II 2S200 PCI Board
Catalin Baetoniu:
21516: 00/03/24: Re: No- FPGA openness
22329: 00/05/05: Re: How to Prevent theft of FPGA design
22331: 00/05/05: Re: How to Prevent theft of FPGA design
22332: 00/05/05: Re: How to Prevent theft of FPGA design
22368: 00/05/06: Re: How to Prevent theft of FPGA design
22374: 00/05/06: Re: Configuration process %-(
29338: 01/02/15: Re: Rijndael
29524: 01/02/25: Metastability data for Spartan2, Virtex and VirtexE?
29802: 01/03/11: Re: Using LVDS I/O buffers on Virtex-II
31098: 01/05/11: Re: SpartanII: non clock pad drives clock net ?
34935: 01/09/14: Re: Block RAM initialization
35001: 01/09/17: Re: how to simulate virtex components?
Catalin Patulea (eigma):
130460: 08/03/25: Re: Remote access to Altera FPGA via jtagd in Linux
catherina:
30118: 01/03/23: speech
30119: 01/03/23: tst
30120: 01/03/23: tst
30153: 01/03/26: hybrid design entry
30163: 01/03/26: Re: hybrid design entry
Catherine Dezan:
6896: 97/07/07: Two days courses on XC6200 - First in FRANCE (BREST)
Catherine Trammell:
104122: 06/06/19: Aurora core example simulation
cathy:
109085: 06/09/20: Question about initializing on-chip block mem in XPS?
109090: 06/09/20: Re: Question about initializing on-chip block mem in XPS?
109106: 06/09/20: Re: Question about initializing on-chip block mem in XPS?
109146: 06/09/21: Re: Question about initializing on-chip block mem in XPS?
109178: 06/09/21: Re: Question about initializing on-chip block mem in XPS?
111152: 06/10/30: Question about importing modules to XPS.
112680: 06/11/27: What's the speed grade for the XC5VLX50 on xilinx ML501 evaluation board?
112688: 06/11/27: Re: What's the speed grade for the XC5VLX50 on xilinx ML501 evaluation board?
115008: 07/01/29: question about DCM usage in virtex 5
115016: 07/01/29: Re: question about DCM usage in virtex 5
115417: 07/02/09: uestion about "clock signal" in Xilinx EDK design. (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING )
115421: 07/02/09: Re: uestion about "clock signal" in Xilinx EDK design. (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING )
115445: 07/02/11: question about DCM in virtex5: fails the maximum period check
115480: 07/02/12: Re: question about DCM in virtex5: fails the maximum period check
115891: 07/02/23: Re: MicroBlaze and OPB block ram interface controller run at different frequency
cationebox@gmail.com:
94472: 06/01/12: Re: How to create a delay BUF?
127498: 07/12/28: what is the difference between system side XAUI and line side XAUI?
catto:
152535: 11/09/08: reduce EDK synthesis time
Cauleys:
7942: 97/11/01: REMEMBER THE WATKINS MAN??
Cavailles Eric:
51137: 03/01/03: Latch edge sensitive on data & RESET
cavalry:
151374: 11/03/29: Spartan 3e FPGA and data from matlab workspace.
cb:
61172: 03/09/29: Re: USB Core (Japanese Version)
CB:
53311: 03/03/10: Altera Clock
53340: 03/03/11: Re: Altera Clock
53673: 03/03/19: Altera ACEX 1K
53959: 03/03/28: Quartus Synthesis
54735: 03/04/17: spartan2e vs cyclone
54800: 03/04/18: Re: spartan2e vs cyclone
55393: 03/05/06: Re: use of DRAM as massive FIFO
57861: 03/07/08: Re: Rant mode ON
59280: 03/08/13: Re: Limitations of Quartus II V3.0 Web
59854: 03/08/29: Re: pricing, cyclone or spartan
CBFalconer:
31636: 01/06/01: Re: My80-- i8080A instruction compatible processor core
31666: 01/06/02: Re: My80-- i8080A instruction compatible processor core
33737: 01/08/03: Re: 4 (8) bit Microporcessor Implementation
50454: 02/12/11: Re: Some boards for designers...
56042: 03/05/27: Re: JTAG madness
56527: 03/06/07: Re: Logical analyzer via USB or printer port
57151: 03/06/24: Re: regarding I2C protocols
64925: 04/01/16: Re: Hardware to test (FPGA-based) prototype?
67650: 04/03/16: Re: Schematic Edition Tool : Suggestions
72935: 04/09/08: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
85878: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
94982: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95121: 06/01/20: Re: OT:Shooting Ourselves in the Foot
106010: 06/08/05: Re: Where are Huffman encoding applications?
108086: 06/09/05: Re: Please help me with (insert task here)
108230: 06/09/06: Re: Please help me with (insert task here)
109201: 06/09/21: Re: Dell Laptop for Embedded Work
109239: 06/09/22: Re: Dell Laptop for Embedded Work
109283: 06/09/22: IBM Thinkpads, used (was: Dell Laptop for Embedded Work)
110269: 06/10/13: Re: OT: Internships?
111102: 06/10/29: Re: Hardware mapping of algorithms
113692: 06/12/19: Re: interrupt handling using microblaze with XPS
113707: 06/12/19: Re: interrupt handling using microblaze with XPS
115519: 07/02/13: Re: Building Coaxial transmission line on PCB?
115678: 07/02/16: Re: Building Coaxial transmission line on PCB?
115719: 07/02/17: Re: Building Coaxial transmission line on PCB?
117750: 07/04/09: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
118606: 07/04/30: Re: debounce state diagram FSM
118660: 07/05/01: Re: debounce state diagram FSM
118701: 07/05/02: Re: debounce state diagram FSM
118702: 07/05/02: Re: debounce state diagram FSM
118740: 07/05/02: Re: debounce state diagram FSM - topical
124071: 07/09/11: Re: Uses of Gray code in digital design
124086: 07/09/11: Re: Uses of Gray code in digital design
124095: 07/09/12: Re: Uses of Gray code in digital design
125363: 07/10/23: Re: Changing refresh rate for DRAM while in operation?
125433: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
125491: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
126678: 07/11/29: Re: lossless compression in hardware: what to do in case of
126788: 07/12/02: Re: lossless compression in hardware: what to do in case of
131923: 08/05/07: Re: ANNC: FPGA Design Software Webcast
131961: 08/05/08: Re: ANNC: FPGA Design Software Webcast
131963: 08/05/08: Re: ANNC: FPGA Design Software Webcast
131973: 08/05/08: Re: ANNC: FPGA Design Software Webcast
132808: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132873: 08/06/09: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
133493: 08/07/01: Re: lwip for FPGA
133932: 08/07/19: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133938: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133948: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133959: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
140227: 09/05/04: Re: High-speed signals crossing a split-ground
<cbkohw@penis.nl>:
14571: 99/02/04: _____FAQ list for this newsgroup_____ 8899
cbr_929rr:
109647: 06/10/02: I2S serial to parallel conversion and generating C,V and Z bits
109649: 06/10/02: Re: I2S serial to parallel conversion and generating C,V and Z bits
109655: 06/10/02: Re: Looking for HDL code for sin( a ) and x ** y Functions
109658: 06/10/02: Re: Looking for HDL code for sin( a ) and x ** y Functions
109799: 06/10/05: SMPTE310 interface
109803: 06/10/05: Re: SMPTE310 interface
110607: 06/10/18: Using Opencores I2S master
110662: 06/10/19: Re: Using Opencores I2S master
111043: 06/10/27: Re: Using Opencores I2S master
CC:
114764: 07/01/23: Xilinx Constraints Editor doesn't work anymore?
CC Nguyen:
53392: 03/03/12: PCI parity question
53402: 03/03/12: Re: PCI parity question
53410: 03/03/12: Re: PCI parity question
54388: 03/04/09: Double Edge FlipFlop
55675: 03/05/15: Re: Doubling data output without DRR banks and without double clock frequency
ccc:
28706: 01/01/22: test
ccchen:
60682: 03/09/19: DigiLab2 Spartan 2 : Can't download..
60917: 03/09/24: Re: DigiLab2 Spartan 2 : Can't download..
CCnguyen:
54484: 03/04/11: Re: Double Edge FlipFlop
CCNguyen:
54585: 03/04/14: Re: Double Edge FlipFlop
CCON:
66020: 04/02/11: Re: SPARTAN2 BUFG mapping
ccon:
66030: 04/02/11: Re: FIR filter coefficient (with COE file)
66429: 04/02/19: Virtex-II Speed grade -6 exist?
66445: 04/02/19: Re: Virtex-II Speed grade -6 exist?
67493: 04/03/12: Re: Virtex 2 P -> PPC write to block RAM
67816: 04/03/19: Re: Why It Is not Recommended to Infer latches in VLSI Design...
<ccon67@netscape.net>:
84855: 05/05/30: Re: VHDL vs. Schematic Capture
84890: 05/05/31: How fast multiplier in VirtexE?
84950: 05/06/01: Re: problems with Ultra DMA operations with ATA HDD
93475: 05/12/22: edif to vhd black box
94165: 06/01/06: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
ccu:
29398: 01/02/19: ALtera CPLD
cdb:
149427: 10/10/25: 0x80000000 Integer not supported??
149430: 10/10/25: Re: 0x80000000 Integer not supported??
cde:
57214: 03/06/25: Re: Transfer between clock domains at 350 MHz
cdsipjp:
76975: 04/12/17: Re: Xilinx Student Foundation Edition on Windows-XP ??
<cdsmith69@gmail.com>:
94101: 06/01/05: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94111: 06/01/05: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94222: 06/01/08: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94120: 06/01/05: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94224: 06/01/08: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94242: 06/01/08: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94220: 06/01/08: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94223: 06/01/08: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94212: 06/01/07: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94296: 06/01/09: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94329: 06/01/10: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
<cealone@aol.com>:
15480: 99/03/25: "WHAT’S THAT ROTTEN SMELL IN PHOENIX?"...We need your help!
<cecarrion1@gmail.com>:
90711: 05/10/19: Re: dagen.exe,where can i get it,thanks(for digital filter)
Cecil Bayona:
158937: 16/05/27: Advice to a newbie
158940: 16/05/27: Re: Advice to a newbie
158943: 16/05/27: Re: Advice to a newbie
158944: 16/05/27: Re: Advice to a newbie
158948: 16/05/27: Re: Advice to a newbie
158949: 16/05/28: Re: Advice to a newbie
158952: 16/05/28: Re: Advice to a newbie
158958: 16/05/28: Re: Advice to a newbie
158961: 16/05/28: Re: Advice to a newbie
158962: 16/05/28: Re: Advice to a newbie
158973: 16/05/30: Re: Advice to a newbie
158979: 16/05/30: Re: Advice to a newbie
158998: 16/06/03: Re: Advice to a newbie
159000: 16/06/03: Re: Advice to a newbie
159002: 16/06/03: Re: Advice to a newbie
159006: 16/06/04: Re: Advice to a newbie
159011: 16/06/10: Re: Advice to a newbie
159013: 16/06/10: Re: Advice to a newbie
159015: 16/06/10: Re: J1 forth processor in FPGA - possibility of interactive work?
159031: 16/06/17: Re: J1 forth processor in FPGA - possibility of interactive work?
159033: 16/06/18: Re: Active HDL Generic Controls
159036: 16/06/18: Re: Active HDL Generic Controls
159038: 16/06/19: Re: Active HDL Generic Controls
159040: 16/06/24: Re: J1 forth processor in FPGA - possibility of interactive work?
159041: 16/06/29: Problem with Lattice Diamond IPExpress software.
159117: 16/08/04: Re: Vivado parses wicked slow
159119: 16/08/04: Re: Vivado parses wicked slow
159183: 16/08/29: Re: Help me choose an FPGA to design network protocols
159185: 16/08/29: Re: Help me choose an FPGA to design network protocols
159188: 16/08/29: Re: Help me choose an FPGA to design network protocols
159191: 16/08/29: Zero Address CPU logic
159193: 16/08/30: Re: Zero Address CPU logic
159266: 16/09/18: Re: requirement for PC for VHDL design
159268: 16/09/18: Re: requirement for PC for VHDL design
159345: 16/10/13: Re: CORDIC in a land of built-in multipliers
159398: 16/10/24: Re: Free timing diagram drawing software
159416: 16/10/25: Re: Free timing diagram drawing software
159419: 16/10/26: Re: Free timing diagram drawing software
159464: 16/11/19: Re: Tools on Linux
159537: 16/12/05: Linux OS for FPGA worth
159539: 16/12/06: Re: Linux OS for FPGA worth
159959: 17/05/02: Re: RISC-V Support in FPGA
160009: 17/05/10: Re: increment or decrement one of 16, 16-bit registers
160134: 17/06/16: Re: Whups. Lattice Diamond says my package does not exist.
160174: 17/07/22: Re: sram
Cecil Kaplinsky:
4057: 96/09/06: Re: EPROM Xilinx second source
Cecile Chicheportiche:
20201: 00/01/31: Xilinx memory instantiation (VHDL, FPGA Express 3.3)
cecilia annovi:
79948: 05/02/26: block adder for Altera!
79971: 05/02/27: Re: block adder for Altera!
80021: 05/02/28: packages(2)
80098: 05/03/01: Re: packages(2)
80099: 05/03/01: Re: block adder for Altera!
cedi:
51922: 03/01/26: Bus models & test benches
cedric:
77928: 05/01/20: Simulation error with ModelSim
77989: 05/01/21: Poblem with Xilinx ISE
78502: 05/02/01: Constraint on a asynchronous signal
79325: 05/02/17: Simple counter
Cedric Lichtenau:
9103: 98/02/20: Re: buft and bufe
Cees Binkhorst:
150438: 11/01/21: Re: Overview for non-technicals.
150470: 11/01/24: Re: Overview for non-technicals.
cehon:
90704: 05/10/19: dagen.exe,where can i get it,thanks(for digital filter)
Celeritous:
14530: 99/02/03: VHDL clocked one-shot Implementation Problem
14581: 99/02/04: Re: VHDL clocked one-shot Implementation Problem
Celia C.:
3900: 96/08/16: Re: Technical Job posting ( and ads) not related to the newsgroup.
4846: 96/12/19: Re: Exemplar's Leonardo on Linux
celia clause:
1563: 95/07/17: Re: AT&T FPGAs - Opinions needed
Celia Clause:
3427: 96/05/28: Re: impossible for Synthesizer to optimize FSM??!
<cell_rx@msn.com>:
89051: 05/09/03: IC design contract
Cemal Coemert:
17931: 99/09/17: DSP in FPGA
28854: 01/01/26: Re: Field Programmable Gate Array selection and task suitability
Cemal Coemert (TIP):
16154: 99/05/06: DSP in FPGA
33587: 01/07/31: Re: multi-context FPGA
43921: 02/06/06: Re: FPGA destruction vs power management
44634: 02/06/25: Re: fast adders using HDL in Xilinx fpga
2cents:
149626: 10/11/12: Re: cool BGA pattern
149631: 10/11/12: Re: cool BGA pattern
149638: 10/11/12: Re: cool BGA pattern
149658: 10/11/15: Re: cool BGA pattern
149702: 10/11/18: Re: cool BGA pattern
150038: 10/12/07: Re: Linux on Microblaze
151067: 11/03/03: Latest Xilinx Software
cenzatol@dei.unipd.it:
112788: 06/11/29: Bus Lock
Cephas Lin:
8070: 97/11/14: Digital PLL?
<cepope@mindspring.com>:
<cepope@nc.rr.com>:
134596: 08/08/20: need efficient multichannel DDC on V4
CEREBRAL ASSASSIN:
Ceri Workman:
4757: 96/12/11: Re: Xilinx configuration PROM
cesarp:
124397: 07/09/20: DMA scatter gather with PLB bus?
124425: 07/09/21: Re: DMA scatter gather with PLB bus?
CEWI466:
1043: 95/04/19: Re: journal suggestions
CF:
60670: 03/09/19: Parallel JTAG cable on a USB-only W2K laptop?
60737: 03/09/20: Re: Parallel JTAG cable on a USB-only W2K laptop?
<cfbsoftware@gmail.com>:
157954: 15/05/22: Re: Oberon Operating System + Compiler + Graphic on a Spartan 3 FPGA
158233: 15/09/26: Re: Soft core processors: RISC versus stack/accumulator for equal
158244: 15/09/28: Re: Soft core processors: RISC versus stack/accumulator for equal
159394: 16/10/24: Re: verilog code
159637: 17/01/25: Re: Anyone use 1's compliment or signed magnitude?
159661: 17/01/26: Re: Anyone use 1's compliment or signed magnitude?
cfelton:
146012: 10/03/03: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146030: 10/03/04: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146863: 10/03/30: Re: Xilinx Webpack v11.4 availability
147057: 10/04/12: Re: I'd rather switch than fight!
147067: 10/04/12: Re: I'd rather switch than fight!
147068: 10/04/12: Re: I'd rather switch than fight!
147081: 10/04/13: Re: I'd rather switch than fight!
147116: 10/04/14: Re: I'd rather switch than fight!
147937: 10/06/03: Re: How good are Actel tools
148363: 10/07/15: Re: Another Xilinx webpack download rant
150193: 10/12/30: XST Fails 2D array wild card sensitivity list
150194: 10/12/30: Re: Verilog inout, I2C
150197: 10/12/30: Re: I Give Up!
150699: 11/02/04: Re: Trivia: Where are you on the HDL Map?
150700: 11/02/04: Re: Trivia: Where are you on the HDL Map?
150705: 11/02/04: Re: Bit-accurate C simulation
150737: 11/02/07: Re: Trivia: Where are you on the HDL Map?
150748: 11/02/08: Re: Trivia: Where are you on the HDL Map?
150749: 11/02/08: Re: Trivia: Where are you on the HDL Map?
cfischer:
10903: 98/06/29: Re: Free Computer (Read--Easy, No money down)
cfk:
43306: 02/05/18: button & 3 LED's
43310: 02/05/18: Re: Bidirectional DONE?
43826: 02/06/04: chipscope
43907: 02/06/06: IOSTANDARD
43971: 02/06/07: Re: IOSTANDARD
43973: 02/06/07: opencore PCI bridge versus LogiCORE
44246: 02/06/14: GCK input routing
44247: 02/06/14: Re: MAP problem with RLOC'ed macros
44274: 02/06/15: Re: Stupid WebPack question
44436: 02/06/20: Re: Power supply caps on PCB
44497: 02/06/21: adding timing constraints
44552: 02/06/23: Re: Bad Virtex2 devices - any similar experiences
44555: 02/06/23: CLK/2
44923: 02/07/05: N-bit, 2-input adder
45363: 02/07/20: Re: Problem with OpenCore PCI IP Core
45581: 02/07/27: Re: 32-bit PCI Target core
45582: 02/07/27: Re: Problem with mapping
45704: 02/08/01: Re: Impedance Measureing
46276: 02/08/23: Alliance VLSI software
46279: 02/08/23: Re: Help for Schematic Components
46294: 02/08/24: Re: Help for Schematic Components
46305: 02/08/25: sensing an oscillator
46315: 02/08/26: Re: sensing an oscillator
50954: 02/12/24: Prom Splitting
54521: 03/04/12: Re: Help installing Altera web tools
54539: 03/04/13: Re: Help installing Altera web tools
55320: 03/05/03: 802.11
55331: 03/05/04: Re: 802.11
55364: 03/05/06: Re: 802.11
55751: 03/05/18: 802.11
57011: 03/06/20: Re: Output signal problem.
58866: 03/08/03: Re: Unused Pins on big Virtex-II
59121: 03/08/08: Synopsys search path
59375: 03/08/17: Re: serial communication between pc and altera fpga
60174: 03/09/06: Re: VGA display
<cfp.hctlopen@gmail.com>:
155153: 13/05/09: Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs
CG:
9528: 98/03/21: Re: Dual port
ch:
32175: 01/06/18: ee
<ch794@freenet.buffalo.edu>:
6684: 97/06/13: FPGA-like chip
cha:
2029: 95/10/04: Memory Protection Fault
2043: 95/10/05: Viewsim S/D
CHa5253105:
12918: 98/11/04: Re: Concept or Viewlogic viewer?
<cha>:
2050: 95/10/06: Programming a daisy chain of XC4000
2057: 95/10/07: XsimMake fails
2081: 95/10/11: I NEED YOUR HELP !!!!!!!!!!!!!!
2085: 95/10/11: Re: I NEED YOUR HELP !!!!!!!!!!!!!!
2078: 95/10/11: Internal error 1012 (ppr)
2079: 95/10/11: XACT 5.1 is incompatible with everything!!!!!!!!
2133: 95/10/18: Re: "XACT 5.1 is incompatible with everything!!!!!!!!" -- a mild exaggeration, plus some Win95 hints
2183: 95/10/27: Internal Error 1012 & its causes
2233: 95/11/07: Re: X-Blox...The good, bad and ugly
2274: 95/11/16: WHO WAS THE XACT'S PROGRAMMER?
Chad Bearden:
7368: 97/09/03: hdtv interpolation and decimation
17827: 99/09/08: Virus virtex_arch.zip in file?
61736: 03/10/09: pci-x133 to parallel pci-66
61765: 03/10/10: Re: pci-x133 to parallel pci-66
61767: 03/10/10: Re: pci-x133 to parallel pci-66
62003: 03/10/16: pci protocol analyzer
62011: 03/10/16: 3rd party pci dma engine
<chadlamb@my-deja.com>:
17697: 99/08/25: Virtex BRAM Initialization
17710: 99/08/25: Re: Virtex BRAM Initialization
21666: 00/03/28: Re: Xilinx DLL properties
21667: 00/03/28: Re: Preferred Configuration Approach
22507: 00/05/10: Re: virtex configuration with synplify
25849: 00/09/22: Re: JTAG CPLD FPGA
25851: 00/09/22: Re: Virtex 1800 series ISP proms
27273: 00/11/16: Re: Problems wirh JTAG-Configuration of 18V512 and Spartan XCS40
<chadland@online.no>:
108844: 06/09/18: Writing VHDL, Software dummy!
108897: 06/09/18: Re: Writing VHDL, Software dummy!
Chaffey, Paul:
30640: 01/04/20: Free timing diagram editor
30723: 01/04/26: TimingTool and Netscape
Chai Mee Joon:
28611: 01/01/18: WTB: Virtex-based board
chai2m:
141859: 09/07/14: Master initialization problem with xilinx 32 bit pci master/target ipcore
chaitanya163:
156887: 14/07/22: Generating a desired synthesizable binary pulse train on FPGA using VHDL
ChaitanyaB:
142245: 09/07/30: Re: Daisychaining fpga with SPI flash?
chaitanyakurmala@gmail.com:
128479: 08/01/28: equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera Stratix
145581: 10/02/14: optimal no of inputs to be given in a test bench
chaitu11311@gmail.com:
96830: 06/02/11: which one among the available FPGAs is best for a fresher?
<chakanp@hem1.passagen.se>:
9429: 98/03/13: Re: Altera Programmer with NT4
9796: 98/04/06: Re: installation altera maxplus2 8.2
chakra:
100219: 06/04/05: EDK7.1 - error in Libgen for Linux OS - Xilinx ML300 board
100226: 06/04/05: Re: EDK7.1 - error in Libgen for Linux OS - Xilinx ML300 board
100631: 06/04/13: Problem: Invalid Processor Version Number 0x00000000- EDK-7.1- latest service pack, ML310, bootloop, download bitsream
100994: 06/04/23: Re: Problem: Invalid Processor Version Number 0x00000000- EDK-7.1- latest service pack, ML310, bootloop, download bitsream
101112: 06/04/25: USB slot on Xilinx ML310 board - linux platform
101851: 06/05/07: booting problem ML300 :eth0: Could not read PHY control register; err
102128: 06/05/10: Re: booting problem ML300 :eth0: Could not read PHY control register; err
102344: 06/05/15: Re: booting problem ML300 :eth0: Could not read PHY control register; err
118147: 07/04/18: Issues with the BBD file, using a core generated using ISE coregenerator
118158: 07/04/18: Re: Issues with the BBD file, using a core generated using ISE coregenerator
118739: 07/05/02: OPB Master Peripheral
121000: 07/06/21: Re: OPB Master Peripheral
121619: 07/07/09: DDR SDRAM simulation model, ML300, Infineon
121620: 07/07/09: Re: DDR SDRAM simulation model, ML300, Infineon
121636: 07/07/10: Re: DDR SDRAM simulation model, ML300, Infineon
128428: 08/01/25: OV7660 CMOS camera
129569: 08/02/27: Bus2IP_WR/RDCE XIO_Out/in32 EDK 9.1
129582: 08/02/27: Re: Making changes to custom IP in EDK
129698: 08/03/03: Re: Bus2IP_WR/RDCE XIO_Out/in32 EDK 9.1
139230: 09/03/23: cutting down opb_clk cycles while read-write BRAM-DDR in FPGA
ChampDog:
113882: 06/12/27: Re: What next next big thing coming for HDL?
113883: 06/12/27: Re: What next next big thing coming for HDL?
Chandrakiran:
38418: 02/01/14: Re: Xilinx PAR and Editor speed up
chandrakiran Verma:
38575: 02/01/17: Floorplanning :Problem in floorplanning
Chandramohan Sateesh:
17997: 99/09/22: Re: xilinx v2.1i
19360: 99/12/16: Re: Synopsys backannotation
31374: 01/05/21: Re: XilinxCoreLib with Renoir
Chandrasekhar:
72240: 04/08/11: CLOCK_SIGNAL Constraint.
76649: 04/12/07: Clock Gating !!!
<Chandru.Kundagol@gmail.com>:
100919: 06/04/21: problem with shift operation
Chanemou:
71671: 04/07/27: PCI driver for ARM processor
Changchun WAN:
41158: 02/03/22: HELP me, about chipscope analyzer
change c:/user/winvn/winvn.ini Not configured change c:/user/winvn/winvn.ini:
1119: 95/05/02: Re: Looking for XNF format definition
Changeun:
28456: 01/01/13: I wanna Model Sim cracked
changewhere:
79693: 05/02/23: what's the difference between syn FIFO and asyn FIFO?
ChangHo Bae:
15898: 99/04/20: texture mapping hardware
Changho Bae:
10544: 98/05/29: Re: Altera FLEX8k configuration problem
chankc:
46795: 02/09/09: Can FPGA implements ADC?
49059: 02/10/30: Anyone has VHDL code for decimator and interpolater?
49344: 02/11/09: Request for multi-stage digital decimation filter's core.
49426: 02/11/12: Re: Anyone has VHDL code for decimator and interpolater?
Channing Wen:
10134: 98/04/29: How to implement a UART use FPGA with less cells.
73127: 04/09/15: Re: spartan-3 I/O timing
<channing-wen@usa.net>:
10002: 98/04/21: Arbiter help !!!
10031: 98/04/23: Re: Arbiter help !!!
12553: 98/10/16: How to decrease the XC95144's work current?
21188: 00/03/09: Re: Xilinx Foundation 2.1:Functional simulation
<channing@21cn.com>:
24020: 00/07/23: Routing Resources for Xilinx BlockRAM
24021: 00/07/23: Routing Resources for Xilinx BlockRAM
25418: 00/09/11: Problem of Virtex-E I/O
25419: 00/09/11: Problem of Virtex-E I/O
<channing@my-deja.com>:
17050: 99/06/28: How to build a NetBridge use FPGA
23741: 00/07/06: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
24055: 00/07/25: Re: Routing Resources for Xilinx BlockRAM
24136: 00/07/27: Question of Virtex DLL
Channing_W:
73286: 04/09/18: Re: Xilinx Prototype Board with CAN controller
73648: 04/09/27: Re: Spartan-3 VCCIO ramp up time
74375: 04/10/09: Re: Xilinx lead free parts hidden fact
74627: 04/10/15: Re: WebPACK post-PAR min clock period?
Chao:
68017: 04/03/24: Spartan-3 Mapping error with ISE 6.1i
68345: 04/04/01: Re: Spartan-3 Mapping error with ISE 6.1i
69102: 04/04/27: JTAG, Master Serial Mode
70262: 04/06/10: How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?
70353: 04/06/14: Re: How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?
70760: 04/06/26: simprim X_FF component
70826: 04/06/29: Re: simprim X_FF component
106647: 06/08/16: Is necessary to use Modsim on DDR Memory development?
108231: 06/09/06: TI TFP410 DVI transmitter help?
108293: 06/09/07: Re: TI TFP410 DVI transmitter help?
113339: 06/12/11: DDR2 DIMM memory termination resistors?
113391: 06/12/12: Re: DDR2 DIMM memory termination resistors?
123137: 07/08/16: FIFO16 on virtex4 error?
123231: 07/08/20: Re: FIFO16 on virtex4 error?
Chaos Master:
67544: 04/03/13: Re: ANN: new Pulsonix version 3 PCB software released
<chark.chen@gmail.com>:
100829: 06/04/18: Re: MaxPlus2 and the Byteblaster MV
Charles:
23001: 00/06/08: Re: Where's OptiMagic?
54450: 03/04/10: CIC Filter with RNS
54516: 03/04/12: Re: Modelsim - FPGA - Simulink integration
62346: 03/10/27: Re: View the signal in the analog domain ModelSim
115749: 07/02/19: ACTEL ProAsic Plus
140954: 09/05/31: Re: 11.1 & USB cable drivers
140955: 09/05/31: Re: 11.1 & USB cable drivers
145119: 10/01/28: FPGA Editor - Post Route Simulation after changes in Ncd file
charles:
70171: 04/06/07: DCM in Xilinx
70187: 04/06/08: slice # change from .syr to map report
70200: 04/06/09: Re: DCM in Xilinx
70335: 04/06/13: a newbie question
70339: 04/06/13: Re: a newbie question
70414: 04/06/16: Re: a newbie question
70415: 04/06/16: importing a design from maxplus2 to quartus II ver 3
73191: 04/09/15: standalone operation of ISE text editor or MTI text editor
Charles B. Cameron:
65936: 04/02/10: Re: negative hold time
Charles Bailey:
69821: 04/05/20: Re: Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench
Charles Barnes:
54026: 03/03/31: Input Characteristics : HCMOS vs TTL
Charles Brain:
23485: 00/06/27: First time user Spartan problem
23491: 00/06/27: Re: First time user Spartan problem
23494: 00/06/27: Re: First time user Spartan problem
23512: 00/06/28: Re: First time user Spartan problem (Panic over)
Charles Braquet:
49536: 02/11/14: configuration with Altera EPC16?
62383: 03/10/28: Re: Sort of Running Quartus II on SuSE Linux 8.1
Charles F. Shelor:
1255: 95/05/23: Yet Another Seminar Announcement
1370: 95/06/08: (no subject)
1371: 95/06/08: Virtually FREE VHDL/ASIC seminars
1922: 95/09/20: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
7666: 97/10/01: Logic Synthesis Methodology shortcourse
8274: 97/12/04: VHDL -> XNF via Synopsys
8797: 98/01/27: Re: comparing asic gates with gates in FPGA's
8818: 98/01/28: Re: comparing asic gates with gates in FPGA's
14942: 99/02/26: wanted: info about Fast Ethernet cores
Charles Flaig:
45: 94/08/03: Re: Welcome new XILINX users
Charles Gardiner:
3148: 96/04/14: Crosspoint Solutions
25462: 00/09/12: Accessing internal signals and ports for writing to a file using
31290: 01/05/17: Re: Digital PLL (DPLL) design help
31637: 01/06/01: Re: Help in FIFO design
52873: 03/02/25: AHB
54745: 03/04/17: Re: open SOC-bus system required!
80453: 05/03/06: Re: State Machine Trouble
86319: 05/06/25: Re: How do I convert a polynomial into a parallel scrambler formula?
137135: 08/12/26: Re: PCI newbie problems
137140: 08/12/27: Re: PCI newbie problems
137147: 08/12/28: Re: FPGA > ASIC
137280: 09/01/07: Re: Which revision control do fpga designers use (2009)
137839: 09/01/31: Re: Pci Express on Virtex 5: PC doesn't reboot
138134: 09/02/07: Re: Req for Recommendations: Modelsim vs IUS & VCS
138143: 09/02/07: Re: Req for Recommendations: Modelsim vs IUS & VCS
141639: 09/07/02: Re: Cheapest FPGA with decent PCI- e interface ?
141970: 09/07/20: Re: How do you handle build variants in VHDL?
142167: 09/07/28: Re: Lattice EC - some .bit files not loading from SPI flash
142266: 09/07/31: Re: Lattice EC - some .bit files not loading from SPI flash
142296: 09/08/02: Re: Questa price
142509: 09/08/14: Re: Mixed language simulation on the cheap
143195: 09/09/25: Re: Lattice ispLever not starting
143289: 09/09/30: Re: Searching for cost effective PCI express x1 core..
143618: 09/10/19: Re: License issues
144971: 10/01/18: Re: SystemVerilog Verification Example using Quartus and ModelSim
146201: 10/03/08: Re: Some Active-HDL questions
146443: 10/03/18: Re: Bus Master DMA with PCI Express
146511: 10/03/21: Re: Finally, selling my old Xilinx/Viewlogic software package
146525: 10/03/22: Re: Changing Generics in Simulation
146555: 10/03/23: Re: Why hardware designers should switch to Eclipse
148247: 10/07/02: Re: DMA operation to 64-bits PC platform
148250: 10/07/02: Re: DMA operation to 64-bits PC platform
148261: 10/07/02: Re: DMA operation to 64-bits PC platform
148275: 10/07/04: Re: DMA operation to 64-bits PC platform
148278: 10/07/04: Re: DMA operation to 64-bits PC platform
148304: 10/07/06: Re: DMA operation to 64-bits PC platform
148388: 10/07/17: Re: Dumb VHDL Question -- Type Conversion
148389: 10/07/17: Re: Dumb VHDL Question -- Type Conversion
Charles Kaseff:
5590: 97/02/26: Re: Xilinx or Altera?
Charles Krinke:
51033: 02/12/27: optimization
55855: 03/05/21: Re: Register in FPGA
56105: 03/05/28: Re: JTAG madness
56555: 03/06/09: Re: Masters Project Topic
56849: 03/06/17: Re: VGA LCD display controller in FPGA
57811: 03/07/07: GSR
Charles Lyttle:
30057: 01/03/22: Re: TOA measurement
30094: 01/03/23: Re: TOA measurement
30127: 01/03/24: Re: TOA measurement
Charles M. Elias:
58166: 03/07/16: Re: I/Os with Cypress chip
58257: 03/07/18: Re: I/Os with Cypress chip
60932: 03/09/25: Re: Reading from FPGA Issue
64376: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
Charles Manning:
3534: 96/06/16: Re: Simple Xilinx board
3805: 96/08/05: Re: assigning LOC in XACT
6475: 97/05/27: Re: Fine Pitch PQFP : anyone any hassles?
Charles Michael Heard heard@btr.com:
371: 94/11/01: Re: linear feedback shift registers
393: 94/11/05: Re: SRAM and antifuse for interconnects
407: 94/11/09: Re: about downloading FPGAs
414: 94/11/11: Re: about downloading FPGAs
450: 94/11/20: Re: Which PC HDL synthesis tool is best?
451: 94/11/21: Re: any XC4000 Horror Stories?
Charles Mosher:
8144: 97/11/21: Re: what is metastability time of a flip_flop
Charles P. Ohrbom:
2494: 95/12/18: UART in PLD
Charles Paez - CEMISID - ULA:
782: 95/03/01: slif2xnf or eqn2xnf
1052: 95/04/21: subscription
Charles Reed:
5818: 97/03/18: Re: A viewlogic story
Charles Richmond:
145443: 10/02/09: Re: using an FPGA to emulate a vintage computer
145444: 10/02/09: Re: using an FPGA to emulate a vintage computer
145463: 10/02/10: Re: using an FPGA to emulate a vintage computer
145761: 10/02/22: Re: using an FPGA to emulate a vintage computer
145788: 10/02/23: Re: using an FPGA to emulate a vintage computer
145789: 10/02/23: Re: using an FPGA to emulate a vintage computer
145814: 10/02/24: Re: using an FPGA to emulate a vintage computer
145815: 10/02/24: Re: using an FPGA to emulate a vintage computer
145816: 10/02/24: Re: using an FPGA to emulate a vintage computer
145857: 10/02/26: Re: using an FPGA to emulate a vintage computer
145858: 10/02/26: Re: using an FPGA to emulate a vintage computer
145859: 10/02/26: Re: using an FPGA to emulate a vintage computer
145897: 10/02/27: Re: using an FPGA to emulate a vintage computer
145898: 10/02/27: Re: using an FPGA to emulate a vintage computer
145998: 10/03/02: Re: using an FPGA to emulate a vintage computer
146149: 10/03/06: Re: using an FPGA to emulate a vintage computer
146150: 10/03/06: Re: using an FPGA to emulate a vintage computer
146151: 10/03/06: Re: using an FPGA to emulate a vintage computer
146152: 10/03/06: Re: using an FPGA to emulate a vintage computer
146188: 10/03/07: Re: using an FPGA to emulate a vintage computer
146189: 10/03/07: Re: using an FPGA to emulate a vintage computer
146212: 10/03/08: Re: using an FPGA to emulate a vintage computer
146213: 10/03/08: Re: using an FPGA to emulate a vintage computer
Charles Ross:
32317: 01/06/22: Unisim Library Question?
32384: 01/06/25: Re: Unisim Library Question?
32433: 01/06/26: Re: Unisim Library Question?
35091: 01/09/20: Virtex Clock Enable and Synplify
35118: 01/09/21: Re: Virtex Clock Enable and Synplify
Charles Shelor:
457: 94/11/23: Re: any XC4000 Horror Stories?
622: 95/01/20: Re: ACTEL and EXEMPLAR
661: 95/01/31: Re: Inefficiency(?)
695: 95/02/08: Re: Low cost Boundary Scan?
Charles Shelor-Consultant:
4: 94/07/27: Welcome new XILINX users
Charles Steinkuehler:
120585: 07/06/11: Re: Affordable pcie card ?
Charles Stevens:
4762: 96/12/12: Configuration EEPROMS for Altera Flex10K & Flex8K
6740: 97/06/22: SW updates for Sunshine EXPRO 80 programmer & a LCC44 adapter
9896: 98/04/11: Re: VHDL compiler differences ?
Charles Stuart:
51909: 03/01/25: registered bi-directional IOB?
59140: 03/08/10: Xilinx virtex II DCM CLKFX output not working
Charles Sweeney:
7639: 97/09/30: Re: Advantages of VHDL vs. Verilog?
7707: 97/10/06: Re: FPGA multiprocessors
7732: 97/10/08: Re: FPGA multiprocessors => vs. uniprocessors
7882: 97/10/27: Re: Xilinx 4000 on an ISA bus...
7981: 97/11/05: Re: interface between FPGA & user?
8180: 97/11/25: Re: what is metastability time of a flip_flop
8209: 97/11/28: Re: Free C hardware synthesizer (still available ???)
Charles W. Hubbard:
2518: 95/12/23: Re: [q][Reverse Engineering Protection]
4862: 96/12/20: Re: Proper target for design
Charles Wagner:
25463: 00/09/12: unexpanded XU macros
25777: 00/09/20: unexpanded XU macros
40029: 02/02/25: unisims simprims
44661: 02/06/26: amplify and xilinx : map error 679
46422: 02/08/29: virtex target library
46462: 02/08/30: RAM in CCC behavioral FPGA
46596: 02/09/04: RAM in CCC behavioral FPGA
47748: 02/10/03: XDW
55843: 03/05/21: BC pipelined loop synthesis
128601: 08/01/31: Xpower
130025: 08/03/13: ALTERA SOPC : ptf-sopc files
132361: 08/05/23: Avalon interconnect fabric : arbiter
Charles Xavier:
132588: 08/06/02: Re: xilinx and jtag
132951: 08/06/11: FPGA to solve the two most annoying problems on usenet - Suggestions
132957: 08/06/11: Re: FPGA to solve the two most annoying problems on usenet -
133031: 08/06/14: Re: FPGA to solve the two most annoying problems on usenet -
133043: 08/06/15: Re: FPGA to solve the two most annoying problems on usenet -
Charles Y. Hitchcock:
2425: 95/12/04: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
Charles Zheng:
70152: 04/06/05: parameter feature of AHDL in Xilinx
Charles, NG:
92344: 05/11/28: Re: async fifo design
114517: 07/01/18: Re: ARM AHBA 1Kbyte boundary issue
115361: 07/02/08: Re: ISE 9.1 Installation crash SuSE 10.2
123527: 07/08/29: Re: PCIe question
124126: 07/09/12: Re: Uses of Gray code in digital design
charles.eddleston@gmail.com:
101089: 06/04/25: Re: Xilinx Virtex-4 OCM Usage Issues
101105: 06/04/25: Re: Xilinx Virtex-4 OCM Usage Issues
101225: 06/04/27: Re: Xilinx Virtex-4 OCM Usage Issues
101289: 06/04/28: Re: Xilinx Virtex-4 OCM Usage Issues
101518: 06/05/02: Re: Xilinx Virtex-4 OCM Usage Issues
<charles.eddleston@gmail.com>:
101049: 06/04/24: Xilinx Virtex-4 OCM Usage Issues
<charles.elias@wpafb.af.mil>:
103716: 06/06/09: Re: Good free or paid merge software that edits two similar files?
103802: 06/06/12: Re: Good free or paid merge software that edits two similar files?
131690: 08/04/29: Functional Simulation of Virtex-4 Block Memory
131736: 08/04/30: Re: Functional Simulation of Virtex-4 Block Memory
131759: 08/05/01: Re: Functional Simulation of Virtex-4 Block Memory
<charles.papon.90@gmail.com>:
157772: 15/03/12: Re: Chisel as alternative HDL
<charles_elias@my-deja.com>:
20587: 00/02/15: Re: Altera vs Cypress?
<charlesg77@yahoo.com>:
78077: 05/01/24: EPROMs
Charlie:
152651: 11/09/22: Re: Browser-Based Timing Diagram Editor
Charlie Burns:
1068: 95/04/24: Re: (none)
1214: 95/05/15: 1000 pin fpga's ?
2662: 96/01/21: Re: Virtual Computer Corp. still in business?
4694: 96/12/01: Re: Moore vs Mealy state machines
Charlie E.:
150497: 11/01/24: Re: Xilinx news
150498: 11/01/24: Re: Xilinx news
150572: 11/01/26: Re: Xilinx news
Charlie Edmondson:
93204: 05/12/15: Re: Xilinx' encrypted HPICE models in PSPICE
95493: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95503: 06/01/23: Re: OT:Shooting Ourselves in the Foot
107877: 06/09/01: Re: Performance Appraisals
107892: 06/09/01: Re: Performance Appraisals
108214: 06/09/06: Re: Performance Appraisals
Charlie Gibbs:
145420: 10/02/08: Re: using an FPGA to emulate a vintage computer
145502: 10/02/12: Re: using an FPGA to emulate a vintage computer
Charlie Martin:
156250: 14/01/24: chip-to-chip serial comms
Charlie Root:
51153: 03/01/04: xst adding rams?
charlie78:
137517: 09/01/21: ML505 - How to read/write SRAM?
137597: 09/01/23: Re: ML505 - How to read/write SRAM?
137599: 09/01/23: Re: ML505 - How to read/write SRAM?
137641: 09/01/26: Re: ML505 - How to read/write SRAM?
137811: 09/01/30: XPS PS2 INTERFACE - ML505 and EDK 10.1
137814: 09/01/30: Re: XPS PS2 INTERFACE - ML505 and EDK 10.1
138091: 09/02/06: Rotary Encoder - Microblaze and ML505
138096: 09/02/06: Re: Rotary Encoder - Microblaze and ML505
138232: 09/02/10: Re: XPS PS2 INTERFACE - ML505 and EDK 10.1
138262: 09/02/11: Read a PS2 Keyboard input
138379: 09/02/18: ERROR: overlaps section...
138464: 09/02/24: Add a library in SDK project,
138465: 09/02/24: Add a library in SDK project,
Charon:
6189: 97/04/24: Re: Pentium Pro Worth it for Altera Max Plus?
charon:
122485: 07/07/28: EDK 9.1.02i warnings flood
122498: 07/07/29: Re: EDK 9.1.02i warnings flood
Charunethran:
148850: 10/09/02: debit source code
chat:
87178: 05/07/18: sample for virtex4
113838: 06/12/24: mobius, from codetronix, anyone has been tested
Chatpapon Prasartsee:
38823: 02/01/26: Mapping between Xlinx 4K and Spartan-II
Chaudhry:
31948: 01/06/09: FPGA based STN LCD Controller/Driver
Chauhan:
98834: 06/03/16: Re: Urgent Help Needed!!!!!
98855: 06/03/17: Re: Urgent Help Needed!!!!!
98946: 06/03/17: Re: Urgent Help Needed!!!!!
98949: 06/03/17: Re: Urgent Help Needed!!!!!
98970: 06/03/17: Re: Urgent Help Needed!!!!!
98971: 06/03/17: Re: Urgent Help Needed!!!!!
che_fong:
78520: 05/02/02: Re: See Peter's High-Wire Act next Tuesday
78587: 05/02/03: Re: See Peter's High-Wire Act next Tuesday
78594: 05/02/03: Re: See Peter's High-Wire Act next Tuesday
78658: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
81508: 05/03/25: Re: Altera's power consumption net seminar
89156: 05/09/06: Re: Altera Power Net Seminar #2
Cheah Soo Lan:
16204: 99/05/10: Downloading of Bitstream to program FPGA
<cheapforwholesale666@126.com>:
133444: 08/06/29: Discount Price !! Richmond D&G Shoes, Chanel Bape Belts , Jimmy Choo
checkyourwork:
checo:
119710: 07/05/24: VGA signal through breadboard?
119753: 07/05/25: Re: VGA signal through breadboard?
119759: 07/05/25: Re: VGA signal through breadboard?
119789: 07/05/25: Re: VGA signal through breadboard?
129504: 08/02/26: Re: Interview questions
132205: 08/05/17: FPGA art
132208: 08/05/17: Re: FPGA art
133261: 08/06/22: Cellular automata on a S3E SK
133729: 08/07/11: Re: VHDL code for DDFS
cheema:
50487: 02/12/11: HDL for Hough tranform
Cheese ][:
11740: 98/09/06: Re: 22V10 programming
chefren:
Chelam:
97670: 06/02/25: XC9500 JTAG Initialize problem
Chelman Wong:
1999: 95/09/29: AT&T ORCA usable gate count?
Chen Bin:
59891: 03/08/31: A student's question
Chen Wei Tseng:
49305: 02/11/08: Re: Modular Design for Project Manager 5.1.02
49644: 02/11/18: Re: about schmatic symbol
50184: 02/12/04: Re: HowTo 'freeze' a placement
50185: 02/12/04: Re: Weird problem with RPM
50221: 02/12/05: Re: HowTo 'freeze' a placement
50246: 02/12/06: Re: HowTo 'freeze' a placement
50263: 02/12/06: Re: HowTo 'freeze' a placement
50344: 02/12/09: Re: HowTo 'freeze' a placement
50425: 02/12/10: Re: Area contrain for a Module
50545: 02/12/12: Re: RPM Using ISE5.1i FloorPlanner
50596: 02/12/13: Re: RPM Using ISE5.1i FloorPlanner
51124: 03/01/02: Re: Question about HDL bencher (Xilinx) from newbie?
51206: 03/01/06: Re: Constraining a purely combinatorial logic path
51207: 03/01/06: Re: Constraining a purely combinatorial logic path
51220: 03/01/07: Re: Constraining a purely combinatorial logic path
51810: 03/01/22: Re: ISE 5.1 help
51846: 03/01/23: Re: Partial Reconfiguration : Xapp290 Example
51991: 03/01/28: Re: Installing 2 versions of Xilinx software in the same machine
52053: 03/01/29: Re: Reconfigure only some elements
52176: 03/02/03: Re: xilinx tools: How to convert Schematic design to VHDL code
52207: 03/02/04: Re: xilinx tools: How to convert Schematic design to VHDL code
52393: 03/02/07: Re: Xilinx ISE 4.2i killing Windows 2000?
52452: 03/02/10: Re: Xilinx ISE 4.2i killing Windows 2000?
52777: 03/02/21: Re: questions: create mcs-file / problem with downloading
52942: 03/02/26: Re: do xilinx has this option ?
53193: 03/03/05: Re: Partial Reconfiguration : Modular Design Help
54807: 03/04/18: Re: fpga_edline.exe
54945: 03/04/22: Re: ISE 5.1i : Timing Analyzer
55001: 03/04/23: Re: declaration of macro
55553: 03/05/12: Re: OK I am pissed off with Xilinx webpack.
55558: 03/05/12: Re: OK I am pissed off with Xilinx webpack.
55622: 03/05/14: Re: "Primitives" in XST?
55884: 03/05/22: Re: Change the value of a register in an implemented design
56296: 03/06/02: Re: Xilinx : BEL constraint vs. ModelSim
57572: 03/07/02: Re: FPGA Editor and Xilinx ISE 5.1i
58534: 03/07/25: Re: XAPP058 SVF2XSVF converter problems
58807: 03/08/01: Re: reconfiguration VirtexE via JTAG (full or partial)
58808: 03/08/01: Re: reconfiguration VirtexE via JTAG (full or partial)
58932: 03/08/04: Re: reconfiguration VirtexE via JTAG (full or partial)
59168: 03/08/11: Re: Xilinx Webpack ISE and Verilog-2001?
59958: 03/09/02: Re: parallel port
60506: 03/09/15: Re: What are Pull ups?
60772: 03/09/22: Re: Configuration Options:
60775: 03/09/22: Re: Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG
60843: 03/09/23: Re: Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG
60848: 03/09/23: Re: Corrupt Xilinx 18vxx poms
60900: 03/09/24: Re: Configuration Options:
60943: 03/09/25: Re: Configuration Options:
62227: 03/10/22: Re: Virtex II MJA
62481: 03/10/30: Re: TAP controller state vs PROG pin
63048: 03/11/13: Re: unknown devices in JTAG chain
64526: 04/01/06: Re: readback spartan2e
64634: 04/01/09: Re: Readbackn on Virtex II Pro devices
66847: 04/02/27: Re: Inquiry on configuration file analysis
66849: 04/02/27: Re: V2Pro config problems with HSTL_II_DCI pads...
67022: 04/03/03: Re: Xilinx Spartan 3 configuration
67067: 04/03/04: Re: Xilinx Spartan 3 configuration
67359: 04/03/10: Re: xilinx jtag problems
68341: 04/04/01: Re: XC18V master parallel configuration
68449: 04/04/05: Re: Virtex-E, FDRI register
<chen_yuru888@126.com>:
128300: 08/01/20: Re: How FPGA downconvert Giga SPS ADC data?
chenboya@gmail.com:
93624: 05/12/26: Re: Where to find the Altera Schematic
Chendu:
110819: 06/10/23: Memory Replicator
cheng:
23894: 00/07/14: Help FFT core!
Chengping Zhang:
29530: 01/02/25: I want to learn sth about FPGA
<chengwelsion@gmail.com>:
93229: 05/12/15: Get Start for XtremeDSP Developement Board -IV
ChenSongWei:
25862: 00/09/23: Category : why is 0?
26850: 00/11/01: Reference Design Xapp205.zip
chensw20hotmail.com:
37634: 01/12/18: Re: is it OK?
chenwei:
12735: 98/10/26: (no subject)
Cheny:
56343: 03/06/03: Re: Stapl Player vs. SVF Player
cheny:
30556: 01/04/16: cheny_w@hotmail.com
<chenyong20000@gmail.com>:
138622: 09/03/02: PCIE with Avalon I/F
141002: 09/06/02: how to run synplify & ise in tcl?
chenzcdyb:
135543: 08/10/07: trigger problem with chipscope
cheponis:
47300: 02/09/23: Altera Cyclone low-cost FPGA chips?
Cherif Chibane:
1118: 95/05/02: Lattice EPLDs
1407: 95/06/17: test
<cherin99@gmail.com>:
132378: 08/05/23: FPGA Programing file
132395: 08/05/25: Re: FPGA Programing file
chesi:
126650: 07/11/29: Cascaded DCMs with variable phase shift (Xilinx)
126717: 07/11/29: Re: Cascaded DCMs with variable phase shift (Xilinx)
127074: 07/12/11: Re: DDS generator with interpolated samples for Spartan3E development
<chessaurus@yahoo.com>:
96490: 06/02/04: High-density logic with simple, documented architecture ?
chestnut:
129041: 08/02/13: Re: When are FPGAs the right choice?
129044: 08/02/13: HELP on PLL and DCM
129852: 08/03/06: Xilinx MIG2.0 DDR2 memory controller
130477: 08/03/25: why Xilinx doesn't support Dual-Rank DIMM
133467: 08/06/30: What is TIEOFF_X0Y31
133560: 08/07/03: Re: What is TIEOFF_X0Y31
133562: 08/07/03: Re: Have you ever experimented some problem with External Memory?
135901: 08/10/21: Re: Question on timing constraints
Chet:
141420: 09/06/23: Re: 11.1 & USB cable drivers
141485: 09/06/25: Re: 11.1 & USB cable drivers
141493: 09/06/25: Re: Cable autodetection/programming the Xilinx Virtex2Pro FPGA failing.
Chet Stemen:
87741: 05/07/29: Xilinx ISE WebPACK-7.1i on NetBSD
87743: 05/07/30: Re: Xilinx ISE WebPACK-7.1i on NetBSD
87744: 05/07/30: Xilinx ISE WebPACK-7.1i on NetBSD
Chetan Tolia:
8991: 98/02/12: Xilinx Xc6264 Synthesis Route
chethansharma:
150739: 11/02/08: Power consumption of Spartan-3A XC3SD1800A
chewie:
138409: 09/02/20: Re: GTKWave 3.2.0 for Windows is available
138414: 09/02/20: Re: GTKWave 3.2.0 for Windows is available
141366: 09/06/20: Re: TimingAnalyzer is now freeware
141368: 09/06/20: Re: TimingAnalyzer is now freeware
141686: 09/07/03: Re: TimingAnalyzer is now freeware
chewie54:
119171: 07/05/14: Anyone using the TimingAnalyzer
chewy:
140238: 09/05/05: Re: FIFO that latches data asynchronic manner
Chez:
32920: 01/07/11: need help implementing state diagram of a 2input mealy machine!
32921: 01/07/11: Re: need help implementing state diagram of a 2input mealy machine!
<chgentso@gmail.com>:
139661: 09/04/08: Xilinx EDK 10.1 - SDRAM access using MPMC/VFBC by peripheral
139662: 09/04/08: Re: Xilinx EDK 10.1 - SDRAM access using MPMC/VFBC by peripheral
chhavi:
97533: 06/02/23: using evaluated ip core with edk 7.1 i
chi:
63925: 03/12/09: ISP for XCR3256XL
64454: 04/01/05: how to set the ISP mode for programming CPLD?
64497: 04/01/05: Where i can get the programming sequence of CoolRunner?
64586: 04/01/08: Re: Where i can get the programming sequence of CoolRunner?
64798: 04/01/14: Can i get a sample XSVF file?
65029: 04/01/19: Re: how to set the ISP mode for programming CPLD?
65030: 04/01/19: Help required on CoolRunner (XCR3256XL) In-System Programming
66194: 04/02/13: quartussII 3.0 , block editor, how to connect signals of buses
66690: 04/02/25: Re: quartus II 3.0 , block editor, how to connect signals of buses
66905: 04/02/29: nios board, apex, tutorial doesn't work
67001: 04/03/03: anyone using nios kit APEX?
Chi Fung:
17622: 99/08/16: Constant port map in component instantiation
17641: 99/08/18: VHDL'93 on Xilinx Foundation
17652: 99/08/19: Re: VHDL'93 on Xilinx Foundation
Chi-Ping Hsu:
404: 94/11/08: Re: Xilinx chip partitioning
<chicago1@notes.techni-source.com>:
3899: 96/08/16: FPGA help needed
Chico:
140307: 09/05/08: Quartus II negative bus dimensions in Schematic file
140309: 09/05/08: Re: Quartus II negative bus dimensions in Schematic file
chifalcon:
151898: 11/06/02: How could I get LUT-level netlist in Xilinx ISE?
151908: 11/06/02: Re: How could I get LUT-level netlist in Xilinx ISE?
151909: 11/06/02: Re: How could I get LUT-level netlist in Xilinx ISE?
151916: 11/06/03: Re: How could I get LUT-level netlist in Xilinx ISE?
152022: 11/06/22: P&R based on the post-map simulation model?
152061: 11/06/29: What's the black and while round on FPGA slice?
Chih-chang Lin:
769: 95/02/27: Placement for FPGA
790: 95/03/02: FPGA Custom Computing Machine
791: 95/03/02: FPGA Custom Computing Machine
Chih-Ching Chen:
2478: 95/12/14: Gated Clock Problem in Xilinx FPGA Implementation
3241: 96/05/02: How to use the notplace constrain in Xilinx chip?
Chih-Hsun Lin:
35030: 01/09/18: Increase routing delay in XILINX FPGA editor
35049: 01/09/19: Re: Increase routing delay in XILINX FPGA editor
35103: 01/09/21: Re: Increase routing delay in XILINX FPGA editor
Chih-Zong Lin:
21474: 00/03/23: [REQ] download function of Xilinx CPLD
21925: 00/04/07: Any free design of 8051 in the net?
Child K.L. Sun:
18435: 99/10/24: Delta-Sigma DAC
18464: 99/10/26: Comparison between Altera and Xilinx
18465: 99/10/26: Re: Delta-Sigma DAC
18550: 99/10/30: Re: Comparison between Altera and Xilinx
18604: 99/11/03: High Speed Enough!?
18632: 99/11/04: Re: High Speed Enough!?
18680: 99/11/07: FPGA's interface ....
18681: 99/11/07: ROM or SRAM !?
18691: 99/11/08: Re: ROM or SRAM !?
<chillihung@i-cable.com>:
28320: 01/01/06: rt18139.c
Chin-Long Wey:
10564: 98/05/29: ICCD 98 Program
11944: 98/09/20: ICCD 98 Program
11945: 98/09/20: ICCD 98 Program
Ching Hu:
75669: 04/11/12: Re: asynchronous bus transfers
76425: 04/12/02: Re: clocks switch
77807: 05/01/17: Re: Cheap source for GAL's
Ching Wang:
55269: 03/05/02: IP Core for CAN communication
55302: 03/05/02: Re: IP Core for CAN communication
Ching-Yau Jong:
374: 94/11/01: about downloading FPGAs
732: 95/02/19: Verilog models for Xilinx LCAs required
Chinix:
80007: 05/02/28: Re: Update EDK 6.1 to EDK 6.3
80008: 05/02/28: synthesis tool for systemc
80144: 05/03/01: Frustration on Xilinx Device Drivers API
80278: 05/03/03: where to get Xilinx Driver API document?help!
82249: 05/04/09: How to debug with XMD
82408: 05/04/12: Ethnet samples using EDK??
87069: 05/07/14: Why cann't this block be synthesized in top level
87075: 05/07/14: Re: Why cann't this block be synthesized in top level
87076: 05/07/14: Re: Why cann't this block be synthesized in top level
87080: 05/07/14: Re: Why cann't this block be synthesized in top level
Chinmay:
40288: 02/03/04: can "initial signal values" and other "for.....use" statements damage fpgas?
chinmayshah.edi@googlemail.com:
100801: 06/04/18: blowfish encryption algorithm
chinnathurai:
148465: 10/07/26: sdram stable clock
148611: 10/08/06: xilinx usb cable
Chintan:
91982: 05/11/18: Bidirectional bus control
92022: 05/11/19: Asynchronous design
92025: 05/11/19: Re: Asynchronous design
Chintan Trehan:
86026: 05/06/20: System Generator
Chip:
49812: 02/11/21: exp^x in virtex 2
49870: 02/11/22: Re: exp^x in virtex 2
50205: 02/12/04: 285MHz multipliers
53357: 03/03/11: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
53543: 03/03/15: blockram optimized away
53554: 03/03/15: Re: blockram optimized away
61899: 03/10/14: Re: Electronic Dice ( 3 die ) In VHDL
Chip Wood:
38433: 02/01/14: Re: speech recognition - active noise cancellation
38434: 02/01/14: Re: speech recognition - active noise cancellation
Chip Brown:
16257: 99/05/12: Re: Fancy Dram problem
Chip Fox:
41804: 02/04/08: How to INIT ROM in VHDL for WebPack/ModelSimXE?
41867: 02/04/09: Re: How to INIT ROM in VHDL for WebPack/ModelSimXE?
Chip Weems:
4747: 96/12/10: Call for Papers: CAMP '97
Chip Willman:
15432: 99/03/24: Re: Jedec programming standard?
chipdesignart:
116267: 07/03/05: A Very good VLSI Chip design website
<chipfactory@hotmail.com>:
17292: 99/07/19: License sharing for synopsys/cadence/modeltech
Chipman:
24368: 00/08/04: CoolRunner Tri-State...
<chipnayak@gmail.com>:
154766: 13/01/04: Re: Looking for evaluators for NEW Vector Processor for FPGAs, offers
<chithrakn@gmail.com>:
130195: 08/03/17: Chipscope
Chiu See Ming <EEE3>:
522: 94/12/19: Any Way to Download a XNF to FPGA
532: 94/12/24: multipliers!
Chiuj:
18928: 99/11/22: Re: PADS Experience?
chkcmc:
10305: 98/05/11: How to design frequency doubler ?
<chlin@telecom.ece.ntua.gr>:
41408: 02/03/27: Re: simulation issues
Chloe:
92600: 05/12/02: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
92787: 05/12/06: Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
92790: 05/12/06: Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
92853: 05/12/07: Simulating Post-Synthesis Model on Xilinx FPGA
92892: 05/12/08: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92896: 05/12/08: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92898: 05/12/08: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92899: 05/12/08: Re: Simulating Post-Synthesis Model on Xilinx FPGA
93043: 05/12/12: Xilinx FPGA - Wrongly Translated Inputs
93049: 05/12/12: Re: Xilinx FPGA - Wrongly Translated Inputs
<chnmyi@gmail.com>:
125310: 07/10/19: Re: Dynamic Reconfiguration books
Cho Kyung Choon:
2048: 95/10/06: Need large vhdl codes
2065: 95/10/09: [Need] large VHDL codes.
2080: 95/10/11: [NEED] bigger VHDL codes 4 partitionning
2092: 95/10/13: [NEED] bigger VHDL codes 4 partitionning
Cho Moon -- Lattice Semiconductor:
193: 94/09/16: Re: Lattice ISP software: really bad or just different?
chong:
85850: 05/06/16: question about xilinx micro kernel
Chopper:
151990: 11/06/19: Re: Xilinx or Altera
151997: 11/06/20: Re: Xilinx or Altera
Choudhary:
59372: 03/08/17: custom memory array implementaion
Chr. Moecking:
11552: 98/08/23: Re: professional autorouters
chris:
32738: 01/07/06: Problems with Virtex Block Ram Propagation Delay
32760: 01/07/07: maintaining net names after synthesis and place and route... synthesis tool: synplicity
32768: 01/07/08: Need some help using Synplify ... and also considering Xilinx Modular Flow
32807: 01/07/09: Re: Need some help using Synplify ... and also considering Xilinx Modular Flow
32958: 01/07/12: reading a vcd file into verilog xl
33027: 01/07/15: Re: Which Chip Family?
33047: 01/07/16: Re: Book Recommendation (bit different)
33277: 01/07/21: Re: Soldering Ceramic BGA's
33802: 01/08/05: Re: Which is the best Design Toolchain?
33803: 01/08/05: Re: Slightly off topic - PCs for running FPGA tools
33866: 01/08/06: working proto of something cool...whats the next step
36228: 01/11/02: Re: Guided Design, Xilinx Virtex-E
38343: 02/01/11: speech recognition - active noise cancellation
39465: 02/02/10: inconsistent results after place and route on xilinx XC2V3000
41987: 02/04/12: Re: prototyping an ASIC
42021: 02/04/12: Re: prototyping an ASIC
51101: 03/01/01: Re: BP programmer questions, prices, alternatives
51157: 03/01/04: How can you tell if your clock signals are on the clock net?
55510: 03/05/11: Re: Xilinx parts listed on ebay..
65229: 04/01/22: error in Quartus
65282: 04/01/23: Re: error in Quartus
65962: 04/02/10: attribute +generate statement
67416: 04/03/11: what exactly means fanout ?
67601: 04/03/15: Re: Programmed ground pins v physical grounding (Xilinx CPLD)
67656: 04/03/16: Re: Programmed ground pins v physical grounding (Xilinx CPLD)
67896: 04/03/22: Re: XCV2000E survived 3.3V core voltage!
70086: 04/06/02: How can I get an output clock phased align with the input clock.
70107: 04/06/03: Re: How can I get an output clock phased align with the input clock.
70251: 04/06/10: Frequency synthesizer.
113770: 06/12/20: Re: New user help required
136011: 08/10/27: Re: Small FPGA boards with USB/Ethernet
144592: 09/12/18: Re: GTKWave 3.3.0 for Windows is available
Chris:
16459: 99/05/24: For Sale: Altera Max+Plus II
18701: 99/11/08: Need a good Pullup for a VHDL Test Bench
18717: 99/11/09: Re: Need a good Pullup for a VHDL Test Bench
35247: 01/09/26: Re: Handle C
35631: 01/10/12: Re: Handel-C
38802: 02/01/25: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
42439: 02/04/24: Re: Floorplanning
50789: 02/12/19: Re: embedded programming of an ACEX1k30
59245: 03/08/13: Limitations of Quartus II V3.0 Web
64643: 04/01/09: FPGA Size
65000: 04/01/18: Downloading to an FPGA
68288: 04/03/31: Re: Metastablility
68290: 04/03/31: Re: Metastablility
68379: 04/04/02: Re: vcom in modelsim
71784: 04/07/30: Static Timing Analysis
72111: 04/08/09: Re: propagation delay
72119: 04/08/09: Re: propagation delay
72559: 04/08/24: Re: Altera MAX II
74934: 04/10/21: Re: Anyone routing signals between balls in FBGA?
74937: 04/10/21: Re: unstable fpga design
74586: 04/10/14: Metastability pipeline causes bad juju
74589: 04/10/14: Re: Metastability pipeline causes bad juju
74590: 04/10/14: Re: Same Bitstream: Different Performance
74596: 04/10/14: Re: low cost MPEG4 codec (from Atmel )
74599: 04/10/14: Re: Metastability pipeline causes bad juju
74631: 04/10/15: Re: Metastability pipeline causes bad juju
74664: 04/10/15: Re: Metastability pipeline causes bad juju
79280: 05/02/16: Re: Efficient Voltage Regulators Spartan 3 Current Requirements
80954: 05/03/15: Same Problem
81005: 05/03/16: [Newbie] Parallel merging and insertion sort on FPGA
84334: 05/05/17: Virtex-2 JTAG problem
84412: 05/05/18: Re: Virtex-2 JTAG problem
86080: 05/06/21: Re: FPGAs: Where will they go?
89975: 05/09/30: Virtex-4 FX20 PPC405 Startup Issue
90042: 05/10/03: Re: Virtex-4 FX20 PPC405 Startup Issue
90409: 05/10/12: Re: Virtex-4 FX20 PPC405 Startup Issue
91205: 05/11/01: Re: Virtex4 temperature-sensing feature... does it work?
110814: 06/10/23: Survey on Quartus SOPC/Nios-II
110846: 06/10/24: Re: Survey on Quartus SOPC/Nios-II
110900: 06/10/25: Re: Survey on Quartus SOPC/Nios-II
110906: 06/10/25: Re: Survey on Quartus SOPC/Nios-II
110911: 06/10/25: Re: Survey on Quartus SOPC/Nios-II
110957: 06/10/25: Re: Survey on Quartus SOPC/Nios-II
111023: 06/10/27: Re: Survey on Quartus SOPC/Nios-II
111066: 06/10/27: Re: Survey on Quartus SOPC/Nios-II
111091: 06/10/28: Re: Survey on Quartus SOPC/Nios-II
111268: 06/10/31: Re: Question about bandwidth of scope?
111293: 06/10/31: Re: Question about bandwidth of scope?
111560: 06/11/06: I2C Master in Verilog
118920: 07/05/07: Re: About DDR SDRAM
119012: 07/05/09: Re: Xilinx software quality - how low can it go ?!
119019: 07/05/09: Re: Where can I find the pass transistor's working curve under 1.2V?
143271: 09/09/29: Re: USB programmable Open Source Hardware
143273: 09/09/29: Re: USB programmable Open Source Hardware
143274: 09/09/29: Re: Automated test framework
143304: 09/09/30: Re: USB IP block vendors?
155534: 13/07/15: Re: Low cost board with built-in USB for fast data transfer and lots
155535: 13/07/15: Re: Low cost board with built-in USB for fast data transfer and lots
155537: 13/07/16: Re: Low cost board with built-in USB for fast data transfer and lots
155553: 13/07/18: Metastability mitigation and I/O registers
155556: 13/07/18: Re: Metastability mitigation and I/O registers
155558: 13/07/18: Re: Metastability mitigation and I/O registers
155655: 13/07/31: Re: Lattice Announces EOL for XP and EC/P Product Lines
155683: 13/08/04: Re: Lattice Announces EOL for XP and EC/P Product Lines
155685: 13/08/04: Re: Lattice Announces EOL for XP and EC/P Product Lines
155711: 13/08/13: [HELP]problem with asynchronous fifo ip
155761: 13/08/28: Re: Actel Designer Warning: CMP201: Net drives no load
155762: 13/08/28: Re: Actel Designer Warning: CMP201: Net drives no load
155779: 13/08/30: Re: Actel Designer Warning: CMP201: Net drives no load
155786: 13/09/04: Re: Actel Designer Warning: CMP201: Net drives no load
155789: 13/09/04: Re: Actel Designer Warning: CMP201: Net drives no load
Chris Murphy:
115893: 07/02/23: Small FPGA Dev Board with Ethernet
Chris Abele:
138645: 09/03/02: Re: Character generator ROM and VGA controller for Spartan 3E
139225: 09/03/23: Re: Looking for a low-cost development kit
139906: 09/04/18: Re: source for Spartan 3E chips
140207: 09/05/04: Re: High-speed signals crossing a split-ground
141309: 09/06/16: Re: About Altera patent application "Logic Cell Supporting Addition
141310: 09/06/16: Re: About Altera patent application "Logic Cell Supporting Addition
143082: 09/09/18: Re: FPGA for acoustic adaptive beamforming
144746: 09/12/30: Re: Seeking some advice
145594: 10/02/15: Re: optimal no of inputs to be given in a test bench
146561: 10/03/22: Re: Why hardware designers should switch to Eclipse
147911: 10/06/01: Re: Graphical User Interface project on Spartan-3 FPGA
148694: 10/08/17: Re: Getting started with FPGA
149708: 10/11/19: Re: hot- or cold-plugging altera cyclone-3 LVDS inputs causing damage?
150207: 10/12/31: Re: I Give Up!
150819: 11/02/14: Re: Xilinx USB programming cable.
Chris Alexander:
73693: 04/09/28: Re: what to do with the DCM locked signal?
73694: 04/09/28: Re: Simple Counter in Verilog
73109: 04/09/14: Spartan 2E gets hot after configuration
73234: 04/09/16: Re: Simulation Warning
73275: 04/09/17: Re: beginner's question
73298: 04/09/18: Re: Statix II vs. Virtex 4
73473: 04/09/22: Re: Mr. Greenfield, spare us the propaganda !
73474: 04/09/22: Re: Stratix II vs. Virtex 4 - availability & fab partnership
75013: 04/10/24: Re: Looking for FPGA design services in India or similar
74139: 04/10/04: Re: Asynchronous reset timing problem
74903: 04/10/21: Re: unstable fpga design
Chris Anderson:
25426: 00/09/11: Code distribution without loss of IP?
29102: 01/02/06: PAL/GAL 22V10 (CE) programmers?
Chris Arndt:
33660: 01/08/01: Re: Foundation 2.1 Schematic in WebPack
33762: 01/08/03: Re: Does Flexlm Licensing Work on Windows 2000 Pro?
68727: 04/04/15: Re: System Generator HDL co-simulatin problem
68728: 04/04/15: Re: System Generator HDL co-simulatin problem
70301: 04/06/11: Re: Xilinx System Generator problem: ERROR:NgdBuild:604
Chris Balough:
54361: 03/04/08: Re: Altera not supplying Leonardo any more
62362: 03/10/27: Re: Beginners advice for selecting an environment for FPGA design
68343: 04/04/01: Re: AHDL, VERILOG or VHDL??
68401: 04/04/02: Re: AHDL, VERILOG or VHDL??
Chris Beg:
88475: 05/08/18: looking for OLD OLD software
Chris Bray:
6457: 97/05/25: VHDL
Chris Briggs:
29194: 01/02/09: Re: Synplify on Windows2000?
30199: 01/03/28: PCI-X core
71943: 04/08/04: Re: Manipulation on netlist for faster simulation.
99466: 06/03/24: Re: Accessing ModelSim Environment variables in Verilog code
Chris Burrows:
139035: 09/03/19: Re: Zero operand CPUs - debugging
145334: 10/02/06: Re: using an FPGA to emulate a vintage computer
Chris Burton:
2410: 95/12/01: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2411: 95/12/01: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2452: 95/12/07: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
Chris Carlen:
57111: 03/06/23: ISE Webpack : "zipfile not found"
57112: 03/06/23: Xilinx ISE Webpack on Linux?
57197: 03/06/25: Webpack 5.2i can't synthesize
57202: 03/06/25: Xilinx Webpack bugs bugs bugs
57263: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57265: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57289: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57649: 03/07/03: Re: XPLA3 vs. MAX3000A
57651: 03/07/03: Re: xilinx and web pack questions newbe
57652: 03/07/03: Re: check one two check check
58488: 03/07/24: Should I use ABEL?
58546: 03/07/25: Re: Should I use ABEL?
63019: 03/11/12: Will XPLA3 phase out?
63585: 03/11/25: Quote from Xilinx re: XPLA3
64274: 03/12/23: Xilinx Johnson counter Verilog example bug?
64438: 04/01/04: Re: Xilinx Johnson counter Verilog example bug?
64558: 04/01/07: Re: Xilinx Question
64559: 04/01/07: Synthesis in VHDL vs. Verilog
64724: 04/01/12: Re: Synthesis in VHDL vs. Verilog --Thanks folks
64864: 04/01/15: timescale
64945: 04/01/16: Re: timescale
66668: 04/02/24: Why warnings: "Input <xyz> never used???"
66763: 04/02/26: Re: Why warnings: "Input <xyz> never used???"
66764: 04/02/26: How to work with global clocks and buffers in CPLD?
66804: 04/02/26: Re: Why warnings: "Input <xyz> never used???"
66937: 04/03/01: Re: Why warnings: "Input <xyz> never used???"
66947: 04/03/01: Is WebPACK 6.1 generally broken, and what of 6.2?
66990: 04/03/02: Re: Is WebPACK 6.1 generally broken, and what of 6.2?
69152: 04/04/28: Comment on my code style
69161: 04/04/28: Re: Comment on my code style
69225: 04/04/30: Re: Comment on my code style
70835: 04/06/29: Trouble with $readmemh in ModelSim
70843: 04/06/29: Re: Trouble with $readmemh in ModelSim
70844: 04/06/29: Re: Trouble with $readmemh in ModelSim
70930: 04/07/01: Re: Trouble with $readmemh in ModelSim
76692: 04/12/08: Re: fpga prices
87655: 05/07/27: Delay Generators in FPGAs
87797: 05/08/01: Spartan3 with WebPack?
87851: 05/08/02: Re: Spartan3 with WebPack?
109183: 06/09/21: Dell Laptop for Embedded Work
109198: 06/09/21: Re: Dell Laptop for Embedded Work
109199: 06/09/21: Re: Dell Laptop for Embedded Work
109200: 06/09/21: Re: Dell Laptop for Embedded Work
109202: 06/09/21: Re: Dell Laptop for Embedded Work
109252: 06/09/22: Re: Dell Laptop for Embedded Work
114896: 07/01/25: Can't assign pins in Webpack 8.2i schematic design
122206: 07/07/23: VCD file doesn't show anything in GtkWave
122251: 07/07/24: Re: VCD file doesn't show anything in GtkWave
122377: 07/07/26: Re: VCD file doesn't show anything in GtkWave
122378: 07/07/26: Re: VCD file doesn't show anything in GtkWave
122567: 07/07/31: Re: VCD file doesn't show anything in GtkWave
Chris Case:
112850: 06/11/29: Re: MPMC2: MPMC2 with DDR2 SDRAM
Chris Cheung:
66192: 04/02/13: LVDS on Spartan 3
66978: 04/03/02: Xilinx : RLOC ORIGIN
67723: 04/03/18: Re: Spartan III availability
67725: 04/03/18: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig> not replaced by logic."
67906: 04/03/22: Quick Syntax question...
69463: 04/05/11: Re: FPGA vs Microprocessor: newbie question
69518: 04/05/12: Re: unused IO on SPARTAN-IIE
70129: 04/06/03: PAR runtime error
Chris Clark:
100349: 06/04/07: Re: Virtex-4 RocketIO and G.709 OTU-2
Chris Cowdery:
38977: 02/01/29: Flex10KA vs MAX7000S
39037: 02/01/30: Re: Flex10KA vs MAX7000S
40404: 02/03/06: Using a battery instead of Config device
Chris Dick:
30014: 01/03/20: Re: FFT in FPGAs
39757: 02/02/19: Re: Coregen Half-Band FIR filter implemenation does not work
Chris Dodge:
493: 94/12/06: WWW sites for Product Info
Chris Dunlap:
21996: 00/04/11: Re: Errors during synthesis
21997: 00/04/11: Re: JTAG PROBLEM
22235: 00/05/02: Re: Start Up Reset after config on Virtex design
28731: 01/01/22: Re: Verilog model of Xilinx macro in VHDL Testbench fails
29306: 01/02/13: Re: ROM initialization in VHDL for Virtex
29314: 01/02/13: Re: Configuration of FPGA using SPROM
29336: 01/02/14: Re: XILINX FPGA programming through JTAG
29369: 01/02/16: Re: help
29370: 01/02/16: Re: Configuration of FPGA using SPROM
29400: 01/02/19: Re: Configuration of FPGA using SPROM
29401: 01/02/19: Re: what
29423: 01/02/20: Re: to you sir Peter Alfke...
29557: 01/02/26: Re: VHDL:case
29737: 01/03/06: Re: More detailed Spartan II CLB drawings?
30187: 01/03/27: Re: Xilinx Core generator with WebPack ISE
30212: 01/03/28: Re: PCI-X core
30359: 01/04/04: Re: Xilinx Foundation 2.1i License
30704: 01/04/24: Re: what does it mean in fe.log?
42491: 02/04/25: Re: SpartanXL libraries (OSC4 element)
Chris Ebeling:
61011: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61033: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
63186: 03/11/17: Re: Virtex II multipler performance
65888: 04/02/09: Re: How may I restrain the P&R to only a small area...
65893: 04/02/09: Re: How may I restrain the P&R to only a small area...
75404: 04/11/04: Re: Xilinx V-II BUFGMUX oddities..
76773: 04/12/10: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76779: 04/12/10: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76818: 04/12/13: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
78589: 05/02/03: Re: Modifying a post PAR xilinx design
Chris Eilbeck:
13153: 98/11/17: Re: DES in VHDL
13027: 98/11/12: DES in VHDL?
13043: 98/11/12: Re: DES in VHDL?
13180: 98/11/18: Serial EPROMs
14009: 99/01/07: Re: fpga socket
14632: 99/02/07: Re: DES in VHDL for FPGAs
16747: 99/06/06: Re: FPGA/ VHDL books: any stores in central London
30344: 01/04/03: Atmel FPSLIC devices
31133: 01/05/12: Xilinx and Actel
31262: 01/05/16: Re: Xilinx and Actel
31263: 01/05/16: Re: Xilinx and Actel
31548: 01/05/30: Re: ORCAD Capture Symbols
31550: 01/05/30: Re: ORCAD Capture Symbols
31565: 01/05/30: Re: ORCAD Capture Symbols
35133: 01/09/22: Re: Complex mixer LUT
Chris Elliott:
35366: 01/10/01: Xilinx Spartan-II slave parallel configuration
Chris F Clark:
77254: 05/01/01: Re: Verilog /DIP Switch Question....
77265: 05/01/02: Re: Verilog /DIP Switch Question....
93401: 05/12/21: Re: More beginner's verilog questions
93461: 05/12/22: Re: More beginner's verilog questions
93649: 05/12/27: Re: More beginner's verilog questions
97802: 06/02/27: Re: Why wouldn't this infer a flop with async reset and sync enable
99297: 06/03/22: Re: Verilog's integer and reg?
99298: 06/03/22: Re: Verilog's integer and reg?
Chris Felton:
138557: 09/02/27: Re: Send data from FPGA to PC via USB
140474: 09/05/14: Re: Open source processors
Chris Finan:
135780: 08/10/15: Re: PLL in Altera PCI core ?
Chris Foran:
23147: 00/06/15: Re: difference between fpga and epld
Chris Francis:
97751: 06/02/27: VirtexII routing data widths
97755: 06/02/27: Re: VirtexII routing data widths
98044: 06/03/03: Re: VirtexII routing data widths (further query)
98089: 06/03/04: Re: VirtexII routing data widths (further query)
Chris Fritz:
24431: 00/08/08: Re: Crossing Clock Domains.
24462: 00/08/09: Re: Crossing Clock Domains.
Chris G Abbott:
541: 94/12/28: Which FPGA should I be looking at
548: 94/12/29: Re: Which FPGA should I be looking at
549: 94/12/30: FlexiLogic - Few Questions
550: 94/12/30: PLDShell - Question
1019: 95/04/15: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
1029: 95/04/18: Re: Viewlogic 4.1 & Windows '95
1040: 95/04/19: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
1130: 95/05/03: Re: Lattice EPLDs
1248: 95/05/22: Re: PLDShell Plus
Chris G. Schneider:
28630: 01/01/18: Best design for asyn. interface DSP <-> FPGA?
28634: 01/01/18: Re: revision control tools ??
28658: 01/01/19: Re: Best design for asyn. interface DSP <-> FPGA?
28675: 01/01/20: Re: Best design for asyn. interface DSP <-> FPGA?
28946: 01/01/30: Re: Spartan 2 DLL
29143: 01/02/07: Re: Mentor Advice
29231: 01/02/10: Re: Wired-or on Virtex FPGAs
29416: 01/02/20: Re: 5 Clocks in a spartan-II
29417: 01/02/20: Re: UCF problem "- Could not find NET "
29503: 01/02/23: Re: UCF mode for vim (Re: UCF mode for Emacs?)
29504: 01/02/23: Re: UCF mode for Emacs?
29583: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
29585: 01/02/27: Xilinx P&R problem?
30631: 01/04/19: Re: PAR single pass vs multi-pass differences
30654: 01/04/21: Re: Wanted: ISA bus implementation for Xilinx
31332: 01/05/19: Re: Xilinx Service Pack 8 Now Available
31333: 01/05/19: Re: Tutorial
Chris Gammell:
97047: 06/02/15: EDK Woes and Worries
97050: 06/02/15: Re: EDK Woes and Worries
97092: 06/02/16: Re: EDK Woes and Worries
97287: 06/02/20: Re: Cheating at homework (from "Re: FPGA - software or hardware?"t
Chris Graham:
77706: 05/01/14: I2C --> SPI or Parallel Port Concentrator
77707: 05/01/14: Re: I2C --> SPI or Parallel Port Concentrator
77733: 05/01/15: Re: I2C --> SPI or Parallel Port Concentrator
Chris H:
127298: 07/12/17: Re: PCI Parallel port card for JTAG / programming?
147228: 10/04/19: Re: Need to run old 8051 firmware
147253: 10/04/21: Re: Need to run old 8051 firmware
147258: 10/04/21: Re: Need to run old 8051 firmware
Chris Hart:
4573: 96/11/16: VHDL adder: how do I get at the carry bit?
4574: 96/11/16: Re: Has anyone changed from ViewLogic to Foundation [Q]
4672: 96/11/27: Re: VHDL adder: how do I get at the carry bit?
5625: 97/03/03: Place and Route on Pentium Pro Benchmark?
Chris Harthan:
48016: 02/10/09: Re: Booting a FPGA via USB
48057: 02/10/10: Re: Booting a FPGA via USB
Chris Harwood:
58227: 03/07/17: PCI - disabling
Chris Herron:
4435: 96/10/29: Novice: Flex 8000 ?
Chris Hersman:
2647: 96/01/18: Programming Actels in circuit?
Chris Higgs:
147048: 10/04/12: Re: I'd rather switch than fight!
147050: 10/04/12: Re: I'd rather switch than fight!
147075: 10/04/13: Re: I'd rather switch than fight!
147083: 10/04/13: Re: I'd rather switch than fight!
147108: 10/04/14: Re: I'd rather switch than fight!
147333: 10/04/23: Re: I'd rather switch than fight!
147341: 10/04/23: Re: I'd rather switch than fight!
150409: 11/01/17: Re: Location constraints questions
156446: 14/04/07: Re: [cross-post][long] svn workflow for fpga development
157192: 14/10/29: Re: XILINX PCIe read of slow device
Chris Hills:
6808: 97/06/29: Re: Smart Card Design and Interface. How?
24841: 00/08/20: Re: Arg! 8051 - 6502 and friends
94998: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95230: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95232: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95233: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95235: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95277: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95317: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95325: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95362: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95403: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95456: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95538: 06/01/24: Re: OT:Shooting Ourselves in the Foot
95604: 06/01/24: Re: OT:Shooting Ourselves in the Foot
Chris Hopkins:
52540: 03/02/12: Re: regarding PCI specification in that configuration register doubt
Chris Humphres:
4102: 96/09/10: Re: Quick and Easy Money (NOT A SCAM!)
Chris Jones:
66617: 04/02/24: Routing algorithm - help needed
66754: 04/02/26: Automatic Placement algorithm, help needed
68662: 04/04/13: Layout problem
97551: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
100015: 06/04/01: Re: Doubt about SERDES
156472: 14/04/09: Re: on-chip bypass caps
156474: 14/04/09: Re: on-chip bypass caps
Chris Kwok:
668: 95/02/01: unsubscribe
Chris Lee:
10460: 98/05/19: Archives for comp.arch.fpga?
Chris Lewis:
43696: 02/05/29: Director of FPGA Design - New York City
Chris M. Thomasson:
160927: 18/12/21: Re: Merry Christmas / Happy Holidays
Chris Maryan:
124758: 07/10/03: Detecting if an error happened in ModelSim
124762: 07/10/03: Re: Detecting if an error happened in ModelSim
124763: 07/10/03: Re: Detecting if an error happened in ModelSim
124767: 07/10/03: Re: Detecting if an error happened in ModelSim
124773: 07/10/04: Re: Detecting if an error happened in ModelSim
125465: 07/10/26: Re: Power supply filter capacitors
126712: 07/11/29: Re: Hand solder that FPGA on your prototype
126737: 07/11/30: Re: Drawing timing-diagrams for documentation
127279: 07/12/16: Re: DDS generator with interpolated samples for Spartan3E development
128559: 08/01/30: ROM/LUT
128680: 08/02/03: Re: Scaling data
128732: 08/02/05: Re: How to optimize my design area to fit?
133415: 08/06/27: Re: FPGA based database searching
137021: 08/12/19: Re: FPGA partial/catastrophic failure mode question
137279: 09/01/07: Re: Which revision control do fpga designers use (2009)
137282: 09/01/07: Re: Which revision control do fpga designers use (2009)
137370: 09/01/12: Re: Xilinx Area Group Constraint Usage
137381: 09/01/13: Re: Xilinx Area Group Constraint Usage
137903: 09/02/02: Re: Heavily pipelined design
138276: 09/02/11: Re: Implementing reset / enable in FPGA question
138559: 09/02/27: Re: virtex 5 columns
143378: 09/10/07: Re: Virtex 5 HDMI
145805: 10/02/24: Xilinx iodelay
146717: 10/03/26: Re: Ring Oscillator -> counter differences
147051: 10/04/12: Re: Module wise FPGA resource utilization report
147117: 10/04/14: Re: Read from the compact flash
147518: 10/04/29: Re: Large Fanout
147613: 10/05/07: Re: FPGA Compilation Time Windows vs Linux
147896: 10/05/31: Re: Effect of fanout on route delay (Spartan3)
148635: 10/08/10: Re: Instantiating non-global clock buffers (Xilinx ISE)
148646: 10/08/11: Re: Instantiating non-global clock buffers (Xilinx ISE)
149356: 10/10/18: Re: Regarding Synchronization of multiple control signals
149761: 10/11/23: Re: minimum clock period of a combinational circuit
149795: 10/11/24: Re: PlanAhead
149826: 10/11/25: Re: PlanAhead
149838: 10/11/26: Re: Multiple clock domains
149969: 10/12/03: Re: FPGA BOARD QUESTION
149970: 10/12/03: Re: SPI master controller with no embedded microprocessor
150130: 10/12/15: Re: Xilinx support makes me want to scream
150271: 11/01/07: OT: Fast Circuits
150430: 11/01/20: Re: Overview for non-technicals.
150434: 11/01/20: Re: Overview for non-technicals.
150517: 11/01/25: Re: Zero Padding Circuit Design
150518: 11/01/25: Re: tft lcd with xilinx fpga
150683: 11/02/03: Re: Suggestions for a FPGA friendly 10 Mbit/s industrial bus ?
150684: 11/02/03: Re: Trivia: Where are you on the HDL Map?
150856: 11/02/16: Re: Regarding passing a control signal from fast to slow cloak domain
150900: 11/02/20: Re: Regarding passing a control signal from fast to slow cloak domain
150915: 11/02/21: Re: timing issues at high speed
151035: 11/03/01: Re: PLL Cyclone III vs PLL(DLL) Spartan-3AN
151037: 11/03/01: Re: Slice Usage
151423: 11/04/06: Re: RocketIO
151453: 11/04/10: Re: Do people do this by hand?
153356: 12/02/06: Re: 'x' state on one bit of the input bus of an adder cause the
Chris Mc Clements:
27187: 00/11/14: Re: How to read schematic after synthesis
27378: 00/11/20: Virtex-E Global Set/Reset
32938: 01/07/12: Re: Virtex2: Is it possible to place distributed DPRAM
34677: 01/09/03: Re: Clock Multiplication
Chris Menz:
81689: 05/03/30: Re: Quartus II 4.1 Problem
Chris Morgan:
19891: 00/01/16: Re: HW resources increased
19898: 00/01/16: Re: HW resources increased
chris pitzel:
17374: 99/07/23: Re: PCI Controller chip Announcement
Chris Plachta:
22108: 00/04/24: Any good third-party place and route tools?
Chris Rosewarne:
52500: 03/02/11: Re: XST choking hazard
52505: 03/02/11: Re: Distributed RAM/ROM
52546: 03/02/12: Re: Floorplanning of design written in verilogHDL Designer question
52547: 03/02/12: Re: Fractional Divide
52608: 03/02/16: Re: Virtex-E 600--2'sC/Straight Binary?
52639: 03/02/17: Re: HDL Bench
52641: 03/02/17: Re: pos-map and post-PAR mismatch
52741: 03/02/20: Re: pos-map and post-PAR mismatch
52764: 03/02/20: Free Tool for defining FPGA pinouts
53000: 03/02/27: Re: Newbie Qn: Power connections with virtex FPGAs
53061: 03/03/02: Re: Virtex II - Driving more than one global clock net from one incoming clock pin
53062: 03/03/02: Re: guided par question
53187: 03/03/05: Re: Xilinx EDIF Flow and Blackbox Instantiation
Chris Rottner:
9696: 98/03/31: Re: Comparison of Orcad Express, Foundation Series, & Viewlogic WVO?
9924: 98/04/14: Re: Version Control for schematics?
10679: 98/06/10: Re: ViewDraw Info
10770: 98/06/17: ANNOUNCE: FPGA design with FPGA Express - UK Seminars
13055: 98/11/13: Re: WorkView office Library files need
Chris Rutten:
46423: 02/08/29: Virtex2 Pro Device support in Webpack?
46447: 02/08/30: tristate bus
chris rutten:
45329: 02/07/19: Re: XC2V1500 & XC2V2000 availabilty
45330: 02/07/19: Re: some questions from a fpga newer
Chris S:
84953: 05/06/01: C-1 how to reflash..
Chris Samwald:
7403: 97/09/07: Semi-Custom Analog IC Project Ideas???
8552: 98/01/08: RCA Digital Video Protocol Standards?
Chris Saturn:
59386: 03/08/18: Quartus and dcfifo
59433: 03/08/19: Re: Quartus and dcfifo
chris shaw:
27327: 00/11/18: Re: reset pulse ?
chris Shaw:
52685: 03/02/19: ABEL Help!
52730: 03/02/20: Re: ABEL Help!
Chris Shenton:
22675: 00/05/17: Re: Best choice between FPGA and CPLD
22835: 00/05/26: Re: CRC
23019: 00/06/09: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
23836: 00/07/12: Re: Xilinx XC4000E / Renoir
Chris Shipman:
1405: 95/06/16: Orbit Semiconductor
Chris Smoot:
72421: 04/08/18: Verilog ASIC conversion to Xilinx FPGA - GOTCHA
Chris Softley:
34518: 01/08/28: Level sensitive latches in Xilinx Virtex
34522: 01/08/28: Re: Level sensitive latches in Xilinx Virtex
34558: 01/08/29: Re: Level sensitive latches in Xilinx Virtex
Chris Sorenson:
103773: 06/06/10: Re: Xilinx ISE S/W Install kernel version "mismatch"
Chris Squires:
17076: 99/06/29: Re: altera flex 10k20 dedicated input
19329: 99/12/14: Re: State machine ok with binary encoding but unstable with one hot encoding
19347: 99/12/15: Re: State machine ok with binary encoding but unstable with one hot encoding
Chris Starr:
Chris Stephens:
9600: 98/03/25: New infomation resource on embedded microprcessors
10241: 98/05/06: Free tickets to UK Embedded Systems Show.
11503: 98/08/19: 30 new pages of embedded products + UK Embedded Show
13228: 98/11/20: UK Microprocessor H/W & S/W Developers - read on
17822: 99/09/08: The Embedded Web
32932: 01/07/12: How to get " The Embedded Newsletter "
Chris Stinson:
38096: 02/01/04: Re: Configuration Times of FPGAs
Chris Stratton:
75272: 04/10/31: Re: XST: suppressing incorrect optimizations in VHDL code
75294: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
74854: 04/10/20: Re: counter skrews up design
75364: 04/11/03: Re: compactflash interface problem
75430: 04/11/05: Re: minimum module name length in 6.3i?
75484: 04/11/07: Re: the compactflash true ide mode access
75705: 04/11/12: Re: C Compiler for Picoblaze !!!!!
75720: 04/11/12: Re: digital analog conversion
75737: 04/11/13: Re: Spartan3 Block RAM from WebPACK
75850: 04/11/16: Re: Spartan3 Block RAM from WebPACK
76001: 04/11/22: Re: Xilinx EDK - Unable to initialize BRAM in Simulation
76020: 04/11/22: Re: Spartan 3 output voltage level
76041: 04/11/23: Re: Help! What is this card?
Chris Suslowicz:
33797: 01/08/05: Re: Why did Zephram spool outside all the users? We can't post procedures unless Brion will grudgingly dig afterwards.
chris talsma:
155516: 13/07/13: Re: Low cost board with built-in USB for fast data transfer and lots
Chris Tate:
16189: 99/05/08: Re: BGA Prototyping ?
Chris Taylor:
281: 94/10/12: FLEX8000 architecture / routability with fixed pin-out
Chris Torek:
57309: 03/06/27: Re: Eighty layers of metal!
Chris Ward:
29961: 01/03/19: FPGA based Neural Networks
52373: 03/02/07: LFSR: Galois and Fibonacci
52443: 03/02/10: Re: LFSR: Galois and Fibonacci
52630: 03/02/17: Re: LFSR: Galois and Fibonacci
52649: 03/02/18: Re: LFSR: Galois and Fibonacci
Chris Waterman:
14897: 99/02/23: FLEX PROBLEM
Chris Wilkson:
41414: 02/03/27: FPGA config without boot PROM???
Chris Wright:
5905: 97/03/25: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
5917: 97/03/26: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
Chris Zimman:
43767: 02/06/01: NIOS GNUPro tool chain + SDK for Linux
chris.felton@gmail.com:
109110: 06/09/20: Re: Which soft core to use?
109238: 06/09/22: Re: Spartan-3E USB for I/O?
<chris.felton@gmail.com>:
105150: 06/07/14: Re: FPGA board for USB experiments?
<Chris.Gammell@gmail.com>:
95690: 06/01/25: Spartan-3 Starter Board
95015: 06/01/20: Re: OT:Shooting Ourselves in the Foot
<chris.hallahan@nuvation.com>:
83080: 05/04/22: Re: ATA FPGA IP Core
114689: 07/01/22: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
<Chris.omitthisbit.Brown@arm.andthisbit.com>:
11421: 98/08/12: Re: VHDL-C
chris.wei:
27681: 00/12/02: pcmcia host controller ??
Chris@Austin:
120745: 07/06/15: help on clock fowarding between 2 FPGAs
<chris@intercon.net>:
chris_ivan:
90957: 05/10/25: Re: a few questions
90958: 05/10/25: Re: a few questions
91025: 05/10/27: Re: crc on only data or including the address
99546: 06/03/26: Re: VHDL LUT
99961: 06/03/31: =?iso-8859-1?q?Re:_how_to_read_this_book=AB_Digital_integrated_circuits.a_design_perspective(Second_Edition)=BB?=
chris_s:
57606: 03/07/02: XPLA3 vs. MAX3000A
57678: 03/07/03: Re: XPLA3 vs. MAX3000A
Chris_S:
33782: 01/08/04: Where's SpartanXL in WebPack?
57632: 03/07/03: Re: XPLA3 vs. MAX3000A
57633: 03/07/03: Re: What a fascinating board!
57663: 03/07/03: Re: XPLA3 vs. MAX3000A
57666: 03/07/03: Re: XPLA3 vs. MAX3000A
57670: 03/07/03: Re: XPLA3 vs. MAX3000A
57705: 03/07/03: Re: XPLA3 vs. MAX3000A
57751: 03/07/05: Re: XPLA3 vs. MAX3000A
57757: 03/07/05: Re: XPLA3 vs. MAX3000A
57761: 03/07/06: What About CPLD Standardization ?
chrisabele:
155096: 13/04/12: Re: Programming the old Spartan S3E Sample Board
155289: 13/06/22: Re: New soft processor core paper publisher?
157517: 14/12/14: Re: Using FPGA to feed 80386
157550: 14/12/15: Re: Using FPGA to feed 80386
157961: 15/06/04: Re: Free timing diagram drawing software
<chrisawest@gmail.com>:
86738: 05/07/05: Re: xp3/xp6 in ispLever
101041: 06/04/24: Re: Altera Stratix II GX LVDS max speed
<chrisbw@gmail.com>:
85181: 05/06/06: Re: Hope for OS X tools...
99502: 06/03/25: Re: OpenSPARC released
99503: 06/03/25: Re: OpenSPARC released
99547: 06/03/26: Re: OpenSPARC released
99635: 06/03/27: Re: OpenSPARC released
chrisdekoh:
147220: 10/04/19: clock routing to generic IO pins?
<chrisdekoh@gmail.com>:
128925: 08/02/10: microblaze firmware + UART handshaking blues
128926: 08/02/10: Re: Timing Constraint not met
128954: 08/02/11: Re: microblaze firmware + UART handshaking blues
129014: 08/02/12: Re: microblaze firmware + UART handshaking blues
129070: 08/02/13: Re: microblaze firmware + UART handshaking blues
129447: 08/02/24: more microblaze firmware blues. tool chain version problem?
131264: 08/04/17: attached a 2nd peripheral to FSL bus. how to use it in software?
131309: 08/04/18: Re: attached a 2nd peripheral to FSL bus. how to use it in software?
131349: 08/04/20: synchronous reset problems on FPGA
131370: 08/04/20: Re: synchronous reset problems on FPGA
131373: 08/04/20: Re: synchronous reset problems on FPGA
131382: 08/04/20: Re: synchronous reset problems on FPGA
131454: 08/04/21: Re: attached a 2nd peripheral to FSL bus. how to use it in software?
131744: 08/04/30: co-sim for handel C with modelsim vs pure modelsim VHDL simulation
131857: 08/05/04: EDK9.2i simulation problems.
131872: 08/05/05: Re: EDK9.2i simulation problems.
132602: 08/06/02: using hard tri-mode ethernet MAC and MPMC on virtex 5
132713: 08/06/05: Re: using hard tri-mode ethernet MAC and MPMC on virtex 5
132859: 08/06/09: how to prevent timer code firmware running on Microblaze from being
132911: 08/06/10: Re: how to prevent timer code firmware running on Microblaze from
133450: 08/06/30: lwip for FPGA
133646: 08/07/08: Re: lwip for FPGA
134090: 08/07/24: Xilinx FFT core's IFFT function not working? Dun Xilinx TEST their
134107: 08/07/25: Re: Xilinx FFT core's IFFT function not working? Dun Xilinx TEST
134212: 08/07/30: using the mex file model for xfft_v5 Xilinx core-generator
134273: 08/08/04: fixed FFT point implementation woes
135764: 08/10/15: DDR2 timing questions
ChrisEilbeck:
11757: 98/09/07: Re: 22V10 programming
ChrisH:
10730: 98/06/13: Re: book on ASIC
chriskoh:
104229: 06/06/21: using Celoxica's RC10 with microblaze's EDK kit
108588: 06/09/13: xilinx platform studio 7.1i
113435: 06/12/13: more of ERROR:MapLib:661
113450: 06/12/13: Re: more of ERROR:MapLib:661
113682: 06/12/19: interrupt handling using microblaze with XPS
115013: 07/01/29: DCM instantiation in XPS7.1i and ISE7.1. Bug or error?
124112: 07/09/12: precision errors. microblaze vs matlab single precision... huh?
124127: 07/09/12: Re: precision errors. microblaze vs matlab single precision... huh?
124131: 07/09/12: Re: precision errors. microblaze vs matlab single precision... huh?
124158: 07/09/12: Re: precision errors. microblaze vs matlab single precision... huh?
ChrisKuo@Austin:
120747: 07/06/15: Need help on clock forwarding on Xilinx Virtex-5
chrisnonso:
158312: 15/10/10: Re: FPGA/HDL/HLS/Digital design centered Master degree online
chrispy35:
108610: 06/09/13: resets on synplicity inferred RAMs
christelle:
23802: 00/07/10: Quartus
Christer Ericson:
19624: 00/01/05: Re: An online division unit with constant divisor
105662: 06/07/28: Re: Hardware book like "Code Complete"?
Christian:
54090: 03/04/02: ALTERA APEX 20K Series: Are there configurable pullups in IO cells?
54555: 03/04/14: Tristate-Bus-Termination; fast pullup req'd
54557: 03/04/14: Re: Tristate-Bus-Termination; fast pullup req'd
54662: 03/04/15: open SOC-bus system required!
55027: 03/04/24: Re: open SOC-bus system required!
55028: 03/04/24: Re: open SOC-bus system required!
Christian =?iso-8859-1?Q?Sch=E4fer?=:
10061: 98/04/25: Re: How low can they go?
Christian Cartland - Glover:
6192: 97/04/24: Re: EDIF200
Christian Ciressan:
6829: 97/07/01: FPGA -> NLP question !
6830: 97/07/01: FPGA ->NLP question !
Christian E. Boehme:
72631: 04/08/27: Xilinx Spartan II and 5V PCI
72632: 04/08/27: Xilinx XC9572XL delay prediction
72727: 04/08/30: Re: Xilinx Spartan II and 5V PCI
72759: 04/09/01: Re: Xilinx Spartan II and 5V PCI
72761: 04/09/01: Re: Xilinx Spartan II and 5V PCI
72763: 04/09/01: Re: Xilinx Spartan II and 5V PCI
72790: 04/09/02: Re: Xilinx Spartan II and 5V PCI
72791: 04/09/02: Re: Xilinx Spartan II and 5V PCI
73988: 04/10/02: Re: Xilinx ISE 6.2i WebPack & project restoration
73989: 04/10/02: Re: Xilinx Constraints
72852: 04/09/05: Re: PCI Noise
72868: 04/09/06: OD/OC outputs with Xilinx Spartan II
72900: 04/09/08: Re: OD/OC outputs with Xilinx Spartan II
72949: 04/09/09: Re: OD/OC outputs with Xilinx Spartan II
73621: 04/09/26: Xilinx ISE 6.2i WebPack & project restoration
74947: 04/10/22: Re: Simultaneously Switching Outputs in Spartan-II
74816: 04/10/20: Simultaneously Switching Outputs in Spartan-II
Christian Gelinek:
82999: 05/04/21: Xilinx ISE Warning: FF/Latch <> is unconnected in block <>
83053: 05/04/22: Re: Xilinx ISE Warning: FF/Latch <> is unconnected in block <>
Christian Geuer-Pollmann:
15748: 99/04/12: Regular Expressions in VHDL / FPGA's
Christian Gollwitzer:
159715: 17/02/14: Re: All-real FFT for FPGA
159724: 17/02/14: Re: All-real FFT for FPGA
Christian Grebe:
2161: 95/10/23: Re: Where to find more info on PCI
2167: 95/10/24: Re: Problem using Xilinx XC4025
2199: 95/10/31: Re: AT&T vs. Xilinx
2227: 95/11/06: Re: XC4025 routing
2228: 95/11/06: Re: Xilinx XSI FPGA User Guide
3541: 96/06/18: Re: XC4025
Christian Haase:
57264: 03/06/26: Dynamic Reconfiguration, Virtex II Pro
57481: 03/07/01: Re: Dynamic Reconfiguration, Virtex II Pro
57778: 03/07/07: Dynamic Reconfiguration, Contentions
57887: 03/07/09: Re: Dynamic Reconfiguration, Contentions
57940: 03/07/10: Partial Bitstream, Virtex-II, Virtex-II PRO
60207: 03/09/08: Re: Partial Reconfiguration : 2 reconfig modules
60595: 03/09/17: Re: Making hard macros in Xilinx FPGA Editor
60596: 03/09/17: Re: Partial Reconfiguration : 2 reconfig modules
60997: 03/09/26: Partial Reconfiguration, ISE 6.1
61207: 03/09/30: Configuration Clause, XST
62124: 03/10/20: Re: Virtex CLB
63798: 03/12/04: Re: Need a few tips working with an Xilinx FPGA
64025: 03/12/12: EDK, reset module, interrupts
64060: 03/12/15: Re: EDK, reset module, interrupts
64556: 04/01/07: plb_sdram, timing error
68522: 04/04/07: Re: timing constraints... again
68801: 04/04/19: plb_ddr_v1_00_b, PLB_SMErr
69277: 04/05/04: ASIC design
Christian Habermann:
22763: 00/05/23: Virtex: Verify and Readback; Capture_Virtex
22913: 00/06/01: Virtual Workbench VW-300, verify
Christian Illinger:
7336: 97/08/28: Mach131
30976: 01/05/07: Licensing PB in Synplify_pro 6.2
Christian Iseli:
79: 94/08/11: Would you like a free C to netlist compiler?
698: 95/02/09: ANNOUNCE: Free C++ to netlist compiler available
2417: 95/12/02: Free C hardware synthesizer available
Christian Kirschenlohr:
106544: 06/08/15: Re: Crystal input for FPGA
108322: 06/09/08: Re: ddr with multiple users
113312: 06/12/11: Re: Video Mux using FPGA
120581: 07/06/11: Re: DVI over fiber
120913: 07/06/20: Re: Interesting problems about high performance computing
120922: 07/06/20: Re: Graduate/Junior FPGA Designer concerns
123389: 07/08/27: Looking for VME-Bus Core
Christian Kramer:
46449: 02/08/30: Crashes while reading from memory with Nios
49061: 02/10/31: CLK4p in Nios board schematic
61701: 03/10/09: Quartus, JTAG, Programming Hardware
Christian Lehmann:
38512: 02/01/16: info about NIOS softcore processor
Christian Lotze:
55805: 03/05/20: newbie question plx9054 and memory access
Christian Ludlam:
109974: 06/10/09: Re: An implementation of a clean reset signal
Christian Martin:
30116: 01/03/23: Accumulator - Core in XC4K
Christian Mautner:
5279: 97/02/03: boundary scan - vhdl - xilinx
17991: 99/09/21: Re: test
21972: 00/04/10: Re: Xilinx Foundation 2.1 error
21973: 00/04/10: Re: setup and hold time violation
22019: 00/04/12: Re: Multiple Clock design, setup & hold time violation
22088: 00/04/20: Re: PULL-UPs on Xilinx-FPGA pads
22206: 00/05/01: Re: Verilog Compiler ?
22315: 00/05/04: Re: [BitGen] - pb option UserClk
22317: 00/05/04: edif
22360: 00/05/05: Re: [BitGen] - pb option UserClk
22361: 00/05/05: Re: [BitGen] - pb option UserClk
22358: 00/05/05: Re: edif
22362: 00/05/05: Re: edif
22376: 00/05/06: Re: edif
22390: 00/05/07: Re: [BitGen] - pb option UserClk
22739: 00/05/21: Re: Help for a novice of Xilinx Foundation
22749: 00/05/22: Re: Xilinx tools
22952: 00/06/05: Re: Convert Xilinx Foundation ourput to C/C++ compatible file.
22935: 00/06/04: Re: Convert Xilinx Foundation ourput to C/C++ compatible file.
24360: 00/08/04: Re: models of digital ICs
24361: 00/08/04: Re: FPGA selection
24439: 00/08/08: Re: HELP! Strange Xilinx Software Error
24473: 00/08/10: leonardo/altera/LPM_RAM_DP
24520: 00/08/11: Re: Deterministic FPGA routing?
24521: 00/08/11: Re: Replacement for Altera ByteBlaster & ByteBlasterMV
25149: 00/08/28: Re: make for design flow (was: Deterministic FPGA routing?)
25235: 00/08/31: Re: run time doubled with Xilinx 3.1i upgrade
25236: 00/08/31: Re: make for design flow (was: Deterministic FPGA routing?)
25404: 00/09/10: Re: About XNF, EDIF and UCF
Christian Metzler:
108599: 06/09/13: Xilinx Platform Cable USB on Linux: Impact always wants to update
Christian Obel:
58975: 03/08/05: Block ram simulation
123331: 07/08/24: Annoying
Christian Peter:
83160: 05/04/25: Re: CCD and Graphics - which FPGA?
Christian Plessl:
29154: 01/02/08: Wired-or on Virtex FPGAs
29192: 01/02/09: Re: Wired-or on Virtex FPGAs
29274: 01/02/12: Re: Wired-or on Virtex FPGAs
29724: 01/03/06: Re: Suggestions for I/O card
29784: 01/03/09: Spartan-II Evaluation Board
37639: 01/12/18: Xilinx Foundation - Routing constraints/prohibit
38307: 02/01/11: Re: Avoid routing through a certain area (Xilinx)
38413: 02/01/14: Re: Avoid routing through a certain area (Xilinx)
38547: 02/01/17: Virtex2 ICAP
38559: 02/01/17: Re: Virtex2 ICAP
40734: 02/03/14: Re: Where can I get the information on implementing CPU with FPGA?
40924: 02/03/18: Re: questions from a newby
41202: 02/03/22: Evaluation board for Virtex-II pro
42766: 02/05/02: Re: XC4000 readback woes
42811: 02/05/03: Re: XC4000 readback woes
43078: 02/05/13: Re: JVM using FPGAs
44583: 02/06/24: Re: book recommenation
44669: 02/06/26: Re: Virtex-E Readback.
52457: 03/02/10: Re: Multicontext FPGA
52464: 03/02/10: Re: Multicontext FPGA
Christian Reichherzer:
27234: 00/11/16: Problems wirh JTAG-Configuration of 18V512 and Spartan XCS40
Christian Reithmeier:
25155: 00/08/29: Re: Problems Fitting Design When Inserting More Than One Internal Global Buffer...
Christian Riesch:
60538: 03/09/16: ByteblasterMV and QuartusII 3.0
Christian Schaefer:
6736: 97/06/20: Re: XCHECKER Download to Xilinx 9500 CPLDs
7366: 97/09/02: asynchronous designs with VHDL ?
7764: 97/10/13: Synopsys, XACT, XC4000: CLB estimates
7773: 97/10/14: Synopsys: OPT-906
Christian Schleiffer:
105119: 06/07/14: OPB or FSL?
105137: 06/07/14: Re: OPB or FSL?
107024: 06/08/23: Re: fastest FPGA
112490: 06/11/23: Problems connecting MicroBlaze to custom IP
112493: 06/11/23: Re: Problems connecting MicroBlaze to custom IP
112514: 06/11/23: Re: Problems connecting MicroBlaze to custom IP
112515: 06/11/23: Re: Problems connecting MicroBlaze to custom IP
112742: 06/11/28: Re: EDK Bug
112744: 06/11/28: Re: EDK Bug
Christian Schmitz:
Christian Schneider:
59471: 03/08/20: Re: random address
59608: 03/08/23: Re: Some questions about Xilinx ISE
59654: 03/08/25: Re: Enhancing PAR with FPGA floorplanners
59710: 03/08/26: Re: Enhancing PAR with FPGA floorplanners
59953: 03/09/02: Re: What does + synthesize to?
60850: 03/09/23: Re: Location constraint
79056: 05/02/12: Re: Basics of BFM
79497: 05/02/20: Re: Shift register example?
79596: 05/02/21: Re: Shift register example?
80095: 05/03/01: Re: FPGA tool benchmarks on Linux systems
80097: 05/03/01: Re: FPGA interface to an asynchronous microcontroller memory bus
80105: 05/03/01: Re: FPGA tool benchmarks on Linux systems
80211: 05/03/02: Re: Xilinx ISE7.1
80215: 05/03/02: Re: Part of a ranged signal
80311: 05/03/03: Re: Xilinx ISE7.1
80662: 05/03/09: Re: RPM creation
Christian Schrader:
130037: 08/03/13: Re: Problem with Spartan 3 StarterKit
Christian Schuhegger:
52548: 03/02/13: is there a xnf2edif program?
christian sternell:
55202: 03/04/30: spartan 3 development board
55407: 03/05/06: Re: spartan 3 development board
Christian Weber:
55120: 03/04/28: Re: open SOC-bus system required!
Christian Werner:
27452: 00/11/22: Virtex-PCI-Boards
Christian Widtmann:
56751: 03/06/13: Problem with tristate-inout-pins of PS/2-Host
56797: 03/06/16: Re: Problem with tristate-inout-pins of PS/2-Host
148075: 10/06/18: Re: Xilinx Timing Constraings
Christian Wiencke:
28407: 01/01/11: Problem with Simulation of VirtexE Block SelectRAM
Christian Wiesner:
113617: 06/12/18: OFFSET Constraining a Signal behind a DCM?
114514: 07/01/18: Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?
114515: 07/01/18: Re: Xilinx website login problems
114657: 07/01/22: Re: Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?
115250: 07/02/05: Re: Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?
Christian Zander:
61110: 03/09/28: Sparten-IIE Configuration (Slave Parallel Mode)
61230: 03/09/30: Re: Sparten-IIE Configuration (Slave Parallel Mode)
christian.bau:
118879: 07/05/05: Re: debounce state diagram FSM
Christina:
Christine Price:
7111: 97/08/01: Re: jtag isp guidance request
Christof:
79657: 05/02/22: FPGA board with best cost/CLB ratio?
Christof Abt:
28625: 01/01/18: Re: revision control tools ??
Christof Paar:
3693: 96/07/16: q
4262: 96/10/07: Re: FPGA for Reed-Solomon Codec
7604: 97/09/26: Reed-Solomon Coder Arithmetic
9156: 98/02/25: Re: Galois field
12270: 98/10/07: Faculty Position
12339: 98/10/09: FCCM 99?
12489: 98/10/13: Re: DES in FPGA
13087: 98/11/15: Re: DES in VHDL?
13064: 98/11/14: Re: DES in VHDL?
14594: 99/02/05: Re: DES in VHDL for FPGAs
14936: 99/02/25: Re: Your view on this article?
14978: 99/03/01: CFP: Crypto Workshop
15794: 99/04/14: CHES CFP
18916: 99/11/21: CHES 2000
19439: 99/12/21: M1 timings
19638: 00/01/05: Re: Decoding RSPC (Reed Solomon Product Code)
20342: 00/02/06: CFP --- CHES 200
21297: 00/03/15: CHES 2000 --- 3rd CFP
21884: 00/04/05: CHES 2000 deadline extended
23359: 00/06/23: CHES 2000 accepted papers
23956: 00/07/18: CHES 2000 Program
26396: 00/10/14: CHES 2001 Workshop
28447: 01/01/12: CHES 2001 --- 2nd CFP
29035: 01/02/02: CHES 2001 --- Final CFP
29758: 01/03/07: CHES 2001 registration!
30318: 01/04/02: accepted papers at CHES 2001
30885: 01/05/02: Final Program CHES 2001
36918: 01/11/26: CHES 2002 - Call For Papers
40150: 02/02/28: Call for Papers CHES 2002
41933: 02/04/11: CHES 2002 --- Final CFP
50151: 02/12/03: CHES 2003 - 1st CFP
55836: 03/05/21: CHES 2003: accepted papers etc.
65249: 04/01/22: CHES 2004, 2nd CFP
Christof Teuscher:
16259: 99/05/12: Re: Virtex development boards
23313: 00/06/22: Re: FPGAs for Bioinformatics accelerators
Christofire:
36170: 01/10/31: Hardware Software Partitioning help required.
Christoph Brinkhaus:
51967: 03/01/27: Re: WTB: 16L8 / 20L8 programmer
66806: 04/02/27: Re: Basic jitter from a CPLD (XC7500XL)
68491: 04/04/06: Re: Msg for Rudolf Usselmann
71045: 04/07/06: Re: Has anybody used the DAC in the new Nu Horizons Spartan 3 development board
71124: 04/07/09: Re: Has anybody used the DAC in the new Nu Horizons Spartan 3 development board
74488: 04/10/12: Re: level converter for high frequencies
78977: 05/02/10: Re: PACE error
Christoph Cronimund:
19676: 00/01/07: Versatile digital filter for signal processing systems
Christoph Fritsch:
47220: 02/09/20: Re: Apex unused pins voluntarily assigned by Quartus?
47319: 02/09/23: Re: Unused pins in Apex20KE
Christoph Grimm:
5447: 97/02/17: Re: Mealy/Moore state machines
Christoph Grundner:
57636: 03/07/03: create JAM-File for Xilinx device
57779: 03/07/07: Re: create JAM-File for Xilinx device
Christoph Hauzeneder:
28464: 01/01/14: Re: I wanna Model Sim cracked
28734: 01/01/22: Re: Firewire bus driven/received by Xilinx using LVDS
35821: 01/10/18: Re: Firewire chipset
49608: 02/11/17: Re: CoolBlaze and PicoBlaze
51736: 03/01/20: Re: Virtex 2 FPGA Board ...
Christoph Lauer:
82050: 05/04/06: HWICAP BRAM access (with EDK)
82136: 05/04/07: Major Adresses on Xilinx Virtex-II
84314: 05/05/17: edk sram interface - board definitions files xbd
88052: 05/08/08: Active module phase with multiple module instances
88098: 05/08/09: partial reconfig with multipiers
93017: 05/12/12: modelsim settings in edk
93021: 05/12/12: Re: modelsim settings in edk
Christoph Loew:
73210: 04/09/16: Re: Looking for a Design for a Small FPGA Board
christophe:
christophe ALEXANDRE:
101589: 06/05/03: ML405 board
101733: 06/05/05: Re: ML405 board
121226: 07/06/28: vista 64 bits
121562: 07/07/08: Re: vista 64 bits
121925: 07/07/15: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
Christophe BARNICHON:
9607: 98/03/25: xilinx M1.4 / XC3000 problem
Christophe Beaumont:
5216: 97/01/31: Re: DES Challenge
christophe combaret:
16830: 99/06/11: actel desktop
Christophe Heyert:
23016: 00/06/09: using DDL in virtex FPGA
23076: 00/06/13: DLL in virtex fpga
23486: 00/06/27: configuration of RAM created with coregen
24707: 00/08/17: multiplying DLL in Virtex
25917: 00/09/26: Coregen
26077: 00/10/03: Re: Coregen
26078: 00/10/03: Re: Xilinx Demo Board
christophe Macia:
9713: 98/04/01: bootstrap loader
ChristopheGuelff:
30309: 01/04/02: good knwoledge in fpga or vhdl
43493: 02/05/22: We need people with good knowledge about FPGA
47487: 02/09/26: CPCNG project : website updated
47494: 02/09/26: Re: CPCNG project : website updated
86263: 05/06/23: Need help for Xilinx FPGA
Christopher:
3297: 96/05/10: Looking for free FPGA softw./Xilinx
3316: 96/05/13: Re: Looking for free FPGA softw./Xilinx
56925: 03/06/18: Altera FPGA
57031: 03/06/20: Quartus II VHDL 2 modules
57121: 03/06/23: Quartus design Module Help
120446: 07/06/07: Re: asynchronous circuit design
Christopher Cole:
46248: 02/08/22: Re: Want a most simple develop board's design example for Xilinx FPGA(SP-II)?
48120: 02/10/11: Re: Intel ARM 'XScale' cores as IP blocks that can be synthesized into an FPGA/ASIC?
94349: 06/01/10: ISE 8.1i WebPack available
101512: 06/05/02: windrvr for Linux broken in 2.6.16
104286: 06/06/22: Spartan 3E Starter Kit - diff b/t rev. C and D?
108275: 06/09/07: Xilinx Impact Cable Drivers for 64-bit Linux?
122610: 07/08/01: Xilinx Webpack for Linux 64 bit?
Christopher Duncan:
39926: 02/02/22: OT - Programmer war stories
Christopher Fairbairn:
10796: 98/06/19: Getting into using FPGAs
54548: 03/04/14: ISE WebPack under Linux (use of command line tools)
54712: 03/04/17: Re: ISE WebPack under Linux (use of command line tools)
54840: 03/04/20: Re: ISE WebPack under Linux (use of command line tools)
62503: 03/10/31: Wishbone interface, FPGA newbie and advice
62543: 03/11/01: Re: Wishbone interface, FPGA newbie and advice
62547: 03/11/01: Re: Wishbone interface, FPGA newbie and advice
Christopher Felton:
151418: 11/04/05: Re: SCons build tool as an alternative to makefiles
151558: 11/04/19: Re: iir filter
151578: 11/04/21: Re: NibzX7 processor
151612: 11/04/26: Re: Lattice Breakout Boards
151684: 11/05/05: Re: remove Xilinx webtalk
151686: 11/05/05: Re: remove Xilinx webtalk
151735: 11/05/13: Re: J1 forth processor in FPGA - possibility of interactive work?
151895: 11/06/02: Re: FFT using logic gates only
152955: 11/11/04: Re: Fundamental DSP/speech processing patent for sale
153127: 11/12/08: Re: Horsepower On Tap
154191: 12/08/31: Re: General Build Question
154554: 12/11/27: Re: VHDL expert puzzle
154559: 12/11/28: Re: VHDL expert puzzle
154560: 12/11/28: Re: VHDL expert puzzle
154727: 12/12/29: Re: Chisel as alternative HDL
154734: 12/12/31: Re: Chisel as alternative HDL
154739: 13/01/02: Re: Chisel as alternative HDL
154754: 13/01/04: Re: Chisel as alternative HDL
154760: 13/01/04: Re: Chisel as alternative HDL
154772: 13/01/06: Re: Chisel as alternative HDL
154773: 13/01/06: Re: Chisel as alternative HDL
154777: 13/01/07: Re: Chisel as alternative HDL
154778: 13/01/07: Re: Chisel as alternative HDL
154885: 13/01/28: DSP in FPGA (was Re: Ray Andraka's Book?)
154890: 13/01/28: Re: DSP in FPGA (was Re: Ray Andraka's Book?)
154917: 13/02/13: Re: Chisel as alternative HDL
154918: 13/02/13: Re: Chisel as alternative HDL
154920: 13/02/13: Re: Chisel as alternative HDL
154922: 13/02/14: Re: Chisel as alternative HDL
156943: 14/08/01: Re: Professional VHDL Examples?
156989: 14/08/13: Re: Basic question: sequence of execution within FPGAs
157975: 15/06/09: Re: Open/Free HLS weapon of choice ?
157978: 15/06/09: Re: Open/Free HLS weapon of choice ?
Christopher G. Holmes:
2839: 96/02/15: Abel mode for Emacs?
3290: 96/05/09: Re: Is XC7336 the least expensive CPLD?
Christopher G. Tscharner:
88: 94/08/12: Re: Proprietary Configuration Data
105: 94/08/16: Re: translator needed
465: 94/11/25: FPGAs not CPLDs was Re: any XC4000 Horror Stories?
Christopher Head:
147638: 10/05/11: Re: Expecting sequential output, but RTL shows concurrent
147777: 10/05/23: Re: spartan6 configuration
150116: 10/12/14: Re: Xilinx Flash PROM and Config rate for Spartan 6 FPGA
150173: 10/12/24: Re: Un-encrypted bit file and Device DNA
151152: 11/03/11: Re: Pull up/down resistors on Spartan-3E configuration inputs
151236: 11/03/17: Re: Command line for fuse (behavioral sim), for ISE WebPack
151940: 11/06/10: Area Optimization
151957: 11/06/14: Re: Area Optimization
151979: 11/06/16: Re: Area Optimization
152201: 11/07/19: Re: XST 13.1 explodes with generic of enum type with only one
153778: 12/05/16: Xilinx ISE Multiple Drivers Error
153784: 12/05/18: Re: Xilinx ISE Multiple Drivers Error
153785: 12/05/18: Re: Xilinx ISE Multiple Drivers Error
153788: 12/05/20: Re: Xilinx ISE Multiple Drivers Error
153817: 12/05/26: Re: Xilinx ISE Multiple Drivers Error
154263: 12/09/19: Re: Global Reset using Global Buffer
154317: 12/09/27: Re: Global Reset using Global Buffer
154954: 13/03/03: Xilinx XST and initializing block RAMs
154958: 13/03/03: Re: Xilinx XST and initializing block RAMs
154972: 13/03/05: Re: Xilinx XST and initializing block RAMs
154973: 13/03/05: Re: Xilinx XST and initializing block RAMs
Christopher Holmes:
40563: 02/03/10: Re: digital video PLL
Christopher J Burian:
332: 94/10/22: I/O pin currents on Xilinx FPGAs?
346: 94/10/25: Re: I/O pin currents on Xilinx FPGAs?
Christopher J. Holland:
34048: 01/08/12: Digilab 10K10 resources / samples?
34069: 01/08/13: Re: Digilab 10K10 resources / samples?
Christopher J. White:
1338: 95/06/02: Xilinx Master/Slave Serial Configuration
1376: 95/06/09: 256k Serial Configuration PROM for Xilinx???
Christopher Malkin:
23762: 00/07/07: calculating modulo N
Christopher Price:
4915: 96/12/30: vga output
Christopher Puff:
6612: 97/06/05: Re: Your recommendation needed
Christopher R. Carlen:
47732: 02/10/02: Need advice wiring up a CPLD
47754: 02/10/03: Re: Need advice wiring up a CPLD
47766: 02/10/03: Re: Need advice wiring up a CPLD
47767: 02/10/03: Re: Need advice wiring up a CPLD
47768: 02/10/03: Re: Need advice wiring up a CPLD
50705: 02/12/17: How to asynchronously reset a flip-flop?
50744: 02/12/18: Re: How to asynchronously reset a flip-flop?
Christopher Red:
70263: 04/06/10: run-time management of logic resources
Christopher Saunter:
36353: 01/11/07: Modifying BlockRAM contents in a bitstream?
37604: 01/12/17: Re: Multiplying by squaring using Block RAM.
37610: 01/12/17: Re: Certicom challenge and FPGA based modular math
39867: 02/02/21: Re: Here is an argument and can anyone help me out
39932: 02/02/22: Re: Here is an argument and can anyone help me out
40246: 02/03/03: Re: Creation of FPGA tips and tricks forum - help required
40648: 02/03/12: Re: Mystery two wire interface, or am I being dense?
40745: 02/03/14: Re: Proto boards for labs
40838: 02/03/16: Extracting schematics to a vector file
41193: 02/03/22: Re: Interconnect system for multiple FPGA's ?
41287: 02/03/25: Re: Pipelined sorting algorithms...
41291: 02/03/25: Re: Pipelined sorting algorithms...
41338: 02/03/26: Re: Pipelined sorting algorithms...
41642: 02/04/04: Schematic Stuff
41793: 02/04/08: Re: Schematic Stuff
41853: 02/04/09: Re: Xilinx Prototype Platforms
42487: 02/04/25: Re: Prototyping Boards for Hobbyist CPU/System Designs
43444: 02/05/21: 5V differential -> Virtex 2
43536: 02/05/23: Re: 5V differential -> Virtex 2
43802: 02/06/03: Re: divide by 5
46147: 02/08/20: Re: Poor man's DSP/FPGA instructional tool?
46333: 02/08/26: Re: Poor man's DSP/FPGA instructional tool?
46425: 02/08/29: LabVIEW -> FPGA
47342: 02/09/24: Re: Timing accuracy with Modelsim
47522: 02/09/27: Re: CPCNG project : website updated
47599: 02/09/30: Re: Large Multiplexer
47694: 02/10/02: Re: Large Multiplexer
49072: 02/10/31: V2Pro board with gigabit Ethernet?
56133: 03/05/29: Re: need help on sending 500Mbit/s data through 100 feet of cable, Giga-Ethernet?
56395: 03/06/04: Re: ANN: Confluence -> Python for Hardware Verification
60683: 03/09/19: Re: DigiLab2 Spartan 2 : Can't download..
Christopher VanBeek:
2820: 96/02/12: Re: Xilinx FPGA's with Mentor Tools?
Christos:
59789: 03/08/28: Moving Sum
59841: 03/08/29: Re: Moving Sum
59917: 03/09/01: Re: Moving Sum
59941: 03/09/02: Re: Moving Sum
60002: 03/09/03: Re: Moving Sum
60108: 03/09/05: Include design file using QuartusII
60110: 03/09/05: Re: Moving Sum
60877: 03/09/24: Re: Interfacing external NVRAM
61703: 03/10/09: Quartus II simulation question.
61841: 03/10/14: Re: Quartus II simulation question.
62300: 03/10/24: Re: Thank to you and Google
63007: 03/11/12: Re: Local nodes are not visible anymore after simulation (Altera Quartus II )
65879: 04/02/09: Re: [Quartus] File folders changed -> errors
67341: 04/03/10: Re: Using ALTPLL
67352: 04/03/10: Re: Using ALTPLL
68740: 04/04/16: Re: vhdl example for use of external SRAM as a dual ported RAM?
70998: 04/07/05: Re: crc32 vhdl implementation (4 bit data)
71529: 04/07/21: Re: Changing directory name in Quartus
72454: 04/08/19: Re: Viewing internal nets during Quartus functional simulation
78813: 05/02/08: Re: Retaining not used nodes
78961: 05/02/10: Re: Virtual Pins in QuartusII
79019: 05/02/11: Altera's Megafunction altaccumulator
79096: 05/02/14: Re: Altera's Megafunction altaccumulator
81713: 05/03/30: Re: Bus expansion
Christos Dimitrakakis:
5368: 97/02/11: Random Number Generators with Xilinx FPGA xc4000 series
5394: 97/02/13: MG Autologic, Xilinx FPGAs and X-Blox
5712: 97/03/10: Xilinx FPGA & SIMMs
5894: 97/03/24: fast resampling
6270: 97/05/07: [Help] Buggy LFSR in Xilinx Application notes???
6306: 97/05/13: Cheap way to develop for FPGAs?
<christovt@gmail.com>:
124752: 07/10/03: Partial/Incorrect configuration of FPGA from flash PROM.
Christy Looby:
7747: 97/10/10: Re: How fast can fully pipelined XC4000 logic go?
chronoer:
98379: 06/03/09: delay in altera cyclone about led
98386: 06/03/09: Re: delay in altera cyclone about led
98392: 06/03/09: Re: delay in altera cyclone about led
chsw:
25916: 00/09/26: Re: Category : why is 0?
25935: 00/09/26: Category : Subject
26730: 00/10/26: what's meaning?
26743: 00/10/26: Re: what's meaning?
26774: 00/10/27: why?
26803: 00/10/30: why?
27508: 00/11/26: how do i?
26876: 00/11/02: Block Ram
27057: 00/11/08: Reference Design Xapp205.zip
27650: 00/12/01: glbl
27683: 00/12/02: Re: glbl
27688: 00/12/02: Re: glbl
27752: 00/12/06: what's meaning?
28215: 01/01/01: help
28476: 01/01/14: Synplify Pro6.13
28481: 01/01/15: fifo
28514: 01/01/16: answer
chthon:
153181: 12/01/04: Trying to select a development board, can somebody help me make an
153629: 12/04/07: Any people having experience with HWICAP?
153631: 12/04/07: Re: Any people having experience with HWICAP?
153633: 12/04/07: Re: Any people having experience with HWICAP?
153657: 12/04/10: Partial reconfiguration: bus macros
153664: 12/04/10: The Xilinx Definition Language
153692: 12/04/24: Hard macros: can anybody give me practical advice?
153700: 12/04/25: Re: RPMs in xilinx 13.2
153703: 12/04/26: Re: RPMs in xilinx 13.2
153704: 12/04/26: Re: No bitstream generation on ISE 13.4 evaluation license
155741: 13/08/25: Synthesis and mapping of ALU
155865: 13/10/08: Granularity of components for FPGA synthesis?
155869: 13/10/08: Re: Granularity of components for FPGA synthesis?
156416: 14/04/02: Any good reference works on serial buses?
Chu Ng:
456: 94/11/23: Converts Fortran or C to VHDL
"Chu, Fred":
29620: 01/03/01: Re: Soldering and Unsoldering PQFP by hand ...
Chua Kah Hean:
36139: 01/10/30: BRAM usage reduction in FIFO design: First Scenario
36140: 01/10/30: Second Scenario: BRAM usage reduction in FIFO design
36172: 01/10/31: Re: BRAM usage reduction in FIFO design: First Scenario
36173: 01/10/31: Re: Second Scenario: BRAM usage reduction in FIFO design
36243: 01/11/03: Re: BRAM usage reduction in FIFO design: First Scenario
36540: 01/11/11: Re: Hex numbers in VHDL
37181: 01/12/03: Re: 128-bit scrambling and CRC computations
37219: 01/12/03: Re: 128-bit scrambling and CRC computations
37251: 01/12/04: Re: Crossing a clock domain
37432: 01/12/10: Re: Translating....
Chuang Hsien-Ho:
573: 95/01/09: Bhat's work
574: 95/01/09: Motorola FPGA
1021: 95/04/17: BLIF to XNF translator
1421: 95/06/20: Find One Paper of D.F.Wong
1436: 95/06/22: Inter-Chip Delay vs. CLB Delay
2591: 96/01/09: Emulation for a wireless chip
2628: 96/01/15: Re: Emulation for a wireless chip
Chuck:
40981: 02/03/19: virtex 2 orcad symbols?
Chuck Benz:
58753: 03/07/31: free tool (PERL script) for exploring gate netlists (ALTERA EQN format for now)
Chuck Bodgers:
85187: 05/06/06: Re: Clock doubler to double an input 13.5 Mhz
85204: 05/06/06: Re: Clock doubler to double an input 13.5 Mhz
Chuck Carlson:
20058: 00/01/25: xilinx foundation: map exceptions
20171: 00/01/29: Can Foundation import Viewlogic?
21728: 00/03/30: Foundation 2.1 Macro HIZ outputs
21871: 00/04/04: Clocks and BUFGP
Chuck Corley:
1: 94/07/27: Re: This (new) froup
865: 95/03/16: Re: meeting others through personal ads (advertisement)
1176: 95/05/11: Re: Overheating (was Re: Compression algo's for FPGA's)
Chuck Dillon:
85799: 05/06/16: Re: Idea exploration - Image stabilization by means of software.
Chuck F.:
93540: 05/12/23: Re: RTL for Z8000 series CPU?
93559: 05/12/24: Re: RTL for Z8000 series CPU?
Chuck Gales:
64232: 03/12/21: Spartan II Block Ram
64243: 03/12/22: Re: Spartan II Block Ram
64255: 03/12/22: Re: Spartan II Block Ram
64256: 03/12/22: Re: Spartan II Block Ram
64261: 03/12/23: Re: Spartan II Block Ram
Chuck Gollnick x196:
946: 95/03/31: NeoCad/Xilinx for AT+T ORCA users
1495: 95/06/30: Xilinx PCI Macros??
1579: 95/07/20: "Circuit Loops" in NeoCad??
1608: 95/07/27: Re: Actel Place and Route response
Chuck Harris:
77652: 05/01/13: Re: Exportability of EDA industry from North America?
77661: 05/01/13: Re: Exportability of EDA industry from North America?
77759: 05/01/16: Re: Exportability of EDA industry from North America?
77761: 05/01/16: Re: Exportability of EDA industry from North America?
77768: 05/01/17: Re: Exportability of EDA industry from North America?
77785: 05/01/17: Re: Exportability of EDA industry from North America?
77818: 05/01/17: Re: Exportability of EDA industry from North America?
77850: 05/01/18: Re: Exportability of EDA industry from North America?
77852: 05/01/18: Re: Exportability of EDA industry from North America?
77859: 05/01/18: Re: Exportability of EDA industry from North America?
77860: 05/01/18: Re: Exportability of EDA industry from North America?
77861: 05/01/18: Re: Exportability of EDA industry from North America?
131308: 08/04/18: Re: Survey: FPGA PCB layout
131416: 08/04/21: Re: Survey: FPGA PCB layout
131645: 08/04/27: Re: Survey: FPGA PCB layout
Chuck Levin:
62748: 03/11/06: Re: latch and shift 15 bits.
63445: 03/11/21: Re: PCI interface with attached PLD
63466: 03/11/21: Re: PCI interface with attached PLD
63470: 03/11/21: Re: PCI interface with attached PLD
107096: 06/08/24: QuickLogic
Chuck McGinley:
9: 94/07/28: Re: Learning about FPGAs
Chuck McManis:
69620: 04/05/16: Re: Video Blob Analysis on FPGAs
69632: 04/05/16: Phase relationship management
69635: 04/05/17: Re: is it possible to design usb only with fpga?
69638: 04/05/17: std_logic_vector vs unsigned
69640: 04/05/17: Re: Which board to buy? Status of open source tools?
69677: 04/05/18: Re: std_logic_vector vs unsigned
69678: 04/05/18: Re: Video Blob Analysis on FPGAs
69679: 04/05/18: Re: Phase relationship management
69728: 04/05/19: Re: How to select an FPGA size (beginner)
69789: 04/05/20: Re: How to select an FPGA size (beginner)
69864: 04/05/22: More fun with VHDL
69871: 04/05/23: Altium FPGA board
69892: 04/05/23: Re: More fun with VHDL
69893: 04/05/23: Re: Altium FPGA board
69975: 04/05/26: Re: Altium FPGA board
70031: 04/05/28: Re: Altium FPGA board
Chuck Morrill:
5095: 97/01/22: Re: What Does ASIC Stand For?
Chuck Parsons:
8309: 97/12/07: Re: what is metastability time of a flip_flop
8310: 97/12/07: Re: what is metastability time of a flip_flop
8383: 97/12/11: Re: what is metastability time of a flip_flop
8403: 97/12/12: Re: what is metastability time of a flip_flop
8404: 97/12/12: Re: what is metastability time of a flip_flop
8405: 97/12/12: Re: what is metastability time of a flip_flop
8415: 97/12/13: Re: what is metastability time of a flip_flop
8416: 97/12/13: Re: what is metastability time of a flip_flop
8423: 97/12/13: Re: what is metastability time of a flip_flop
8424: 97/12/13: Re: what is metastability time of a flip_flop
8347: 97/12/09: Re: what is metastability time of a flip_flop
8371: 97/12/10: Re: what is metastability time of a flip_flop
8370: 97/12/10: Re: what is metastability time of a flip_flop
Chuck Shinn:
10334: 98/05/12: Re: Looking for Ultra 2 SCSI Synthesizable Core
Chuck Simmons:
54455: 03/04/11: Re: Using DP RAM for message passing
Chuck Woodring:
27718: 00/12/05: ORCAD EXPRESS / Synplicity (feeling stuck)
28597: 01/01/18: spartanII chip availability
28867: 01/01/26: Re: Advice on FPGA board.
28939: 01/01/30: Re: Advice on FPGA board.
30685: 01/04/23: timing.dly file in Xilinx
31585: 01/05/31: fct logic and xc4000xl inputs
31606: 01/05/31: Re: fct logic and xc4000xl inputs
31902: 01/06/08: system clock speed
38086: 02/01/04: multiplexing a clock
42182: 02/04/18: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
chudar:
97514: 06/02/23: need byteblaster II source code
chuk:
64849: 04/01/15: Generating clock delays
65035: 04/01/19: simulating
65091: 04/01/20: ERROR:HDLParsers:164
65529: 04/02/01: Clocking an FPGA??
66105: 04/02/12: clock
67332: 04/03/10: A hardware question?
70631: 04/06/22: VIRTEX v Spartan 3
70769: 04/06/27: clk inputs, are they all same?
71377: 04/07/16: twos to ones and ones to twos compliments
Chumnarn P.:
131266: 08/04/17: Re: Xilinx and Modelsim?
131271: 08/04/17: Re: Simulation tools for Xilinx ISE
Chung Yew Liang:
19076: 99/11/28: Great way to get a new hardware and its free
Chy Talles:
43793: 02/06/03: Instantiating Coregen Dual-port RAM in Verilog
Chyr-Pyng Su:
6034: 97/04/07: FFT in FPGA
ciappalastringa:
85713: 05/06/14: xilinx ise 7.1i linux and "can't access this folder path is too long"
88952: 05/09/01: Mentor FPGA Advantage, a simple question
89074: 05/09/05: Re: Mentor FPGA Advantage, a simple question
Ciaran McGloin:
33208: 01/07/19: Re: DDS Xilinx Core
cid:
135861: 08/10/18: Entry Level FPGA Jobs and Outsourcing
135895: 08/10/20: Re: Entry Level FPGA Jobs and Outsourcing
136666: 08/11/29: How to evaluate program efficiency/functionality
136672: 08/11/30: Re: How to evaluate program efficiency/functionality
Cindy:
40416: 02/03/06: Virtex-II : Temperature Sensing Diodes
40419: 02/03/06: Re: MXE 5.5e speed
Cindy Harris:
12860: 98/11/02: Concept or Viewlogic viewer?
cippalippa:
112866: 06/11/30: Opencores DDR SDRAM controller
112953: 06/12/02: Re: Opencores DDR SDRAM controller
112971: 06/12/03: Re: Opencores DDR SDRAM controller
113263: 06/12/09: Re: Opencores DDR SDRAM controller
113349: 06/12/11: Re: Opencores DDR SDRAM controller
113495: 06/12/14: Re: Opencores DDR SDRAM controller
<circaeng@hotmail.com>:
100768: 06/04/17: Re: Where is the xilinx online store gone?
Cisa:
47614: 02/09/30: Configuration:Startup
47616: 02/09/30: Search help about architecture of STARTUP?
47635: 02/10/01: Re: Search help about architecture of STARTUP?
47673: 02/10/01: Re: Configuration:Startup
47733: 02/10/02: Re: Configuration:Startup
47782: 02/10/03: Re: Configuration:Startup
47837: 02/10/04: Re: Configuration:Startup
51517: 03/01/15: How can I use DCM to 1/24 freq-division?
CISCO SYSTEMS:
5816: 97/03/18: Cisco's SIBU is looking for ASIC and Systems Engineers
5855: 97/03/20: Cisco's SIBU is looking for ASIC and Systems Engineers
5911: 97/03/25: Cisco's SIBU is looking for ASIC and Systems Engineers
5962: 97/03/31: Cisco's SIBU is looking for ASIC and Systems Engineers
5989: 97/04/03: Cisco's SIBU is looking for ASIC and Systems Engineers
6043: 97/04/07: Cisco's SIBU is looking for ASIC and Systems Engineers
6071: 97/04/09: Cisco's SIBU is looking for ASIC and Systems Engineers
6091: 97/04/11: Cisco's SIBU is looking for ASIC and Systems Engineers
6130: 97/04/14: Cisco's SIBU is looking for ASIC and Systems Engineers
cisivakumar:
90698: 05/10/19: Implementation of 1024 point FFT in Actel FPGA
<cjfocf@mnet.com>:
23977: 00/07/19: Re: I found it for you 6334
<cjouwr@zwallet.com>:
<cjt101@yahoo.com>:
131879: 08/05/06: Looking for FPGA/CPLD skills to develop prototype
cka:
72614: 04/08/26: PP1000SetupDMAChannel( ) function in celoxica RC1000
<cking@accutron.ie>:
709: 95/02/13: Real-time fractal gen in h/w
761: 95/02/24: Fractal Generation Summary (longish)
ckingknowledge:
106611: 06/08/16: Re: Webpack ISE simulator error
<ckpun1978@gmail.com>:
87667: 05/07/27: How to pass parameters to do file in commandline when running vsim?
87701: 05/07/28: Re: How to pass parameters to do file in commandline when running vsim?
Cla:
121878: 07/07/14: Which embedded O/S for a 32-bit RISC microcontroller?
Claas Richter:
23079: 00/06/13: Harddisk <--> FPGA <--> PC
23443: 00/06/25: IDE-Interface for FPGA
Claire:
136182: 08/11/05: Learning programming an FPGAs
Claire Murphy:
119738: 07/05/25: ML505 : beginners problems
119886: 07/05/29: Re: ML505 : beginners problems
119893: 07/05/29: Re: ML505 : beginners problems
119958: 07/05/30: Re: ML505 : beginners problems
claire pistre:
85638: 05/06/13: Pb with an IPCore Dual Port Memory
clairemurphs223hotmail.com:
119965: 07/05/30: Re: ML505 : beginners problems
claps:
69407: 04/05/10: Re: SAA7111 YUV
Clarence Brown (Cla):
2327: 95/11/20: Device Programmer Selection
Clark Pope:
32101: 01/06/13: Re: DQPSK encoding table.
32492: 01/06/27: Modelsim waveform
32739: 01/07/06: Re: Core Generator IQ NCO
33344: 01/07/23: Re: Silo-3 Demo Program Crashes onDell 4100
38815: 02/01/25: Re: Coregen Half-Band FIR filter implemenation does not work
39796: 02/02/19: Re: Coregen Half-Band FIR filter implemenation does not work
39797: 02/02/19: Virtex II multiplier pipeline
44184: 02/06/13: Multiple constraints, same net?
64952: 04/01/16: Re: Avnet Virtex-II Pro Development Kit Help
66217: 04/02/14: DCM Jitter?
68279: 04/03/31: Xilinx XCF16 or XCF08 serial proms needed.
70185: 04/06/08: IR_CAPTURE fail on Virtex2
70229: 04/06/09: Re: IR_CAPTURE fail on Virtex2
70489: 04/06/17: Re: compressing Xilinx bitstreams
71398: 04/07/16: Re: ChipScope Pro : Stimulation
134605: 08/08/20: Re: need efficient multichannel DDC on V4
134645: 08/08/23: Scripting xsvf generation?
Claude Klimos:
4741: 96/12/10: Poll: Please Take 2 Minutes to Answer...
Claude Sylvain:
98495: 06/03/10: Plateform FLASH PROM configuration using a Microblaze.
98509: 06/03/11: Re: Plateform FLASH PROM configuration using a Microblaze.
98511: 06/03/11: Re: Plateform FLASH PROM configuration using a Microblaze.
98525: 06/03/12: Re: Plateform FLASH PROM configuration using a Microblaze.
98527: 06/03/12: Re: Plateform FLASH PROM configuration using a Microblaze.
98528: 06/03/12: Re: Plateform FLASH PROM configuration using a Microblaze.
98542: 06/03/12: Re: Plateform FLASH PROM configuration using a Microblaze.
98617: 06/03/13: Re: Plateform FLASH PROM configuration using a Microblaze.
153625: 12/04/05: Re: LX9 and internal reset - Do I need one?
153707: 12/04/28: Re: Platform Cable USB II in Windows 7 not Found (ISE 13.4)
Claudio:
13479: 98/12/04: Xilinx F1.5b 64k segnent linitation
39933: 02/02/22: Re: Linux tools
65214: 04/01/22: Xilinx old development tool
90370: 05/10/11: LUT 4:1 VS FF
90390: 05/10/11: Re: LUT 4:1 VS FF
90401: 05/10/11: Re: LUT 4:1 VS FF
90435: 05/10/12: Re: LUT 4:1 VS FF
109404: 06/09/26: Re: QuartusII: how to find out all the instances of a VHDL module in a design?
109537: 06/09/28: Re: QuartusII: how to find out all the instances of a VHDL module in a design?
109539: 06/09/28: How to oerform a functional simulation of a QuartusII design with Modelsim?
CLAUDIO DROGUETT:
17984: 99/09/21: Gane dinero ya !!
Claus =?ISO-8859-15?Q?Ladekj=E6r?= Wilson:
Claus Ritter:
38087: 02/01/04: Configuration Times of FPGAs
Clay:
113503: 06/12/14: Re: IQ multiplier
Clay Gloster, Jr.:
6703: 97/06/17: Java and Giga Ops FPGA Boards
Clay S. Turner:
22398: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
59275: 03/08/13: Re: FPGA/DSP Expert - business partner for innovative FFT
62544: 03/10/31: Re: Shannon Entropy for Black Holes
80248: 05/03/02: Re: [Promo] Danville releases SHARC kit for $199
85952: 05/06/18: Re: Idea exploration - Image stabilization by means of software.
87947: 05/08/04: Re: System Engineering in the R/D World
<clay@ewbridge.com>:
20208: 00/01/31: AMD SCxxx + Xilinx XCSxx
20207: 00/01/31: AMD SCxxx + Xilinx XCSxx
Claytong_nz:
144276: 09/11/24: Help needed with Quicklogic QL8X12B-1PL68M tools and programmer
144293: 09/11/25: Re: Help needed with Quicklogic QL8X12B-1PL68M tools and programmer
144297: 09/11/25: Re: Help needed with Quicklogic QL8X12B-1PL68M tools and programmer
144347: 09/11/29: Re: Help needed with Quicklogic QL8X12B-1PL68M tools and programmer
<clean_living@my-deja.com>:
24263: 00/08/02: foundation 2.1i problems
<clemenr@wmin.ac.uk>:
92598: 05/12/01: Curious about FPGAs
92625: 05/12/02: Re: Curious about FPGAs
Clemens:
128878: 08/02/08: Timing Constraint not met
128885: 08/02/08: Question to VHDL code fragment
128937: 08/02/11: Critical Path analysis
131980: 08/05/09: Xilinx Platform USB Cable II
131982: 08/05/09: Re: Xilinx Platform USB Cable II
131986: 08/05/09: Re: Xilinx Platform USB Cable II
132234: 08/05/19: 2-bit Pseudo Random Number Generator
132238: 08/05/19: Re: 2-bit Pseudo Random Number Generator
133706: 08/07/10: Chipscope data port limitation to 256 bits
133711: 08/07/10: Re: Chipscope data port limitation to 256 bits
Clemens Blank:
129354: 08/02/21: Interview questions
129356: 08/02/21: Re: Interview questions
clemens fischer:
93342: 05/12/20: Re: software application on the virtex-ii pro
Clemens Hagen:
82691: 05/04/16: FPGA Design Introduction
82987: 05/04/21: VHDL or Verilog
Clemens Hermann:
82327: 05/04/11: Altera and VHDL library
82459: 05/04/13: Re: Altera and VHDL library
82963: 05/04/20: AHDL and quartus II simulation
Clemens Pichler:
133748: 08/07/12: Why cant XST sythesis this piece of code
Clemens Ragger:
78978: 05/02/10: Re: C program to big for microblaze?
78981: 05/02/10: C program to big for microblaze?
79035: 05/02/11: Re: C program to big for microblaze?
Clemens Reinrich:
79264: 05/02/16: FPGA programming newbie
Clement:
122865: 07/08/08: High Speed ADC
clement:
9782: 98/04/04: Waveform To Verilog RTL Synthesis
<clementw@msn.com>:
6044: 97/04/07: WaveScript (TM) Compiler for FSM synthesis
clevin1234:
33961: 01/08/09: Re: Question on use of FPGA in a special Data Aquisition system
33962: 01/08/09: Re: PCI Postcode Display
33966: 01/08/09: Re: PCI Postcode Display
34200: 01/08/16: Re: Slowing PCI for FPGA
34936: 01/09/14: Re: configuration latency for PCI bridge in FPGA
36509: 01/11/10: Re: 64-bit PCI core for Lattice CPLD?
38065: 02/01/03: Re: PCI Solution: LogiCore?
41721: 02/04/05: Re: 32 bit accumulator/comparator PWM?
41730: 02/04/06: Re: 32 bit accumulator/comparator PWM?
<clidsxxw@entireweb.com>:
<client.services@esbisc.easymax.com>:
Cliff Bradshaw:
7110: 97/08/01: Programming the Xilinx 4036XL :)
Cliff Hirsch:
8961: 98/02/09: Semiconductor Times semiconductor startups web site
Cliff Schuring:
128487: 08/01/28: Re: effect of xray on fpga electronic circuits
<cliffc@sunburst-design.com>:
91683: 05/11/10: Re: Best Async FIFO Implementation
Clifford Heath:
105456: 06/07/24: ByteBlasterMV?
105939: 06/08/03: Re: Where are Huffman encoding applications?
105980: 06/08/04: Re: Where are Huffman encoding applications?
Clifton T. Sharp Jr.:
11656: 98/08/29: Re: New Evolutionary Electronics Book
12914: 98/11/04: Re: New free FPGA CPU
<climber.tim@gmail.com>:
130145: 08/03/17: Designing CPU
130872: 08/04/03: Downloading some data from flash memory thru JTAG.
131905: 08/05/06: FPGA dev kit with 4-8 Cyclones or Spartans
131911: 08/05/06: Re: FPGA dev kit with 4-8 Cyclones or Spartans
Clint Olsen:
5470: 97/02/18: Re: Mealy/Moore state machines
9258: 98/03/05: Re: The case for free operating systems and EDA
9327: 98/03/06: Re: The case for free operating systems and EDA
9343: 98/03/07: Re: The case for free operating systems and EDA
Clint Sharp:
82440: 05/04/12: Re: Reverse engineering masked ROMs, PLAs
Clive Bittlestone:
1131: 95/05/03: Re: Lattice EPLDs
1147: 95/05/04: Re: Lattice EPLDs
1253: 95/05/22: CUPL manual/info
CloneNumber66:
89664: 05/09/21: Altera Programming Cables and EPCS16/64
closset:
22837: 00/05/26: Abel conversion to VHDL
clown:
9396: 98/03/09: Re: fghk
clsan:
60211: 03/09/08: mouse to Nios Development kit
60296: 03/09/10: Re: mouse to Nios Development kit
60636: 03/09/18: Re: mouse to Nios Development kit
60676: 03/09/19: Re: mouse to Nios Development kit
clvrmnky:
152895: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
Clyde R. Shappee:
17738: 99/08/28: Re: VHDL to debounce & latch input from a switch
20333: 00/02/05: Re: Conditional compilation in VHDL?
20459: 00/02/11: Re: Altera vs Cypress?
29293: 01/02/13: Re: double precision floating point arithmetic
33900: 01/08/08: Re: Looking for a Particular Used Book
36512: 01/11/10: Re: VHDL testbench question
40884: 02/03/17: Re: just bought...
44928: 02/07/06: Re: Lessons Learned -- Need your inputs
47378: 02/09/24: Unpredictable Place and Route
47453: 02/09/25: Re: Unpredictable Place and Route
47496: 02/09/26: Re: Unpredictable Place and Route
47538: 02/09/27: Re: Unpredictable Place and Route
47980: 02/10/08: Simple Counters in Xilinx Spartan II
47984: 02/10/08: Re: Simple Counters in Xilinx Spartan II
48317: 02/10/15: Re: How to keep components from being optimized out of VHDL
49555: 02/11/14: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
50317: 02/12/08: Pierce Crystal Oscillator in Cypress 37128 CPLD
50318: 02/12/08: Re: Clocking in a Spartan IIE
50451: 02/12/10: Re: Pierce Crystal Oscillator in Cypress 37128 CPLD
51195: 03/01/06: Constraining a purely combinatorial logic path
51204: 03/01/06: Re: Constraining a purely combinatorial logic path
51212: 03/01/06: Re: Constraining a purely combinatorial logic path
51213: 03/01/06: Re: Constraining a purely combinatorial logic path
51230: 03/01/07: Re: Constraining a purely combinatorial logic path
51454: 03/01/13: Re: How to coerce a list of discrete signals to an array in VHDL
51701: 03/01/19: Re: XST vs Synplify observations
52135: 03/02/02: Re: FSM and XST
52817: 03/02/23: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
52864: 03/02/24: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
52916: 03/02/25: Re: Should I choose Xilink or Altera for a small project
53251: 03/03/07: Re: PCB board design software vs outsourcing?
53414: 03/03/12: Re: RESET --- Synchronous Vs Asynchronous
53481: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
58033: 03/07/12: Re: Quartus warning in NUMERIC_STD.vhd
58047: 03/07/13: Re: Quartus warning in NUMERIC_STD.vhd
60390: 03/09/11: Re: Webpack Vs. ISE
60473: 03/09/14: Re: Webpack Vs. ISE
60613: 03/09/17: Re: Webpack Vs. ISE
Clyde R. Visser:
32924: 01/07/12: Xilinx makefile under RedHat
Clyde Torres:
75298: 04/11/02: Re: "frying" FPGAs
Clyder:
142373: 09/08/07: Re: Peter Alfke
CM:
129175: 08/02/17: Re: PC configuration for fastest compiles (synthesis, place and
Cm Heong:
11557: 98/08/24: Paul Donachs Thesis
11594: 98/08/26: Re: Paul Donachs Thesis
12131: 98/10/01: Re: Where can I get comp.arch.fpga newsarticle archive?
<cmajdi@gmail.com>:
159867: 17/04/12: how to convert analog signal cccam video to digital using systemc
CMJsemi:
4872: 96/12/23: XLNX M-1
cmoore:
126459: 07/11/23: Re: PCI Mezzanine Card with Xilinx Virtex-II
CMOS:
88219: 05/08/12: high speed image capture
88273: 05/08/13: Re: high speed image capture
88277: 05/08/14: Avnet spartan3E development board
88563: 05/08/22: digilent boards
88618: 05/08/23: xilinx or digilent
88620: 05/08/23: Re: xilinx or digilent
88622: 05/08/23: Re: xilinx or digilent
88675: 05/08/24: Re: xilinx or digilent
88676: 05/08/24: TTL, CMOS and spartan
88797: 05/08/28: digilent spartan 3 kit example project
88840: 05/08/29: 8087 co-processor
89151: 05/09/06: spartan 3 starter kit auto configuration at power up
89520: 05/09/16: Digilent USB2 module in B1 expansion slot
89628: 05/09/20: digilent USB2 module
89648: 05/09/21: Re: digilent USB2 module
89649: 05/09/21: Re: digilent USB2 module
89783: 05/09/26: vhdl state maching problem
89815: 05/09/27: Re: vhdl state maching problem
90045: 05/10/03: vhdl question
90055: 05/10/03: Re: vhdl question
90120: 05/10/05: Re: vhdl question
90140: 05/10/05: Re: vhdl question
90561: 05/10/16: chipscope pro problem
90581: 05/10/17: using i2c core
90622: 05/10/17: Re: using i2c core
90691: 05/10/18: Re: using i2c core
90693: 05/10/18: Re: using i2c core
90710: 05/10/19: Re: using i2c core
90740: 05/10/19: Re: using i2c core
90786: 05/10/20: Re: using i2c core
90830: 05/10/21: Re: using i2c core
90900: 05/10/24: Re: using i2c core
91790: 05/11/13: i2c slave does not acknowlege
91793: 05/11/13: PC networking through modems
91836: 05/11/14: Re: i2c slave does not acknowlege
92210: 05/11/23: CMOS sensor stops aquring images..
96085: 06/01/30: starting MacroBlaze development
96472: 06/02/03: core generator
96475: 06/02/04: Re: core generator
96481: 06/02/04: advanced vhdl lerning
97098: 06/02/16: VHDL or verilog
97130: 06/02/16: Re: VHDL or verilog
101528: 06/05/02: mux problem
101599: 06/05/03: ports of multidimentional arrays in verilog.
103343: 06/05/31: combining state machines.
110465: 06/10/16: buying xilinx spartan 3E kit just for EDK ?
110707: 06/10/20: Re: buying xilinx spartan 3E kit just for EDK ?
113851: 06/12/25: better ways for debugging?
114103: 07/01/04: Re: better ways for debugging?
114196: 07/01/07: how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?
115079: 07/01/30: how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations
115260: 07/02/05: or1k on spartan 3, 400K gate version
115288: 07/02/05: Re: or1k on spartan 3, 400K gate version
115439: 07/02/11: substracting a whole array of values at once
115442: 07/02/11: Re: substracting a whole array of values at once
115527: 07/02/13: Re: substracting a whole array of values at once
115529: 07/02/13: Re: substracting a whole array of values at once
115582: 07/02/14: Re: substracting a whole array of values at once
116216: 07/03/05: is bluespec pupolar in industry?
116893: 07/03/20: FF's are inffered instead of distributed RAM
116973: 07/03/21: how to shift mutiple bytes in an array in one clock cycle?
117152: 07/03/24: shift register with distributed ram
117153: 07/03/24: shift register with distributed ram
117618: 07/04/04: having a state machine in a datapath element a bad design practice?
117766: 07/04/10: is there any opensource alternatives to platformstudio and microblaze development?
117776: 07/04/10: Re: is there any opensource alternatives to platformstudio and microblaze development?
125221: 07/10/18: systemc thread processes are called with the same thread in windows
140623: 09/05/20: please recommend a soft processor for small image processing tasks
140642: 09/05/20: Re: please recommend a soft processor for small image processing
140651: 09/05/21: Re: please recommend a soft processor for small image processing
140676: 09/05/21: Re: please recommend a soft processor for small image processing
140679: 09/05/21: Re: please recommend a soft processor for small image processing
140885: 09/05/28: simulating a program inside a soft core with systemc
141571: 09/06/28: usefulness of Virtex-II devices
141626: 09/07/01: Re: usefulness of Virtex-II devices
cms:
118922: 07/05/07: Re: FF setup and hold time.
124783: 07/10/04: JPEG-LS hardware implementation
124784: 07/10/04: Re: Companies that Manufacture Multi-FPGA Hardware
124786: 07/10/04: Re: JPEG-LS hardware implementation
124841: 07/10/07: Re: JPEG-LS hardware implementation
124845: 07/10/07: Re: JPEG-LS hardware implementation
124897: 07/10/10: Re: Quartus-II 7.2 web-edition Systemverilog improvements
126778: 07/12/02: Re: What option can change the path sign "\" in Quartus ?
126779: 07/12/02: Re: What option can change the path sign "\" in Quartus ?
126781: 07/12/02: Re: lossless compression in hardware: what to do in case of
126782: 07/12/02: Re: Interfacing Cyclone III to 3.3v LVDS devices
136276: 08/11/09: Re: Synplicity/Synplify and Systemverilog support?
136450: 08/11/17: Re: Synplicity/Synplify and Systemverilog support?
136814: 08/12/06: Re: SystemVerilog OOP and OVM Summary
cmsmith1:
18582: 99/11/01: Looking for a few more discontinued Xilinx chips.
cn99:
38386: 02/01/13: Re: Homebrew computers using FPGA?
Cnguyen:
55171: 03/04/29: Re: visualizing a Counter on a FPGA
cnspy:
34767: 01/09/07: Re: Wanted: ISA bus implementation for Xilinx
34891: 01/09/13: Re: Counter problem
34892: 01/09/13: convert
34894: 01/09/13: delay
Code Mangler:
21139: 00/03/07: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
Code Warriors:
CODE_IS_BAD:
82991: 05/04/21: Simulation in modelsim.... Multiple Drivers.......
82993: 05/04/21: Re: VHDL or Verilog
83011: 05/04/21: Re: Simulation in modelsim.... Multiple Drivers.......
83043: 05/04/21: Timing Reports Xilinx.....Max. freq of operation?
83051: 05/04/22: Re: Simulation in modelsim.... Multiple Drivers.......
83052: 05/04/22: Re: sharing a common resource... potential problems...
83061: 05/04/22: Re: Timing Reports Xilinx.....Max. freq of operation?
83563: 05/05/03: Max freq. of operation in FPGA?
83614: 05/05/03: Re: Max freq. of operation in FPGA?
83615: 05/05/03: Re: VHDL help with adding modules
83876: 05/05/09: 8051 IP core
84072: 05/05/11: Re: 8051 IP core
84287: 05/05/16: Re: 8051 IP core
84318: 05/05/17: Re: 8051 IP core
84323: 05/05/17: Re: 8051 IP core
84434: 05/05/18: How many logic cells are there in one slice
84437: 05/05/18: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84443: 05/05/19: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84781: 05/05/26: 2:1 mux in one LUT
85352: 05/06/08: Connecting two INOUT ports
85688: 05/06/13: Viewing internal signal in Modelsim (post P&R)
89069: 05/09/04: Reading internal signals through a testbench.
CODE_IS_BUG:
82645: 05/04/15: sharing a common resource... potential problems...
codejk:
89770: 05/09/26: External dpram similar to blockram of Xilinx device
90063: 05/10/04: Floating point multiplication on Spartan3 device
90107: 05/10/04: Re: Floating point multiplication on Spartan3 device
90164: 05/10/05: Re: Floating point multiplication on Spartan3 device
90166: 05/10/05: Re: Floating point multiplication on Spartan3 device
90325: 05/10/10: Questions on DCI split termination of spartan-3
CodeLogic:
9781: 98/04/05: "Offshore" design services
9901: 98/04/12: Design "Outsource" Offshore ?
CODES-ISSS:
Cody:
71333: 04/07/15: How to deal with unrouted nets in a partial reconfigurable assembly?
71523: 04/07/21: Re: Area constraint on a sub-module
coffee_bender:
145904: 10/02/27: Re: What is the most area efficient CRC method
Cog_Rad_link:
97770: 06/02/27: NGCBUILD .. MDT error on Virtex 4
ColdStart:
148623: 10/08/09: Signal value clears for no reason [VHDL, ISE 10.1]
Colin:
70815: 04/06/29: Programming Nios Ethernet Development Kit
70841: 04/06/29: Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"
71101: 04/07/07: Nios - Ethernet Frame Format
71369: 04/07/15: Re: Nios - Ethernet Frame Format
71370: 04/07/15: Network Communication Using Nios Daughter Board
139504: 09/04/01: Virtex-5 DDRII SRAM Calibration Issues
colin:
72379: 04/08/17: embedded PCI
72413: 04/08/18: Re: embedded PCI
72481: 04/08/20: Re: embedded PCI
72511: 04/08/21: Re: embedded PCI
72820: 04/09/03: spartan3 pci above 33MHz
72847: 04/09/05: Re: spartan3 pci above 33MHz
74520: 04/10/13: spartan 3 on 4 layers
74536: 04/10/13: 1.2V
76470: 04/12/03: making an fpga hot
86832: 05/07/07: Re: Spartan3 pci above 33MHz
87367: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
91722: 05/11/11: fastest possible USB
94490: 06/01/12: boundary scan of altera epm570F
94530: 06/01/13: Re: boundary scan of altera epm570F
95573: 06/01/24: rocket IOs with web pack
96340: 06/02/02: Re: BGA central ground matrix
96400: 06/02/03: Re: BGA central ground matrix
96718: 06/02/09: Re: cheap USB analyzer based on FPGA
97085: 06/02/16: pci express ac coupling
100560: 06/04/12: Re: Testing sample Aurora design on ML321 board
101074: 06/04/25: Re: How to avoid lossing channel bonding when using Rocket IO?
101254: 06/04/28: Re: Assigning MGT's in sample Aurora Design
101268: 06/04/28: Re: HSTL classes and termination schemes
101272: 06/04/28: Re: HSTL classes and termination schemes
101507: 06/05/02: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
103279: 06/05/30: Re: PCI Header types !!!
103714: 06/06/09: Re: Good free or paid merge software that edits two similar files?
104582: 06/06/30: rocketIO simulation
104843: 06/07/07: detecting gnd
108772: 06/09/16: coolrunner II jtag
110043: 06/10/10: longest webcase record
110105: 06/10/11: Re: longest webcase record
110137: 06/10/11: Re: longest webcase record -- perhaps it is explained?
110161: 06/10/11: Re: longest webcase record -- perhaps it is explained?
110195: 06/10/12: Re: longest webcase record -- understandably so
110205: 06/10/12: Re: longest webcase record -- understandably so
110274: 06/10/13: Re: longest webcase record -- understandably so
110458: 06/10/16: Re: longest webcase record -- understandably so
110481: 06/10/16: Re: longest webcase record -- understandably so
110511: 06/10/17: Re: longest webcase record
112147: 06/11/17: Re: use boundary scan in spartan-3
112170: 06/11/17: Re: use boundary scan in spartan-3
113357: 06/12/11: config prom power
113997: 07/01/02: lead free bga pads
114072: 07/01/04: Re: lead free bga pads
116221: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
118565: 07/04/30: Re: TigerSHARC TS201 to PLX 9656
119879: 07/05/29: Re: Has anyone used Sundance Boards?.
120826: 07/06/18: Re: Xilinx FPGA Pinout spreadsheets
122278: 07/07/25: pci express pinout
122296: 07/07/25: Re: pci express pinout
122443: 07/07/27: Re: Can multiple Ferrite Beads be used to connect ...?
122515: 07/07/30: Re: Can multiple Ferrite Beads be used to connect ...?
125132: 07/10/16: ethernet phy or mac
125284: 07/10/19: Re: ethernet phy or mac
125414: 07/10/25: xilinx spi flash programming
125427: 07/10/25: Re: xilinx spi flash programming
125609: 07/10/30: Re: kicad or orcad virtex5 symbol
125702: 07/11/01: Re: 2 FPGAs /w programming FLASH in one JTAG chain
126282: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126436: 07/11/22: Re: PCI Mezzanine Card with Xilinx Virtex-II
127396: 07/12/20: Re: Routing Vccint on four-layer PCB
130774: 08/04/01: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
133695: 08/07/10: Re: JTAG IR length detection
135734: 08/10/14: Re: writing files to micro-SD with spartan 3e
136648: 08/11/27: Re: FMC/VITA 57
136896: 08/12/11: Re: Sampling a clock
137813: 09/01/30: byteblaster cloning
138323: 09/02/16: virtex 5 decoupling
138504: 09/02/25: virtex 5 columns
143486: 09/10/13: A simple rs232 CLI
143561: 09/10/16: Re: A simple rs232 CLI
145002: 10/01/19: Re: Easy PC software tool - Bad experience
146802: 10/03/29: upgrading to ISE 11.x
147531: 10/04/30: Re: ISE tools not detecting IOSTANDARD conflicts within bank
148377: 10/07/16: Re: help regarding daisy chained fpgas
148432: 10/07/22: Re: Using std_ulogic at synthesis level
149391: 10/10/21: Re: IO pin question
149589: 10/11/08: Re: PCI Parallel port detection in XILINX
149897: 10/12/01: Re: What should I use for highspeed/low latency communication beteen
149898: 10/12/01: Re: PCI Architecture Question for Data Acquisition Board
150828: 11/02/15: Re: Xilinx USB programming cable.
151540: 11/04/18: Re: Oscilloscope recommendations Ghz range?
151543: 11/04/18: Re: Oscilloscope recommendations Ghz range?
151774: 11/05/17: Re: Best syntheses
151847: 11/05/24: Re: Fall Times and Pullup
152191: 11/07/18: Re: FPGA not getting programmed
154102: 12/08/08: spartan 6 ddr2 pinout
154108: 12/08/09: Re: spartan 6 ddr2 pinout
154264: 12/09/19: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
156444: 14/04/07: Re: Simulation deltas
156671: 14/06/02: Re: Zynq devices, boards and suppliers
156753: 14/06/18: Re: PLA? PAL? PLD? GAL?
158874: 16/05/13: Re: FPGA boards in egypt
159279: 16/09/21: Re: requirement for PC for VHDL design
159323: 16/10/06: xilinx aurora lane order
159330: 16/10/06: Re: xilinx aurora lane order
159864: 17/04/12: Re: FPGA as heater
159979: 17/05/04: Re: creating a seed on a FPGA.
Colin Anderson:
75708: 04/11/12: Basic DVI example?
Colin Bury:
40176: 02/03/01: Clock multiplier/ADPLL in PLD
Colin Carruthers:
4512: 96/11/07: Re: Info on FPGA Internal Architecture/ Programming
Colin Cook:
38031: 02/01/01: Re: Virtex-II FPGA Chips Availability
38066: 02/01/03: Re: PCI Solution: LogiCore?
colin cook:
18194: 99/10/06: will Xlilnx jtag cable work with as a replacement for Altara's BitBlaster
Colin F:
97427: 06/02/22: RC1000pp with XCV400
Colin Hall:
57465: 03/07/01: Suitable motherboard for Spartan-IIE PCI design
Colin Hankins:
101604: 06/05/03: How to create a fixed netlist IP core?
102254: 06/05/12: Synchronous Scrambler
102336: 06/05/15: Re: Synchronous Scrambler
103381: 06/05/31: Re: generating IP cores
103552: 06/06/05: Re: Jtag Programmer
108535: 06/09/12: Xilinx ISE 8.2 Problem
113896: 06/12/28: Re: ethernet checksum nightmare
114281: 07/01/10: Re: PCI-Express TLP example
114294: 07/01/10: Re: PCI-Express TLP example
115202: 07/02/02: Re: PCI Express user group
116643: 07/03/14: Re: PCI - Express
117268: 07/03/27: Re: PCI-Express drivers with Xilinx FPGA?
117843: 07/04/11: Re: Query in Parallel CRC(urgent)
120571: 07/06/10: Re: Affordable pcie card ?
122080: 07/07/18: Re: 8B/10B decoding after serial transmission problem?
126166: 07/11/15: Lattice Semi
127804: 08/01/08: True Dual Port RAM
127924: 08/01/10: Re: True Dual Port RAM
129253: 08/02/19: Re: Using Lattice ispLEVER with VHDL libraries
129301: 08/02/20: Re: Using Lattice ispLEVER with VHDL libraries
colin hankins:
59672: 03/08/25: Xilinx bit files
62843: 03/11/09: ISE 5.2 to 6.1
Colin Jackson:
59223: 03/08/12: Datasheet for National PAL20L10
59262: 03/08/13: Re: Datasheet for National PAL20L10
59341: 03/08/15: Re: comp.lang.vhdl
59353: 03/08/15: VHDL for FPGA VME Slave
59820: 03/08/28: Re: Datasheet for National PAL20L10
60505: 03/09/15: Re: USB transceiver for FPGA
60550: 03/09/16: Re: USB transceiver for FPGA
61210: 03/09/30: Re: USB Core (Japanese Version)
61289: 03/10/01: Re: USB Core (Japanese Version)
Colin Marquardt:
23700: 00/07/05: Re: VHDL code for LFSR
26861: 00/11/01: Re: help on a simple ALU
30903: 01/05/02: Re: VHDL coding question.
33905: 01/08/07: Re: Looking for a Particular Used Book
45512: 02/07/25: Re: Another way to simulate
47994: 02/10/09: Re: Simple Counters in Xilinx Spartan II
48052: 02/10/10: Re: Why can't Altera sw be as good as Xilinx's sw?
51811: 03/01/22: Re: Schematic design approach compared to VHDL entry approach
55129: 03/04/28: Re: Any experience (good or bad) with Northwest Logic PCI core?
55872: 03/05/22: Re: a (PC) workstation for FPGA development
56483: 03/06/06: Re: Xilinx Block RAM
87094: 05/07/15: Re: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
103946: 06/06/15: Re: How to get lowest price for a ModelSim license?
106812: 06/08/20: Re: Hardware book like "Code Complete"?
Colin O'Flynn:
36849: 01/11/21: PCMCIA interface and CPLD
36951: 01/11/27: Re: Simple Logic State Analyser
37001: 01/11/28: Re: Simple Logic State Analyser
39584: 02/02/13: Atmel CPLD chip design software?
41263: 02/03/23: Re: Electronic Parts Locator
41474: 02/03/29: Re: Homebuilt Altera-programmer totally dead...
41485: 02/03/29: Re: Homebuilt Altera-programmer totally dead...
Colin Paul de Gloucester:
158593: 16/01/11: Re: Programming waveshare core3s250e with Impact and ISE 14.1
Colin Paul Gloster:
48852: 02/10/25: Re: Verilog vs VHDL discussion on comp.arch.verilog group
48996: 02/10/29: Re: Xilinx ISE 4.2i Student edition on Windows XP
48998: 02/10/29: Re: Modelsim help
48999: 02/10/29: Re: Xilinx ISE 4.2i Student edition on Windows XP
52453: 03/02/10: Re: Synthesis Scripts
58796: 03/08/01: Re: VHDL predefined constants
97272: 06/02/20: Cheating at homework (from "Re: FPGA - software or hardware?")
97842: 06/02/28: Re: Is FPGA code called gateware?
98993: 06/03/18: Re: 8051 IP core with JTAG debugger for FPGA?
98994: 06/03/18: Re: 8051 IP core with JTAG debugger for FPGA?
101605: 06/05/03: Re: Reliability CPLD/FPGA vs Microcontroller
102736: 06/05/19: Re: LISP Workshop at ECOOP06
105273: 06/07/19: Re: corrupted data when accessing dual port bram in Cyclone II
106488: 06/08/14: Re: Arbiter schemes?
114796: 07/01/24: Re: Good hardware design code re-use strategies, reference book
115258: 07/02/05: Re: SystemC hangs abruptly
115310: 07/02/07: Re: Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?
115533: 07/02/13: Re: Setting VHDL standard in Xilinx ISE
115539: 07/02/13: Re: Which is your favorite FPGA language?
115587: 07/02/14: Re: Which is your favorite FPGA language?
115669: 07/02/16: Re: Do you like Virtex-5 ?
115672: 07/02/16: Re: Do you like Virtex-5 ?
115865: 07/02/22: Re: Do you like Virtex-5 ?
116079: 07/03/01: Re: Where can i get free CAN VHDL core
116647: 07/03/14: Re: VHDL and Latch
116648: 07/03/14: Re: VHDL and Latch
116690: 07/03/15: Re: VHDL and Latch
117193: 07/03/26: Re: Where is Open Source for FPGA development?
117243: 07/03/27: Re: Open-source CPU-core for standard-cell ASIC?
117340: 07/03/28: Re: Where is Open Source for FPGA development?
117769: 07/04/10: C/C++ for hardware (from "Re: Embedded languages based on early Ada (from "Re: Preferred OS, processor family for running embedded Ada?")")
117832: 07/04/11: Re: A new way to define systems of systems?
118239: 07/04/20: Re: Free Hardware
118290: 07/04/23: Re: Free Hardware
118335: 07/04/24: Re: Problem with real data type
118338: 07/04/24: VHDL support from vendors (from "Re: Problem with real data type")
118417: 07/04/26: Re: VHDL editing with UltraEdit
118467: 07/04/27: Re: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
118542: 07/04/29: Re: VHDL editing with UltraEdit
119220: 07/05/15: Re: Xilinx ISE 9.1 Simulator does not work with glibc 2.5
119223: 07/05/15: Re: coregen -> simulation error in modelsim
119283: 07/05/16: Re: how to delay a signal in virtex FPGA
119362: 07/05/17: Re: VHDL newbie: building sequential circuits with basic gates
119460: 07/05/20: Re: VHDL newbie: building sequential circuits with basic gates
119469: 07/05/21: Re: VHDL newbie: building sequential circuits with basic gates
119478: 07/05/21: Re: seeking insights for potential reconfigurable computing application platforms
120211: 07/06/03: Re: Microcontrollers have a better predictable time behaviour than FPGAs
120375: 07/06/06: Re: Topics and Ideas for BS Project
120444: 07/06/07: Re: Topics and Ideas for BS Project
120512: 07/06/08: Re: Topics and Ideas for BS Project
120620: 07/06/12: Re: Apart from IEEE, is there some another journals for publishing an FPGA article?
120679: 07/06/13: Re: Topics and Ideas for BS Project
120703: 07/06/14: Re: Topics and Ideas for BS Project
121017: 07/06/22: Re: Interesting problems about high performance computing
121788: 07/07/13: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
122561: 07/07/31: Re: X values in ASIC
122877: 07/08/09: Re: secure interfacing between an fpga and a connected device
122879: 07/08/09: Re: New Xilinx forum.
122908: 07/08/10: Re: New Xilinx forum.
123430: 07/08/28: Re: Null statement in VHDL
123449: 07/08/28: Re: Null statement in VHDL
123501: 07/08/29: Re: New keyword 'orif' and its implications
123561: 07/08/30: Re: New keyword 'orif' and its implications
123622: 07/08/31: Re: New keyword 'orif' and its implications
123733: 07/09/03: Re: New keyword 'orif' and its implications
125301: 07/10/19: Re: VHDL trivia?
126153: 07/11/15: Re: synopsys translate_off
126224: 07/11/17: Re: VHDL language is out of date! Why? I will explain.
126410: 07/11/21: Re: VHDL language is out of date! Why? I will explain.
130610: 08/03/28: Sorry to Those Who Deem This to be Spam: Employment or Scholarship
130893: 08/04/04: Re: Sorry to Those Who Deem This to be Spam: Employment or Scholarship
130894: 08/04/04: Re: Sorry to Those Who Deem This to be Spam: Employment or Scholarship
131089: 08/04/10: Re: Intel plans to tackle cosmic ray threat (actually they have been
131090: 08/04/10: Re: Intel plans to tackle cosmic ray threat (actually they have been
131091: 08/04/10: Re: system level language: why all this fuss about
131125: 08/04/11: Re: Intel plans to tackle cosmic ray threat (actually they have been
131298: 08/04/18: Re: Intel plans to tackle cosmic ray threat (actually they have been
132360: 08/05/23: Re: VHDL document generation utilities
134040: 08/07/22: Anomalous pasting in Xilinx WebPACK 10.1
134075: 08/07/24: Re: The littlest CPU
134139: 08/07/27: Re: Creating new operators
134140: 08/07/27: Re: Creating new operators
134182: 08/07/29: Re: Creating new operators
134183: 08/07/29: Re: Creating new operators
135120: 08/09/17: Re: Moving to Altera from Xilinx
135172: 08/09/19: Re: Help~ How to develope with FPGA board?
135173: 08/09/19: Re: Moving to Altera from Xilinx
137129: 08/12/24: Re: which HLL for HPC applications implementation?
141999: 09/07/21: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
143472: 09/10/12: Re: Win a Dev Kit--Join Us on Twitter & Facebook
143537: 09/10/15: Re: Win a Dev Kit--Join Us on Twitter & Facebook
143552: 09/10/15: Does anyone have current contact details for Jerry D. Harthcock?
143654: 09/10/20: Re: where can price list of FPGA be found?
143656: 09/10/20: Re: License issues
143685: 09/10/21: Re: License issues
143806: 09/10/27: Re: Win a Dev Kit--Join Us on Twitter & Facebook
147962: 10/06/04: Re: Software bloat (Larkin was right)
152455: 11/08/25: Re: Regarding virtex II pro xilinx XC2VP30 FF896
Colin Seymour:
82827: 05/04/18: Re: Flowcharts and diagrams
colin_toogood@yahoo.com:
76759: 04/12/10: default changes with new release
77411: 05/01/06: Re: Queries regarding PCI with Spartan3
85642: 05/06/13: Re: OrCAD Symbol For Xilinx V2PRO
139194: 09/03/23: Re: How big is my vhdl and am I approaching some size limitation on
140588: 09/05/19: Re: XILINX license model restricts longtime availability
140649: 09/05/21: Re: Sigasi Public Beta: future of VHDL design
142956: 09/09/10: Re: ANN: Coding style guidance for FPGA memory
143491: 09/10/13: Re: A simple rs232 CLI
153194: 12/01/06: voltage drop on STRATIX FPGA supply planes
<colleen.heckman@gmail.com>:
157991: 15/06/18: Free Webinar: Overcome the challenges of powering FPGAs
<collinds104@yahoo.co.uk>:
121096: 07/06/25: Re: weird PACE Error, not one google result
Colm Clancy:
26827: 00/10/31: Re: Xilinix Foundation Question
27877: 00/12/13: Re: Dual-ported RAM instantiation in Virtex-E ?
27909: 00/12/14: Re: Dual-ported RAM instantiation in Virtex-E ?
57485: 03/07/01: Re: NgdBuild:477 - clock net xx has non-clock connections
63934: 03/12/09: Re: Too many signals [Xilinx Foundation 4.1i]
ColmF:
104610: 06/07/01: Cyclone-II Configuration via a PCI bus
com.gmail@peattie.mike:
77893: 05/01/19: Re: Very Stupid XST verilog synthesis question...
80736: 05/03/10: Re: conditional port generation in Verilog 2001
comcast:
91113: 05/10/29: Re: Virtex-4 DSP48 - special features (Peter Alfke?)
commone:
119123: 07/05/12: Power Consumption Estimation for PCI card, any advice?
119139: 07/05/12: Re: Power Consumption Estimation for PCI card, any advice?
119148: 07/05/14: Re: Power Consumption Estimation for PCI card, any advice?
119265: 07/05/15: Re: Power Consumption Estimation for PCI card, any advice?
119953: 07/05/30: what is register packing?
120160: 07/06/01: Re: what is register packing?
121109: 07/06/25: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
121125: 07/06/26: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
121160: 07/06/27: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
122054: 07/07/18: Can multiple Ferrite Beads be used to connect ...?
122084: 07/07/19: Re: Can multiple Ferrite Beads be used to connect ...?
122096: 07/07/19: Re: Can multiple Ferrite Beads be used to connect ...?
122107: 07/07/19: Re: Can multiple Ferrite Beads be used to connect ...?
122111: 07/07/19: Re: Can multiple Ferrite Beads be used to connect ...?
122117: 07/07/19: Re: Can multiple Ferrite Beads be used to connect ...?
122158: 07/07/20: Re: Can multiple Ferrite Beads be used to connect ...?
122178: 07/07/23: Re: Can multiple Ferrite Beads be used to connect ...?
122786: 07/08/07: Re: Can multiple Ferrite Beads be used to connect ...?
122794: 07/08/07: Re: Can multiple Ferrite Beads be used to connect ...?
122804: 07/08/07: Re: Can multiple Ferrite Beads be used to connect ...?
122833: 07/08/08: Re: Can multiple Ferrite Beads be used to connect ...?
124796: 07/10/04: Problem about ADV7181B debugging
126042: 07/11/13: Re: bidirectional in fpga
127026: 07/12/09: Questions about Timing closure Floorplan and individual timing constraints
134304: 08/08/05: Re: Why PCI9054 fails to assert pci interrupt when local interrupt input is pulled down? Any advice? Thanks
135454: 08/10/02: Two questions about Xilinx constraints setting
135457: 08/10/02: Re: Two questions about Xilinx constraints setting
135461: 08/10/02: Re: Two questions about Xilinx constraints setting
135462: 08/10/02: Re: Two questions about Xilinx constraints setting
comp arch:
150500: 11/01/24: Re: Xilinx news
150501: 11/01/24: Re: Xilinx news
150597: 11/01/27: Re: Wow! No TestbenchWow!
150630: 11/01/29: Re: FPGA changes behaviour when the resource's usage percentage changes
150673: 11/02/02: Re: FPGA changes behaviour when the resource's usage percentage changes
150697: 11/02/04: Re: Trivia: Where are you on the HDL Map?
150872: 11/02/17: Re: Simulation vs. Hardware mismatch
Comp Arch Lab Group #6:
2333: 95/11/21: request for synthesizable VHDL for RAM
comp-arch-fpga-owner:
1499: 95/07/03: Comp.Arch.FPGA Reflector V1 #268
comp.arch.fpga:
114735: 07/01/23: Re: FPGA damage from bad bitstream
114799: 07/01/24: Re: FPGA damage from bad bitstream
114948: 07/01/27: Re: Higher studies
115286: 07/02/05: Re: circle generation algorithm
115327: 07/02/07: Re: Questions about pci transactions in my core
115734: 07/02/18: Re: Does Xilinx XST synthesize combinational divider?
116034: 07/02/28: Virtex 4 FX Sonet Alignment
116044: 07/02/28: Re: Virtex 4 FX Sonet Alignment
116090: 07/03/01: Re: Virtex 4 FX Sonet Alignment
116094: 07/03/01: Re: Virtex 4 FX Sonet Alignment
116104: 07/03/01: Re: Virtex 4 FX Sonet Alignment
116270: 07/03/06: Re: VHDL and Latch
116388: 07/03/08: Re: FPGA Vs ASIC design and implementation
116482: 07/03/09: Re: Xilin X-Fest Lunacy
116530: 07/03/12: Re: Estimating number of FPGAs needed for an application
116541: 07/03/12: Re: Xilin X-Fest Lunacy
116675: 07/03/15: Re: Xilin X-Fest Lunacy
116720: 07/03/15: Problem with XESS XSA 3S1000!
116809: 07/03/19: Re: FPGA vs. GPP anyone?
117186: 07/03/26: Re: Where is Open Source for FPGA development?
117306: 07/03/28: Re: Where is Open Source for FPGA development?
117318: 07/03/28: Re: FPGA board with multiple Ethernet connections (Gigabit Ethernet)
117348: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117406: 07/03/30: Re: Complex Baseband
117515: 07/04/03: Re: Where is Open Source for FPGA development?
117595: 07/04/04: Re: Complex Baseband
117836: 07/04/11: Re: FIFO newbie question
117992: 07/04/16: Re: Why 166Mhz DDR?
118224: 07/04/19: Re: Regarding drivers for FPGA based PCI cards
118317: 07/04/23: Re: Problem with real data type
118323: 07/04/23: Re: Problem with real data type
118472: 07/04/27: Re: physical chip size
118507: 07/04/28: Re: one extra slipway board from fccm
118540: 07/04/29: Re: physical chip size
118571: 07/04/30: Re: Xilinx software quality - how low can it go ?!
118688: 07/05/02: Re: Unused Pin setting on per-pin basis
118750: 07/05/03: Re: Video scaler for Spartan 3E?
118764: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118832: 07/05/04: Re: Video scaler for Spartan 3E?
119201: 07/05/15: Re: An Open-Source suggestion for Xilinx
119204: 07/05/15: Re: An Open-Source suggestion for Xilinx
119491: 07/05/21: Re: Timing not met but working on board
119504: 07/05/21: Re: Does FPGA need CPU for processing a packet/frame
119584: 07/05/23: Re: Does FPGA need CPU for processing a packet/frame
119633: 07/05/24: Re: 6502 and CPU licences in general
119760: 07/05/25: Re: 6502 and CPU licences in general
119955: 07/05/30: Re: Linux device driver for FPGA Xilinx Virtex-4
120020: 07/05/31: Re: data compression algorithms on FPGA
120024: 07/05/31: Re: data compression algorithms on FPGA
120176: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
120457: 07/06/07: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
120818: 07/06/18: Re: anyone know a FPGA designer?
121088: 07/06/25: Re: corgen cic = terrible efficiency?
121220: 07/06/28: Re: Bit error counter - how to make it faster
121251: 07/06/29: Re: Analogue like signal interaction within cpld possible ????
121301: 07/07/01: Re: Analogue like signal interaction within cpld possible ????
121362: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121372: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121790: 07/07/13: Re: highly-parallel highspeed connection between two FPGA boards
122477: 07/07/28: Re: Best CPU platform(s) for FPGA synthesis
122499: 07/07/29: Re: Best CPU platform(s) for FPGA synthesis
122834: 07/08/08: Re: New Xilinx forum.
122836: 07/08/08: Re: New Xilinx forum.
122876: 07/08/09: Re: High Speed ADC
122884: 07/08/09: Re: Write of 64 from PowerPC to my IP conected to the PLB?
122898: 07/08/09: Re: High Speed ADC
122899: 07/08/09: Re: secure interfacing between an fpga and a connected device
122925: 07/08/10: Re: Write of 64 from PowerPC to my IP conected to the PLB?
123017: 07/08/14: Re: Amount of wire and logic
123049: 07/08/15: Re: System ACE failure on ML405
123099: 07/08/16: Re: Amount of wire and logic
123112: 07/08/16: Re: MGT Link
123113: 07/08/16: Re: Scilab / Matrix
123348: 07/08/24: Re: Speed test between FPGA and DSP or PC.
123424: 07/08/28: Re: Null statement in VHDL
123429: 07/08/28: Re: Null statement in VHDL
123453: 07/08/28: Re: Null statement in VHDL
123480: 07/08/28: Re: PCB Layers
123503: 07/08/29: Re: New keyword 'orif' and its implications
123574: 07/08/30: Re: New keyword 'orif' and its implications
123683: 07/09/01: Re: New keyword 'orif' and its implications
123694: 07/09/02: Re: New keyword 'orif' and its implications
123754: 07/09/04: Re: Null statement in VHDL
123936: 07/09/07: Re: ANNC: New Boundary-Scan Software
124026: 07/09/11: Re: What is called carry chain structure in FPGA is called in IC?
124301: 07/09/18: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124348: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124354: 07/09/19: Re: Population Count circuit
124356: 07/09/19: Re: FPGA history
124482: 07/09/24: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124484: 07/09/24: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124509: 07/09/25: Re: Never buy Altera!!!!
124540: 07/09/26: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124553: 07/09/26: Re: Logic minimization software with LUT6 support?
124587: 07/09/27: Re: Logic minimization software with LUT6 support?
124727: 07/10/02: Re: Test and Measurements - Large FPGA
124780: 07/10/04: Re: Companies that Manufacture Multi-FPGA Hardware
124810: 07/10/05: Re: Optimized bitcounting on FPGA
125654: 07/10/31: Re: Is it possible to debug a vhdl design over jtag?
125749: 07/11/02: Re: Another way to handle floating inputs.
125750: 07/11/02: Re: Synthesizing with specific primitive-elements
126811: 07/12/03: Re: Xilinx ISE Bugs
126856: 07/12/04: Re: lossless compression in hardware: what to do in case of
126869: 07/12/05: Re: EDK IPIF development workflow
126870: 07/12/05: Re: lossless compression in hardware: what to do in case of
127190: 07/12/13: Re: Debugging designs that are running on FPGA
127267: 07/12/16: Re: SAS with FPGAs
127282: 07/12/17: Re: Ethernet data rates using Spartan-3 FPGA
127316: 07/12/18: Re: multidimensional arrays in VHDL?
127355: 07/12/19: Re: BGA reflow soldering using vapor phase
128054: 08/01/14: Re: sine and cosine wave generation
128124: 08/01/16: Re: speed... CORDIC vs. pure arithmetic expression
128147: 08/01/16: Re: gaussian filter in Altera FPGA
128148: 08/01/16: Re: speed... CORDIC vs. pure arithmetic expression
128245: 08/01/18: Re: Source of accurate frequency
128372: 08/01/23: Re: data capture
128422: 08/01/25: Fixedpoint Multiply/Accumulate in DSP48
128450: 08/01/26: Re: buying fpga kits in denmark
128519: 08/01/29: Re: Fixedpoint Multiply/Accumulate in DSP48
128643: 08/02/01: Re: Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require 9
128659: 08/02/01: Re: Fixedpoint Multiply/Accumulate in DSP48
128814: 08/02/07: Re: function/process to generate sine and cosine wave
128903: 08/02/09: Re: function/process to generate sine and cosine wave
128943: 08/02/11: Re: Unsigned to signed vector.
128973: 08/02/12: Re: how to implement this...
129235: 08/02/19: Re: FPGA Programming solution
129623: 08/02/29: Re: How to connect FPGA to a ASIC Board?
<comp.arch.fpga.FAQ@gmail.com>:
95077: 06/01/20: need for a group FAQ?
95080: 06/01/20: Re: need for a group FAQ?
<comp.arch.fpga.posting.account@googlemail.com>:
108985: 06/09/19: Metastability resolution
108989: 06/09/19: Re: Metastability resolution
108991: 06/09/19: Re: Metastability resolution
108993: 06/09/19: Re: Metastability resolution
109105: 06/09/20: Re: Metastability resolution
<comp@hotmail.com>:
30070: 01/03/22: Nokia 8850 zu gewinnen 5859
<comparchfpga@yahoo.com>:
80299: 05/03/03: making an fpga hot - addendum
80323: 05/03/03: Re: making an fpga hot - addendum
Compilit:
29814: 01/03/12: IP Cores, Megacores
29815: 01/03/12: Re: cpul vs vhdl
29886: 01/03/15: Re: IP Cores, Megacores
29895: 01/03/15: Re: IP Cores, Megacores
29900: 01/03/16: Re: Archive of Electronic Engineering jobs incl: ASIC,DSP,VHDL,FPGA,RF etc..
29903: 01/03/16: Re: IP Cores, Megacores
30145: 01/03/25: Re: NIOS 16-Bit
30226: 01/03/28: Books for trade
30237: 01/03/29: Re: Books for trade
30322: 01/04/02: Re: Books for trade
30364: 01/04/04: Re: FPGA V CPLD
30431: 01/04/07: Handel-C
30432: 01/04/07: Re: Handel-C
30434: 01/04/07: Re: Books for trade
30928: 01/05/03: EEjobs@yahoogroups.com
30964: 01/05/04: Re: Good VHDL/synthesis book
Completely Fazed:
34381: 01/08/22: Virtex-II place and route : Design doesn't route
<18734757@compuserve.com>:
6957: 97/07/16: GET FREE 2100 $ex-Web $Sites FREE! @?
<98776555554453@compuserve.com>:
6963: 97/07/16: FREE...Don't Pay For $ex $site Pa$$words,
<100611.1036@compuserve.com>:
1520: 95/07/06: Re: aynchronous ripple counter
Computalaw Ltd:
10156: 98/04/30: Seeking tester for new contract licence service
computerarchitect:
157984: 15/06/10: Energy efficiency of FPGA vs GPU vs CPU
COMTECH ELECTRONICS:
1402: 95/06/15: Unified Library for Xilinx
Con Cac:
38786: 02/01/24: www.fpga.org
Con-Digital:
concerned_altera:
89536: 05/09/18: Re: CPU benchmark for Xilinx PAR
configuration:
25177: 00/08/29: Re: Xilinx 18V02 Prom Parallel mode fails
Confused Frank (Remove the dots):
87577: 05/07/26: Confused with "task" keyword.
<confusedpp@gmail.com>:
119384: 07/05/17: SystemC and TLM
Cong shiping:
4647: 96/11/26: How to use Xilinx ?
cong shiping:
4706: 96/12/04: Re: How to use Xilinx ?
4707: 96/12/04: Re: Cypress CPLD, pASIC380 Programmer
4930: 97/01/01: Re: I2C Bus Interface in FPGAs
<cong_sp@tky0.attnet.or.jp>:
5143: 97/01/27: XACT's fitting speed
Conor Carr:
52692: 03/02/19: Spartan 1 : Help
Conor McLaughlin Proyecto ERASMUS:
1795: 95/09/04: Re: Comp.Arch.FPGA Reflector V1 #305
Constantin Jean-Claude:
4054: 96/09/06: Re: Want to learn FPGA! Please advise......
4056: 96/09/06: EPROM Xilinx second source
<consten2013@gmail.com>:
161558: 19/11/29: tell me what you think!
161559: 19/11/29: Re: tell me what you think!
Contact Lenses:
7092: 97/07/30: Contact Lenses for Internet users
<contactus@bargainshotline.com>:
31227: 01/05/15: BargainsHotLine.com New Free Way To SAVE $ MONEY $
cookielady:
47785: 02/10/04: Re: Altera FPGA as ISA I/O device
47823: 02/10/04: Re: Altera FPGA as ISA I/O device
Cool Morning ...:
46831: 02/09/10: FPGA comes with a DAC?
47291: 02/09/23: Re: VHDL Training Formal and Self-Study
47297: 02/09/23: Any online M.Sc level engineering programs from a reputable university?
47500: 02/09/27: Is it possible to build a Ring Oscillator in an FPGA chip?
cool.rezaul:
141670: 09/07/02: SDRAM problem
Cooley:
55976: 03/05/26: about the uclinux in Altera Nios
55977: 03/05/26: about the uclinux in Altera Nios
56581: 03/06/10: how to get into xilinx ftp?
56741: 03/06/13: Are there any free DSP core?
coolsaroj@gmail.com:
98832: 06/03/16: Re: Urgent Help Needed!!!!!
<coolsaroj@gmail.com>:
98781: 06/03/16: Urgent Help Needed!!!!!
<Cooper@interpath.net>:
1576: 95/07/20: Re: FPGA Software...
Coos Haak:
137065: 08/12/21: Re: Bit width in CPU cores
137093: 08/12/23: Re: Bit width in CPU cores
Cor van Loos:
32051: 01/06/11: Re: Triscend A5: can it reconfigure itself?
Corby James:
243: 94/09/30: PCMCIA
Cord Elias:
4977: 97/01/08: Re: Oscillator with PLD's or FPGA's
coredev:
142486: 09/08/12: Can I suppress invoking Block SelectRAMs in virtex5?
coreDEVIL:
68210: 04/03/30: Is there any Sync separator IP(Intellectual property) exists?
68214: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
Corer:
114619: 07/01/21: digilent nexys vga glitches
114633: 07/01/21: Re: digilent nexys vga glitches
114634: 07/01/21: Re: digilent nexys vga glitches
114682: 07/01/22: Re: digilent nexys vga glitches
114767: 07/01/24: Re: digilent nexys vga glitches
corley:
110222: 06/10/12: Re: Trying to get plb_temac working
110225: 06/10/12: ISO plb_temac driver for linux 2.4
Cornel Arnet:
64974: 04/01/17: Timing Simulation ModelSim / Quartus
65050: 04/01/19: Re: Timing Simulation ModelSim / Quartus
Correlious:
87140: 05/07/16: Re: How to Interface External Ram with FPGA
87141: 05/07/16: Re: Bus Macros
87433: 05/07/23: Re: Transfert data to Memec Virtex II Pro Card from PC
cort:
17919: 99/09/17: Re: PROBLEMS WITH ORCA
cortyus:
38140: 02/01/06: WARNING
Cory:
22529: 00/05/10: Re: Xilinx Foundation PAR hangs
Cory Rauch:
23425: 00/06/24: Computer Resource
<coshzz@gmail.com>:
87134: 05/07/16: post-place & route simulation of simple project problem.
87135: 05/07/16: Re: post-place & route simulation of simple project problem.
87357: 05/07/21: Re: post-place & route simulation of simple project problem.
87813: 05/08/01: Re: Xilinx Multiple Spartan 3
Costantino Sertorio:
3336: 96/05/15: Good book / FAQ?
Cotton Seed:
7935: 97/10/31: Questions about FPGA hardware design
7955: 97/11/02: Re: Questions about FPGA hardware design
<cottons@concmp.com>:
27249: 00/11/16: 5v parallel cable with 2.5/3.3v spartan II?
<course@garnet.berkeley.edu>:
1417: 95/06/19: ASIC TEST, etc. courses from UC Berkeley
1518: 95/07/06: Berkeley Announces 2 Short Courses
1519: 95/07/06: Packaging/Test Courses from Berkeley
1534: 95/07/10: BGAs, Flip Chip, COB, SMT, MCMs-courses this summer
1560: 95/07/15: Surface Mount/Fine Pitch course in San Francisco
1561: 95/07/16: SMT Short course August 8-9 in San Francisco
1833: 95/09/07: Berkeley CVD & ESD courses in Sept/Oct
2044: 95/10/06: Berkeley announces Advanced Product Development Course
3025: 96/03/15: Electronic Packaging Technologies Course in San Francisco
3691: 96/07/16: Fall IC Technology courses at UC Berkeley Extension
3919: 96/08/20: ESD and Gate Oxide Damage Short Courses from UC Berkeley in San Francisco, California this Fall
4845: 96/12/19: Silcon Processing Courses from Berkeley this winter
Courtenay Johnson:
17415: 99/07/26: Xilinx Virtex Block Select RAM, is is reg or flow thru output
cow:
141772: 09/07/08: About configuring FPGAs
CP:
41922: 02/04/10: Re: how to synchronise asynchronous inputs?
145098: 10/01/27: VHDL Manipulation and Generation Intrerface - vMAGIC 0.3.0 released
145229: 10/02/02: Re: Single Port Rom created by Core Generator configurable by generic
147071: 10/04/12: Re: Module wise FPGA resource utilization report
147989: 10/06/10: Re: Alternative to Chipscope
148706: 10/08/18: vMAGIC 0.3.9 released
<cpandya@yahoo.com>:
117987: 07/04/15: FPGA High speed Transceivers for source synchronus bus application
124805: 07/10/04: How to do one hot state machine in verilog for Xilinx V5 using XST
124807: 07/10/04: Re: How to do one hot state machine in verilog for Xilinx V5 using XST
125249: 07/10/18: FPGA pin swapping utility
125946: 07/11/09: Bitslip function in the V5 GTP Transmitter
126620: 07/11/28: System ACE debug
128526: 08/01/29: Spartan3 I/O question
128548: 08/01/30: Re: Spartan3 I/O question
130850: 08/04/03: Spartan3 JTAG flash In System Programming over Ethernet
137085: 08/12/22: Need comment on the following Verilog always block
137636: 09/01/25: ISERDES and timing simulation
138838: 09/03/12: How to initialize the Xilinx FIFO with predetermined value on
140960: 09/05/31: Virtex4 LX DCM Minimum Input Frequency
157964: 15/06/06: Is it possible to have a parameterized verilog module name in verilog
cpex:
69154: 04/04/28: good starter kit
69182: 04/04/29: Re: good starter kit
cpfpga:
139431: 09/03/29: doubts regarding fpga spartan3E kit use.
cplante:
149400: 10/10/21: Re: Combined Microprocessor and FPGA
149409: 10/10/22: Re: Combined Microprocessor and FPGA
cpld-fpga-asic:
134706: 08/08/27: FPGA/CPLD Design Group on LinkedIn
136446: 08/11/17: Link for Joining the FPGA/CPLD Design Group on LinkedIn
137177: 08/12/30: FPGA/CPLD Design Group on LinkedIn
141577: 09/06/28: FPGA / CPLD Group on LinkedIn -- Networking Group
<cpld.fpga.asic@gmail.com>:
132977: 08/06/11: Link for Joining the FPGA/CPLD Design Group on LinkedIn
132994: 08/06/12: Automotive Temperature +100 deg C+ FPGA's -- who's parts are
cpmetz@googlemail.com:
113376: 06/12/12: Question about Verilog Semantics / Xilinx Synthesis of embedded EMAC
113410: 06/12/13: Re: Question about Verilog Semantics / Xilinx Synthesis of embedded EMAC
114037: 07/01/03: Re: PPC cache errata
114075: 07/01/04: Re: PPC cache errata
114138: 07/01/05: Re: PPC cache errata
cpope:
113614: 06/12/18: Re: ppc elf data and vectors sections
113712: 06/12/19: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
114049: 07/01/03: xilinx spi example under linux
114198: 07/01/07: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114366: 07/01/12: Re: 16-bit DDR memory controller in EDK
114414: 07/01/15: Re: 16-bit DDR memory controller in EDK
114485: 07/01/17: Re: PCI Card with FPGA
114516: 07/01/18: Re: PCI Card with FPGA
115331: 07/02/07: Impact of only one bank powered?
115750: 07/02/19: low cost xilinx prom burner?
115774: 07/02/20: Re: low cost xilinx prom burner?
115805: 07/02/21: Re: low cost xilinx prom burner?
115825: 07/02/21: Re: low cost xilinx prom burner?
116824: 07/03/19: direct access on opb_emc
117004: 07/03/21: Re: direct access on opb_emc
117578: 07/04/04: fifo occupancy bigger than fifo size?
117614: 07/04/04: Re: fifo occupancy bigger than fifo size?
117626: 07/04/05: Re: fifo occupancy bigger than fifo size?
117662: 07/04/06: Re: virtex 4vfx12 evaluation kit schematics
118629: 07/05/01: switched to xcf32p prom and now doesn't run
118634: 07/05/01: Re: switched to xcf32p prom and now doesn't run
118734: 07/05/02: Re: switched to xcf32p prom and now doesn't run
118917: 07/05/07: Ubuntu and Webpack?
118937: 07/05/07: Re: Ubuntu and Webpack?
120889: 07/06/19: V4 PPC to sleep?
121045: 07/06/23: corgen cic = terrible efficiency?
121091: 07/06/25: Re: corgen cic = terrible efficiency?
121093: 07/06/25: Re: corgen cic = terrible efficiency?
121182: 07/06/27: Re: corgen cic = terrible efficiency?
121183: 07/06/27: Re: corgen cic = terrible efficiency?
121188: 07/06/27: Re: corgen cic = terrible efficiency?
121239: 07/06/28: modelsim search path
121258: 07/06/29: Re: modelsim search path
121264: 07/06/29: Re: modelsim search path
121297: 07/06/30: intermitent boot in V4
121307: 07/07/01: Re: intermitent boot in V4
122182: 07/07/23: xilinx multichannel fir alignment
122205: 07/07/23: Re: xilinx multichannel fir alignment
122208: 07/07/23: Re: xilinx multichannel fir alignment
122676: 07/08/02: V4FX PPC suspend/resume
122711: 07/08/04: Re: V4FX PPC suspend/resume
122757: 07/08/06: xilinx plb_ddr to self refresh mode
123170: 07/08/17: Re: Minimal power?
124159: 07/09/12: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
124180: 07/09/13: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
124201: 07/09/14: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
124213: 07/09/14: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
124795: 07/10/04: Best way to export XPS project to ISE?
126168: 07/11/15: TI DSP soft core in Xilinx?
126186: 07/11/16: Re: TI DSP soft core in Xilinx?
126217: 07/11/17: Re: TI DSP soft core in Xilinx?
127222: 07/12/14: serial ATA question
<cpu16x1832@wmconnect.com>:
88792: 05/08/28: Maybe a very cool FPGA a throw away idea for Xilinx
CPU2000:
83864: 05/05/08: Re: Looking for Xilinx Power-PC consultant
83917: 05/05/09: Re: 8051 IP core
83918: 05/05/09: Re: DDR speed of the XUPV2P Board from Digilent
83919: 05/05/09: Re: IP core supply
crackeur:
42031: 02/04/13: webpack ISE
42578: 02/04/28: static logic vs LUT
Crackpot:
20832: 00/02/23: Re: Bit Serial Arithmetic De-mystified
20834: 00/02/23: Re: Bit Serial Arithmetic De-mystified
Craig:
130846: 08/04/03: Re: counterfeit Xilinx ?
130966: 08/04/07: Re: Conterfeit parts guidance
Craig Abramson:
33071: 01/07/17: Utopia Interface
Craig Cholvin:
49461: 02/11/12: Re: Partial Reconfiguration, Modular Design
Craig Conway:
68071: 04/03/25: Xilinx Virtex2Pro DDR output glitch free?
76857: 04/12/14: Xilinx speed grading
76883: 04/12/15: Re: Xilinx speed grading
craig domeny:
13351: 98/11/30: Re: Example of clock circuit needed !
Craig from FL:
30366: 01/04/04: Re: salary info for FPGA/HardwareEng's
Craig Humphrey:
18790: 99/11/16: OLD programming Software
Craig Jackson:
1609: 95/07/28: Re: Xilinx EPLD's
2111: 95/10/17: Re: Altera Flex10K new family
Craig Jin:
1064: 95/04/24: (none)
Craig McAdam:
29358: 01/02/15: Xilinx GSR in Verilog simulations
41164: 02/03/21: Interconnect system for multiple FPGA's ?
41357: 02/03/26: Re: Interconnect system for multiple FPGA's ?
41359: 02/03/26: Re: Interconnect system for multiple FPGA's ?
craig mcclure:
45259: 02/07/17: ALTERA PLMG5192 programming adapter
Craig Moore:
121772: 07/07/13: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121883: 07/07/14: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121884: 07/07/14: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121885: 07/07/14: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
Craig Slorach:
4481: 96/11/04: Info on FPGA Internal Architecture/ Programming
5781: 97/03/14: EDIF Format Specification
8265: 97/12/04: Xilinx 3000 Series (old software) to 4000 on New Software
8921: 98/02/07: Re: Looking for XC6200 Sw
8922: 98/02/07: Re: Looking for XC6200 Sw
8923: 98/02/07: Re: Looking for XC6200 Sw
8924: 98/02/07: Re: Looking for XC6200 Sw
8925: 98/02/07: Re: Looking for XC6200 Sw
8926: 98/02/07: Re: Looking for XC6200 Sw
8927: 98/02/07: Re: Looking for XC6200 Sw
8928: 98/02/07: Re: Looking for XC6200 Sw
8929: 98/02/07: Re: Looking for XC6200 Sw
8930: 98/02/07: Re: Looking for XC6200 Sw
8931: 98/02/07: Re: Looking for XC6200 Sw
13336: 98/11/26: Re: Detailed Configuration Format
13337: 98/11/26: Re: Add-in board with FPGA Secondary Processor
13616: 98/12/13: Re: Magazine IEEE for FPGA ???
14789: 99/02/17: Re: xnf de-compiler
17312: 99/07/20: Re: Xilinx/Synopsys License Problem
21789: 00/03/31: Re: Adrian Thompson's and GA work on Xilinx
21848: 00/04/04: Re: Adrian Thompson's and GA work on Xilinx
21901: 00/04/06: Re: JBits
22168: 00/04/28: Re: DSP (FPGA) description
23101: 00/06/14: Re: Source for Filter Design
Craig Taniguchi:
21677: 00/03/29: Re: FPGA & single point failure
21679: 00/03/29: Re: FPGA & single point failure
Craig Tsui:
53109: 03/03/04: rudimentary way to program CPLD
Craig Ward:
39728: 02/02/18: Faster designs
39799: 02/02/20: Re: Faster designs
42082: 02/04/15: XilinX Jtag Cable available in UK.
Craig Yarbrough:
11767: 98/09/08: Re: Design Re-use, IP cores, Megafunctions, etc...
11769: 98/09/08: Re: Xilinx CLPD
11770: 98/09/08: Re: Code coverage tools
11776: 98/09/08: Re: Xilinx CLPD
11843: 98/09/13: Re: ASIC -> FPGA async issues
16587: 99/05/28: Generating GSR From Within Chip
100166: 06/04/04: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
100172: 06/04/04: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
100177: 06/04/04: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
114326: 07/01/11: Xilinx Floorplanner 'Replace All With Placement' and still logic left over!
114327: 07/01/11: Re: crossing clock domain ??
<craig.taylor@xilinx.com>:
130822: 08/04/02: Re: counterfeit Xilinx ?
130823: 08/04/02: Conterfeit parts guidance
<craig_jacobs@asl-tk.com>:
12309: 98/10/08: Verilog Vs VHDL
16147: 99/05/06: Re: BGA Prototyping ?
<craigm9203@my-deja.com>:
25360: 00/09/08: Jobs at Xilinx
CraigR:
73879: 04/09/30: ASIC vs FPGA and In-Circuit Reconfigurability (ICR)?
73896: 04/09/30: Re: ASIC vs FPGA and In-Circuit Reconfigurability (ICR)?
73972: 04/10/01: Re: ASIC vs FPGA and In-Circuit Reconfigurability (ICR)?
craigtmoore@googlemail.com:
121759: 07/07/12: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
crazidoll:
crazycool:
81461: 05/03/24: Project vlog-mode on SourceForge.net
crazyd:
78881: 05/02/09: ASIC vs DSP vs FPGA
83427: 05/04/29: Patent issues in implementing embedded fpgas
create:
126763: 07/12/01: Using SRAM Memory CY7C1386C
Creed Huddleston:
7625: 97/09/29: Advantages of VHDL vs. Verilog?
<creemers_roger@hotmail.com>:
90364: 05/10/11: Problems with phase shift dcm
crescent:
143841: 09/10/29: Trouble in booting V5 FPGA from SPI flash.
143853: 09/10/29: Re: Trouble in booting V5 FPGA from SPI flash.
143886: 09/11/01: Re: Trouble in booting V5 FPGA from SPI flash.
<Crhonos04@gmail.com>:
132135: 08/05/15: Camera link interface
132229: 08/05/19: Re: Camera link interface
132230: 08/05/19: Re: Camera link interface
Crimson_M:
75928: 04/11/19: Performance of Xilinx System Generator RTL?
cris:
142581: 09/08/18: Post sythesys vs FPGA board implementation
cristal:
148957: 10/09/15: Problem with FSL, Dual Microblaze and Xilkernel.
149028: 10/09/21: Re: Problem with FSL, Dual Microblaze and Xilkernel.
Cristian:
50139: 02/12/03: PROM for XC2S300
cristian:
73315: 04/09/18: Re: Verilog vs VHDL for Loops
75965: 04/11/20: 18x18 Multipliers - Spartan III
76004: 04/11/22: Re: 18x18 Multipliers - Spartan III
76243: 04/11/29: Re: 18x18 Multipliers - Spartan III
Cristian CIRESSAN:
101043: 06/04/24: Re: Bluetooth with FPGA?????
Cristian P. Masgras:
2454: 95/12/07: Synario and 22V10 problems
2474: 95/12/12: Re: Synario and 22V10 problems
Cristiano Miani:
7998: 97/11/06: I Need help on Lattice's Synario download
crj:
59609: 03/08/24: Altera RBF format CRC
Crni Gorac:
36870: 01/11/22: Altera Quartus fork bus on block diagram
36887: 01/11/22: Re: Altera Quartus fork bus on block diagram
36904: 01/11/24: Re: Altera Quartus fork bus on block diagram
crob:
42175: 02/04/17: Re: Problems with Nios 2.0
42313: 02/04/19: Re: Source code for a NIOS instruction set simulator?
42384: 02/04/22: Re: was: NIOS ISS, MicroBlaze Cycle Accurate ISS
51315: 03/01/10: Re: NIOS - first attempt
61437: 03/10/03: Re: Quartus II tutorial vs the real world
cromr:
84524: 05/05/20: Synopsys Designware IP... can be used for Xilinx FPGA??
84779: 05/05/26: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
cruzin:
63879: 03/12/07: How to assign inferred logic to resource in Quartus
64787: 04/01/13: Nios memory
64842: 04/01/14: What does nios-run do?
64983: 04/01/17: Re: What does nios-run do?
65006: 04/01/18: Re: What does nios-run do?
65007: 04/01/18: Avalon DMA problems
65160: 04/01/21: How can I have multiple drivers of one inout port?
Crystal Harvey:
4578: 96/11/17: Re: VHDL code editor for Windows NT.
cs_posting@hotmail.com:
142586: 09/08/18: Re: Xilinx 3E design programs fine with 500E but fails with 250E
<cs_posting@hotmail.com>:
85235: 05/06/06: Re: Spartan 3 ata interface
85355: 05/06/08: Re: Spartan 3 ata interface
85403: 05/06/08: Re: General gripe session ....
85990: 05/06/19: Re: Retrieving code from an old PAL
90664: 05/10/18: Re: Storing a file onto FPGA
92488: 05/11/30: Download old Quartus versions (4.0, 4.1)
92546: 05/12/01: Re: Download old Quartus versions (4.0, 4.1)
92618: 05/12/02: Re: Download old Quartus versions (4.0, 4.1)
96197: 06/01/31: Re: Digilent FPGA & Handel-C
96200: 06/01/31: Re: Digilent FPGA & Handel-C
96201: 06/01/31: Re: Digilent FPGA & Handel-C
96131: 06/01/30: Re: XDL Tools wiki site
96098: 06/01/30: Re: Acquiring video frames and processing pixels in Xilinx
96119: 06/01/30: Re: Xilinx Legal
96124: 06/01/30: Re: Xilinx Legal
96133: 06/01/30: Re: Xilinx Legal
96135: 06/01/30: Re: Xilinx Legal
96146: 06/01/30: Re: Xilinx Legal
96175: 06/01/31: Re: Xilinx Legal
96186: 06/01/31: Re: Xilinx Legal
96260: 06/02/01: Re: Xilinx Legal
96251: 06/02/01: Re: BPSK modulation on Xilinx FPGA
96294: 06/02/01: Re: BPSK modulation on Xilinx FPGA
96394: 06/02/02: Re: Microblaze question
96444: 06/02/03: Re: FPGA growth vs. ASIC growth
96469: 06/02/03: Re: FPGA growth vs. ASIC growth
96602: 06/02/07: Re: Microblaze using SPI flash as instruction memory
96907: 06/02/13: Re: cheap USB analyzer based on FPGA
97464: 06/02/22: Re: Communication between FPGA and PC with ethernet
97465: 06/02/22: Input stage for VHF frequency counter in an FPGA?
97508: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
97564: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
97636: 06/02/24: Re: Input stage for VHF frequency counter in an FPGA?
97653: 06/02/25: Re: Input stage for VHF frequency counter in an FPGA?
97667: 06/02/25: Re: fpga to 5v ttl logic
97691: 06/02/26: Re: fpga to 5v ttl logic
97701: 06/02/26: Re: VGA specification
97715: 06/02/26: Re: VGA specification
97772: 06/02/27: Re: miniuart
98169: 06/03/06: Re: why use an FPGA when a CPLD will do ??
98303: 06/03/08: Re: The IDE interface
98307: 06/03/08: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
98314: 06/03/08: Re: The IDE interface
98315: 06/03/08: Re: 5v Xilinx development board
98329: 06/03/08: Re: 5v Xilinx development board
98340: 06/03/08: Re: Connect USB device to Spartan 3 FPGA
98489: 06/03/10: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
98729: 06/03/15: Re: xiilnx spartan 3 starter kit connection to Ethernet LAN
98864: 06/03/17: Re: for all those who believe in ASICs....
98893: 06/03/17: Re: for all those who believe in ASICs....
98896: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
98927: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
99128: 06/03/20: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
99313: 06/03/22: Re: Urgent Help Needed!!!!!
101925: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
107839: 06/09/01: 5V FPGAs & CPLDs in 2006?
107916: 06/09/02: Re: 5V FPGAs & CPLDs in 2006?
108210: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108211: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
109914: 06/10/07: Re: Spartan 3 Starter Kit I/O ports
110319: 06/10/13: Re: VGA timing
115112: 07/01/31: Re: USB 2.0 Streaming using FPGAs
115207: 07/02/02: Re: XST broken for XC9536?
115728: 07/02/17: Nexys from Digilent... aka, binge hacking
115757: 07/02/19: Re: ACTEL ProAsic Plus
115764: 07/02/19: Re: low cost xilinx prom burner?
115765: 07/02/19: Re: ACTEL ProAsic Plus
115794: 07/02/20: Re: low cost xilinx prom burner?
115799: 07/02/20: Re: Nexys from Digilent... aka, binge hacking
115800: 07/02/20: Re: Selecting device in Project Properties : no XC2V1000?
115812: 07/02/21: Re: low cost xilinx prom burner?
115813: 07/02/21: Re: low cost xilinx prom burner?
116024: 07/02/27: Re: Xilinx platform cable USB API?
116045: 07/02/28: Re: Xilinx USB flatform cable length mistery ?
116049: 07/02/28: Re: Altera Byte Blaster Cable on Linux
116095: 07/03/01: Re: what does a 'blank check' do exactly
116172: 07/03/02: Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc.
116655: 07/03/14: Re: Programming XCF from MicroBlaze over JTAG???
116686: 07/03/15: Re: doubt in verilog coding
116692: 07/03/15: Re: Programming XCF from MicroBlaze over JTAG???
116735: 07/03/16: Re: Programming XCF from MicroBlaze over JTAG???
116745: 07/03/16: Re: Programming XCF from MicroBlaze over JTAG???
116815: 07/03/19: Re: Jam STAPL Player extensions
116818: 07/03/19: Re: Jam STAPL Player extensions
116844: 07/03/19: Re: Programming XCF from MicroBlaze over JTAG???
116894: 07/03/20: Re: FPGA with 5V and PLCC package
116959: 07/03/21: Re: Off topic: what is the purpoe of XST?
116964: 07/03/21: Re: FPGA with 5V and PLCC package
116975: 07/03/21: Re: FPGA with 5V and PLCC package
116976: 07/03/21: Re: FPGA with 5V and PLCC package
117010: 07/03/21: Re: Off topic: what is the purpoe of XST?
117034: 07/03/21: Re: FPGA with 5V and PLCC package
117059: 07/03/22: Re: FPGA with 5V and PLCC package
117741: 07/04/09: Word sync in Cypress FX2 fifos /w 8 bit bus
117747: 07/04/09: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
117757: 07/04/09: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
118195: 07/04/19: Re: Summer with fpgas
118197: 07/04/19: Re: Summer with fpgas
118198: 07/04/19: Re: Summer with fpgas
118234: 07/04/20: Re: Summer with fpgas
118255: 07/04/20: Re: Free Hardware
118297: 07/04/23: Re: Summer with fpgas
118298: 07/04/23: Re: FPGA Newbie
118348: 07/04/24: Re: FPGA and DAC for wave generation
118491: 07/04/27: Re: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
118579: 07/04/30: Re: Xilinx software quality - how low can it go ?!
119364: 07/05/17: Re: An Open-Source suggestion for Xilinx
119365: 07/05/17: Re: can JTAG port of CPLD gets damaged?
119366: 07/05/17: Re: VHDL newbie: building sequential circuits with basic gates
119758: 07/05/25: Re: VGA signal through breadboard?
119762: 07/05/25: Re: VGA signal through breadboard?
119907: 07/05/29: Re: Linux device driver for FPGA Xilinx Virtex-4
119908: 07/05/29: Re: VGA signal through breadboard?
119976: 07/05/30: Xilinx CIC core in Spartan 3?
119984: 07/05/30: Re: Nexys by Digilen xbd file
120026: 07/05/31: Re: Nexys by Digilen xbd file
120032: 07/05/31: Re: Nexys by Digilen xbd file
120120: 07/06/01: Re: Nexys by Digilen xbd file
120129: 07/06/01: Re: Nexys by Digilen xbd file
120139: 07/06/01: Re: Nexys by Digilen xbd file
120322: 07/06/05: Re: Portable TCP/IP socket library
120415: 07/06/06: Re: Portable TCP/IP socket library
120497: 07/06/07: Re: A first FPGA project
120584: 07/06/11: Re: Altera FPGA programming problem.
120697: 07/06/13: Re: custom peripheral registers
120711: 07/06/14: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120714: 07/06/14: Re: c code to initialize a peripheral
120730: 07/06/14: Re: c code to initialize a peripheral
120742: 07/06/15: Re: c code to initialize a peripheral
120866: 07/06/19: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120870: 07/06/19: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120872: 07/06/19: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120965: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120967: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120974: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120982: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120997: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
121007: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
121009: 07/06/21: Re: Nios II problem
121019: 07/06/22: Re: Can anyone identify the manufacturer of this Chip ?
121040: 07/06/23: Re: |!|!|!|!|!|!|!Sparten 3E : !!!USB 2.0 Driver in the FPGA!!!|!!|!|!|!|!|!|!|!
121318: 07/07/02: Re: About the parallel port jtag programmer,
121369: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121489: 07/07/05: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121495: 07/07/05: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121958: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
124506: 07/09/25: Never buy Altera!!!!
124508: 07/09/25: Re: Never buy Altera!!!!
124525: 07/09/25: Re: Never buy Altera!!!!
124565: 07/09/26: Re: Never buy Altera!!!!
124638: 07/09/28: Re: Low-level FPGA programming?
124756: 07/10/03: Re: Basic VHDL Development kit
124764: 07/10/03: Re: Basic VHDL Development kit
124769: 07/10/03: Re: Basic VHDL Development kit
124875: 07/10/09: Re: XUPV2P from digilentinc
124989: 07/10/14: Re: Quartus II 7.2 web edition - Linux or not?
125124: 07/10/16: Re: FPGA quiz: what can be wrong
125137: 07/10/16: Re: Xilinx:is it possible to install Impact 9.1only?
125256: 07/10/18: Re: Fast Sampling of digital signals
125330: 07/10/22: Re: Own soft-processor
125939: 07/11/09: ROM (altsyncram) corruption
125947: 07/11/09: Re: ROM (altsyncram) corruption
125954: 07/11/09: Re: ROM (altsyncram) corruption
125955: 07/11/09: Re: Xilinx Parallel Cable IV, API spec
125956: 07/11/09: Re: Non-volatile FPGA in a small package
125967: 07/11/10: Re: Xilinx Parallel Cable IV, API spec
125985: 07/11/11: Re: Non-volatile FPGA in a small package
125989: 07/11/11: Re: Xilinx Parallel Cable IV, API spec
126074: 07/11/14: Re: FPGA for hobby use
126084: 07/11/14: Re: FPGA for hobby use
126097: 07/11/14: Re: FPGA for hobby use
126098: 07/11/14: Re: FPGA for hobby use
126100: 07/11/14: Re: FPGA for hobby use
126198: 07/11/16: Re: VHDL language is out of date! Why? I will explain.
131041: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131064: 08/04/09: Re: Spartan3 JTAG flash In System Programming over Ethernet
131183: 08/04/14: Re: Intel plans to tackle cosmic ray threat (actually they have been
131771: 08/05/01: Re: Old FPGA question
132871: 08/06/09: Re: how to prevent timer code firmware running on Microblaze from
132881: 08/06/09: Re: how to prevent timer code firmware running on Microblaze from
133899: 08/07/18: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
133907: 08/07/18: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
133914: 08/07/18: Re: Nintendo DS Screenshots / Video Capture
133926: 08/07/19: Re: Howto disable Quartus infering M4Ks??
133992: 08/07/21: Re: audio serial port i2s
134012: 08/07/21: Re: audio serial port i2s
134013: 08/07/21: Re: Linux on V4FX100
134087: 08/07/24: Re: using j-link jtag from iar systems to program spratan 3 with
134504: 08/08/14: Re: Using a Spartan 3 FPGA kit with a USB/DB9
134511: 08/08/15: Re: Development board with SD card.
134598: 08/08/20: Re: need efficient multichannel DDC on V4
134608: 08/08/20: Re: need efficient multichannel DDC on V4
134620: 08/08/21: Re: How to "propagate" a serial signal
134630: 08/08/21: Re: How to "propagate" a serial signal
135078: 08/09/14: Re: Quartus II compile speedup with New Quad Core Intel machine
135092: 08/09/15: Re: Moving to Altera from Xilinx
135374: 08/09/29: Re: Sending UDP packets over Ethernet
135400: 08/09/30: Re: Difference between PLD and General purpose CPU`
135421: 08/10/01: Gee Thanks Altera, I really enjoy having a break waiting on your
135476: 08/10/03: Re: Gee Thanks Altera, I really enjoy having a break waiting on your
135770: 08/10/15: Re: sensitive fpga
135903: 08/10/21: Re: Entry Level FPGA Jobs and Outsourcing
135905: 08/10/21: Re: Update Altera MAXII UFM post production
136272: 08/11/08: Re: Linux on Microblaze
136302: 08/11/10: Re: Linux on Microblaze
137926: 09/02/02: Re: Rotate video
137927: 09/02/02: Re: Rotate video
138705: 09/03/05: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
csantos:
124951: 07/10/12: Re: Graphical VHDL Viewer ?
124968: 07/10/13: Re: Graphical VHDL Viewer ?
125171: 07/10/17: Re: High level FPGA work flow: available tool?
125199: 07/10/17: Re: High level FPGA work flow: available tool?
125697: 07/11/01: Re: Capability of a FPGA device.
csc:
10519: 98/05/27: VHDL workshop at carlifornia region
CSchuster:
53880: 03/03/26: Translating 2 CLKDLLs for SpartanII architecture
53916: 03/03/27: Re: Translating 2 CLKDLLs for SpartanII architecture
Cser Laszlo:
23027: 00/06/09: Readout of an FPGA?
<cshroff@gmail.com>:
116751: 07/03/16: Virtex5 LXT and synthesis..
116759: 07/03/16: Re: Virtex5 LXT and synthesis..
<csisterna@hotmail.com>:
120895: 07/06/19: noisy rising edge clock - non-monotonic clock
<csjacobs@my-deja.com>:
20147: 00/01/28: Re: ADC to DSP... FIFO?
22257: 00/05/03: Re: How to Prevent theft of FPGA design
22258: 00/05/03: Re: How to Prevent theft of FPGA design
22465: 00/05/09: Re: Looking for Altera programmer in France
<csoolan@dso.org.sg>:
17160: 99/07/06: Benchmark circuits - in VHDL for FPGA
cspatel:
88206: 05/08/11: Microblaze
CsquaredPhD:
100352: 06/04/07: Re: Virtex-4 RocketIO and G.709 OTU-2
<cstring625@yahoo.com>:
124186: 07/09/13: Virtex-4 PCB design
<ctaniguchi1@gmail.com>:
122620: 07/08/01: Static Timing Analysis Using Primetime for FPGAs
122623: 07/08/01: Re: Static Timing Analysis Using Primetime for FPGAs
CTips:
81944: 05/04/04: Re: can c++ code be loaded to a hardware PGA coprocessor card
CTSportPilot:
129835: 08/03/06: Re: Blast from the past
129842: 08/03/06: Re: Blast from the past
129987: 08/03/12: Re: Blast from the past
129988: 08/03/12: Re: Blast from the past
CTU FEE Jan Krakora:
119894: 07/05/29: Re: Problems to simulate (behavioural) in XPS
119895: 07/05/29: Re: Problems to simulate (behavioural) in XPS
120104: 07/06/01: Re: Problems to simulate (behavioural) in XPS
Cuervo:
15177: 99/03/11: Re: need info
<cuga.smonster@gmail.com>:
129332: 08/02/21: System generator hardware co-simulation interface
cuong:
17607: 99/08/13: Virtx' Configuration with the Xchecker cable
<curcuru@ibm.net>:
646: 95/01/27: Re: FLEXlogic
767: 95/02/26: Re: Lattice ispLSI starter kit
<curiousjyo111@gmail.com>:
117669: 07/04/06: Re: Transition from ASIC to FPGA
117670: 07/04/06: Re: Transition from ASIC to FPGA
currentsource:
149802: 10/11/24: Verilog preprocessor macro syntax
Curt Johnson:
141251: 09/06/12: Re: NTSC/PAL Encoder using FPGA and DAC
142921: 09/09/08: Re: Spartan 3 loading from MCU slave serial problems
143995: 09/11/06: Re: OK Xilinx users, it's time I was let in on the joke...
144005: 09/11/06: Re: OK Xilinx users, it's time I was let in on the joke...
144047: 09/11/09: Re: OK Xilinx users, it's time I was let in on the joke...
144051: 09/11/09: Re: Sinewave generation
144112: 09/11/11: Re: OK Xilinx users, it's time I was let in on the joke...
144432: 09/12/07: Re: very wide counter (42-bit)
145702: 10/02/19: Re: System design in FPGA
147586: 10/05/05: Re: FIFO Depth Calculation
Curt Schibonski:
4198: 96/09/25: 4800 baud serial input to xc4000
Curtis Fischaber:
26845: 00/10/31: Re: Alliance under Linux?
26980: 00/11/06: Re: Quick Foundation SPIV install question
Curtis Lyson:
8066: 97/11/13: MAX7000S
<curtis_m_watson@yahoo.com>:
112815: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
cutemonster:
110595: 06/10/18: FIR filter fpga help
110610: 06/10/18: Re: FIR filter fpga help
110614: 06/10/18: Re: FIR filter fpga help
113694: 06/12/19: Dynamic DCM Controller help
113698: 06/12/19: Dynamic DCM Controller help
120506: 07/06/08: adaptive filter FPGA
120561: 07/06/10: Re: adaptive filter FPGA
120564: 07/06/10: Re: adaptive filter FPGA
120637: 07/06/12: Re: adaptive filter FPGA
120689: 07/06/13: Re: adaptive filter FPGA
120713: 07/06/14: Re: adaptive filter FPGA
120725: 07/06/14: Re: adaptive filter FPGA
120753: 07/06/15: what is the correct way to capture ADC using fpga
120758: 07/06/15: Re: virtex-II DCM phase shift problems
120763: 07/06/15: Re: virtex-II DCM phase shift problems
120764: 07/06/15: Re: what is the correct way to capture ADC using fpga
120816: 07/06/18: how to assert PSEN for DCM
120842: 07/06/18: want to pay for DCM active phase shift controller.
120877: 07/06/19: Re: want to pay for DCM active phase shift controller.
cvaldess:
148918: 10/09/09: Re: Want to get into FPGA
<cvxxuq@heal.com>:
18274: 99/10/11: HEAL YOURSELF 7754
CW:
64843: 04/01/15: 1.8v SpartanIIE
CWatters:
78417: 05/01/31: Re: Active HIGH / Active LOW
78418: 05/01/31: Re: Active HIGH / Active LOW
cwoodring:
65320: 04/01/24: xilinx EDK and Webpack 6.x
82114: 05/04/06: Re: LVDS PCI card is needed
82116: 05/04/06: xilinx appnote 636
83200: 05/04/25: Re: Space Invaders!
95625: 06/01/24: Re: LVDS Input buffer in VHDL (ISE)
95626: 06/01/24: testbench.tdo file Xilinx ISE 7.1
97194: 06/02/18: Xilinx System Generator Black Box
97196: 06/02/18: Re: Xilinx UCF area constraints disappearing
103746: 06/06/09: edk 8.1
121553: 07/07/07: XilinxSystemGenerator and Simulink
121658: 07/07/11: Re: XilinxSystemGenerator and Simulink
122078: 07/07/18: Re: Xilinx System generator vs Simulink HDL Coder
127007: 07/12/08: Xilinx EDK simulation
129649: 08/03/01: Avnet/Memec V4FX12LC proto card and SysGen
129881: 08/03/07: Re: Avnet/Memec V4FX12LC proto card and SysGen
135381: 08/09/29: pciAutoConfiguration on MVME5500
135434: 08/10/01: Re: pciAutoConfiguration on MVME5500
136847: 08/12/08: Re: Altera FPGA development board for high speed Video processing
140087: 09/04/27: Re: FPGA/DSP/Video Board
141239: 09/06/11: Re: Xilinx DDS cannot pass simulation in Simulink
<cwthomas@bittware.com>:
153135: 11/12/09: Need Clocked 1.5+Ghz LVDS buffer. Or bright ideas!
cxg:
80690: 05/03/10: re:cyclone's pll
<cxu_dl@yahoo.com>:
121020: 07/06/22: How to deal with unavoidable setup time violation in CoolRunner II cpld?
121021: 07/06/22: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
121033: 07/06/22: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
121034: 07/06/22: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
Cy Drellinger:
140896: 09/05/28: ISE USB Slave Parallel programming
Cy Drollinger:
73798: 04/09/29: VHDL Project Verilog open core compatibility?
Cyber Millionair:
3750: 96/07/25: A New " America Online"......$19.96\month Unlimited access!!!
<cyber_hearts@hotmail.com>:
12713: 98/10/24: Looking for Love in ALL the Wrong Places???
cyber_spook:
30166: 01/03/26: Re: Xilinx FPGA Config file sizes.
30448: 01/04/08: Re: Handel-C
30467: 01/04/09: Re: Handel-C
30468: 01/04/09: Re: Handel-C
30483: 01/04/10: Re: Handel-C
30484: 01/04/10: Re: free software
30511: 01/04/11: Re: Handel-C
30532: 01/04/12: Re: Modlesim5.5
30533: 01/04/12: Re: Handel-C
30739: 01/04/26: Re: Configuration via PCI JTAG
30764: 01/04/27: Re: Configuration via PCI JTAG
30857: 01/05/01: Re: C++ To Gates
31048: 01/05/10: Re: Good VHDL/synthesis book
31224: 01/05/15: PCI The Real Hardware
31271: 01/05/16: Re: PCI The Real Hardware
31300: 01/05/17: Re: PCI The Real Hardware
31461: 01/05/25: Re: JTAG source
31623: 01/05/31: Re: [Q]setup-time violation
31624: 01/05/31: Re: Help in FIFO design
31891: 01/06/07: Re: Help in FIFO design
31892: 01/06/07: Re: Help in FIFO design
31894: 01/06/07: Re: Help in FIFO design
31895: 01/06/07: looking for work
32119: 01/06/14: Re: Hardware FPGA Eng. for Optical Net Co in Dallas
32443: 01/06/26: Re: Stupid Xilinx Patent
32481: 01/06/27: Re: Stupid Xilinx Patent
32482: 01/06/27: Re: Can 3" CDROMs Damage 5" CDROM Drives?
32521: 01/06/28: Is the Grass Greener for an Engineer in the USA?
32553: 01/06/29: Re: Newbee and FAQ
32803: 01/07/09: What chip!?
32865: 01/07/10: Re: Altera synthesis tools WAS: What chip!?
32867: 01/07/10: Re: What chip!?
32868: 01/07/10: Re: What chip!?
32869: 01/07/10: Re: What chip!?
32871: 01/07/10: Re: assigning signals with Altera Max+PlusII vhdl
32872: 01/07/10: Re: FPGA on flex?
32913: 01/07/11: Re: Altera synthesis tools WAS: What chip!?
33107: 01/07/17: Fibre Channel info?
33175: 01/07/18: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33256: 01/07/20: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33339: 01/07/23: Re: Soldering Ceramic BGA's
33410: 01/07/25: Re: FPGA Express or Spectrum?
33595: 01/07/31: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
CyberFunk:
65701: 04/02/05: Xilinx PAD name to (X,Y) RPM coordinate
65763: 04/02/06: Re: Xilinx PAD name to (X,Y) RPM coordinate
cybin:
28764: 01/01/23: Xilinx will NEVER support Linux
28800: 01/01/24: Re: Xilinx will NEVER support Linux
31692: 01/06/03: XtremeDSP Ready for prime time?
<cycfkh@theblairwitch.com>:
18441: 99/10/24: Womens Wrestling!!!!!!!!!!!
cycle:
35050: 01/09/19: virtex II (2v3000) configuration problem
35075: 01/09/20: Re: virtex II (2v3000) configuration problem
Cyclonefreak:
139653: 09/04/08: Pin Assignment
cyd:
87921: 05/08/03: Modulation Clock to set FPGA timing
87964: 05/08/04: Re: Modulation Clock to set FPGA timing
88604: 05/08/23: Re: Modulation Clock to set FPGA timing
90150: 05/10/05: Xilinx ISE 7.1i file management
CyForce:
<cyncsm@you.com>:
31162: 01/05/14: Find your sole mate here!! Post your FREE personal ADs here!
Cynthia Victor:
30195: 01/03/27: Any Expert FPGA Engineers out there?
Cynthis Sutton:
10162: 98/04/30: Make Money Fast
Cyra.Nargolwalla:
41481: 02/03/29: Re: Unusually Large Routing Delay From a FF To a Pin in FLEX10KE
44528: 02/06/22: Re: Logic Minimization in Max+Plus II
Cyril Muller:
6591: 97/06/04: XILINX CONFIGUTATION CRCs
Cyrille de Brébisson:
41486: 02/03/29: Re: powerpc in virtex2pro
41938: 02/04/11: Availability of Virtex II pro
41960: 02/04/11: Difference between the Virtex and the Virtex II
42130: 02/04/16: Virtex Development Board with a 4M or more gates
43422: 02/05/21: Shift register or state machine
43866: 02/06/04: Hard macro in FPGA, or how to cut a big project in smaller ones
43940: 02/06/06: Re: divide by 5
44372: 02/06/18: Re: Pls Recommend a Xilinx development Board
44373: 02/06/18: beginer's question: what does tran means in verilog
44488: 02/06/21: Re: xilinx, jtag vs. serial parallel mode
Cyrille Lambert:
68365: 04/04/02: Configuration Bitstream : Virtex-E, FDRI register
68367: 04/04/02: Virtex-E, FDRI register
72573: 04/08/25: Configuration : Virtex-E, CLB column
73773: 04/09/29: Virtex-II : Architecture
73856: 04/09/30: Re: Virtex-II : Architecture
Cyrille_:
143276: 09/09/29: How to program Spartan 3 Altium nanoboard with Xilinx tools ?
143330: 09/10/02: Re: How to program Spartan 3 Altium nanoboard with Xilinx tools ?
<cyrilw@my-deja.com>:
22509: 00/05/10: Re: Hardware TCP/IP stack?
Cysip:
17952: 99/09/19: SHORT COURSES DSP/MULTIMEDIA/COMMUNICATIONS. http://www.cysip.com
<czajnik@czajsoft.pl>:
119367: 07/05/17: Re: SERDES question (Lattice ispHSI)
czam:
139459: 09/03/30: Re: Fiber optics protocols for mid range speed
139478: 09/03/31: Re: Fiber optics protocols for mid range speed
czeczek:
109702: 06/10/03: Xilinx PowerPC & MicroBlaze Development Kit
109859: 06/10/06: Re: Xilinx PowerPC & MicroBlaze Development Kit
109967: 06/10/09: Re: Xilinx-Modelsim on Linux
czerstwy:
88416: 05/08/17: Problem with quartus 5.0 sp1
88430: 05/08/18: Re: Problem with quartus 5.0 sp1
103731: 06/06/09: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
<czhou1949@home.com>:
34041: 01/08/12: Re: PCI Postcode Display
34284: 01/08/18: Re: PCI Postcode Display
Cédric Gaudin:
47565: 02/09/29: Re: Unused pins in Apex20KE
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