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Randy,
There is a Xilinx Application Note appropriately titled "Pulse-Width
Modulation in Xilinx Programmable Logic" You can get it from the
Xilinx web site at http://www.xilinx.com/appnotes/pwm.pdf
Regards,
-- Brian Philofsky
Xilinx Applications
Randy Bickford wrote:
> Can anyone point me to a design example for implementating a pulse width
> modulation (PWM) circuit in a PLD? Design handbooks, tutorials, app
> notes?
>
> Thank you
> --
> Randy Bickford Expert Microsystems, Inc.
> Tel (916) 989-2018 7932 Country Trail Drive, Suite 1
> Fax (916) 989-4277 Orangevale, Ca 95662-2120
> rando@expmicrosys.com http://www.expmicrosys.com
--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------
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Randy,
<BR>
<BR> There is a Xilinx Application Note appropriately
titled "Pulse-Width
<BR>Modulation in Xilinx Programmable Logic" You can get it from
the
<BR>Xilinx web site at <A HREF="http://www.xilinx.com/appnotes/pwm.pdf">http://www.xilinx.com/appnotes/pwm.pdf</A>
<BR>
<BR>Regards,
<BR>
<BR>-- Brian Philofsky
<BR> Xilinx Applications
<BR>
<P>Randy Bickford wrote:
<BLOCKQUOTE TYPE=CITE>Can anyone point me to a design example for implementating
a pulse width
<BR>modulation (PWM) circuit in a PLD? Design handbooks, tutorials,
app
<BR>notes?
<P>Thank you
<BR>--
<BR>Randy Bickford
Expert Microsystems, Inc.
<BR>Tel (916) 989-2018 7932 Country Trail
Drive, Suite 1
<BR>Fax (916) 989-4277 Orangevale, Ca
95662-2120
<BR>rando@expmicrosys.com <A HREF="http://www.expmicrosys.com">http://www.expmicrosys.com</A></BLOCKQUOTE>
<PRE>--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------</PRE>
</HTML>
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Article: 8551Yekta Ayduk wrote: > > Do serial EEPROMS exist for Xilinx configuration in the market to > replace Xilinx OTP PROMS? ATMEL makes 17C65,17C128 and 17C256 EEPROMS that will work with Xilinx. Good Luck. Leo.Article: 8552
Hi all, I'm not sure if this is the best place to be posting this, but I am not aware of a more appropriate forum. I am thinking of trying to design and build a very simple FPGA and microcontroller based television display driver. I have heard rumours that the "Digital RCA inputs" and "Digital SVideo" inputs would be the way to go for this, but I am unable to find the specs for the communications protocol. Does anyone know where I can obtain the specs for the Digital RCA inputs and the SVideo inputs. Framing format, timing diagrams, etc... ? Any help would be appreciated. Thanks, Chris SamwaldArticle: 8553
See the app brief: Pulse Width Modulation in Xilinx, by Gary Lawman click on http://www.xilinx.com/appnotes/pwm.pdf Peter Alfke, Xilinx ApplicationsArticle: 8554
No one has responded to my original message. It seems, we are forced to include a power-supply voltage level monitor IC on our PCBs. We really resent having to do this!! The message that Xilinx has given us is that they are not responsible for erroneous configuration when power supplies that take longer then 4ms to go from 3 volts to 4.75 volts. There are numerous power supplies out there that do not come close to meeting this requirement! So it is my responsibility as a board designer to hold off Xilinx configuration until a safe programming voltage is detected. All designers using Xilinx FPGAs should verify that power supplies used to powerup their boards meet the Xilinx requirements. For me the cost of using a Xilinx FPGA has gone up by the cost of the power supply monitor IC! As a note, the majority of the time the FPGA will successfully configure on power-up even if a slow ramp-up supply is used. On other occassions the FPGA configures correctly with 99% of its functionality. So the FPGA appears to work but yet there can be one register that is malfunctioning. On other occassions the FPGA can come up completly dead. The odd thing about this is that in all cases the FPGA thinks it has successfully configured since it drives the DONE line active upon completion of configuration. Acromag Web Surfer <webuser@acromag.com> wrote in article <01bd0747$22dca580$7cef1fce@browser.acromag.com>... > We have used the Xilinx XC5200 FPGA family and XC17XXXD serial PROM parts > in a number of designs. We configure via master serial mode with the INIT~ > line tied to the PROM OE~ line with an external 4.7K pullup resistor. > After a number of customer complaints reporting product malfunctions, we > investigated and learned that the Xilinx FPGA will not reliable configure > on power up if the power supply has a slower then 4ms (typically) rise time > from 3 volts to 4.75 volts. Note that 4ms is a short time since we have a > number of supplies that require greater then 50ms to rise from 3 volts to > 4.75 volts. This is a serious problem! > > Has any one else experienced this problem? Do you have any recommended > solutions? > > One solution is to have all our customers use power supplies that power up > quickly. This is not a realistic request. Another solution is to hold off > configuration until a safe configuration voltage is reached (i.e 4.75 > volts). This requires a power supply monitor circuit that would hold the > INIT~ line low until 4.75 volts is detected. This circuit can easily be > included on the configuration PROM dice. Since the PROM's OE~ signal is > often tied to the INIT~ signal, the PROM can then hold off configuration > (with its built in power supply monitor circuit) until a safe programming > voltage is detected. Does anyone know of such a PROM? > > >Article: 8555
Poul-Henning Kamp wrote: > Hi gang, > > Description: > > A) 32 bit synchronous counter, input clock selectable > either from external pin or from PCI clock. > The frequency will generally be in the 5..50 MHz > range, the higher it can do the better. > This counter must be readable from the PCI interface. > B) 32 bit latch which captures the above counter at > the rising edge of an external signal. > This latch must be readable from the PCI interface. > (I wouldn't mind if there were a multiple of these > registers.) > Some suggestions: XC4013E-1 and the PCI intrface available as a Core from Xilinx. 32-bit counter is trivial, even at 50 MHz. It is easy to store 16 or 32 values ( or more ) in additional CLBs, since the read-out would be word-sequential. Density is not an issue. The only tricky part is the synchronizing of the strobe ( latch request ) to the count clock, since I assume they are asynchrous to each other. Careful double synchronization might be a good idea. Just my $ 0.02 worth. Peter Alfke >Article: 8556
hi,
> Description:
>
> A) 32 bit synchronous counter, input clock selectable
> either from external pin or from PCI clock.
> The frequency will generally be in the 5..50 MHz
> range, the higher it can do the better.
> This counter must be readable from the PCI interface.
> B) 32 bit latch which captures the above counter at
> the rising edge of an external signal.
> This latch must be readable from the PCI interface.
> (I wouldn't mind if there were a multiple of these
> registers.)
> C) Standard 32-bit PCI interface.
> D) PCB with PCI connector and connections for the
> external signals mentioned above. (It is alright
> to use any existing PCB you may have already.)
such a board could also be excellent for tuning
the performance of software programs (if multiple
counters were present, and someone wrote some tool
hooks into gprof, etc).
i've been designing counters and performance-measuring
circuits for a custom multiprocessor we're building here
at the university of toronto (64 MIPS R4400 processors,
about 4GB of RAM, 20 disks, etc). this kind of thing is
right up my alley... except that i was planning to switch
my research area back to FPGA architecture development.
i can easily design the FPGA circuits you mention above,
but the cost of manufacturing just the circuit board is significant. a
4-layer circuit board containing what you
want would cost about US$100 per board, and the FPGA and
misc. components might cost around $50, plus assembly.
is it worth about $200 to you and others? i think you
would have to sell at least 10 boards to make this project financially
viable.
> I'm not rich, and I do FreeBSD in my sparetime, so I
> cannot hire a company to do this for me, but I'm hoping
> that somebody out there could help me produce a couple of
> these gadgets at a price I can afford...
i'd love to help you out, so let's stay in touch on this.
i don't have any money to contribute, but i can put in some
time to design the circuits. i guess if we continue with
this, then i would need some money before starting to manufacture
anything. i already have access to all of
the CAD tools necessary to design such a board. i don't
know much about PCI yet, but i want to learn it some time!
btw, if you find some other board already made, it will
probably be cheaper.
> will make a standard PC run circles around any other
> computer when it comes to timekeeping as a NTP stratum
> 1 server, but don't expect to sell hundred of them.
i'm wondering -- why would such a PC would be so good?
what makes it better? i don't know much about timekeeping.
guy
ps - you can visit my homepage at
http://www.eecg.toronto.edu/~lemieux
to get an idea for the performance-monitoring
stuff and our multiprocessor (NUMAchine).
chapter 4 of my thesis describes some circuits
for performance measurement.
Article: 8557
I have 6 xilinx XC4044XL's connected on a bidirectional bus. At each fpga
the IOB is setup as follows (hope you can read this crude drawing):
------------------------+
|
bus ------> f/f (IOB) -------> Tristate -------+---> BI-DIR PAD (bus)
|
|
bus <----- f/f (IOB) <------- input buffer <---+ |
The pads are all connected on the board to give the bidirectional bus. I'm
performing a timing analysis on the bus and am having difficulties with the
hold time calculations. I'm using the delay line and therefore the hold time
is 0ns. If the max clock skew on the receiving fpga (the five that are not
sending the signal are receiving) is 5.5 ns and I assume that the minimum
skew on the sending one is 0ns (I know it can't be zero).
I looked at an article titled "A Look at Minimum Delays", which I found on
the Xilinx web page, which basically states that one can use 25% of the max clock to out of a signal for the min clock to out. The max clock to out for
my part is 10.3ns plus 3ns for the SLOW option. 0.25 * 13.3 = 3.3ns.
Therefore it appears that I potentially have a negative margin on my hold time:
The sending fpga has 0ns skew, the receiving has 5.5ns skew, the clock to
out minimum of the sending fpga is 3.3ns. thus the margin is
0 - 5.5 + 3.3 = -2.2ns
Now I realize that the clock skew on the sending fpga cannot be zero and the
bus will not instanty change at the receiving fpga either. What I'm looking
for, is what is that minimum skew for the fpga when using the global low
skew clock? Also do you see any flaws in my analysis above?
Article: 8558
Does anybody know how to connect an Altera Flex10k device to a PC
Parallel Port, particularly the electrical specifications do to this (not
to program the device, but to exchange data between PC and Flex10k).
Thank you in advance.
-------------------==== Posted via Deja News ====-----------------------
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Article: 8559I believe that Hans means that there are 64,231 separate cases that should yield a 1 and the rest of the 32M should yield a 0. -- Greg xxxgread@voicenet.com (REMOVE 'xxx' before sending) Steven Groom <arrownz@ihug.co.nz> wrote in article <34B400B9.3D6D2CF@ihug.co.nz>... > Hans wrote: > > > Hi, > > > > I wonder if anybody can help me. I am trying to synthesize a very large 24 by 1 > > bit look-up table. Of the 32M addresses 64231 should produce a ‘1’. I know this > > table is very large and possibly synthesis is not feasible, however, I would > > like to have a go at it. > > I don't know about VHDL, but Altera AHDL would have a statement like... > > case a[] is > when 64231 => > cs=1; > when others => > cs=0; > end case; > > Does this help? > > Regards, > > Steven Groom > Field Applications Engineer > Arrow (NZ) > >Article: 8560
Is there somebody who is familiar with the lines starting with an "E" is the programming file of a mach 211 device. I am particular interested in the checksum calculations.Article: 8561
Hi.
I was trying out the tutorial for Synopsys/XSI with the calc.vhd design
they have and it worked out completely and error free. But it didn't
include special components from the Design Ware library. I then tried
one of my own designs using a the cosine function from the Design Ware
libraries. My design synthesizes all the way to the end with no errors
or warnings. However, I run into some problems when I try to do
behavioral or timing simulation using a
testbench file.
The warning messages I receive are of similar type and they concern a
NAND gate that is being used from the GTECH library.
Here is a sample warning message:
Warning: vhdlsim,105:
/TESTBENCH/UUT/U2/G1/G2/INC1/L1(0)/L2(0)/L5(0)/L5I/L6/U3/COMPONENT
was not instanced because it is unbound.
These warning messages only appear when I try simulating the design
using vhdldbx. The simulation halts as soon as the nand gates are
reached.
Here is what is displayed when the simulation stops:
1 --synopsys synthesis_off
2 -- $Header:
/am/remote/ped52/src/dware/ice/dev/packages/gtech/src/RCS/GTECH_NAND2_sim.vhd,v
1.2 1994/01/04 11:
49:24 src ss_jer $
3
4 library IEEE;
5 use IEEE.std_logic_1164.all;
6
7 architecture sim of GTECH_NAND2 is
8 begin
9 -> Z <= not (A and B);
10 end sim;
11 --synopsys synthesis_on
If anyone has information regarding this issue or problems of similar
nature, could you please email me. I would like to use some of the
Design Ware components in my designs since they are supposed to be
optimized, but I am fairly new to the Design Ware and GTECH libraries.
Thanks in advance for any info anyone can provide.
Nestor Caouras
nestor@ece.concordia.ca
http://www.ece.concordia.ca/~nestor/addr.html
|-------------------------------------------|
| Dept. of Electrical and Computer Eng. |
| Concordia University |
| 1455 de Maisonneuve Blvd (West) |
| Montreal, Quebec, Canada H3G 1M8. |
| Tel: (514)848-8784 Fax: (514)848-2802 |
|-------------------------------------------|
Article: 8562
>>>>> "Guy" == Guy Gerard Lemieux <lemieux@eecg.toronto.edu> writes:
Guy> hi,
>> Description:
>>
>> A) 32 bit synchronous counter, input clock selectable
>> either from external pin or from PCI clock.
>> The frequency will generally be in the 5..50 MHz
>> range, the higher it can do the better.
>> This counter must be readable from the PCI interface.
[snip happens...]
Guy> i can easily design the FPGA circuits you mention above,
Guy> but the cost of manufacturing just the circuit board is significant. a
Guy> 4-layer circuit board containing what you
Guy> want would cost about US$100 per board, and the FPGA and
Guy> misc. components might cost around $50, plus assembly.
Guy> is it worth about $200 to you and others? i think you
Guy> would have to sell at least 10 boards to make this project financially
Guy> viable.
Certainly someone in this newsgroup probably has some old prototype
PCI boards w/FPGAs or EPLDs. One man's garbage could be another's
treasure here. I did a design that could easily be modified; however,
the prototypes are currently in use. If your patient, and no one else
comes through within the year, I suspect I could accommodate your request.
--
Michael G. Reeves email: miker@rbc.dec.com
Digital Equipment Corp. voice: (619) 618-7000 x7131
16868 Via Del Campo Court facsimile: (619) 618-7910
San Diego, CA 92127
Article: 8563In article <34ad4205.74803682@news.netcomuk.co.uk>, Peter <z80@ds.com> wrote: > >>What customers will be able to, or want to, use a million gate device? >A lot fewer than the PR machine claims. > >>What the tool flow will be (Schematics anyone?). >Depends on the above. Schematics are certainly an easier way to get >into FPGAs in a quick and useful way than VHDL etc. Obviously when you pretend to be a visinaire you cannot afford to write the statement mentioned above. A person that believes schematics are easier to design than VHDL absolutely cannot understand the high end FPGA market. Stick to the low end stuff. > >>Big FPGA's become like big ASIC designs, so why not do the ASIC? >Quite. I reckon the very big FPGAs are useful for very specialised low >volume high cost products, but much more for ASIC prototyping. Either >way, volumes will be low. > >>What will the P&R time be? >I think the question would be better phrased as what % utilisation >will be achievable. > >>How much IP core will be around? (and will it be appropriate?) >IP cores are useful only with big devices. > >I know lots of people who use FPGAs, and their ways of doing things >just don't square up with the FPGA vendor PR stuff in the press. >People still use large volumes of 10 year old XC3020 and 3030, because >they replace a lot of logic and are cheap. > >IMHO. > >Peter. > >Return address is invalid to help stop junk mail. >E-mail replies to z80@digiXYZserve.com but >remove the XYZ.Article: 8564
In article <34B33324.7BFA@netas.com.tr>,
Yekta Ayduk <yekta@netas.com.tr> wrote:
>
> Do serial EEPROMS exist for Xilinx configuration in the market to
> replace Xilinx OTP PROMS?
Atmel makes them, for more details check out :
http://www.atmel.com/atmel/products/prod182.htm
Martin Mason
Atmel Corp.
-------------------==== Posted via Deja News ====-----------------------
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Article: 8565Greetings, For the latest in Windows 95 Shareware, visit WWW.WIN-SHAREWARE.COM Be sure to enter our monthly drawing for a chance to win registered shareware!! Shareware Authors! Upload your windows products to the hottest new shareware site on the net!!! Regards, G. Mace WIN-SHAREWARE.COM ---------- ><>=<==<><>>><==>><=Article: 8566
Rita Madarassy <madarass@cats.ucsc.edu> wrote in article <693nrv$qfn@darkstar.ucsc.edu>... : In article <34ad4205.74803682@news.netcomuk.co.uk>, Peter <z80@ds.com> wrote: hi, to chime in, i pretty much agree with peter. : > : >>What customers will be able to, or want to, use a million gate device? : >A lot fewer than the PR machine claims. : > : >>What the tool flow will be (Schematics anyone?). : >Depends on the above. Schematics are certainly an easier way to get : >into FPGAs in a quick and useful way than VHDL etc. : i don't think that many designs will use a million gate device. it seems that most designs we do now fit in 10,000 gates or less - we have devices on the shelf that are much larger but really don't use them all that much. in fact, a fair proportion of designs fit nicely into 2,000 gates. i don't have hard industry-wide numbers but i am preparing a survey among users to get this sort of information. and the *puny* 10,000 gate devices, which i use relatively frequently, on a relatively fast pc, still take a while to place and route and simulate. perhaps someone could post some data on some of their experiences for a *million* gate device for: 1. time for place and route 2. time for gate level logic simulation 3. time for static timing analysis : Obviously when you pretend to be a visinaire you cannot afford : to write the statement mentioned above. A person that believes : schematics are easier to design than VHDL absolutely cannot understand : the high end FPGA market. i also agree with peter that schematics are an easier way to get into fpga's than vhdl (or verilog or whatever but i know vhdl). the learning curve to get an engineer up and running and doing fpga chip designs at a basic level with schematics is measured, typically, in hours. at that point, the majority of the work could be done with some assistance along the way. i believe the learning curve for synthesizable vhdl and fpga chip design is considerably higher. i know the amount of time that i spent on the proverbial learning curve for vhdl, and it was *WAY* higher than the time it takes to sit someone down, show him how to access libraries, plop down some components, and wire them up. : : Stick to the low end stuff. : hmmm ... i guess this must apply to me, too, although i must state that i don't pretend to be a visionary of any sort, just a dumb old design engineer slinging some gates. and i am increasing my skills and experience into the larger devices, since they are needed to get some jobs done. but, perhaps this isn't my field, i should dump electronics, and take up economics :-) -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 8567
In article <01bd1c3f$fa791ac0$6aef1fce@przebienda.acromag.com>, "Louis Przebienda" <lprzebienda@acromag.com> writes: > It seems, we are forced to include a power-supply voltage level monitor IC > on our PCBs. We really resent having to do this!! Getting started at power up is a very hard problem. You are probably lucky that you encountered this trouble now rather than weeks/months from now when you have more units in the field. The best solution I know of is to get the people who build the power supply to give you an "OK" signal and merge that into your reset logic. Most backplanes have a signal like that. If you are using something like a well mounted power brick your best bet is probably one of the magic voltage-watcher chips. I gave up on RC time-delay kludges ages ago. Expecting a complicated digital chip to also have the special analog stuff (voltage reference) so it can do the power up case without help is probably wishful thinking. It would raise the price on all the chips that don't need that feature. On the other hand, if enough people are willing to pay for it I'm sure somebody will build it. Tell your sales rep. -- These are my opinions, not necessarily my employers.Article: 8568
At this moment, Xilinx does not offer erasable Serial PROMs, but Atmel does. The Atmel parts are pin- and functionally compatible with the Xilinx devices, but they are slower ( no big deal at 2 MHz, but can be a problem at 15 MHz CCLK rate ) and there has been a reported confusion within Atmel about how to program the active Low RESET polarity, Hopefully, this confusion is a thing of the past. Otherwise, there should be no problem. Peter Alfke, Xilinx ApplicationsArticle: 8569
FLEX6K(new product from Altera) can use gated signal as global signal. In logic synthesis option, you will have internal global option for this device in Max+PlusII V8.1. This might be the case(FLEX10K also possible). To make sure you shoule let me know what kind of device and which version of software you are using right now. KAWAMATA ÀÌ(°¡) <68o0rq$jjp$1@news.tokyo.mbn.or.jp> ¸Þ½ÃÁö¿¡¼ ÀÛ¼ºÇÏ¿´½À´Ï´Ù... >Does anyone know about this? >I entered a schematic into MaxPlus2 and >compiled. >There were some gated reset in my schematic, >therefore I expected no global reset could be used >for the gated reset signal. >But the result of the compile showed me that >the reset signal used global signal. >It confused me and I wondered I can go ahead >with using the global signal. >Has anyone had an experience like that ? > >Article: 8570
KAWAMATA wrote: > > Does anyone know about this? > I entered a schematic into MaxPlus2 and > compiled. > There were some gated reset in my schematic, > therefore I expected no global reset could be used > for the gated reset signal. > But the result of the compile showed me that > the reset signal used global signal. > It confused me and I wondered I can go ahead > with using the global signal. > Has anyone had an experience like that ? I beleive that the Latest FLEX 10 k's and the latest MAX+PLUSII do support Global Signals that are derived within the Part. This is nice if you must have derived clocks. We used to send them out of the part and then back in on a global pin. DougArticle: 8571
ees1ht@ee.surrey.ac.uk (Hans) wrote:
>Hi,
>
>I wonder if anybody can help me. I am trying to synthesize a very large 24 by 1
>bit look-up table. Of the 32M addresses 64231 should produce a "1".
If possible, factorise it... (decompose it into smaller LUTs)
(if the addresses are truly random, this won't help much...
if there is some sort of pattern, either a regular one or a clustering,
it can help enormously)
>architecture synthesis of j1j2 is
>begin
> process(abus)
> begin
>-- case abus is
>-- when "000000010000000100000001" => dbus <='1';
>-- when "000000010000001000000100" => dbus <='1';
>-- ????????..
>-- 64231 addresses
>-- ????????..
>-- when others => dbus <='0';
>-- end case;
-- for example, a 2-level factorisation might be
case abus(23 downto 10) is
when "00000001000000" =>
case abus(9 downto 0) is
when "0100000001" => dbus <='1';
when "1000000100" => dbus <='1';
-- when (others in this cluster) => dbus <= '1';
when others => dbus <='0';
end case;
-- when (other clusters) =>
-- inner case statement
when others => dbus <='0';
end case;
>end process;
>
Note that where you factorise will make a difference to the efficiency
of the result, depending on how the 64231 values are spaced in the LUT,
and there are many other efficiency tricks.
e.g. if the same pattern in the low-order bits is repeated several
times, then make its inner case statement a function, and you will be
able to re-use its LUT for several branches of the outer case statement.
This may be a good idea for clarity anyway...
This should be slower than one very large LUT, but if it is very much
smaller, it may actually be as fast or even faster...
- Brian
Article: 8572
"Louis Przebienda" <lprzebienda@acromag.com> writes:
> It seems, we are forced to include a power-supply voltage level monitor IC
> on our PCBs. We really resent having to do this!!
Well, I think that is what you should do regardless. A reset circuit
watching the power level is the best way to guarantee that the voltage
is stable when your board is coming out of reset. Not many kinds of
logic include a reset circuitry.
Do you know in which state the other logic on your board powers up in?
I always use reset circuitry, try one from Maxim, they are available
in SOT-23.
Yours,
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 8573Check out new site for technology jobs...engineering, design, process, CAD, application, software etc. http://www.techjobbank.comArticle: 8574
Attention Altera FLEX10K users: Is anyone else concerned about the imminent increase in Standby Current for the 10K100A from only 0.5mA to 10mA??? I design mobile/battery-powered products and this increase is gigantic relative to my overall power budget. Is there anyone else designing mobile, battery-powered, and/or other products which require low-power consumption or do I have the only application that is power critical? It seems like Altera could continue to offer a low-power version of the device for those who need it. Maybe something like a 10K100AL?
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