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IHMO you are better off to lock it to your C: volume serial # instead, because this can be edited as required, whereas an NIC could pack up and then you have a problem. >If I install the software on Machine X and later I want to >move to Machine Y, do I just move the Ethernet card to Y and >reload the software on Y? > >Thanks Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10176
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Kolaga,
You can do that if you want but you definitely do not need to go to
those lengths. If you upgrade/change machines simply call Xilinx
Customer Service (1-800-624-4782) and we will issue you a new license
for the new machine. As long as you are still under maintenance, there
is generally no questions asked about this. Our policy has been to
trust the customer in situations like these.
-- Brian
Kolaga Gold wrote:
> Isabelle Gonthier wrote:
> > sherstuk@amsd.com wrote:
>
> > > 1) Is SC-FND-BAS-PC protected by a hardware key, or is it
> > > tied to particular computer via ETHERNET card number?
>
> > 1)SC stands for support contract. The part number is
> > DS-FND-BAS-PC. There is no hardware key with the new M1.4.
> > It is
> > tied to either your harddrive serial number or ethernet
> > address.
>
> If I install the software on Machine X and later I want to
> move to Machine Y, do I just move the Ethernet card to Y and
> reload the software on Y?
>
> Thanks
--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------
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<P>Kolaga,
<P> You can do that if you want but you definitely do
not need to go to those lengths. If you upgrade/change machines simply
call Xilinx Customer Service (1-800-624-4782) and we will issue you a new
license for the new machine. As long as you are still under maintenance,
there is generally no questions asked about this. Our policy has
been to trust the customer in situations like these.
<P>-- Brian
<BR>
<P>Kolaga Gold wrote:
<BLOCKQUOTE TYPE=CITE>Isabelle Gonthier wrote:
<BR> > sherstuk@amsd.com wrote:
<P>> > 1) Is SC-FND-BAS-PC protected by a hardware key, or is it
<BR>> > tied to particular computer via ETHERNET card
number?
<P>> 1)SC stands for support
contract. The part number is
<BR>> DS-FND-BAS-PC. There is no hardware key with the new M1.4.
<BR>> It is
<BR>> tied to either your harddrive serial number or ethernet
<BR>> address.
<P>If I install the software on Machine X and later I want to
<BR>move to Machine Y, do I just move the Ethernet card to Y and
<BR>reload the software on Y?
<P>Thanks</BLOCKQUOTE>
<PRE>--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------</PRE>
</HTML>
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Article: 10177John, You'll find enclosed a revised version of your schematics. You'll see what I've changed during my "cleanup". Synario is wonderfully intuitive, so sometimes one may forget that there are still some rules to follow. I have trained many people in using Synario, including long-time users who discovered a lot... Back to your design : I ended with a fit in an ispLSI1016E-125 LJ44 (I had no pinout information so I left the pin assignment as free) giving the longest propagation delay : PADSx -> CS : 23.8 ns worst case. The nbr of GLB levels was 3, but I had asked for area optimization and the critical path are ignored in the cleaned up design (they are not located properly). When I routed again and asked for "speed" optimization, the longest path was 17.6 ns pad to pad. Not bad. So I don't think you have a Tpd problem (but that might depend on the hardware EXTERNAL to the Lattice). Have you checked the polarity of every signal outside the 1016 ? It might be interesting that you check my changes and try to download the new Jedec. Also, with a full-blown Synario, you might simulate the Lattice and the external buffers, with full timing. (an overkill for a simple design like this one). Let me know what comes out anyway. Hope it helps, Bert Cuzeau - ALSE FranceArticle: 10178
Hi.
I was trying to write some VHDL code to generate a new clock based on
another clock and a clock enable (CE) control pin. The goal of my
design is to output a clock pulse that is the same frequency as the
input clock but would be zero if the CE would be zero. When the CE is
one, then the generated clock should look exactly like the original
input clock. Ideally, I would like the clocks to be exactly
synchronized, but I can live with a delay of one clock period.
I guess this problem is similar to having a 2 input AND gate, whose one
input accepts the original clock and the other input accepts the CE
signal.
I have tried to use the input clock (clk) that I am using in the
"if (clk'event and clk='1') then..." statement as an input to an and
gate, but Synopsys doesn't like this syntax at all and generates an
error.
I have also tried using variables, but this method only outputs a single
pulse that is high when CE='1' and low when CE='0', but there are no
transitions. I'm attaching a part of my code for anyone who has dealt
with such control signals.
Any help would be greatly appreciated.
Thanks in advance.
Nestor Caouras
nestor@ece.concordia.ca
http://www.ece.concordia.ca/~nestor/addr.html
|-------------------------------------------|
| Dept. of Electrical and Computer Eng. |
| Concordia University |
| 1455 de Maisonneuve Blvd (West) |
| Montreal, Quebec, Canada H3G 1M8. |
| Tel: (514)848-8784 Fax: (514)848-2802 |
|-------------------------------------------|
>>>>>>>>>>>>>>>filename="arctan_control2_temp.vhdl"
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
entity arctan_control2 is
port( ready, slowclk, reset: in std_logic;
clkout : out std_logic);
end arctan_control2;
-- slowclk is the original input clock operating at frequency Fz MHz
-- ready is a signal that determines the value of the clock enable (CE)
-- input used for the generated output clock "clkout"
architecture behv of arctan_control2 is
signal ready_old : std_logic;
signal clk_net : std_logic;
begin
clk_net <= slowclk;
control: process (slowclk,ready,reset)
variable valid : boolean;
variable cnt : std_logic_vector(2 downto 0);
variable CE : std_logic;
variable clk_tmp : std_logic;
begin
if (reset = '1') then
...
elsif (slowclk'event and slowclk='1') then
clk_tmp := '1'; -- this could be changed or removed depending
if (ready_old = '0' and ready = '1') then -- if a rising edge transition was
-- detected from previous value of "ready"
-- to current value of "ready", then set
-- "valid" flag to TRUE
valid := true;
cnt := "000"; -- initialize the counter to zero
end if;
if valid then
if cnt < 6 then -- count for 6 clock cycles and keep
cnt := cnt + 1; -- CE high
CE := '1';
else
cnt := "000"; -- the max count was reached and CE is
CE := '0'; -- set back to low.
valid := false; -- control flag "valid" also reset
end if;
end if;
ready_old <= ready; -- store the current value of ready for
-- use in the next cycle
clkout <= clk_tmp and CE; -- generate the output clock
end if;
end process;
end behv;
Article: 10179Brian Philofsky wrote: > > Kolaga, > > You can do that if you want but you definitely do not need to go > to those lengths. If you upgrade/change machines simply call Xilinx > Customer Service (1-800-624-4782) and we will issue you a new license > for the new machine. As long as you are still under maintenance, > there is generally no questions asked about this. Our policy has been > to trust the customer in situations like these. > > -- Brian > ------------------------------------------------------------------- > / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) > \ \ ` Xilinx Applications Engineer hotline@xilinx.com > / / 2100 Logic Drive 1-800-255-7778 > \_\/.\ San Jose, California 95124-3450 1-408-879-5199 > ------------------------------------------------------------------- > > -- And what happens if you are not under maintenance? Can you still get a new license? Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10180
ptrei@securitydynamics.com wrote: > I'm developing a design which should take roughly 10k gates, > plus about 1500 registers. > > Here's what the part data for the XC6216 says: > > 'Cell count:' 4096 > 'Typical Gate Count Range:' 16000 - 24000 > > From this, it looks like you can get 4-6 gates/cell. > Looking at the design spec, it appears that each > cell can contain only one gate, and/or a register. > > Is the 'typical gate count' simply marketing hype? > Am I missing something obvious? > > thanks, > > Peter Trei > ptrei@securitydynamics.com -- I am not familiar with the XC6200 series, but it is common when counting gates to count the registers as gates as well. One register counts as 6 gates if used. So it would appear that the high end is about 90% utilization while the low end is closer to 60% utilization. Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10181
> zblazek@kasami.UVic.CA (Zeljko Blazek) wrote: > > > > >Hi everybody, > > > >I am interested in getting some information/opinions on prototyping > >boards for Xilinx chips. > > > >I was looking at getting a cheap prototyping board for a Xilinx XC4010PC84 > >FPGA. From the Xilinx web page, I have found two companies that produce > >what appear to be suitable boards: > > > > 1) APS-X84 FPGA Test Board from Associated Professional Systems (APS) > > > > 2) XS40 Prototyping Board from X Engineering Software Systems (XESS) > > > > > >My minimum requirements are a standalone board with a socket for the Xilinx > >chip, a socket for a serial PROM (although I would also be happy with a > >parallel EPROM) and access to some of the I/O pins on the Xilinx chip. Both > >products offer a lot more than my minimum requirements. > > > >I have tried to read most of the documentation that is given by the > >respective companies. Some of my remaining questions are: > > > > - How easy is it to get up and running with the boards. They both > > appear to come with custom download S/W. We have had some customers who say they have been up and running with one of our XS95 or XS40 Boards in under half an hour. > > > > - Has anybody had any bad (or good) experiences with either of the > > boards. > > > > - What are typical delivery/shipping times for the boards. Do they > > arrive when expected or are there delays. Both XS40 and XS95 boards are stock items. It typically takes 10 working days to get to Canada through customs. > > > > - Are the boards fairly rugged, for example, being able to hold out > > well under the physical abuse of a typical university environment. > > (assuming of course that noboby blows the chips up) We've shipped a lot of boards in the past six months. We have had 3 returned. Two of them had blown FPGAs and the other had a bad regulator. > > > > - Any other information related to the two boards, or any other cheap > > boards that you know of, would also be useful. I am somewhat of a > > novice in this area and so don't really know what are the right > > questions to ask. > > If you really want to go cheap, there is a description in the back of the "Practical Xilinx Designer" lab book from Prentice Hall that shows you how to build the core circuitry of both the XS95 and XS40 Boards. From that you can probably create your own design that does exactly what you want and then you can use the free downloading software from our web site to configure it. > > > >I also have a related question concerning S/W tools. My development > >software is running on a workstation (Sun Solaris). Can I generate > >a configuration file on my workstation, copy it to my PC, and then > >download it to the card, or do I need to do some tweaking of the > >configuration file. I am using the XactStep tools (in order to > >be able to use the older chips). You should be able to take the .BIT files generated from your XACT software on the Sun and download them from a Windows or NT PC using our software without modification. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 10182
Rickman wrote: > > Ingo Cyliax wrote: > > > > Yes, I would love to have my FPGA place&route and Cad tools under Linux. I > > use Win95/NT4.0 for FPGA P&R and Word. Win95 typically crashes 2-3 times > > per work session, NT4.0 is better but needs to be rebooted for config. > > changes, it's also expensive. I do everything else under Linux on my > > notebook. It never crashes and I can change PCCards and network configs. > > without rebooting. Sometimes my Linux sessions run for 1-2 weeks before > > I reboot usually just to run Win95. > > > > I don't just read my Email under Linux. I lay out PCBs, have a VHDL simulator > > and much of my FPGA toolchain runs under Linux as well as the cross-compilers > > (gcc) that I use for micros. Finally, I prefer to write all my articles > > documentation under Linux, and then convert them to Word as a final step. > > Granted, Linux needs some care and feeding just as Win95/NT4.0 does in a > > networked enrionment, but over all it crashes less for the workload I have > > and I wish I had access to more tools on that platform. > > > > Overall, I would say that I'm 10-20% more productive under Linux than Win95, > > just because it crashes and hangs less. With NT4.0 my productivity more on > > par with Linux, except that it's more expensive to run (memory, software, disk > > space requirments). The user interface argument is irrelevent, since it > > doesn't effect my productivity. > > > > Anyway, your mileage may vary. I just want to see more EDA tools for Linux. > > > I don't have a strong opinion either way in this discussion. I am using > Win95 based tools mainly because I am rather Unix/Linux ignorant. > > I am curious about why no vendors have jumped in to offer any comments. > Can we find out what the vendors are planning, or thinking about > planning, or what questions they might have about this topic??? > My conspiracy theory is that a major software company is paying others not to port their software to Linux, since they can't charge money for the operating system. Anyway, why complaint about it, win95/98/NT is really driving down the cost of old hardwares. I can pick up cheap 486 for close to nothing. I use several of them concurrently in a network to simulate multiple FPGAs. (one per 486). I need all the resources for the application, not the operating system. By the way, i can't even load win95 on my 12MB, 25MHz 486 laptop. -- Free VHDL/FPGA simulator: http://www.best.com/~rod1/vhdl EPL c/o WilsonBrianLee@yahoo.com (actually, the other way)Article: 10183
Hello, I have a requirement for a replacement for the above, in quantity of some hundreds. This part was last made by TI c. 1990. It seems the only option is a piggyback board with an FPGA on it. I could do it easily enough but I don't have time now. I see it as a low-end XC4000 device, loaded from a serial EPROM, on a little PCB with a 18-pin 0.3"-spacing header sticking out from underneath. But I don't even have a data sheet on the 9902 - it is that old. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10184
Hello,
I'm using the Xilinx Foundation Series software to implement my FPGA
design. One of the biggest problem with my design are frequent hold time
errors (running at 25 Mhz, clock cycle = 40 ns) reported during timing
simulation.
If I reduce the clock to 12.5 Mhz, the hold time errors disappear and
the signals are valid and my state machine works fine.
Are the hold time errors caused from assigning too wide a signal bus?
For example, in a clock cycle, I need to drive 32 internal signals to
the external bidirection pins. Is it too much for the XC4025E to change
32 flip-flops in 40ns?
To test this out, I reduced to using 8 lines of signal. At 25 Mhz, the
simulation did not report hold time errors. If I increase to 16 lines,
hold time errors occurs.
Cal
Poly undergraduate,
Vo
To
Article: 10185Vo To wrote: > > Hello, > > I'm using the Xilinx Foundation Series software to implement my FPGA > design. One of the biggest problem with my design are frequent hold time > errors (running at 25 Mhz, clock cycle = 40 ns) reported during timing > simulation. > > If I reduce the clock to 12.5 Mhz, the hold time errors disappear and > the signals are valid and my state machine works fine. > > Are the hold time errors caused from assigning too wide a signal bus? > For example, in a clock cycle, I need to drive 32 internal signals to > the external bidirection pins. Is it too much for the XC4025E to change > 32 flip-flops in 40ns? > > To test this out, I reduced to using 8 lines of signal. At 25 Mhz, the > simulation did not report hold time errors. If I increase to 16 lines, > hold time errors occurs. -- I don't know the particulars of your circuit, but my guess is that you are not using the global clock routing. If you don't use the global clock routing, as you add more FFs, the data path does not slow down, but your clock routing does. This will have the data from the previous stage changing from the current clock edge, before the clock reaches the next stage. To fix this, you need to bring the clock onto the chip through a BUFGS rather than an IBUF. Change this buffer and your hold time violation should go away. BTW, you should never get a hold time violation in any FPGA. This is caused by your data delay being too SHORT, which is something that should never happen. If your data path delay is too LONG, you will get setup time violations. Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10186
You may want to contact MEMEC Design Services (http://www.memecdesign.com/) about this. They've done other similar projects in the past, some with Xilinx XC4000 and some with XC5200. They even have a fairly generic 40-pin piggy-back board to replace obsolete peripherals (http://www.xilinx.com/products/logicore/alliance/memec/mds_devmod.pdf). ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Peter wrote in message <354ac3a6.211773073@news.netcomuk.co.uk>... >Hello, > >I have a requirement for a replacement for the above, in quantity of >some hundreds. This part was last made by TI c. 1990. > >It seems the only option is a piggyback board with an FPGA on it. > >I could do it easily enough but I don't have time now. > >I see it as a low-end XC4000 device, loaded from a serial EPROM, on a >little PCB with a 18-pin 0.3"-spacing header sticking out from >underneath. But I don't even have a data sheet on the 9902 - it is >that old. > > >Peter. > >Return address is invalid to help stop junk mail. >E-mail replies to zX80@digiYserve.com but >remove the X and the Y.Article: 10187
ptrei@securitydynamics.com wrote: ...snip... > Here's what the part data for the XC6216 says: > > 'Cell count:' 4096 > 'Typical Gate Count Range:' 16000 - 24000 > > From this, it looks like you can get 4-6 gates/cell. > Looking at the design spec, it appears that each > cell can contain only one gate, and/or a register. > > Is the 'typical gate count' simply marketing hype? > Am I missing something obvious? ...snip... -- I looked at the XC6200 datasheet and it is capable of using both a register and a two input mux in a single logic cell. The mux counts as three gates and the register counts as 6 giving a maximum of 9 gates per cell or over 36 K gates. So the 24 K estimate is about 2/3 of the max. I don't have any idea of how realistic that figure is. They have an interesting architecture. It is very similar to the Atmel line. They both have fine grains, next neighbor routing and partial reconfiguration. But the Atmel arch seems to contain a little more functionality while the Xilinx has better routing. Of course this comparison is with Atmel's older family. I have not looked at their new family in detail. But I don't see where the Xilinx parts are really any better. The speeds are slow, each cell has a 2 ns delay. This is much worse than the XC4000 series with 1 ns per cell and each cell can contain much more logic. In general, this fine grained architecture has very limited application. You application must need to run very fast and be able to be micro pipelined to do it. If you are performing standard types of logic functions, then you will not get any real performance out of this family. Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10188
Hello, We have a piece of equipment that uses an Actel A1020B-PL84C in it's keyboard/display controller which is apparently fried. We're unable to locate the manufacturer of that piece of equipment but we have another one just like it in working order. So we were wondering if it's possible at all to duplicate the working FPGA and how much it's going to cost. Any information will be greatly appreciated. Thanks. Vitaliy Rukhmakov vital@media-r-us.comArticle: 10189
Am considering the design for a hypothetical programmable diplexer, for use in transceivers. Currently, the diplexers are all fixed, ceramic filters affairs that permit one frequency band to be transmitted, while an adjacent frequency band is received. Frequencies would range from 200MHz to perhaps 40GHz. Power output would range from 2 Watts (SSPA) to perhaps 200 Watts. Certainly, the breakdown or burnthrough voltage drops as submicron features get smaller, and the breakdown voltage would remain high with large features. Is there anyone around who still remembers how large the features for an FPGA or ASIC would have to be to handle perhaps 200 Volts at these frequencies? 20 to 50 micron in GaAs or somesuch? Even larger? Jon CummingsArticle: 10190
Hi, I'm using Xilinx Foundation M1.3 for a class, and am wondering if Xilinx will release a Linux version. Under 95 things start to become unstable after a day or two for me (sometimes after a few hours even), and I have to reboot (I don't want NT either). I know they do make some software for various Unices, but a Linux version would be excellent. -- Andrew Veliath andrewtv@usa.net, veliaa@rpi.eduArticle: 10191
With all due respect, I do not understant why anybody likes Linux. It is obvious any UNIX like platform is fading away. Check out the guys from SUN: their system looks more and more like an NT. The finally realized UNIX sucks. UNIX was never designed for interfacing with humans. It was rather designed to interface with phones! The PCs were blessed with an operating system designed for human beings (WIN 95 and even WIN NT). So why do you want to make your machine stupid by adding LINUX? Tell me about a serious EDA tool in the market that is rational enough to code for LINUX!! Hernan Saab In article <m3zpgzdhcl.fsf@ztransform.velsoft.com>, Andrew Veliath <andrewtv@usa.net> wrote: >Hi, > >I'm using Xilinx Foundation M1.3 for a class, and am wondering if >Xilinx will release a Linux version. Under 95 things start to become >unstable after a day or two for me (sometimes after a few hours even), >and I have to reboot (I don't want NT either). > >I know they do make some software for various Unices, but a Linux >version would be excellent. > >-- >Andrew Veliath >andrewtv@usa.net, veliaa@rpi.eduArticle: 10192
In article <6ihd7o$i1q@darkstar.ucsc.edu>, Rita Madarassy <madarass@cats.ucsc.edu> wrote: >With all due respect, I do not understant why anybody likes Linux. >It is obvious any UNIX like platform is fading away. Check out the guys >from SUN: their system looks more and more like an NT. >The finally realized UNIX sucks. No no, they realized that USERS suck ! The users do not like Unix because they read somewhere that cool people think Unix sucks. Therefore, they take a perfectly working Unix or Unix-like kernel, put a big integrated colourfull graphic interface, and put the sticker "NT is not Unix", and users think "cool ! at last something which is not Unix". Linux is a kernel, and a fine one (the NT one is much more sluggish). The cool interface that hides it is under work. In fact, there are several projects, some of which are nearly finished (think about KDE for instance). Considering the kernel performances and stability, and the possibility of a "NT-like" GUI, no wonder that some people like Linux. Moreover, if I am under Linux and do not like the GUI, I simply do not run it. I have others available for free. And I can stick to the good old text console if I like to. With NT, there is no other choice than the Microsoft way. This explains why some people want to use Linux. They are rather numerous these days. They are not anymore a bunch of illuminated strange fools, they are a market. Therefore it makes sense to provide a Linux version. Another Unix advantage: I work with a Sun workstation on my desk. I had to use some fpga designs. The chips were in a DEC Alpha and a NT PC. I could do all the work on the Alpha from my desk. For the PC, I had to walk to go in front of the machine. I know there exists some software called NTrigue that exports the NT graphics through a network... but I also know that this soft is really not cheap. As far as network is concerned, traditionnal Unixes have a much better integration than NT. I do not clearly see why I post this message. Such a subject has always proven to degenerate into an endless flamewar with many insults and zero intelligence. --Thomas PorninArticle: 10193
I do not think you will be able to copy an Actel FPGA. Your ACT1 family comes with two sets of security fuses, one to prevent further programming and for the action probe. There is as far as I know no way you can read back the configuration file. Your best bet is to track down the manufacturer and either get a replacement or get the afm fuse file. Hans. In article <01bd75f5$4a4f7300$0401010a@vitaliy>, vital@media-r-us.com says... > >Hello, > >We have a piece of equipment that uses an Actel A1020B-PL84C in it's >keyboard/display controller which is apparently fried. We're unable to >locate the manufacturer of that piece of equipment but we have another one >just like it in working order. So we were wondering if it's possible at all >to duplicate the working FPGA and how much it's going to cost. > >Any information will be greatly appreciated. > >Thanks. > >Vitaliy Rukhmakov >vital@media-r-us.com >Article: 10194
I've seen so many discussion about the delay in Xilinx, Who knows how to make a dalay in Altera FPGA, EPF10k,EPF8k,etc.?Article: 10195
>You may want to contact MEMEC Design Services (http://www.memecdesign.com/) >about this. They've done other similar projects in the past, some with >Xilinx XC4000 and some with XC5200. They even have a fairly generic 40-pin >piggy-back board to replace obsolete peripherals >(http://www.xilinx.com/products/logicore/alliance/memec/mds_devmod.pdf). Hmmm, lots and lots of $$$$$$... Had I the time, I would have done something like this for around $20k max. No way a *company* doing digital design will touch it for less than double that. What I had in mind was a competent individual. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10196
Have you tried NT4? Far better than win95. I would never use win95 for serious work. >I'm using Xilinx Foundation M1.3 for a class, and am wondering if >Xilinx will release a Linux version. Under 95 things start to become >unstable after a day or two for me (sometimes after a few hours even), >and I have to reboot (I don't want NT either). > >I know they do make some software for various Unices, but a Linux >version would be excellent. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10197
Rita Madarassy <madarass@cats.ucsc.edu> wrote: : With all due respect, I do not understant why anybody likes Linux. : It is obvious any UNIX like platform is fading away. Check out the guys : from SUN: their system looks more and more like an NT. : The finally realized UNIX sucks. : UNIX was never designed for interfacing with humans. It was rather designed : to interface with phones! : The PCs were blessed with an operating system designed for human beings : (WIN 95 and even WIN NT). So why do you want to make your machine stupid : by adding LINUX? : Tell me about a serious EDA tool in the market that is rational enough : to code for LINUX!! http://www.bartels.de -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Free Software: If you contribute nothing, expect nothing --Article: 10198
zhangy wrote: > > I've seen so many discussion about the delay in Xilinx, Who knows how to > make a dalay in Altera FPGA, EPF10k,EPF8k,etc.? -- I think you missed the point. You should not try to use logic elements as delay lines. The delay of any logic element is poorly spec'ed and make a very poor delay line. In the Xilinx parts, they claim that to estimate the value for the minimum, you should use 25% of the maximum value. This gives you a range of 4 to 1 for the delay. Of course having said that, there are some ways you can use a delay. But they will depend on Altera specing a minimum delay. Do you know what that minimum is for a logic element? Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10199
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