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keiser anthony lynn <akeiser@ews.uiuc.edu> wrote: : Greetings, : I am trying to make an xchecker download program to run on Linux. : I have found the schematics on Xilinx's web page, but can find no : information on any of the "commands" that are obviously being stored : in the XC3042 and/or SRAM. Any help you can provide would be : appreciated. Hallo, I don't know what system the original program runs on, but I guess either Dos or win. If these commands are doenloaded via either the serial or parallel port, dosemu or wine might be good programms to spy what is going on on these ports. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 9501
Uwe Bonnes wrote: > > keiser anthony lynn <akeiser@ews.uiuc.edu> wrote: > : I am trying to make an xchecker download program to run on Linux. > : I have found the schematics on Xilinx's web page, but can find no > : information on any of the "commands" that are obviously being stored > : in the XC3042 and/or SRAM. Any help you can provide would be > : appreciated. Depends on what you want to do, but maybe you can use Xilinx's parallel cable, which consists only of two 74HC125 and therefore should be easy to figure out. > I don't know what system the original program runs on, but I guess either > Dos or win. If these commands are doenloaded via either the serial or And Solaris - sort of. TomArticle: 9502
We are looking to encode a complicated algorithm onto either an FPGA or ASIC for space applications. We are interested to know of any space qualified: 1.) FPGAs, 2.) Low volume ASIC processes (e.g. laser programmable, shared wafer etc), 3.) Conventional ASIC processes. Thanks for you help in this matter. -- Stephen King CRL sking@crl.co.ukArticle: 9503
Stephen King wrote: > > We are looking to encode a complicated algorithm onto either an FPGA or > ASIC for space applications. > > We are interested to know of any space qualified: > > 1.) FPGAs, > Might want to look at RH1280 from Actel (http://www.actel.com) > > 2.) Low volume ASIC processes (e.g. laser programmable, shared wafer etc), > One possibility is UTMC rad hard gate arrays (http://www.utmc.com) > > 3.) Conventional ASIC processes. > > Thanks for you help in this matter. > RandyArticle: 9504
In article <Eq0zI6.J3H@world.std.com>, jhallen@world.std.com (Joseph H Allen) writes:
..<del>..
|> I think what he wants is to take all of the possible bitstreams for his
|> application (each generated with XDE), XOR them together and store the
|> differences from a "master" one. It would be a kind of compression...
I did such a compression. Due to a tight timing, I've implemented the address
decoders for a DRAM controller (using a 3042A) without the possibility of in
system reconfiguration (without RAM (like XC4000), this would mean a lot of
wasted FFs).
Because there were various decoding schemes, I got tired of changing the
decoder in the schematic and guided routing. I've then locked the
decoder CLBs to fixed locations, and compared the bitstreams. 'diff' is a very
useful tool ;-) So I've figured out the LUT-position for about 10 CLBs. Now
there's only one 'master' bitstream plus various patch informations. Before
downloading, this information is analyzed and patched into the bitstream...
|> Someone should write a program to automate this process... I.E., it would
|> generate a test design, run makebits and store the xor difference between
|> the result and a blank design. This would probably get you pretty close to
|> a reverse engineered bit-stream format. Then you just need to adapt a few
|> of those berkeley tools, and voila, a freeware xilinx design system :-)
Any volunteers? ;-)
--
Bye
Georg Acher, acher@informatik.tu-muenchen.de
http://www.informatik.tu-muenchen.de/~acher/
"Oh no, not again !" The bowl of petunias
Article: 9505Stephen King wrote: > > We are looking to encode a complicated algorithm onto either an FPGA or > ASIC for space applications. > > We are interested to know of any space qualified: > > 1.) FPGAs, > > 2.) Low volume ASIC processes (e.g. laser programmable, shared wafer etc), > > 3.) Conventional ASIC processes. > > Thanks for you help in this matter. > > -- > Stephen King > CRL > sking@crl.co.uk For FPGAs, Actel has a hardened line, I think they are in the 1280 family. A few years ago harris was working on a rad hard device too, but I don't know if it ever came to market.Article: 9506
In article <350D75C6.D51B486D@xilinx.com>, Peter Alfke <peter.alfke@xilinx.com> writes <snip> >Somebody mentioned reverse engineering. Obviously, NeoCAD did it. >But remember that they were ( are ) a bunch of very experienced >engineers, and they spent a few dozen man-years ( "person-years" to be >politically correct ) on their software effort. And they found out that >it is not a viable stand-alone business. Er, how do you deduce that it wasn't a viable stand-alone business? Surely that Xilinx had to pay (it has been claimed) nearly $20m for NeoCAD, and that both Xilinx and Lucent are still using the technology (which also supported Actel and Motorola, with Altera "in the works") is evidence of the viability of the business? > >So, if you have the time and a few million dollars, and nothing better >to do, you can do it. Otherwise it's much cheaper to buy the software.. > And incidentally, you can't try a P&R of your design in other vendors' FPGAs like you could with NeoCAD. -- David PashleyArticle: 9507
Let me just repeat: Xilinx has no interest in making ( or keeping ) the position of LUT-defining bits a deep mystery. Go ahead and create any neat editor, but you should also assume that you can get the bit positions from us for free and without hassle. Peter Alfke, Xilinx ApplicationsArticle: 9508
Let me just repeat: Xilinx has no interest in making ( or keeping ) the position of LUT-defining bits a deep mystery. Go ahead and create any neat editor, but you should also assume that you can get the bit positions from us for free and without hassle. Peter Alfke, Xilinx ApplicationsArticle: 9509
How about the carry logic bits, which my design also required? -- glen Peter Alfke <peter.alfke@xilinx.com> writes: >Let me just repeat: >Xilinx has no interest in making ( or keeping ) the position of >LUT-defining bits a deep mystery. >Go ahead and create any neat editor, but you should also assume that you >can get the bit positions from us for free and without hassle. >Peter Alfke, Xilinx ApplicationsArticle: 9510
Guitar Man (abuse@erols.com) wrote: : Something I have wanted to do for a long time is to make a pulse width : modulated analog output from a digital signal. For this you will need a : very high speed clock. 100 MHz is not too high. The samples that you [snip] : The limitation of this design is that you need an extremely high speed : clock to reach the upper limit of human hearing with reasonable dynamic : range. For example, 16 bits require 65536 clock pulses per sample X : 40,000 sample per second = 2,560,000,000 Hz or 2.5 GHz clock speed. But : at telephone quality, 12 bits, 4,096 x 8,000 = 32,000,000 Hz or 32 MHz. : This is within the range of an FPGA. Check out how a modern 1 bit D/A convert works. (ie. www.crystal.com) It gets away with a much lower clock signal that above by spreading the "on" and "off" periods in a noise shaped way amongst the available clock periods. Graeme Gill.Article: 9511
In article <01bd5324$d36ff5e0$1d3872c1@sk_ii.crl.co.uk>, sking@crl.co.uk says... > >We are looking to encode a complicated algorithm onto either an FPGA or >ASIC for space applications. > >We are interested to know of any space qualified: > >1.) FPGAs, Actel puts out two, the RH1020 and RH1280. > >2.) Low volume ASIC processes (e.g. laser programmable, shared wafer etc), > >3.) Conventional ASIC processes. > Honeywell has a series of SOI/SOS gate array Asics. You can check them out at www.ssec.honeywell.com UTMC also has gate array Asics, but I don't think they are nearly as radhard as the Honeywell's. If you're into full custom Asics, Harris, Hughes and Raytheon have foundries.Article: 9512
Graeme Gill wrote: > Guitar Man (abuse@erols.com) wrote: > : Something I have wanted to do for a long time is to make a pulse width > : modulated analog output from a digital signal. For this you will need a > : very high speed clock. 100 MHz is not too high. The samples that you > [snip] > : The limitation of this design is that you need an extremely high speed > : clock to reach the upper limit of human hearing with reasonable dynamic > : range. For example, 16 bits require 65536 clock pulses per sample X > : 40,000 sample per second = 2,560,000,000 Hz or 2.5 GHz clock speed. But > : at telephone quality, 12 bits, 4,096 x 8,000 = 32,000,000 Hz or 32 MHz. > : This is within the range of an FPGA. > > Check out how a modern 1 bit D/A convert works. (ie. www.crystal.com) > It gets away with a much lower clock signal that above by spreading > the "on" and "off" periods in a noise shaped way amongst the available > clock periods. > > Graeme Gill. While it is true that they use a much lower clock rate, I believe it is typical to work at 128 x the sample rate, they are using a large amount of analog circuitry. I am more familiar with the delta-sigma ADCs. They have a comparator and an integrator as well as the low pass filter. With a purely digital approach, I don't see a way to do the same functions. Rick CollinsArticle: 9513
stephen: : We are looking to encode a complicated algorithm onto either an FPGA or : ASIC for space applications. : : We are interested to know of any space qualified: : : 1.) FPGAs, rk: actel products, act 1, 2, 3, some members only, act 3 looks the best of the lot right now. rh series, rh1020, rh1280. dx with ram is a no go, latchup. xl has poor rad tolerance from reported data. 40mx, 42mx, no data. others "in development" but can't buy so obviously not qualified. xilinx makes hi-rel, not rad-hard. need shields + seu protection + latchup detection. do-able, depending on application. also, utmc has ut22vp10 "rad-pal", probably smaller than what you want, but worth mentioning. stephen: : 2.) Low volume ASIC processes (e.g. laser programmable, shared wafer etc), rk: some data on chipx. qyh500 series pretty good, esp. @ 3.3 v. cx2001 series, poor seu, logic transient, latchup. btw, laser programmable is prototype; "one-mask" would be for space-flight. stephen: : 3.) Conventional ASIC processes. rk: lots in no particular order. northrop-grumman, honeywell, harris, gec/plessey [sold yet?], lockheed-martin, allied-signal, some others. utmc went fabless, has announced "commercial rad-hard" with ami. lsi logic is out of the business, iirc. : : Thanks for you help in this matter. : : -- : Stephen King : CRL : sking@crl.co.uk :Article: 9514
If you have a web site that doen't support front page extentions, what files do you have to up load to get the hover buttons to work properly? Please help! MichelleArticle: 9515
Stephen King wrote: > > We are looking to encode a complicated algorithm onto either an FPGA or > ASIC for space applications. > > We are interested to know of any space qualified: > > 1.) FPGAs, > Actel do rad-hard versions of the 1280 and the 1020. The RH1280 comes in at about $10000 per part, with a min. order of 10. At the moment, I think they are the only real players. There are other options if you don't need real rad-hard parts though. > 2.) Low volume ASIC processes (e.g. laser programmable, shared wafer etc), > Sorry, don't know. NASA have pages and pages of stuff on the subject on their web pages though. > 3.) Conventional ASIC processes. > For European Space Agency approved ASIC fabs see <http://www.estec.esa.nl/xrmwww/asic/asicpr.wsm.htm> > Thanks for you help in this matter. > > -- > Stephen King > CRL > sking@crl.co.uk Good luck, Alasdair. -- Alasdair Maclean, Senior Development Engineer, GEC Marconi Electro-Optics Ltd., Building 1A, Room 1-11, 4 Ferry Road, Silverknowes, Edinburgh, Scotland EH4 4AD Tel: +44 (0)131 343 5711, Fax: +44 (0)131 343 5050 Email: <mailto:alasdair.maclean@gecm.com>Article: 9516
I am searching for a synthesizable 8B/10B Encoder/Decoder for a FibreChannel Project. Has anybody VHDL or AHDL code for that? Thanks Patrick Mueller email: no_spam_pbmuelle@stud.ee.ethz.ch ( remove no_spam_ )Article: 9517
FOR SALE Actel Programming System
Barely used
$2500 for all this
(>$7000 new)
Designer Series 3.1 and 3.1.1 Software
(Product code DAT-PC)
All disks and documentation intact
Activator 2S Hardware Programmer
with ACT12-144PQFP adapter
Used three times
ALS-218 Action Probe (debugger)
never used
$2500
Contact:
-----------------------------------------------------------
Douglas W. Olsen | voice: 770.622.6286 |
Rockwell Automation | FAX: 770.623.9163 |
2150 Boggs Road | email: dwolsen@ra.rockwell.com |
Duluth, GA 30096 |
Article: 9518We are a hi-tech recruiting firm located in "Canada's Technology Triangle" (Kitchener-Waterloo, Guelph, Cambridge). This is an exciting, vibrant area with tremendous new technologies being developed by hundreds of hi-tech companies. We have an immediate (and URGENT) need for a Senior Design Engineer to deliver leading edge design solutions and enhancements for projection products. Design disciplines include high speed digital circuits to process video and graphic images, fast A/D conversion, phase lock loop, FPGA/PLD designs to support the above, and an understanding of video analogue circuits. An electrical engineering degree and three to five years design experience would be appropriate. This opportunity will allow an individual to succeed on a highly skilled team developing exciting new products. Please reply to NancyK@PriorResource.com For more opportunities and information about this wonderful area, check our web site at www.PriorResource.comArticle: 9519
Does anyone out there know where I can get software (bin or ready to compile) for Linux to download bitfiles to Xilinx FPGA's via Xchecker? Thanks Much, kz cjsmith@uiuc.eduArticle: 9520
> While it is true that they use a much lower clock rate, I believe it is > typical to work at 128 x the sample rate, they are using a large amount of > analog circuitry. I am more familiar with the delta-sigma ADCs. They have a > comparator and an integrator as well as the low pass filter. With a purely > digital approach, I don't see a way to do the same functions. > Rick Collins Hi Rick - It's not obvious, but check the actual operation. The high-speed 1 bit DACs are *entirely digital* except for the simple filter to convert the 11 MHz On/Off bitstream to 16 bit audio analog. That filter can easily be a simple RC filter - it only needs to eliminate noise above a MHz or so. Yes, that *is* hard to believe. If you play with clever algorithms (the noise-spreading ideas mentioned), you can get 2 bits of DAC simplification for every bit of time resolution (i.e. doubling of bit rate). So by adding 8 bits of time resolution - increasing the clock rate by 256 to 1 - you can get 16 bits of DAC performance with a 1 bit output. It *does* require a lot of fast computation. But nowadays that's nearly free and very easy. And the results don't need .001% precision resistors or other parts to be monotonic and linear. It still strikes me as one of the cleverer consumer electronics bits of DSP I've run across. Jim HornArticle: 9521
What is the dual port memory? thanks in advanceArticle: 9522
stephen: : Actel do rad-hard versions of the 1280 and the 1020. The RH1280 comes in : at about $10000 per part, with a min. order of 10. At the moment, I : think they are the only real players. There are other options if you : don't need real rad-hard parts though. rk: "rad-hard" is a term to be used, well, carefully. it needs to be broken down into total dose, single event upset, single event latchup, single event transient, and "other destructive effects" such as antifuse or gate rupture. to the best of my knowledge, there is no full rad-hard fpga in existence, although there are some nice models which do extremely well at some parameters and moderately well at others. stephen: : > 2.) Low volume ASIC processes (e.g. laser programmable, shared wafer etc), : > : : Sorry, don't know. NASA have pages and pages of stuff on the subject on : their web pages though. rk: try: http://rk.gsfc.nasa.gov http://flick.gsfc.nasa.gov/radhome -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9523
This is a multi-part message in MIME format.
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Paul Young of Caterpillar,
Paul we have seen your numerous posts to COMP.ARCH.FPGA. We understand
that you have had some concerns about a missed shipping date around the
Christmas time frame.
We are more than willing to try and resolve this, and in fact have
offered to
refund your shipping costs, out of our pockets. We did pursue the matter
with UPS, and they didn't have any idea what we were talking about. You
are free to pursue the matter with UPS also if you wish, but why do so,
when we have already offered to refund your shipments even if we don't
get a refund from UPS.
I believe your story about the UPS operator , and I believe that there
was a
mix up on the date you wanted the board shipped. I will not publicly
hammer UPS
(after all it was Christmas time). You requested a delayed shipment and
we
tried to accommodate you, but apparently there was a misunderstanding
and we
shipped the board on the day you wanted it to arrive. We further tried
to
accommodate you by doing a partial shipment because the manual was out
of
stock. We never charged you for the second shipment of the manual.
Now Paul, please don't continue to take pot shots at us publicly in
this way.
You made your point that you were unhappy with UPS and with us. We are
still
willing to resolve it in any reasonable way possible. Let us do this,
without
having the public discussions on the internet, where we are forced to
defend
ourselves publicly. This does not reflect well on either of us.
For future reference we CAN NOT and WILL NOT and DID NOT guarantee any
DELAYED
target shipment dates. We DID and WILL try to accommodate any and all
customer requests to the best of our ability, and WILL continue to do
so.We WILL
overnight materials when requested and when in stock. This is standard
practice. We do understand your expectations were not met, and we will
refund
ALL of your shipping costs, in order to satisfy you. Beyond this, I
don't know
what else we can do.
Please email me directly at richard@associatedpro.com for further
Respectfully,
Richard D. Schwarz
President, APS
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web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
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Article: 9524James Horn wrote: > > While it is true that they use a much lower clock rate, I believe it is > > typical to work at 128 x the sample rate, they are using a large amount of > > analog circuitry. I am more familiar with the delta-sigma ADCs. They have a > > comparator and an integrator as well as the low pass filter. With a purely > > digital approach, I don't see a way to do the same functions. > > > Rick Collins > > Hi Rick - > > It's not obvious, but check the actual operation. The high-speed 1 bit > DACs are *entirely digital* except for the simple filter to convert the 11 > MHz On/Off bitstream to 16 bit audio analog. That filter can easily be a > simple RC filter - it only needs to eliminate noise above a MHz or so. > Yes, that *is* hard to believe. > > If you play with clever algorithms (the noise-spreading ideas mentioned), > you can get 2 bits of DAC simplification for every bit of time resolution > (i.e. doubling of bit rate). So by adding 8 bits of time resolution - > increasing the clock rate by 256 to 1 - you can get 16 bits of DAC > performance with a 1 bit output. It *does* require a lot of fast > computation. But nowadays that's nearly free and very easy. And the > results don't need .001% precision resistors or other parts to be > monotonic and linear. > > It still strikes me as one of the cleverer consumer electronics bits of > DSP I've run across. > > Jim Horn I am having trouble finding a good explaination of the delta-sigma DAC. But what I have read about the sigma-delta ADC is that a fair amount of analog circuitry is required on the chip. This is in the modulator and consists of a Summer (op amp) Integrator and Comparator (one bit ADC). I would assume that similar components must make up the delta-sigma DAC. BTW, I have seen the term used both ways; delta-sigma and sigma-delta. Is one for the ADC and the other for the DAC, or are they interchangable? Rick Collins redsp@writeme.com
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