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mikeh@winnet-corp.com wrote: : We have noticed that a 80% full 10K50 which used to take : 2 hours on Ver 8.14 now takes 12 hours on 8.2. : If anyone has any clues how to set the options to get the performance : back I would appreciate it. I've noticed a problem with "Automatic Fast I/O" in the logic synthesis options. If you've got this on, try turning it off. Graeme Gill.Article: 9151
I got also a problem with the automatic fast/IO.
This was in version 8.11 (I don't know in version 8.2)
The strange thing was that in a design which uses about 70% of the
cells, it gave a problem. But when you have a design using about
85% this problem did not occur anymore.
--
Koenraad SCHELFHOUT
Switching Systems Division http://www.alcatel.com/
Microelectronics Department - VH14 _______________
________________________________________\ /-___
\ / /
Phone : (32/3) 240 89 93 \ ALCATEL / /
Fax : (32/3) 240 99 47 \ / /
mailto:ksch@sh.bel.alcatel.be \ / /
_____________________________________________\ / /______
\ / /
Francis Wellesplein, 1 v\/
B-2018 Antwerpen
Belgium
Article: 9152
I am now using MaxPlus2 version 8.2. Before it was 8.11. This is
run on a Sun SparcStation4 with Solaris as OS.
When I select some of the options in the tool, the text associated
to some buttons is only partially displayed. Enlarging the window
is not possible.
So it is for instance very difficult to select an option as edif-out
version (2.0 or 3.0) if you only see :
o edifout (missing text version 2.0)
o edifout (missing text version 2.0)
If you know the order, OK, but for some buttons it is very difficult
to see what they are meant for.
Does somebody knows a workaround ?
Thanks
--
Koenraad SCHELFHOUT
Switching Systems Division http://www.alcatel.com/
Microelectronics Department - VH14 _______________
________________________________________\ /-___
\ / /
Phone : (32/3) 240 89 93 \ ALCATEL / /
Fax : (32/3) 240 99 47 \ / /
mailto:ksch@sh.bel.alcatel.be \ / /
_____________________________________________\ / /______
\ / /
Francis Wellesplein, 1 v\/
B-2018 Antwerpen
Belgium
Article: 9153I´m currently working on a design based on ABEL code and schematic. When I syntesize this design it seems to grow and it doesn´t fit into one of the devices which I have chosed. Can anybody please help how to optimize the design concerning area. Pontus AnderssonArticle: 9154
Jack Lai <jwlai@mmmpcc.org> wrote: >H Girard >Can you tell me what"s is app note numbers, and where can I get these >notes. >Jack Lai Try looking in the Raytheon semiconductor data book , my old copy has this app note as TP-17B I also noted that the core solutions book from xilinx (book dated may 1997) has some correlation cores included in their logicore software the one dimensional units are used as basis to generate larger signal widths . H GirardArticle: 9155
If you want to generate frequencies around 10 MHz with a resolution of 1 kHz, and you really mean a clean single frequency, not an average frequency, then you need a clock period resolution of 100ns divided by 10000, which is 10 picoseconds. Thre is no way to achieve that by purely digital means. You need a 10 MHz VCO or VCXO which you can build or buy for around $10.-, two counters, one dividing the 300 kHz down to 1 kHz, the other one to divide 10 MHz down to 1 kHz ( 9 bits and 14 bits respectively ) and you need a phase/frequency comparator, as described on page 8-161 of the 1994 Xilinx Data Book, also available as XAPP028 on the Xilinx website. This digital circuitry ( counters and phase comparator) takes 15 CLBs in any XC4000-series device. You also need an analog low-pass filter or integrator/voltage amplifier to drive the external VCO. And you have to do some calculations regarding acceptable jitter and desired response time to a frequency change. Peter Alfke, Xilinx Applications Neurotech GmbH wrote: > Has anybody out there already done a completely digital PLL inside an > FPGA > ? > I have to do an XC4028EX and one part of it shall be a programmable > PLL > with > an input clock of about 300kHz and an output of about 10Mhz. But > sometimes > I need exactly 9.998 MHz, sometimes 10.011 and so on, as precise as > possible. > > Any idea ? > Holger Schuppan > > Neurotech@T-Online.deArticle: 9156
Have a look at the publications of our group at http://ece.wpi.edu/Research/crypt You'll find a bunch of papers on Galois field arithmetic, although not directly related to PRNGs (but rather for coding and crypto applications.) Hope this helps, Christof Utku Ozcan (ozcan@netas.com.tr) wrote: : Long ago someone sent a posting which included pesudorandom : number generators. That person represented a model and then : extended it to a Galois field. Do I remember correctly? If : yes, would you please tell some links, books etc? : : Utku -- ************************************************************************* Christof Paar http://ee.wpi.edu/People/faculty/cxp.html Assistant Professor email: christof@ece.wpi.edu Cryptography Group phone: (508) 831 5061 ECE Department, WPI fax: (508) 831 5491 100 Institute Road Worcester, MA 01609, USA *************************************************************************Article: 9157
I work for a company that performs controls consulting services and we recently came across a project that needs an EE engineer versed in FPGA design. I have a couple of questions before I look for someone to fill the position. 1) What does FPGA stand for? 2) Can you give me an example of an FPGA application? If you live in the Boston area, please call me at 617-868-2955. Scott Bedard Data Insights, Inc.Article: 9158
janovetz@ews.uiuc.edu (Jacob W Janovetz) writes:
> I just posted a note asking how to add pullups in Xilinx FPGAs.
> Well, I think I have answered my own question, however, I'd like
> to know your thoughts. The problem is that I could not place
> a pullup on an INPUT node. (Leonardo wouldn't let me) I am
> using direct port mapping to do this.
Try the following approaches:
As a Leonardo command prior to optimize(and I think as a Galileo constraint)
set_attribute <instance_name> -port -name pull -value "pullup"
Or in the VHDL itself :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
ENTITY test2 IS
PORT ( inbus_a, inbus_b, inbus_c : IN std_logic;
en_a, en_b, en_c : IN std_logic;
stopit : IN std_logic;
common : IN std_logic;
outbus : OUT std_logic );
ATTRIBUTE pull: STRING;
ATTRIBUTE pull OF inbus_a: SIGNAL is "pullup";
ATTRIBUTE pull OF inbus_b: SIGNAL is "pulldn";
END test2;
ARCHITECTURE exemplar OF test2 IS
SIGNAL int_bus : std_logic;
BEGIN
pullup(int_bus);
-- RTL description
int_bus <= inbus_a AND stopit WHEN en_a = '1' ELSE 'Z';
int_bus <= inbus_b AND stopit WHEN en_b = '1' ELSE 'Z';
int_bus <= inbus_c AND stopit WHEN en_c = '1' ELSE 'Z';
outbus <= common XOR int_bus;
END exemplar;
The pullup function can be used for internals as shown. Use the
attributes for input pads.
There are ways to set attributes in verilog as well. The docs cover
how to use verilog comments to embed synthesis attributes.
> However, if I redefine the signal as an "inout" it works fine.
> Although this isn't really what the signal is, I don't think
> there is much harm in doing this. Any thoughts?
Yep, in VHDL it is very hard to "drive" an input. Attributes seem to
work best for pad located pullups.
-- Scott Bilik
Article: 9159I'm looking for a VHDL or Verilog core to do a simple DMA controller in an FPGA. I'm not looking for anything real fancy. I need to put 32 channel's worth of DMA into an FPGA and I want it to be cost effective. Some variation of an 8237 or a MC68450 ?? would be fine. If anyone can suggest sources for this, I'd appreciate it. Thanks, GaryArticle: 9160
Neurotech@t-online.de (Neurotech GmbH) wrote: >Has anybody out there already done a completely digital PLL inside an FPGA >? >I have to do an XC4028EX and one part of it shall be a programmable PLL >with >an input clock of about 300kHz and an output of about 10Mhz. But sometimes >I need exactly 9.998 MHz, sometimes 10.011 and so on, as precise as >possible. >Any idea ? >Holger Schuppan >Neurotech@T-Online.de You might consider an fpga to implement the phase detector , digital lead lag loop filter and control to an outside direct digital synthesizer ic like the analog devices types . Those nco's have 32 bit accumulators ,sine rom and dac included in the ic. They can control frequency in 1part in 2**32 from the reference. You need to understand how to compute the coefficients of your lead lag filter . H Girard hgirard@nsicomm.comArticle: 9161
High Speed Digital FPGA Hardware - Modem Technology Job Description: You will participate in the design and development of a flexible communications system breadboard utilizing FPGA's (ASIC) for Motorola's Celestri (tm) Modem Technology development program. These are specialized high-speed modems (Mbps) installed in satellites. Celestri is a multi-year, $13 billion project that will provide high-bandwidth packet switching - connections (e.g., internet) in outer SPACE!!! Celestial Data Communications for the 21st Century!!! Required: BS/MS in Electrical Engineering +4 to 6 years of experience. Familiarity with FPGA based design limitations and mitigation methods. Willingness to accept responsibility & technical challenge Ability to work independently and on a team Focus on customer satisfaction EMAIL your resume TODAY!!! ==> clientserver@msn.com Location: Phoenix/ Chandler, AZ Duration: Contact, Temp to Perm and Full Time Opportunities Pay Rate: $55,000 => $85,000 See our Website: < www.princetoninformation.com > Digital FPGA Hardware Designer - High Speed Digital Design - Modem Technology We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 4-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, Modem Technology development is a big PLUS!!! Experience with PLD's, FPGA's (ASIC), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. This is a great company! Our guarantee is this: If you go in and chat with these people, you WILL want to work there, especially if you can do this type of work. Our client is located in Chandler, Arizona. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail your resume TODAY===> clientserver@msn.comArticle: 9162
Mikhail Matusov wrote: > > This is not about the timing issue which is currently being thoroughly > discussed in another thread. > > My question is if anybody knows how registers are cleared during > power-up. > Is it done with global reset signal so that only those > registers that do not use product term reset are cleared No > or it is done with the same global reset but before reading user information No > or perhaps they are cleared with some hidden signal? Yes >From what I understand of the Data, this Async & 'hidden' global Reset is universal to ALL CPLD's. To activate, some brands need a VMin, and dV/dT spec ( ie is a CAP to a GATE ) and some brands have a 'harder' Vcc threshold sense. - jg -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Optimising Modula-2 Structured Text compilers for ALL 80X51 variants = Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55 = *NEW* Bondout ICE for 89C51/89C52/89C55. OptoISP for 89S, AVR, AT17K. = for more info, mailto:DesignTools@xtra.co.nz Subject : c51ToolsArticle: 9163
Long time ago I have asked this question: On Thu, 22 Jan 1998, Ho Siu Hung wrote: > I go into problems making use of only one CLB to build a 5 variable > function. While tied 4 of my inputs to the FMap and GMap, the last input > theoretically can be tied to the H1 to form a LUT with 5 inputs. However, > synopsis FPGA complier always map this to 2 or 3 CLB without utilizing > HMaps. Does anyone here have tried doing that? How to explicitly specify > the use of HMaps as mux? And I get one reply from a helper: On 22 Jan 1998, Richard Iachetta wrote: > David, you have to enable the feature of the XACT Design Manager called > "Generate 5-Input Functions". I think it defaults off. Its located in > the > Optimize & Map section of Implementation Options. I found that option. But seems XACT M1.3.7 will follow the synthesis result from my Synopsis 3.4b, that comes up with 3 CLBs for one five input function (that is LUT), even I turn on that option. Any option that I should touch inside Synopsis for utilizing H Maps? ------------------------------------------------------------------------------- | Best Regards, +--------+ | Email: eg_hsh@stu.ust.hk | | David Ho | ¦ó²Ðºµ | | cshosh@cs.ust.hk | | Ho Siu Hung +--------+ | | | University of Science and Technology | ICQ#: 798357 | | Computer Engineering Year 3 (CPEG) =======================================| -------------------------------------------------------------------------------Article: 9164
Scott Bedard wrote in message <6d1ltq$shv$1@news.ime.net>... >I work for a company that performs controls consulting services and we >recently came across a project that needs an EE engineer versed in FPGA >design. > >I have a couple of questions before I look for someone to fill the position. > >1) What does FPGA stand for? FPGA stands for Field Programmable Gate Array. You can find a deeper description at http://www.optimagic.com/faq.html#FPGA. There is a host of information available on-line on The Programmable Logic Jump Station at http://www.optimagic.com. >2) Can you give me an example of an FPGA application? FPGAs are found in a wide variety of digital logic applications. They typically support frequencies up to about 50-60 MHz and gate counts up to 25,000 and above. They're programmable, so it's easy and cost-effective to make custom circuits with FPGAs. Changes are nearly free. For very high volumes, you can convert a design to an ASIC, if it makes economic sense. > >If you live in the Boston area, please call me at 617-868-2955. > If you're looking for an FPGA-savvy designer in your area, you can find a list at http://www.optimagic.com/consultants.html#EasternUS. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com -----------------------------------------------------------Article: 9165
: : FPGAs are found in a wide variety of digital logic applications. They : typically support frequencies up to about 50-60 MHz and gate counts up to : 25,000 and above. They're programmable, so it's easy and cost-effective to : make custom circuits with FPGAs. Changes are nearly free. For very high : volumes, you can convert a design to an ASIC, if it makes economic sense. : That's one of the fields of applications ... a kind of substitute for ASIC in low volume or early stages of the applications or rapid prototyping. ....widely used in industry. More radical (and in my opinion more interesting) field is run-time reconfigurable computing. That's mostly still in the research community (there are very few commercially available products). The basic idea here is to allow the circuits buit in FPGA to reconfigure during the operation. A very good article-survey can be found in the December 97 issue of the IEEE Comupter magazine (pp. 38-43, Seeking Solutions in Configurable Computing). IlijaArticle: 9166
jim granville wrote: no,no,no,yes etc :v) From what I know - when a flex part downloads, the registers all start as reset. Some registers start in a SET state if there is a preset signal - so you can define the startup state. You can also set the start condition of the embedded memory arrays with a .MIF file. There is a global reset pin, but you must connect it with logic to the appropriate sites - then the startup state is defined by the logic level on this pin as well. Regards, Steven Groom Field Applcations Engineer Arrow Components (NZ) LtdArticle: 9167
> I go into problems making use of only one CLB to build a 5 variable > function. While tied 4 of my inputs to the FMap and GMap, the last input > theoretically can be tied to the H1 to form a LUT with 5 inputs. However, > synopsis FPGA complier always map this to 2 or 3 CLB without utilizing > HMaps. Does anyone here have tried doing that? How to explicitly specify > the use of HMaps as mux? For all XC4000 families (Classic, A, D, E, H, L, EX, XL, XLT) While you can map any function of 5 variables into two FMAPs (one is actually the G function generator, but you map it with a FMAP also), and the H function generator (with a HMAP), I have no reason to believe that the software is smart enough to do what you want. Although I can't directly address your synthesis tool path, let me explain what I do over in schematic land to achieve the type of results you seem to want. ( Of course, you could just convert to using schematics, and then if you followed my suggestions, all would be wonderful :-) In schematic land, if I want to pack an arbitrary function of 5 variables into a single CLB, I break it down into two functions of 4 variables (same 4 variables), with the two results and the remaining 5th variable feeding a function of 3 variables. The function of 3 variables can be a 2-to-1 mux, but could be any other gate as well, including input inversions, or even cascaded gates, such as a 2 input xor, feeding a 2 input and gate. I draw the the schematics for the 2 separate functions of 4 variables, and the function of 3 variables. I then connect an FMAP to the 4 inputs AND to the output net of that group. I do the same for the second 4 input section, i.e. same 4 inputs, but different output. From your description above, it sounds like you aren't doing this output of the FMAPs connection. I then take these two outputs, plus the remaining input signal, and connect them both to the function of 3 variables, and the HMAP. The output of the HMAP is connected to the output of the 3 variable function. To ensure that the logic is grouped the way I want, I than add an attribute to the 2 FMAPs, and the HMAP. Depending on the situation, one of the following should work: RLOC=RxCy Same x and y for all 3 maps BLKNM=bbbb Force all to be grouped together HBLKNM=ghgjgg Better way to force grouping, especially if part of a library To get this to work in synthesis, I suspect you will need to be somewhat heavy handed to force the output netlist to contain the same type of stuff that I get with schematics. Philip FreidinArticle: 9168
I'm looking at building an FPGA DES key searcher. I'm an experienced software engineer, but a babe in the woods when it comes to hardware design. I'm looking for info which would help me to program a demo board. It looks like this will take about 25k gates (~15-20 if I can reconfigure on the fly). I'm doing this on my own time, so I'm looking for info on: 1. cheap boards (<$500), which will work in a W95 system. 2. cheap or free SW which can work on pieces this size. 3. books and other sources for learning FPGA. thanks, Peter Trei trei!@ziplink.net PS: RSA Data Security is offering a $10k prize for a DES cracker this summer.Article: 9169
You should not need anywhere near 25k gates, provided you put the S-boxes in external EPROMs. The S-boxes are difficult to do - I don't think the XC4000 has wide enough RAM but I could be wrong. OTOH you might want to unroll the 16 loops into inline circuitry, and then yes you might need all the gates. I reckon you could do a DES decryption in the propagation delay of about 20 levels of logic - much less than 100ns in a top-speed FPGA. That's >10M keys/sec. And this is without doing any pipelining, like one decryption per clock, with a 16-clock initial latency. In fact such a design would be more difficult than simply unrolling the loop, and using a bigger device. You will then need a 56-bit comparator, for a (exact) known-plaintext attack, or something rather more complex if you just want to detect when the output is probably some human language (e.g. search for a ASCII character set across the 7 bytes). A very interesting project. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 9170
Erik Kobal wrote: > > We are looking to implement signal arrival time detection using the > correlation method. Our design involves a steady stream of 8-bit > samples at a sampling rate of 20 Msps. Our pattern that we are > attempting to match is 40 samples wide. Now the problem we have arrived > at is the following: we need to perform a 40x8 bit matrix > multiplication. This is only the root of our design problem, since our > application is multichannel. We are not sure whether our design would > work best using a standard DSP, or whether we should use an FPGA to > allow for multiplication in parallel. Any information would be much > appreciated. > > Thank you, > > Erik Kobal, Cleveland State University Assuming your reference is relatively constant, correlation is the same arithmatic operation as FIR filtering with the order of the coefficients reversed. That said, FIR filtering using FPGAs is well documented in app notes from many of the FPGA vendors. The method described in the Xilinx and Altera notes uses a distributed arithmetic technique that essentially breaks the multiplications into partial products, thereby avoiding the need for multipliers. The 20 MSPS rate at 40 taps is easy to do using distributed arithmetic in an FPGA. Off the top of my head, I think each filter will occupy somewhere about 100 Xilinx CLBs to get this data rate. A single DSP won't even get close to 20MSps at 40 taps. Xilinx also describes a symbol correlator in their literature, but that is not what you are looking for. That design correlates a bit stream to find occurrences of a reference pattern. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka Andraka Consulting Group, Inc is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 9171
Thank you for all the information you all provided about FPGA's. I would like to ask a few more questions so as to hopefully get a little more insight. What we need to accomplish is this: We need 16 correlators for 16 channels. Each correlator will need two FIR filters. We are looking to have 40 taps in our application, but we would do fine with 32. Each FIR filter must handle a throughput of 20 MSPS. In the Altera application notes on implementing FIR filters, I read that you can have serial or parallel FIR filters, or a hybrid of the two. Also, the pplication notes mentioned that there are off the shelf FIR filters that can accomadate about 30 MSPS. We would like to look into this as a possible solution instead of programming an FPGA to perform the same function. Would anybody have any insight what would be the best way to go about this? Any help would be greatly appreciated. Thanks again! Erik L. Kobal -- Cleveland State UniversityArticle: 9172
> I'm looking for info which would help me to program a demo board. > It looks like this will take about 25k gates (~15-20 if I can > reconfigure on the fly). > If you are interested in reconfiguration, may I suggest the board put out by Virtual Computer Corp. While is is a little higher than your $500 threshold at $995, it comes complete with all the tools you'll need to play with it, including the LOLA language which gives you a software-like FPGA programming language. The PCI board uses a Xilinx 6200 part. You can check out their website,at http://www.vcc.com/ Tell them I sent you. Other solutions will likely coast you as much by the time you buy the hardware and the tools (if you are a student you can probably do better) -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 9173
Neurotech GmbH wrote: > > Has anybody out there already done a completely digital PLL inside an FPGA > ? > I have to do an XC4028EX and one part of it shall be a programmable PLL > with > an input clock of about 300kHz and an output of about 10Mhz. But sometimes > I need exactly 9.998 MHz, sometimes 10.011 and so on, as precise as > possible. To get the accuracy you are stating here, you will need an extremely high master clock for a totally digital PLL. Too high for current FPGAs unless you limit the desired frequencies and/or accept a lot of jitter. DPLLs are fairly straight forward, but do suffer when the output frequency is not << the master clock. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 9174
Koenraad Schelfhout VH14 8993 wrote: > > I got also a problem with the automatic fast/IO. > This was in version 8.11 (I don't know in version 8.2) > I saw this problem too. You can turn it off and put fast attributes on all of the pins to work around it.
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