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Karl Andersson wrote: > We are working on a project whit the ALTERA Chips > But the we need more" Logic Blocks" i think we need 15 000 . > On each "Block" we only use very litle of the functions. It's hard to give advice with so little information. Please tell us: - what you mean by a "logic block"? - why do you need more? - what are you trying to do? - what architecture are you targeting - and why? Rune BaeverrudArticle: 7826
Hi, I am having trouble configuring my FLEX8000 device (8636A-84pin PLCC/-4 speed grade). I have a smart controller on my project - Intel's 386EX and therefore I use the Passive-Parallel-async configuration scheme. I created an array of bytes from MAX+PLUS II v8.0 TTF file output for use in my embedded C program. 1. I create a high-low-high transition in the nCONFIG line 2. wait for nSTATUS to go high 3. I poll the RDYnBUSY line for ready state (high) 4. I do a I/O write cycle to the FLEX address and write the next byte from the array. 5. I check if nSTATUS gone low = frame error. 6. repeat steps 2-5 for the exact number of bytes needed to be loaded (sizeof (arraybytes)) 7. wait for conf_done. This won't succeed in loading the device. I am working with a Kontron KSE5 386EX ICE - a logic analyzer shows me I get frame error (nSTATUS goes low for a few microsecs) - but all the timings are correct. I checked the 10 first bytes on the logic anal. - and I get good results - also for the last 10 bytes - but the conf_done won't go high because of the frame error, the data in the whereabouts of the frame error IS uncorrect - but I don't understand why. I tried to burn this flex loader program to my ROMs - and install a real CPU. I get the following results: 1. I got a MAXIM705 reset circuit which gives reset signal to CPU when voltage drops below 4.6V or when pushbutton pressed. 2. The CPU get resets while it tries to load the FLEX. 3. The FLEX device probably consumes high sudden currents which cause a voltage drop - that also might be the reason why the data corrupted - the ICE suppply voltage dropped! 4. I got no reset/voltage problems whatsoever when the Altera FLEX8000 device is not in its socket. 5. Tried to add more capacitors to the GND and VCC of the FLEX, MAXIM705 devices - no good. What's wrong? How can I finish loading this device successfully without special power-consumption needs? Thanks a million in advance. --== Ido Kleinman ==-- kleinn@erez.cc.biu.ac.ilArticle: 7827
I've developed a Flex10k PLD design with Max Plus II version 8.0 and want to add the component to a Cadence Concept schematic. I've used "redifnet" utility to create the symbol (*.body file). Does anyone know how I can automatically generate the pinout information (chips_prt file) from the ediff file (*.edo)? Marty Hoffensetz CAE MRad Pty Ltd Adelaide, Australia marty@mrad.com.auArticle: 7828
Jacob W Janovetz wrote: > My question is this: Why does Leonardo add the BUFG to the > pin? It isn't necessary, right? It just helps in making timing > a little better. Because I don't have CS5 connected to a GCK, > how can I force Leonardo (through VHDL) to connect it to a > standard IBUF? Should I define the IBUF as a component in VHDL? During synthesis you can add a buffer of whatever type you like by typing the command "buffer_sig buffer_type signal_name" on the command line. For example, "buffer_sig BUFGP clk" will add a BUFGP type buffer to the clk input. Note, this will not be apparent in netscope or anywhere else until after optimisation, when the technology mapping is done. The same thing can be done in the VHDL source by adding an attribute to the selected signal, for example: attribute BUFFER_SIG of clk : SIGNAL IS "BUFGP"; You could also manually instantiate the buffer in the source VHDL but that will make your source code technology-dependant. See page 6-48 of the Synthesis and Technology Guide for more information. -- Alasdair MacLean, Development Engineer, GEC Marconi Electro-Optics Ltd., GNET: 709-5711; Tel: +44 (0)131 343 5711 Fax: +44 (0)131 343 5050 Email: <mailto:alasdair.maclean@gecm.com>Article: 7829
Christian Schaefer asks: > > > What are the relations between Synopsys estimates, XACT "packed > CLBs" and the actual used number of CLBs? The XACT manual says > nothing about "packed CLBs". > Synopsys performs an estimate of the CLB's it can see. It does not know how many CLBs are consumed by a designware function. For instance if you instantiate a counter in your code, synopsys will look in its designware libraries (starting with those provided by the silicon vendor) to find a counter. When it finds one, it drops it in. Synopsys can not optimize it, and can't count number of CLBs it requires. Packed CLBs differ from unpacked (?) CLBs in that the unpacked (?) CLBs are generally used to improve the routing but don't use the flip flops in the CLB. Packed CLBs are those with LUT and FF used. Cheers Tim. -- Strong words softly spoken. My opinions != Nortel's opinion.Article: 7830
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Martin Hoffensetz wrote:
>
> I've developed a Flex10k PLD design with Max Plus II version 8.0 and
> want to add the component to a Cadence Concept schematic. I've used
> "redifnet" utility to create the symbol (*.body file). Does anyone
> know how I can automatically generate the pinout information (chips_prt
> file) from the ediff file (*.edo)?
we had the same problem, and wrote our own tools to do it.
we get the ACF and verilog output from MaxplusII, then
write out a chips_prt file and use genview to create a body.
you must back-annotate your design to get the pinout into
the ACF (and quit maxplusII to write out the ACF).
since you have to add the VCC/GND pins as well as the programming
pins (they aren't in the ACF file), we created a small library
for each Altera part we have used so far.
i have attached a uuencoded tar file with our stuff.
good luck!
guy
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end
--------------41262BF23E4C--
Article: 7831Yup they have both 8 pin DIL and 28 pin PLCC, all in the data book, and I think its an EPC1, but don't quote me on that In article <627peh$1vga@info4.rus.uni-stuttgart.de>, Andreas Wehr <wehr@mikro.uni-stuttgart.de> writes > >Hi, > >can anybody tell me if there are serial EEPROMs available for >ALTERA FLEX10K devices? > >Thanks, >Andreas > -- David AtkinsArticle: 7832
We can't use xc40005apq160 boundary scan correctly. Example: We drive pins 118.o, 118.t, 177.o and 117.t (the nearest to tdo pin) from internal logic with the values 0 , 1 , 1 , 0 respectively.We test them by oscilloscope: pin 118 is 3-state, 117 is high as expected. We load sample instruction ( I0=1, I1=I2=0) on IR, and , in the Shift DR state we obtain the data 1 (update?) , 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 0, instead of the expected 1(update), 1, 0, X, 0, 1, X, ......... The Bypass instruction works, DR and IR shift correctly during Shift DR and Shift IR states, the TAP controller seems to work. Thanks for your kind answer! Giovanni Mojoli and Sandro Pastore, IFCTR-CNR MilanArticle: 7833
Marc 'Nepomuk' Heuler wrote: > > In article <34471910.1240@ecs.soton.ac.uk.nojunk>, Tim Forcer writes: > > > General comment for people considering using ipsLSI - I think the > > Lattice starter kit is good value, particularly if you get it as part of > > the deal for attending an introductory seminar/presentation. I also > > think Lattice pDS is lousy value. Shame as I find the ICs useful. > > On the free CD, there is a Lattice ISP version of Synario. I use this to > program standard GALs and the isp 1016. ABEL HDL is very nice for being > free. It runs on Win95 and shows you simulation results graphically. > > I also have the starter kit, but never installed the software. hi, i have a sizable library of generic modules i have written for the synario system, that works with the versin lattice gives away. if anyone wants a copy, let me know. bob engle embedded solutions rengle@ix.netcom.comArticle: 7834
Earlier this year IDT announced last buy on their 49c402 16 bit microprocessor slice device. Unfortunately, the second source for this device discontinued earlier. If you have any interest in a VDHL implementation of this device, development on this began earlier this summer. For further info, please send email to rich at rfs@mho.net.Article: 7835
This article cancelled within Tin.Article: 7836
In article <34471910.1240@ecs.soton.ac.uk.nojunk>, Tim Forcer writes: > General comment for people considering using ipsLSI - I think the > Lattice starter kit is good value, particularly if you get it as part of > the deal for attending an introductory seminar/presentation. I also > think Lattice pDS is lousy value. Shame as I find the ICs useful. On the free CD, there is a Lattice ISP version of Synario. I use this to program standard GALs and the isp 1016. ABEL HDL is very nice for being free. It runs on Win95 and shows you simulation results graphically. I also have the starter kit, but never installed the software.Article: 7837
In article <34471910.1240@ecs.soton.ac.uk.nojunk>, Tim Forcer writes: > General comment for people considering using ipsLSI - I think the > Lattice starter kit is good value, particularly if you get it as part of > the deal for attending an introductory seminar/presentation. I also > think Lattice pDS is lousy value. Shame as I find the ICs useful. On the free CD, there is a Lattice ISP version of Synario. I use this to program standard GALs and the isp 1016. ABEL HDL is very nice for being free. It runs on Win95 and shows you simulation results graphically. I also have the starter kit, but never installed the software. ========= WAS CANCELLED BY =======: Rogue cancel from Michael Enlow, X-Cancelled-by etc. are forged. Further information can be acquired at http://www.sputum.com/ucepage.htm You can express your displeasure with Mr. Enlow by contacting him at: enlow@direcpc.com Control: cancel <KiWfB*f8e@aargh.mayn.de>Article: 7838
In article <34471910.1240@ecs.soton.ac.uk.nojunk>, Tim Forcer writes: > General comment for people considering using ipsLSI - I think the > Lattice starter kit is good value, particularly if you get it as part of > the deal for attending an introductory seminar/presentation. I also > think Lattice pDS is lousy value. Shame as I find the ICs useful. On the free CD, there is a Lattice ISP version of Synario. I use this to program standard GALs and the isp 1016. ABEL HDL is very nice for being free. It runs on Win95 and shows you simulation results graphically. I also have the starter kit, but never installed the software. ========= WAS CANCELLED BY =======: Rogue cancel from Michael Enlow, X-Cancelled-by etc. are forged. Further information can be acquired at http://www.sputum.com/ucepage.htm You can express your displeasure with Mr. Enlow by contacting him at: enlow@direcpc.com Control: cancel <KiWfB*f8e@aargh.mayn.de>Article: 7839
On 18 Oct 1997 16:43:33 GMT, janovetz@ews.uiuc.edu (Jacob W Janovetz) wrote: [snip] > My question is this: Why does Leonardo add the BUFG to the >pin? It isn't necessary, right? It just helps in making timing >a little better. Because I don't have CS5 connected to a GCK, >how can I force Leonardo (through VHDL) to connect it to a >standard IBUF? Should I define the IBUF as a component in VHDL? > > Thanks for any notes on this. Perhaps someone can recommend >a different way to handle this, too... > > Cheers, > Jake Hi Jake, You can force Leonardo to use standard IBUFs by unsetting the insert_global_bufs variable. To do this either issue the command "set insert_global_bufs FALSE" or unselect the "Map to Clock/Global Buffers" box in the advanced dialog of the "Optimize" dialog. Hope this helps. Dave -- Development Engineer | e-mail: david.storrar@gecm.com GEC-Marconi Avionics | Tel: +44 (0)131 343 4729 Radar Systems Division | Fax: +44 (0)131 343 4091 --Article: 7840
ecffung@ntu.edu.sg wrote in article <01bcd976$f224d640$0302459b@CHIFUNG.ntu.edu.sg>... > When implementing numerical algorithms (e.g. DCT) on FPGA using VHDL, do I > need > to translate my algorithm into logic function before I can code it in VHDL? > Or, is it > possible to describe a numerical algorithm directly using VHDL and let the > FPGA > tool to synthese the required logic function? The answer to your question is no, you do NOT have to provide the structural representation in VHDL prior to synthesis. That is a function of your software. ---BUT--- From your point of view, you will have to select a FPGA that is large enough to fit what you are trying to accomplish. Doing so blindly, with no respect to synthesis, could be costly in the long haul, because you could end up selecting a part that is larger than it needs to be (more gates == more $$$). Many software systems allow the floor planner to optimize for speed, for size, to balance, etc. All that you can do is realize and test the design first in the biggest part that you can afford, and THEN start optimizing size, speed, both, etc. until you get it down to the size and speed that you can afford. Good luck. pgd -- "In matters of style, swim with the current; in matters of principle, stand like a rock." -- Thomas Jefferson Paul Duncan Airak Engineering RR3 Box 533 415 Chestnut Avenue New Castle, VA 24127-9519 grems at swva dot netArticle: 7841
Ido Kleinman (kleinn@erez.cc.biu.ac.il) wrote: : 1. I create a high-low-high transition in the nCONFIG line : 2. wait for nSTATUS to go high Make sure that the nCONFIG pulse is long enough (ca. 2 microseconds). Also before you start writing put some delay. Altera says that the delay should be about 5 microseconds and I have seen nSTATUS go up earlier (BTW, in my design I don't even test it, I just wait after the nCONFIG pulse and it works for me). : 3. I poll the RDYnBUSY line for ready state (high) : 4. I do a I/O write cycle to the FLEX address and write the next byte from : the array. : 5. I check if nSTATUS gone low = frame error. : 6. repeat steps 2-5 for the exact number of bytes needed to be loaded : (sizeof (arraybytes)) : 7. wait for conf_done. This scheme works fine for me. BTW, what do you do with CS and nCS signals. I keep them high and low respecitvely (i.e. active) during the entire configuration. Also instead of polling RDYnBSY signal in software, you can use it to drive the IOCHRDY signal on the ISA bus and let the bus controller add wait states as necessary. Also make sure that you are reading the file properly. I prefer using RBF instead of TTF and read it as the binary file. IlijaArticle: 7842
Hi, Is anyone aware of any problems relating to the back annotation to VHDL of a design placed and routed in Foundry 9.1? I'm targeting an OR2C40A and, after place and route, the design meets all my PERIOD constraints supplied in the .prf file (as reported by trace), but when the design is back annotated simulations show that the design is not meeting the required period (setup warnings reported). Which should I believe - the PAR results, or the back annotated results? Cheers, Dave -- Development Engineer | e-mail: david.storrar@gecm.com GEC-Marconi Avionics | Tel: +44 (0)131 343 4729 Radar Systems Division | Fax: +44 (0)131 343 4091 --Article: 7843
Does anyone want a FREE commercial Web Site? Go to http://maxpages.com Personal Web Sites are OK too.Article: 7844
Hi all, There is a smidge of a problem when designing with the 5200 using the current Xilinx libraries. The AND2B1 gate has its inputs swapped. The work around is to design your own AND2B1 with an and gate and an inverter. This will be fixed in the next release of software apparently. Just thought you might like to know Tony -- Sent By tony.cooper@virgin.netArticle: 7845
I received the latest version of MAXplus+II (8.1) and installed it on my HP-UX 9.05 system, but it doesn't run. It complains that it can't find /usr/lib/dld.sl (which does not exist on my system). Previous versions of MAXplus+II have run on my system fine without any trouble. Altera says they only support HP-UX 10.20. Has anyone else tried to get MAXplus+II working on an older version of HP-UX? Have you succeeded yet? I don't want to go through a major system upgrade just to get MAXplus+II working. Thanks, Guy Lemieux lemieux@eecg.toronto.eduArticle: 7846
In article <344E5BA3.61DC@ix.netcom.com>, "Robert E. Engle Jr." <rengle@ix.netcom.com> writes >Robert E. Engle Jr. wrote: >> >> hi, i have a sizable library of generic modules i have written for the >> synario system, that works with the versin lattice gives away. if anyone >> wants a copy, let me know. > >rather than e-mail it out, here it is. Thats TWICE I spent time and money downloading this file AND I DONT WANT IT! So I hereby send it back to you. [ Section: 1/1 File: generic.zip Encoder: Turnpike Version 3.03a ] begin 644 generic.zip M4$L#!!0````(`$BE\B+6U^FODP<``-H/```,````0DE02$%313$N4T-(I5?9 Loads of junk deletedArticle: 7847
In article <pFC6NCAtKnT0EwFg@devantech.demon.co.uk>, Gerald Coe <gerry@devantech.demon.co.uk> writes >In article <344E5BA3.61DC@ix.netcom.com>, "Robert E. Engle Jr." ><rengle@ix.netcom.com> writes >>Robert E. Engle Jr. wrote: >>> >>> hi, i have a sizable library of generic modules i have written for the >>> synario system, that works with the versin lattice gives away. if anyone >>> wants a copy, let me know. >> >>rather than e-mail it out, here it is. > >Thats TWICE I spent time and money downloading this file >AND I DONT WANT IT! >So I hereby send it back to you. >[ A UUEncoded file (generic.zip) was included here. ] > Oh! Jesus! What have I done. This was supposed to be emailed to the spammer. And now I've just done the same. I feel a complete idiot. This guy also posted this to another newsgroup, I forget wich one, and when I saw it here as well I saw RED. My profuse an unreserved apologies everyone. I shall pay more attention to what I'm doing next time. -- Kindest Regards, Gerald Coe | We manufacture Pic programmers as well gerry@devantech.demon.co.uk | as 8031, 64180, 80C188EB cpu modules http://www.devantech.demon.co.uk | and a range of C compilers/assemblersArticle: 7848
Sandro Pastore <lau3@promethephs.ifctr.mi.cnr.it> wrote:
:We can't use xc40005apq160 boundary scan correctly.
[snip]
I was able (after some clarification from Xilinx) to use BS
successfuly, to configure the device. The design is on my website, at
http://www.iinet.net.au/~daveb/tricks/fpga-ldr/loader.html
Hope this helps,
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7849Homeworkers Urgently Needed! I Need Mailing Lists and Dependable People Your Junk Mail is Worth $$$$ for details send a large, SASE and $2 for shipping and handling to: Jim Appenzeller 15 Paulus Blvd New Brunswick, NJ 08901
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