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For those interested in a COMPLETE solution to LUCENT FPGA development, APS is now offering COMPLETE LUCENT kits which include the following features: > VHDL Context Sensitive Editor > Full VHDL Simulation with VITAL Support > Full VHDL Synthesis integrated into theVHDL Simulator IDE > Full APEX ORCA ROUTER > APS-L84 FPGA development Board (with DDS, DA, SRAM options) These full featured kits are available now.The simulator is a full featured VHDL simulator with VITAL, source code debugger and context sensitive editor. This kit allows you to go through all aspects of FPGA development including : >Pre-Route VHDL Simulation >VHDL Code Synthesis >ORCA PART ROUTER >Post Route VITAL VHDL Simulation >Hardware downloading and real time evaluation The kits also have upgrade paths to XILINX,ALTERA,ACTEL,QUICKLOGIC,LATTICE,and VANTIS parts in our Synth-All VHDL series! The entire top-end kit sells for $4995.00 !!! Lower priced base options are available. There are No better values available for Lucent FPGA development! see http://www.associatedpro.com/apsArticle: 7851
Are there documented floating point implemenations using FPGAs? Specifically, I am looking for the MFLOP performance that was achieved. I have been told that FP using FPGA can be slow due to the inefficient implementation of barrel shifters, among other components, within the FPGA. Thank, Ken.Article: 7852
Greetings, There was a rumor that a new version of Alliance was going to be released last month (September). However, I checked the web site today (ftp://cao-vlsi.ibp.fr) and there was no trace of it. Does anybody know what is going on? Is there really any ongoing work on updating Alliance? The current version only supports a subset of VHDL 1987. Thanks for any info. LevyArticle: 7853
Levy Lazarre <lazarre@scooby.lklnd.udf.edu> wrote: >Greetings, > There was a rumor that a new version of Alliance was going to be >released last month (September). However, I checked the web site today >(ftp://cao-vlsi.ibp.fr) and there was no trace of it. Does anybody know >what is going on? Is there really any ongoing work on updating Alliance? >The current version only supports a subset of VHDL 1987. >Thanks for any info. >Levy I would guess that this is just a rumor. THe last I heard was that all work had stopped. Alliance was developed at a university, mostly by grad students who have long since moved on. Unless someone has come along and picked up the project, it is all but dead. Tim Olmstead webmaster of the CP/M Unofficial web page http://cdl.uta.edu/cpmArticle: 7854
kasmjs@erols.com wrote: > > Are there documented floating point implemenations using FPGAs? > Specifically, I am looking for the MFLOP performance that was achieved. I > have been told that FP using FPGA can be slow due to the inefficient > implementation of barrel shifters, among other components, within the > FPGA. > > Thank, > > Ken. I am not sure what type of operations you need to perform, but I am doing 1) fixed to float, 2) float * float, 3) float / float 4)renormalization, 5)float to fixed operations. I have implemented these in a 10K50-3. They are extremely pipelined, but run at 70MHz. The resolution of the mantisa is 14 bits, while the exponent is 8 bits.Article: 7855
On 17 Oct 1997, Andreas Wehr wrote: > > Hi, > > can anybody tell me if there are serial EEPROMs available for > ALTERA FLEX10K devices? > > Thanks, > Andreas > Hi Andrea, For FLEX 10k, the EPROM is called EPC1 (Altera reference). There are no EEPROMS. If you need a re-programmable solution for testing, you can use a Bitblaster download cable, that you can deconnect after the data has been transfered. This is what I'm using. Andy Negoi +--------------------------------------+------------------------------------+ | Andy NEGOI | Laboratoire de Physique des | | Tel: +(33) 4 76 85 60 00 poste 6201 | Composants a Semiconducteurs, INPG | | Fax: +(33) 4 76 85 60 70 | 23 Rue des Martyrs B.P. 257 | | e-mail: negoi@enserg.fr | 38016 Grenoble - France | +--------------------------------------+------------------------------------+Article: 7856
Hey - If you've recently acquired Synplicity or Exemplar or are considering doing so I'd like to talk with you. We're doing a market research report on FPGA synthesis tools. If you've ever griped "Why don't EDA manufacturers ever listen to us" here is your chance to get your input and feature requests heard. Give me a call or drop me an email to w a d e n e l s o n @ f r o n t i e r . n e t Wade Nelson, Analyst, TACTICS Market Research Phone 970 259 1494Article: 7857
Let me be the first to flame :
EPC1 is an EPROM supplied in OTP package. It is not an EEPROM, something
many altera customers would like. It is not always convenient to use the
byteblaster to programme Altera's FLEX 10K parts when prototyping.
Some have suggested the atmel 17Cxxx serial EEPROMs, but these parts do not
generate their own clock, which is essential for programming the FLEX 10K parts
without additional external logic.
Steve
In article <HRe7ADAT76S0Iwh9@broadside.demon.co.uk>
david@broadside.demon.co.uk "David Atkins" writes:
> Yup
>
> they have both 8 pin DIL and 28 pin PLCC,
>
> all in the data book, and I think its an EPC1, but don't quote me on
> that
>
> In article <627peh$1vga@info4.rus.uni-stuttgart.de>, Andreas Wehr
> <wehr@mikro.uni-stuttgart.de> writes
> >
> >Hi,
> >
> >can anybody tell me if there are serial EEPROMs available for
> >ALTERA FLEX10K devices?
> >
> >Thanks,
> >Andreas
> >
>
> --
> David Atkins
>
--
Steve Dewey
Steve@s-dewey.demon.co.uk
Too boring to have an interesting or witty .sig file.
Article: 7858See http://cao-vlsi.ibp.fr/alliance/index.fr.html for announcement. Salman timolmst@cyberramp.net wrote: > > Levy Lazarre <lazarre@scooby.lklnd.udf.edu> wrote: > > >Greetings, > > There was a rumor that a new version of Alliance was going to be > >released last month (September). However, I checked the web site today > >(ftp://cao-vlsi.ibp.fr) and there was no trace of it. Does anybody know > >what is going on? Is there really any ongoing work on updating Alliance? > >The current version only supports a subset of VHDL 1987. > >Thanks for any info. > >Levy > > I would guess that this is just a rumor. THe last I heard was that all > work had stopped. Alliance was developed at a university, mostly by > grad students who have long since moved on. Unless someone has come > along and picked up the project, it is all but dead. > > Tim Olmstead > webmaster of the CP/M Unofficial web page > http://cdl.uta.edu/cpm -- ******************************************************************** Visit the Islam Page http://www.wam.umd.edu/~ibrahim ********************************************************************Article: 7859
PAPER SUBMISSION DEADLINE EXTENSION FOR CSD'98 International Conference on Application of Concurrency to System Design There have been several requests for an extension of the deadline for paper submission to the conference. The Technical Committee has been able to set up a review process by e-mail that allowed us to grant such an extension. We request every prospective author to (1) send to the Program Chairs (reisig@informatik.hu-berlin.de, luciano@cadence.com) BY E-MAIL a PLAIN TEXT FILE with the title and abstract of the paper by October 31. (2) send to the Program Chairs BY E-MAIL a POSTSCRIPT FILE with the content of the paper by November 15. The postscript file should be generated (with the maximum portability options (e.g. if you produce it from Word or FrameMaker). Compression (pkzip or gzip) and encoding (uuencode or base64) is acceptable, and recommended for large papers (above 100K). The second e-mail should also contain, in plain text form, the cover page with the authors' addresses (including that cover page in postscript form is acceptable). =========================================================== International Conference on Application of Concurrency to System Design (CSD'98) March 23-26, 1998, Aizu-Wakamatsu, Japan Sponsored by: The IEEE Computer Society - VLSI-TC, The IEICE TG on Concurrent System Technology, The SICE TG on Discrete Event Systems, The IMACS scientific association In Cooperation With: IFIP WG 10.3, 10.5, The University of Aizu The UN University/IIST, Formal Methods Europe GENERAL CHAIR: Shoichi Noguchi - noguchi@u-aizu.ac.jp The University of Aizu, Japan PROGRAM CHAIRS: Wolfgang Reisig (theory) Humboldt Universitat zu Berlin, Germany reisig@informatik.hu-berlin.de tel.+49-30-20181219, fax:+49-30-20181221 Luciano Lavagno (application) Politecnico di Torino, Italy Cadence Berkeley Labs, USA lavagno@polito.it, luciano@cadence.com tel.+39-11-5644150, fax:+39-11-5644099 CONFERENCE CO-CHAIRS: Sadatoshi Kumagai - Osaka Univ., Japan kumagai@pwr.eng.osaka-u.ac.jp tel.+81-06-879-7693, fax:+81-06-875-2672 Alex Kondratyev - kondraty@u-aizu.ac.jp The University of Aizu, Japan tel.+81-242-372557, fax:+81-242-372744 PUBLICATION CHAIR: Masaru Naniwada - NEC Corp., Japan, naniwada@pepo.tmg.nec.co.jp PUBLICITY CHAIR: Tomohiro Yoneda - yoneda@cs.titech.ac.jp, Tokyo Institute of Technology, Japan FINANCE CHAIR: Kazuaki Yamauchi - yamauchi@u-aizu.ac.jp The University of Aizu, Japan LOCAL ARRANGEMENT CHAIR: Yuko Kesen - kesen@u-aizu.ac.jp The University of Aizu, Japan TUTORIAL/CAD BOOTH CHAIR: Alexander Taubin - taubin@u-aizu.ac.jp The University of Aizu,Japan INDUSTRY RELATIONS: Shinichi Honiden - Toshiba Corp., Japan, honiden@ssel.toshiba.co.jp Yoshihiro Ueda - OkI Electric, Japan ueda@wbg.telcom.oki.co.jp Naoshi Uchihira - Toshiba Corp., Japan, uchi@ssel.toshiba.co.jp The International Conference on Application of Concurrency to System Design is being organized as a forum for disseminating advanced research results on theory and practice of design of concurrent systems. While there are a few ``success stories'' in this field, there is a real need to provide practitioners with adequately sound and expressive tools, and researchers with real motivations and examples. The aim of this conference is to contribute towards this goal by bringing together experts in a wide variety of fields related to complex concurrent system design and analysis. TOPICS OF INTEREST: Formal and semi-formal models: Petri nets, Temporal Logics, Data Flow nets, Statecharts, Synchronous Languages, HDLs, etc. Formal methods for CAD and verification of concurrent systems: model checking, asynchronous design, high-level synthesis, hardware/software co-design, etc. Real-time and hybrid systems Case studies of concurrent systems design and verification Presentation of software tools supporting the above topics PAPERS: Submitted papers should be no more than 15 pages in 11-point font with a 60-word abstract, and should include a cover page with authors' physical and e-mail addresses, phone and FAX numbers. Prospective authors should submit BY EMAIL a text file containing the title and an abstract by October 30, and a postscript file containing the FULL manuscript and a cover page by November 15, 1997 to: (1) Theoretical papers: Wolfgang Reisig reisig@informatik.hu-berlin.de (2) Application papers: Luciano Lavagno luciano@cadence.com Accepted papers are intended to appear in series by the IEEE Computer Society Press. A limited number of travel grants will be available for conference contributors. INFORMATION: The University of Aizu: csd@u-aizu.ac.jp, Phone : (+81) 242 37 2557, Fax : (+81) 242 37 2744 On the World Wide Web at URL: http://www.u-aizu.ac.jp/csd98/ IMPORTANT DATES: Abstracts due BY EMAIL: October 30, 1997 Papers due BY EMAIL: November 15, 1997 Notification of acceptance by: December 1, 1997 Final Version by: January 5, 1998 PROGRAM COMMITTEE: Gerard Berry (France) Manfred Broy (Germany) Roy Campbell (USA) Edmund Clarke (USA) Jordi Cortadella (Spain) Jorg Desel (Germany) Javier Esparza (Germany) Jean-Luc Gaudiot (USA) Kunihiko Hiraishi (Japan) Rene Jacquart (France) Tomasz Janowski (Macau) Timothy Kam (USA) Shmuel Katz (Israel) Michael Kishinevsky (Japan) Bob Kurshan (USA) Edward Lee (USA) Dong-Ik Lee (Korea) Shin-ichi Minato (Japan) Takashi Nanya (Japan) Mogens Nielsen (Denmark) Kenji Onaga (Japan) Carl Pixley (USA) Patrick Scaglia (USA) Fabio Somenzi (USA) Pasupathy Subrahmanyam (USA) Achim Sydow (Germany) P.S. Thiagarajan (India) Antti Valmari (Finland) Jim Woodcock (UK) Zhou Chaochen (Macau) =========================================================== -- Kind regards Alexander Taubin THE UNIVERSITY OF AIZU phone +81-242-37-2572 (office) Tsuruga, Ikki-machi, Aizu-Wakamatsu City fax +81-242-37-2744 Fukushima, 965-80 Japan e-mail taubin@u-aizu.ac.jp ---- <A HREF="http://www.u-aizu.ac.jp/~taubin/">------------------------Article: 7860
Hi Folks, I am looking for any information on Wallace tree implementations of Multipliers. I am working on an 8x8 version, and had some files previously designed by another designer, but what is going on is not completely clear. Thus, if anyone has any information I woudl appreciate it. Tony app01@aol.comArticle: 7861
Is there anyone who has done an I2C controller in an FPGA? Thanks, Austin Franklin darkroom@ix.netcom.com to e-mail a reply to this post, remove the number from the reply addressArticle: 7862
Hello...
I have a 'should it be done' question. We have a PC/104 embedded
system (ISA bus) and want to put a Xilinx part on a board with
the PC/104 connector. I'm wondering if it is ok to place the
FPGA directly on the bus (ie without the traditional 74245
bidirectional buffers). When the Xilinx is programming or is
unprogrammed, the pins are in a weak pullup state which should be
ok for the ISA bus.
I've tried this in a prototype situation and everything is
working fine. I can reprogram the Xilinx in-circuit and it doesn't
screw up the PC/104 system. I'm just wondering if this is a
common practice and if it will be reliable between PC/104 systems
and such.
As an unrelated question, during an I/O write, data is latched
(by the FPGA) on the rising edge of IOW*. Does this mean a signal
like this (IOW*) should be on a clock pin of the FPGA to allow a
BUFG to be attached to it?
Cheers,
Jake
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.cen.uiuc.edu/~janovetz/index.html
Article: 7863Jacob W Janovetz wrote: > > Hello... > > I have a 'should it be done' question. We have a PC/104 embedded > system (ISA bus) and want to put a Xilinx part on a board with > the PC/104 connector. I'm wondering if it is ok to place the > FPGA directly on the bus (ie without the traditional 74245 > bidirectional buffers). When the Xilinx is programming or is > unprogrammed, the pins are in a weak pullup state which should be > ok for the ISA bus. > > I've tried this in a prototype situation and everything is > working fine. I can reprogram the Xilinx in-circuit and it doesn't > screw up the PC/104 system. I'm just wondering if this is a > common practice and if it will be reliable between PC/104 systems > and such. > > As an unrelated question, during an I/O write, data is latched > (by the FPGA) on the rising edge of IOW*. Does this mean a signal > like this (IOW*) should be on a clock pin of the FPGA to allow a > BUFG to be attached to it? > > Cheers, > Jake I've done this with out any problems. Just make sure your logic is in a controlled (ISA happy) state when the xilinx exits its programming mode. IOW: You could always route IOW internally to a secondary clock net. Xact will do this automatically. If you don't use a clock net, be very carfull when you review your timing delays using XDELAY. ************** Remove [ANTI_SPAM] to reply **************Article: 7864
Austin Franklin wrote: > > Is there anyone who has done an I2C controller in an FPGA? > > Thanks, > > Austin Franklin > darkroom@ix.netcom.com > > to e-mail a reply to this post, remove the number from the reply address do you need master or slave function? bob engle embedded solutions rengle@ix.netcom.comArticle: 7865
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Article: 7866[snip, snip] > > Is there anyone who has done an I2C controller in an FPGA? > > do you need master or slave function? Yes.Article: 7867
Visit http://www.silicon-systems.com for a free 45 day evaluation of ED4W-HDL, a VHDL and Verilog aware editor. Features include, syntax highlighting, Automatic testbench generation, dozens of free VHDL models, Multi-file search. Regards, JohnArticle: 7868
Memec Design Services has a module for Xilinx FPGA's. It has been used and is available. I'm not sure of cost and features but a datasheet is available on their website: http://www.memecdesign.com/xf-twsi.htm Austin Franklin <darkroo4m@ix.netcom.com> wrote in article > Is there anyone who has done an I2C controller in an FPGA? >Article: 7869
Austin, Try the Altera Freecore Library at http://193.215.128.3/freecore/ It contains a lot of modules designed in AHDL for Altera devices, and has an I2C controller. Good luck! Wayne In article <01bce08a$a65d6ae0$526b5ecf@drt1>, "Austin Franklin" <darkroo4m@ix.netcom.com> wrote: >Is there anyone who has done an I2C controller in an FPGA? > >Thanks, > >Austin Franklin >darkroom@ix.netcom.com > >to e-mail a reply to this post, remove the number from the reply address >Article: 7870
Hi All
I updated the"Alternate Verilog FAQ". Its URL is
http://www.comit.com/~rajesh/verilog/faq/alt_FAQ.html
I added following things.
1. Link to Verilog mode for Emacs
2. Fix for printing Rajeev Madhavan's Verilog quick reference
card.
3. Comit System's Verilog quick reference card
4. Link to EDN in EDA related magazines
5. Added Avanti's name in Simulator companies list.
I removed absolete comparisons between simulators.
Please mail your suggestions.
Thanks
Rajesh Bawankule
(rajesh@comit.com)
--
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Article: 7871Hi All, I having a problem get Workview Office to do what I want. I' m trying to make an adder tree which will add together five 16-bit numbers. I' ve used Xilinx's Core Generator program to make the adders. The first adder adds A[15:0] and B[15:0] resulting in S1[16:0]. The second adder adds C[15:0] and D[15:0] resulting in S2[16:0]. The third adder adds S1[16:0] and S2[16:0] resulting in S3[17:0]. Now comes the problem ... I want to add S3[17:0] and E[15:0]. The adder generated by CoreGen expects two 18 bit inputs, but the one input is only 16 bits wide. Obviously the upper two bits should be zero to make it 18 bits wide. Does anyone know how to make WVOffice do this? I have tried simply connecting the 16 wide bus E to the 18 wide input, but WVO lines up the 16 wide bus to the upper 16 bits of the 18 wide input, leaving the lower two bits zero (or unconnected?). Any suggestions will be greatly appreciated. Thanks, markArticle: 7872
I'm doing bit-serial computation using the XC6216 FPGA and require parallel to serial and serial to parallel convertors. I would appreciate any info on how to implement them on FPGAs (esp. XC6200). Thanks in advance. Reetinder SidhuArticle: 7873
Mark, I get around that problem by first creating a signal "G" which is just tied to the ground signal. Bring your bus E[15:0] out of the adder, put a couple of bends in so you can rename it where it goes into the last adder. Name the bus going into that adder G,G,E[15:0]. This is now a 18 bit bus and will be connected correctly. This same technique is useful for creating constants on a VL bus as well. I use "H" and "L" for high and low and then lable the bus: H,H,L,L for a value of 0xC . Hope this helps John McGibbon Memec Design Services feydo <feydo@lcworkshop.com> wrote in article > The adder generated by CoreGen expects two 18 > bit inputs, but the one input is only 16 bits wide. Obviously the upper > two bits should be zero to make it 18 bits wide. Does anyone know how to > make WVOffice do this? I have tried simply connecting the 16 wide bus E to > the 18 wide input, but WVO lines up the 16 wide bus to the upper 16 bits of > the 18 wide input, leaving the lower two bits zero (or unconnected?). Any > suggestions will be greatly appreciated. > > Thanks, > mark > >Article: 7874
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