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Protel PCB 3 comes with a template for a PCI card. You should be able to print this out before the program crashes.... >Does anyone has the footprints from PCI & ISA Bus Slotcard >for Protel 2,3 PCB or Orcad PCB? >I could not find them in any library . Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 11026
My experience (several hundred FPGA designs) is that routing time is directly proportional to the amount of effort that is put into floorplanning the design. This was true with the Xact Step software, and it is true of M1. I am currently working on 3 very different XC4062XL designs, and they are all high speed complex datapath/DSP/Store-and-forward designs. All are carefully floorplanned, and are using 90% or greater of the chip. Each design takes about 1.5 to 1.75 hours to run PAR. The system is a dual PII-300 with 512Mb of DRAM. System statistics while PAR is running indicate about 50 to 80Mb of memory in use, and the equivalent of only 1 of the dual CPUs in use (PAR is a single threaded app. so what you get is 50% loading of 2 CPUs). This would indicate that runtimes would be less than two hours on you PII-266/128Mb, for these designs. From your description of run times of 6 days, I would have to assume that your design does not have any floorplanning, and has significant amount of datapath logic in it (this is what the auto placer does really poorly on, and once it finishes placing the design, the router has the task of trying to route the design). Is this by chance also an HDL based design? An experiment worth trying is to set the clock period to a far easier target such as 200nS (rather than your 25nS), and then run PAR with a command like: (assumes the output of mapping is map.ncd) Špar -w -l 4 -d 5 map.ncd projname.ncd projname.pcf >> projname.log The "-d 5" tels it to run 5 iterations of routing improvement/cleanup. After running this run trce, and see what the actual max delay was for your FF to FF path. If it is close to 25nS (less than 35nS) then there is some hope. if it is more than 50nS, you are going to have to consider floorplanning and pipelining. Please give more details about your design, and I will try and make some positive suggestions to help. Philip Freidin. In article <6ntapl$q5o@sf18.dseg.ti.com> rjmyers@dseg.ti.com writes: > >I am routing a XC4052XL part, which is using 68% of CLBs. The last time >I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. >Are routes like this typical??? > >I am setting my clock period to 25 ns in the .ucf file, along with >specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). > >Any suggestions welcomed as to what I can do to reduce the length of >place & route. > >Regards, >Bob >Article: 11027
fliptron@netcom.com (Philip Freidin) writes:
> My experience (several hundred FPGA designs) is that routing time is
> directly proportional to the amount of effort that is put into
> floorplanning the design. This was true with the Xact Step software, and
> it is true of M1.
Surely you meant routing time is inversely proportional to the
floorplanning effort?
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 11028In article <caf6fqomg.fsf@ite127.inf.tu-dresden.de> Achim Gratz <gratz@ite.inf.tu-dresden.de> writes: >fliptron@netcom.com (Philip Freidin) writes: >> My experience (several hundred FPGA designs) is that routing time is >> directly proportional to the amount of effort that is put into >> floorplanning the design. This was true with the Xact Step software, and >> it is true of M1. > >Surely you meant routing time is inversely proportional to the >floorplanning effort? >Achim Gratz. Well, yes, that is actually what I meant. Could I claim that I was thinking of a proportionality value of the form "1/N" ?? :-) PhilipArticle: 11029
fliptron@netcom.com (Philip Freidin) writes:
> Well, yes, that is actually what I meant. Could I claim that I was
> thinking of a proportionality value of the form "1/N" ?? :-)
Err ... I guess you could do that, but I thought you were in
engineering, not marketing? ;-)
C: Hello, I bought XY because you claimed linear speedup when adding
additional YZ. I don't see any of it?
M: You are referring to our press release 0123? Did you also sign NDA
4567, where we explain the details?
C: No, I thought that wasn't necessary.
M: Well, your fault - under that NDA we would have told you the whole
story.
[
E: The whole story is: the linear coefficient is zero because the
overhead of adding YZ is eliminating any benefit.
M: OK, we'll make sure that doesn't hurt sales.
Any resemblance to real persons, companies and products is purely
accidental. Additional disclaimers and waivers apply.
]
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 11030
Hi.
I need any help, if somebody can help - help!!!!!!!!!!
I have to build REED - SOLOMON encoder/decoder within FPGA (ALTERA
FLEX10K100)
Do anybody now how to do this or any references??
Thanks in advance
--
---------------------------------------------------
Lev Razamat
PHASECOM Ltd.
HW Development department
e-mail: lrazamat@usa.net
lev5@phasecom.co.il
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Article: 11031I would like to take this opportunity to introduce Electronic Interconnects http://www.pcbdesign.co.za and propose their use to you. The benefit for both being that you will get the work done in the time scales you require, at half the normal cost, and we can offer better job security to our employees. For the high-tech Electronic Industry to survive and prosper in South Africa export targets will have to set and achieved. I hope this meet your favorable consideration and look forward to your response. Regards, Dave Sharples Electronic Interconnects email davers@mweb.co.za Web http://.www.pcbdesign.co.zaArticle: 11032
You can find a list of vendors supplying a Reed-Solomon core for Altera FLEX devices at http://www.altera.com/html/programs/amppmf/function.html#dspecc . ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Lev Razamat wrote in message <6octac$n47$1@news.netvision.net.il>... >Hi. >I need any help, if somebody can help - help!!!!!!!!!! >I have to build REED - SOLOMON encoder/decoder within FPGA (ALTERA >FLEX10K100) >Do anybody now how to do this or any references?? > >Thanks in advance > >-- >--------------------------------------------------- >Lev Razamat >PHASECOM Ltd. >HW Development department >e-mail: lrazamat@usa.net > lev5@phasecom.co.il > > > >Article: 11033
New York, Syracuse; Senior Engineer; Hardware, Imaging, Video, FPGA -Senior Engineer -Syracuse, NY -Salaried, Full-Time, Direct Employee, Solid Benefits (Relocation Assistance Available) Must have: signal processing, algorithms, FPGAs, and exposure to...video, or imaging &/or sensor systems applications. Client using Altera, ViewLogic and Spice CAE/CAD tools. 60-70% design/detailed design; 30-40% systems level work. Please refer to JO# 582RJS in your response. richard_steinman@cmagroup.com Richard Steinman Team Leader rjs@cmagroup.com IT & Software Solutions Team Career Marketing Associates http://www.cmagroup.com/IT.htmlArticle: 11034
In article <01bdac72$36e61720$7d91d9ce@drt3>, "Austin Franklin" <dark9room@ix.netcom.com> wrote: > > or Memecdesign.com (spin off of Xilinx) ? > > I don't believe this to be true. They are not a 'spin off' of Xilinx. > Some of their employees may have worked for, or done some work for Xilinx, > but to call them a 'spin off' is a real stretch. That would mean anyone > who worked for IBM was now 'a spin off of IBM' ;-) > > (an aside joke) ...or did 'you know who' now claim to invent the FPGA too > ;-) > > Austin Franklin > darkroom@ix.netcom.com > > As an engineer with Memec Design Services, I figure I should set the record straight. We definitely are NOT a spin off of Xilinx. Our affiliation with Xilinx is that we market some of our cores through their AllianceCore program. We have about 20 employees, 15 of which are engineers and technicians. We focus almost exclusively on Xilinx designs because we cannot be experts in everything and because our parent company, Insight Electronics, sells Xilinx. If you want something with a little more marketing spin on it, see our website: http://www.memecdesign.com/ Rob Weinstein rob_weinstein@memecdesignDOTcom Memec Design Services Phone: 888-360-9044 or 602-491-4311 -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11035
In article <6o68t8$t11$1@talia.mad.ibernet.es>,
"Juan-Luis Lopez" <jl.lopez@computer.org> wrote:
> Yes, I have been routinely using parallel PRBS for high speed digital
> circuits, where the serial data rate exceeds the FPGA speed, combined with
> external fast ECL S/P or P/S converters.
>
> This configuration has been successfully implemented in several commercial
> products.
>
> A parallel PRBS circuit has the same number of D flip flops of a serial one.
>
> For each clock cycle, the state of the parallel circuit changes as it would
> change in the serial circuit after n clock cycles.
>
> One way to convert a serial generator to a parallel one is to start with the
> serial schematic (shift register plus XOR feedback). Then, for each D flip
> flop of the shift register, you have to re-arrange its input function in
> order to meet the previous condition.
>
> Example for n=2
>
> Serial (x1) generator Parallel (x2) generator
> ----------------------------------------------
> D2=Q1 D2=XOR(Q3,Q4)
> D3=Q2 D3=Q1
> D4=Q3 D4=Q2
> D1=XOR(Q3,Q4) D1=XOR(Q2,Q3)
> output= Q4 output= first half cycle Q4, second half cycle Q3
>
> QQQQ QQQQ
> 1234 1234
> ---- ----
> 1111 1111
> 0111
> 0011 0011
> 0001
> 1000 1000
> 0100
> 0010 0010
> 1001
> 1100 1100
> 0110
> 1011 1011
> 0101
> 1010 1010
> 1101
> 1110 1110
> 1111 repeats!
> 0111 0111 not yet repeating...
> 0011
>
> This procedure can be extended to x3, x4 and so on. Also can be used for any
> polynomial.
>
> The parallel circuit has the same "forbidden" state that the serial one has
> (all outputs at zero for XOR feedback, ones for XNOR feedback), and can be
> avoided using similar procedures.
>
> For BERT purposes you have also to check n bits at a time, and use a
> combinational encoder followed by an adder instead of a simply error
> counter.
>
> I worked this solution on my own. I would like to hear other solutions from
> more people.
>
> Anecdote: Xilinx supports CRC error checking for the configuration of its
> LCAs in serial mode (bit at a time), but does not support it in Express Mode
> (byte at a time). It could have been supported in this way.
>
> Hope this helps
>
> Juan-Luis Lopez Rodriguez
>
>
Altera has an application note available on their web site that covers this
topic. Look for application note 49 at
http://www.altera.com/html/literature/lan.html
There is an example in this app note which shows parallel CRC calculation.
This technique can be applied to any LFSR algorithm.
Cheers,
Jim Means
-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
Article: 11036I just bought a Dataio Chipwriter specificially because it claims to support the Altera EPC1 serial config PROMs and the Xilinx 17xxx ones. Unfortunately, I just tried to burn my first EPC1 and was informed by Dataio tech support that there is a bug in their software with any files created by maxplus2 later than 8.1 (we're on 8.3). Dataio claims to be "working" on the problem (for the last several weeks) but no fix is currently in sight. Their only suggestion is to download MAxplus2 8.1 and recreate the .pof file. I was appalled. Does anyone one have a suggestion of a programmer that actually works? -- Eric Ryherd eric@vautomation.com VAutomation Inc. Synthesizable VHDL and Verilog Cores 20 Trafalgar Sq. #443 Microprocessors and Serial Communications Nashua, NH 03063 8086 80186 V8-uRISC 6502 Z80 USB 1394 HDLC Ethernet (603)882-2282 FAX:(603)882-1587 http://www.vautomation.comArticle: 11037
In article <6o68t8$t11$1@talia.mad.ibernet.es>,
"Juan-Luis Lopez" <jl.lopez@computer.org> wrote:
>
> A parallel PRBS circuit has the same number of D flip flops of a serial one.
>
> For each clock cycle, the state of the parallel circuit changes as it would
> change in the serial circuit after n clock cycles.
>
I am assuming that the problem is how to generate m outputs of the LFSR
simultaneously. I think what you're describing here is the following :
First recall that any LFSR is a "linear" state machine. The relationship
between the inputs and outputs can be described by the linear equations :
x(n+1) = A x(n) the state update equation
y(n) = B x(n) the output update equation
where x(n) is the value of the D registers in the LFSR at time n,
A is a DxD matrix of 1's and 0's (simply related to the LFSR
generating polynomial) and B is just the 1xD matrix (1,0,...,0) if
you're taking the LSB of the LFSR register as the output.
To transform this into a state machine that produces m outputs, you
just modify your state update and output equations to :
x(n+1) = A^m x(n)
y(n) = (B, B A, B A^2, ... , B A^(m-1)) x(n)
A^m is the m-th power of A and can be calculated off line along with
the other matrices B,B A, ..., B A^(m-1). The calculations are carried
over the field of two elements GF(2); all these equations will
generate logic consisting of xor gates.
There's actually another method if you're using VHDL to design all this;
this method also works when your state machine is not linear.
What you do is use a "for loop" statement around the original state machine
while collecting outputs in appropriate registers; the synthesis tool should
optimize away unused logic -- I once tried both approaches and the synthesis
results were identical; that was on an ASIC using Synopsis, I don't know how
good VHDL for FPGA tools have gotten so they may or may not be able to handle
this; you can always fall back on the equation based solution.
Jacob Hirbawi.
-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
Article: 11038
Try www.hammercores.com. They have a fully parameterized Reed-Solomon encoder
and decoder targeted at Altera devices. Just specify
number of total symbols per codeword
number of check symbols per codeword
number of bits per symbol
any valid field polynomial
(an included utility will give you all the valid ones for a
given bit width if you aren't targeting a common
specification)
any generator polynomial
and the appropriate encoder and/or decoder will be generated. You can
then instantiate it into your design.
You can download the cores for free for evaluation purposes. It will generate
any encoder or decoder, you can place and route and simulate, it just won't
generate a programming file until it is registered.
Good luck!
Wayne
In article <6od60t$6ho@dfw-ixnews5.ix.netcom.com>, "Steven K. Knapp"
<sknapp@optimagic.com> wrote:
>You can find a list of vendors supplying a Reed-Solomon core for Altera FLEX
>devices at http://www.altera.com/html/programs/amppmf/function.html#dspecc .
>
>-----------------------------------------------------------
>Steven K. Knapp
>OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
>E-mail: sknapp@optimagic.com
> Web: http://www.optimagic.com
>-----------------------------------------------------------
>
>Lev Razamat wrote in message <6octac$n47$1@news.netvision.net.il>...
>>Hi.
>>I need any help, if somebody can help - help!!!!!!!!!!
>>I have to build REED - SOLOMON encoder/decoder within FPGA (ALTERA
>>FLEX10K100)
>>Do anybody now how to do this or any references??
>>
>>Thanks in advance
>>
>>--
>>---------------------------------------------------
>>Lev Razamat
>>PHASECOM Ltd.
>>HW Development department
>>e-mail: lrazamat@usa.net
>> lev5@phasecom.co.il
>>
>>
>>
>>
>
>
Article: 11039
Help me.
When i'm trying to compile mine vhdl file with sysnopsys synthesis
(M1.3) software
i get a warning message. How can i solve this problem?
-----------------------------------------------------------------------
design_analyzer> compile -map_effort med
Beginning FPGA optimization
---------------------------
Beginning Resource Allocation (constraint driven)
-----------------------------
Structuring 'tellers_22'
Mapping 'tellers_22'
Allocating blocks in 'cont/g0'
Warning: Can't find the architecture 'add_sub_tc(xhm)'
in the library 'xdw_4000xl'. (LBR-1)
Information: Compile terminated abnormally. (OPT-100)
Current design is 'tra_and_cont'.
0
-------------------------------------------------------------------------
E-mail:ydoganc@cas.et.tudelft.nl
Position: Yavuz Doganc is a Master student of the CAS group.
Address:
Yavuz Doganc
Circuits and Systems group
Faculty of Electrical Engineering
Mekelweg 4
2628 CD Delft
The Netherlands
Article: 11040I think that I've found the problem(s) with my Xilinx design that caused the 6 1/2 day routes. Turns out two things seemed to have caused it: 1) Had a latch inside one of my blocks that Exemplar Leonardo got confused with. What happened is that I took the concatinated a few leading 0's onto the output of a latch and tried passing it to a block that handles my bidirectional I/O. For some reason, Leonardo 4.22 got confused and converted my latch into a register. After removing the concatination before I pass the bus to my I/O block, Leonardo and M1.4 process the latch output correctly. 2) Timing constraints used were not correct. Went "back to basics" and learned how to specify TNM groups and generate appropriate TIMESPEC lines. Working my way back up on coverage level (now at 80%). After these changes, it appears that it took about 45 minutes to get through the first Iterative route pass instead of the 1 1/2 days that happened prior to these corrections. Now to figure out how to imbed a BUFGE inside of a block not at the top level... ---- Thanks for all of the suggestions... -BobArticle: 11041
On Tue, 14 Jul 1998 10:06:32 -0500, Robert Myers <rjmyers@rtis.ray.com> wrote: >Now to figure out how to imbed a BUFGE inside of a block not at the top >level... When using Leonardo, pull up the design browser, navigate down your hierarchy until you find the net you want buffered. Select the net and bring up the constraint editor. (tools => constraint editor) Pick "Buffer Signal" and for the value, type BUFGE or whatever you need and hit the "set constraint" button. You're done. (push "done") :-) The signal will be buffered internally. Your script line (for brevity) would look something like: buffer_sig bufge .work.morse.rtl.clk_div The hierarchy doesn't exist in the work library, only in the elaborated present design (rhs of the design browser window), so you shouldn't have to type much :-) You can also PAD an external signal with an IBUF, and buffer the signal with a BUFG_INT which enables you to put a clock pin anywhere on the chip I/O's Strangely, ASIC prototypers seem to like this ability to use the same HDL code without hand hacking the netlist to insert device specifics. Stuart For Email remove "NOSPAM" from the addressArticle: 11042
Does anyone know of a Quickturn users group that meets in the Boston area? Would anyone in the Boston area like to form a Quickturn user group if one doesn't already exist? -- -Doug ------ Doug Smith Sun Microsystems, Inc. Computer Engineer 4 Omni Way, MS UCHL04-203 Workgroup Server Hardware Chelmsford, MA 01824 Phone: (978) 442-0918 Email: doug.smith@sun.com ------Article: 11043
Hello ASIC decision maker: we are ASIC design house that have expertize starting from FPGAs to all the way to full custom chips. If you need ASIC design services please visit us at following URL.We also specialize porting your existing FPGA design to full ASIC. http://www.iss-us.com/AsicTeam.htm Thanks. Khan.Article: 11044
Buy the Altera programming station. There's a ISA board for the PC, a base, and a EPC1 adapter. Burned quite a few proms on mine during development (more than I wanted to, anyway :-)) and never had a problem. Any time we start having problems with our Data I/O Unisite, we go back and use the altera station. JerryArticle: 11045
--------------63D944653B94AE12C1F2AFCC Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Check your setupfile ( .synopsys_dc.setup) so that the search_path , target_library , symbol_library, link_library, and syntheti= c library variables are setup correctly to point out the libraries design compiler (or fpga compiler) needs for the technology you use. Regards Hans Lindkvist, M.Sc.and Lic.Tech in Comp.Eng. Senior Staff Engineer, Advanced Studies, Digital ASIC Research and Wideband Terminals Ericsson Mobile Communications AB Tel : Int+46 46 19 38 66 Scheelev=E4gen 15 Fax : Int+46 46 19 34 55 S-221 83 LUND Email: Hans.Lindkvist@ldecs.ericsson.s= e SWEDEN Yavuz Doganc wrote: > Help me. > When i'm trying to compile mine vhdl file with sysnopsys synthesis > (M1.3) software > i get a warning message. How can i solve this problem? > > -----------------------------------------------------------------------= > design_analyzer> compile -map_effort med > > Beginning FPGA optimization > --------------------------- > Beginning Resource Allocation (constraint driven) > ----------------------------- > Structuring 'tellers_22' > Mapping 'tellers_22' > Allocating blocks in 'cont/g0' > Warning: Can't find the architecture 'add_sub_tc(xhm)' > in the library 'xdw_4000xl'. (LBR-1) > Information: Compile terminated abnormally. (OPT-100) > Current design is 'tra_and_cont'. > 0 > > -----------------------------------------------------------------------= -- > > E-mail:ydoganc@cas.et.tudelft.nl > Position: Yavuz Doganc is a Master student of the CAS group. > Address: > Yavuz Doganc > Circuits and Systems group > Faculty of Electrical Engineering > Mekelweg 4 > 2628 CD Delft > The Netherlands -- Regards Hans --------------63D944653B94AE12C1F2AFCC Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <P>Check your setupfile ( .synopsys_dc.setup) so that the <BR>search_path , target_library , symbol_library, link_library, and synthetic library variables are setup correctly to point out the libraries design compiler (or fpga compiler) needs for the technology you use. <BR> <P>Regards <BR>Hans Lindkvist, M.Sc.and Lic.Tech in Comp.Eng. <BR>Senior Staff Engineer, Advanced Studies, Digital ASIC <BR>Research and Wideband Terminals <BR> <BR>Ericsson Mobile Communications AB Tel : Int+46 46 19 38 66 <BR>Scheelevägen 15 Fax : Int+46 46 19 34 55 <BR>S-221 83 LUND Email: Hans.Lindkvist@ldecs.ericsson.se <BR>SWEDEN <BR> <P>Yavuz Doganc wrote: <BLOCKQUOTE TYPE=CITE>Help me. <BR>When i'm trying to compile mine vhdl file with sysnopsys synthesis <BR>(M1.3) software <BR>i get a warning message. How can i solve this problem? <P>----------------------------------------------------------------------- <BR>design_analyzer> compile -map_effort med <P> Beginning FPGA optimization <BR> --------------------------- <BR> Beginning Resource Allocation (constraint driven) <BR> ----------------------------- <BR> Structuring 'tellers_22' <BR> Mapping 'tellers_22' <BR> Allocating blocks in 'cont/g0' <BR>Warning: Can't find the architecture 'add_sub_tc(xhm)' <BR> in the library 'xdw_4000xl'. (LBR-1) <BR>Information: Compile terminated abnormally. (OPT-100) <BR>Current design is 'tra_and_cont'. <BR>0 <P>------------------------------------------------------------------------- <P>E-mail:ydoganc@cas.et.tudelft.nl <BR>Position: Yavuz Doganc is a Master student of the CAS group. <BR>Address: <BR> Yavuz Doganc <BR> Circuits and Systems group <BR> Faculty of Electrical Engineering <BR> Mekelweg 4 <BR> 2628 CD Delft <BR> The Netherlands</BLOCKQUOTE> <PRE>-- Regards Hans</PRE> </HTML> --------------63D944653B94AE12C1F2AFCC--Article: 11046
In article <35A4E4AB.6E66BC72@eecg.utoronto.ca> jsswartz@eecg.utoronto.ca (Jordan Swartz) writes: >This is for all those hardware designers using FPGAs who are >tired of waiting several hours (or days?) to compile large circuits: > >For my Master's thesis, I'm working on a high-speed routing tool >that is capable of routing a 20,000 4-LUT circuit in 70 seconds. >(on an architecture similar to the Xilinx 4000EX/XL) While some of the following may seem somewhat negative, please keep in mind that your post asks about level of interest in your resarch, and what we as end users would be willing to pay. Therefore, given the reality of what silicon is actually available, your above statement that your target is similar to XC4000EX/XL, indicates that it is not identical to XC4000EX/XL. That means it does not exist. While I am enthusiastic about new software tools to make my life easier, writing tools for an architecture that does not exist does not have much utility for me (from my point of view. you might get an MSEE out of it which is not all bad :-), since I wont be able to use them on the chips I have, and the probability of Xilinx changing their existing XC4000EX/XL, in production chips to suit your software is basically zero. It is also quite unlikely to affect their future silicon. While investigating routing algorithms is a wonderful thing to be doing, the reality is that they have to work with silicon, and there are many tradeoffs made in that domain, to produce chips that can be manufactured at a reasonable price. For instance, building a chip with 50 metal lines per row and column, and "fully pipulating the intersects" might seem like a great architecture from the routers point of view, but in RAM based FPGAs, the silicon cost is prohibitive, as are the net delays. This can be done in anti-fuse, but there are trade offs, such as one-time programmable, and the never mentioned programming transistors that load down all the metal lines that are needed to program the anti-fuses. >I would greatly appreciate it if you could take a few minutes >to answer the following questions: > >Would you be interested in a tool that could place and route >your BIG circuits (20,000 4-LUTs) in under 5 minutes? Sure. Must support available, high volume silicon. > >If you had to give up some quality (20% in circuit delay >and/or 20% less device utilization than say Xilinx M1), >would you still want to use such a tool? Probably not. 20% is about a speed grade, and that can cost 20% to 30% on the chips. I only have to do place and route "once", but I pay for the silicon over and over. If one looks at the time spent doing a project, the place and route time is only an issue if you are waiting for it. I might spend several days to a week doing some part of a design and then do a trial place and route. As I have posted recently on another thread, this typically is 1.5 hours for a fairly full 4062 (about 4600 LUTs). Since I seem to have basically linear route time to design size, I could expect to see this go up to 6 to 10 hours if we are talking about 20000 LUTs. One of the reasons I do trial place and routes it to detect placement/floorplanning errors, and timing challenges. So maybe what you are proposing to create would suit me for the trials (yes I would prefer 5 minutes to 10 hours to find out that I have a timing problem), but I would still want all the available performance the chip can deliver, so a final route with a tool that doesn't sacrifice performance would still be needed. >How much quality >would you be willing to give up for high-speed place and >route? None in the final place and route. 20% would be ok in trial runs. > >How much would you be willing to pay for such a tool? (if it >existed) That would depend on whether it is for an architecture that is similar to the XC4000EX/XL or it was for an architecture called the XC4000EX/XL. Xilinx sells the full Foundation package including place and route, schematics and simulation (for some subset of the chips) for $1000 I think. You would have to compete with that. > >Thanks in advance for your comments. > >Jordan Swartz >Dept of Electrical and Computer Engineering >University of Toronto >http://www.eecg.toronto.edu/~jsswartz/ In summary, I like the idea of faster routers, and hope you can achieve your goals. My only worry is that your target silicon must be a real architecture. Good luck, Philip FreidinArticle: 11047
Hi, I have started HDL design, but I don't have enough support from others in my firm. So please let me know useful "Shell Script" to help with saving time and efforts when operating EDA tools,such as Simulator,Synthesizer and "make". My development environment is as follows. Language: Verilog-HDL Simulator: Cadence Verilog_XL Synthesize: Exemplar Leonard FPGA Mapper: Altera Max+plus II Any information would be appreciated. -- Takanori Fujiki E-Mail:takanori_fujiki@usa.net -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11048
Actually, I tried doing this...ended up with a problem that M1.4 reported --> duplicate driver for net. Seems that when the BUFGE was instantiated this way, it was put in parallel with another buffer. Our Xilinx "guru" massaged the .xnf file(s) to get rid of the extra buffer, only to have M1.4 later report that the BUFGE was not feeding items in the same quadrant. At this time, I've decided to forge on without inserting the BUFGE. Maybe later this year, when Xilinx releases the Floorplanner software, I'll revisit the problem. -Bob In article <35abb1c5.1397132@nntp.netcruiser>, s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb) writes: > On Tue, 14 Jul 1998 10:06:32 -0500, Robert Myers > <rjmyers@rtis.ray.com> wrote: > > > >Now to figure out how to imbed a BUFGE inside of a block not at the top > >level... > > When using Leonardo, pull up the design browser, navigate down your > hierarchy until you find the net you want buffered. > > Select the net and bring up the constraint editor. (tools => > constraint editor) > > Pick "Buffer Signal" and for the value, type BUFGE or whatever you > need and hit the "set constraint" button. > > You're done. (push "done") :-) > > The signal will be buffered internally. > > Your script line (for brevity) would look something like: > > buffer_sig bufge .work.morse.rtl.clk_div > > The hierarchy doesn't exist in the work library, only in the > elaborated present design (rhs of the design browser window), so you > shouldn't have to type much :-) > > You can also PAD an external signal with an IBUF, and buffer the > signal with a BUFG_INT which enables you to put a clock pin anywhere > on the chip I/O's > > Strangely, ASIC prototypers seem to like this ability to use the same > HDL code without hand hacking the netlist to insert device specifics. > > Stuart > For Email remove "NOSPAM" from the addressArticle: 11049
Thanks for your response. > How long does it take for 40,000 and 80,000 LUT (or in CS speak, what > O() does it have)? The routing problem involves searching a graph over and over for routing each net. Worst case, the order is quadratic, but this is a very loose upper bound. The average case order is near-linear, because the algorithm is able to search the routing graph very efficiently. (It depends on the fanout distribution of the circuit, but most circuits don't have too many really high-fanout nets.) Experimentally, we've determined that our algorithm is near-linear. We haven't found a circuit that required quadratic time to route. Based on our experimental complexity measurements, a 40,000 LUT circuit would take about 3 minutes to route and an 80,000 LUT circuit would require about 6 minutes to route. Unfortunately, we don't have any circuits of these sizes to test our algorithm. Our biggest circuit is 20,000 LUTs and was generated using a tool called GEN (www.eecg.toronto.edu/~mdhutton/gen/), which generates synthetic circuits. Does anyone have some "real" BIG benchmark circuits? > Anything less than optimal is going to hurt. My gut feeling is that > 20% is way too much, I'd probably put up with less than 5% only. This seems to be the consensus, most designers are not willing to give up much quality. > While it is painful to wait for the result, you can plan accordingly > if you know upfront how long it'll take. That's my biggest gripe with > some of the current tools, they either don't tell you or tell you lies > or are very sensitive to minor changes. Perhaps it would be more > useful if the tools didn't throw away all their analysis of the design > on each run and keep the design hierarchy where appropriate. I don't > mean the thing currently sold as "incremental mode". Another nice > thing would be if you could stop the tool during a run to check the > result and either continue or take what came out until then. We've also done some work on routability prediction, where we classify routing problems before starting to route as impossible, difficult ( > a couple of minutes to route), and low-stress(< a couple of minutes). We estimate the total wirelength based on the bounding box wirelength of each net in a circuit.
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