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MMmmm very interesting. I have installed that software on many ( more than
200( I teach classes and have to do installs for each new class)) machines
with very few problems. Most problems I did have were hardware and very
obvious. One thing to check is \windows\susie.ini. Make sure all paths in
this file point to somewhere that make sense.
Other stuff: You are running the setup program not just copying files?
\windows is not write protected?
Tried installing some other software, it does work?
Tried a second CD? Do you have one?
Installed both CDs (Design Entry and Design
Implimentation?) and allowed the machine to reboot?
Have FUN!!
Nick
s.timm wrote:
> I have a problem with Foundation 1.4 from Xilinx.
>
> I cant start the program. Every time messages of errors ocour if I try
> to start the program. The messages are different; missing device;
> PCM.EXE not found; differnt types of DLL have errors; ...
> My System is a Pentium 133; 64 MB RAM; HDD1 with 2GB and HDD2 with 12 GB
> (exlusive for the cad-system)
> The OS is WIN95B.
>
> I have insall the OS and the software more times and it dosent help.
>
> Has anyone a idea ?
>
> S. Timm
Article: 10651Donno from Orcad, I have an old war going with them and do not use their tools any more. However anything that writes a correct EDIF or XNF (Does Orcad write a correct file?? Donno) should work fine. There is another product that Xilinx sells called Allience Base (DS-ALI-BAS-PC) that is designed for such situations as yours. You do not get the Foundation front end in this package but you do get a disk with many (Mainly UNIX) vendors libraries on it so as to allow front end independence. As far as Express goes, not a problem Express works just fine with Xilinx Foundation. Have FUN!! Nick Marcus Lankenau wrote: > I want to start with FPGA's and have this question: > > Is it possible to use the Xilinx Foundation Series 1.4 (FND-BAS) as > back-end and Orcad or FPGA-Express as front-end??? > > Marcus LankenauArticle: 10652
Check out Xilinx's new Core gen disk There are fast multipliers on it. Also search the Xilinx web for articals on serial distributed arithmatic. Have Fun Nick Yves Vandervennet TFE wrote: > Hi ! > > I'm involved in the design of a circuit that must > multiply as fast as possible on 12 bits signed fixed point numbers. > Does anybody know where I can find some literature, some articles > and know-how about implementation of such multipliers ? > > Thank you and best regards. > > Yves.Article: 10653
On Tue, 09 Jun 1998 10:16:39 +0200, Yves Vandervennet TFE <yves@elmitel.ulb.ac.be> wrote: See Altera`s web-site (www.altera.com) for documentation: an53, ab127, ab132, ab133,ab134, pib21, fs4 >Hi ! > > I'm involved in the design of a circuit that must >multiply as fast as possible on 12 bits signed fixed point numbers. >Does anybody know where I can find some literature, some articles >and know-how about implementation of such multipliers ? > > Thank you and best regards. > > > Yves. Sincerelly, Victor Levandovsky PLD application instructor Technological University of Podillia Ukraine vic@NSalpha.podol.khmelnitskiy.ua remove@NS.for.email.meArticle: 10654
This is a multi-part message in MIME format. --------------5E3370F24E8509D299A2D21D Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit > I'm involved in the design of a circuit that must > multiply as fast as possible on 12 bits signed fixed point numbers. > Does anybody know where I can find some literature, some articles > and know-how about implementation of such multipliers ? > > Thank you and best regards. > > Yves. Xilinx has a core generator CD (version 1.4) that has a parallel multiplier for two variable operands, 2's complement arithmetic, with full precision output. Claimed performance for a 12x12, signed multiply is 89MHz (XC4000E-1 and use their xnf file). See http://www.xilinx.com/products/logicore/coregen/ for additional information. Regards, Paul --------------5E3370F24E8509D299A2D21D Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Paul T. Shultz Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Paul T. Shultz n: Shultz;Paul T. org: Chesapeake Sciences Corporation adr: 1127B Benfield Blvd.;;;Millersville;MD;21108;USA email;internet: paul@csciences.com title: Staff Engineer tel;work: (410) 923-1300 x3070 tel;fax: (410) 923-2669 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------5E3370F24E8509D299A2D21D--Article: 10655
In article <357d03e0.9557969@news.multiweb.nl>, r.kellenbach@NO_SPAM_multiweb.nl (Rene Kellenbach) writes: > Anybody over here with hands-on experience with the > Lattice ispLSI series? > > After many years of designing with simple PLD's, > I am considering to move to something better. > In-system programmability is an important factor, > so the Lattice stuff seems pretty interesting. > Certainly proved very useful to us, obviously you can get a similar effect using RAM based fpgas and EEPROMs but the ability to just plug a PC into thecard and reprogram them was invaluable. > > What is the best software package to use this > stuff? I have fooled around with the Lattice starters > kit for I while, but I am not impressed. What I would > like is a relatively inexpensive package that allows > mixed HDL and schematic entry. I assume by this you mean the 'raw' purely Lattice software? If that is the case then I agree entirely. > > How about the Lattice ispVHDL/Viewlogic package? > Or the Synario/ABEL software. Which is best and why? > (I have some hands-on experience with ABEL, but not > VHDL. How difficult is this to learn?). > The ISP Synario Starter Software is downloadable from the Lattice website or was available as a free CD and reflects the the state of the Synario/ABEL software when I last used it (some time ago) This just restricts the devices you can use but was otherwise the same. My general comment about the tools we used is 'unfinished' with inconsistencies between the various parts of the package and a very 'quirky' schematic capture - however the latest version may be different. > What about the performance of the chips? The timing > model seems much simpler than FPGA's. > Do I need a timing simulator or will a simple calculation > by hand suffice? > What kind of system speed are we talking about? Most > companies talk about flipflop toggle rates only, but > what can be expected in real life? > The timing model is a lot simpler than FPGAs, but obviously the harder you push the devices the more attention one has to pay to the timing. Generally, provided one chooses the speed rating necessary relatively conservatively, one can simply use 'levels of logic' with a few calculations or Timing simulations for confirmation purposes. If you are pushing the speed, I personally would at least want a timing simulator available.(If only for the 'feelgood' factor). As far as 'real life' speeds are concerned, it depends on what you want to do and the relative costs of the devices and development time - We found 40M clocks ok on 70M devices, but it is heavily application dependant (and very much so on how much time/effort you are prepared to spend getting the design to fit). In short, the timing model is relatively simple, try a few examples using the sort of logic you'd expect to put in them . Cheers KimArticle: 10656
Hi, I was wondering if any one knows as to which implementation (event-driven or process-oriented) is used for majority of the VHDL/Verilog Simulators. Any major advantages for one implementation over the other. How will the wall clock time be affected with one implementation over the other. I mean if we have a design which is to be simulated, which implementation would be faster with respect to the wall clock time. If it depends on the design, then what factors in the design. I would appreciate if any one has useful pointers. Particularly I would be interested in simulators like Mentor's QuickHDL, Cadence LeapFrog, and other major vendors like Synopsis. Thanks, Deepu ~~~~~~~~~~~~~ deepu@ece.vill.edu / deepu@computer.org ~~~~~~~~~~~~~ | Deepu Talla | If it is not necessary to change | | | it is necessary not to change ... | | Phone: (610)225-0243 (R) | | | (610)519-7371 (O) | whatever, whoever, wherever, whenever| ~~~~~~~~~~~~~~~~ http://www.ece.vill.edu/~deepu ~~~~~~~~~~~~~~~~~~~Article: 10657
aaj15@dial.pipex.com (Kim Carter) wrote: >> In-system programmability is an important factor, >> so the Lattice stuff seems pretty interesting. > >Certainly proved very useful to us, obviously you can get >a similar effect using RAM based fpgas and EEPROMs but the >ability to just plug a PC into thecard and reprogram them was >invaluable. Agreed. Besides, I need better design protection - RAM-based FPGA's do not offer this, AFAIK. Also, I like the ability to program a circuit board without the use of expensive programmers - and I some of our projects need field-upgrades. With Lattice ispLSI, a simple notebook computer suffices. >The ISP Synario Starter Software is downloadable from the Lattice >website or was available as a free CD and reflects the the state >of the Synario/ABEL software when I last used it (some time ago) I have this Starter CD - seems pretty straightforward, but it is limited in device selection and libraries. Don't know about the Real Thing. >This just restricts the devices you can use but was otherwise >the same. My general comment about the tools we used is 'unfinished' >with inconsistencies between the various parts of the package and a >very 'quirky' schematic capture - however the latest version may >be different. Hmm...sounds scary. Maybe the ispVHDL/Viewlogic combo is more consistent and not as quirky as Synario. It also seems far more complicated to learn - do you have any experience with this stuff? >Generally, provided one chooses the speed rating necessary relatively >conservatively, one can simply use 'levels of logic' with a few calculations >or Timing simulations for confirmation purposes. For one of my designs, I will need maximum performance, so 'conservatively' is out of the question. >If you are pushing the speed, I personally would at least want a timing >simulator available.(If only for the 'feelgood' factor). I will look into that. >As far as 'real life' speeds are concerned, it depends on what you want to >do and the relative costs of the devices and development time - We found >40M clocks ok on 70M devices, but it is heavily application dependant (and >very much so on how much time/effort you are prepared to spend getting the >design to fit). In short, the timing model is relatively simple, try a few >examples using the sort of logic you'd expect to put in them . I need system clocks up to 70 or 80 MHz. However, Lattice offers 180 MHz devices now, so I guess this is OK. Thanks a lot, Kim. Best Regards, Rene Kellenbach The Netherlands.Article: 10658
Yves Vandervennet TFE wrote: > Hi ! > > I'm involved in the design of a circuit that must > multiply as fast as possible on 12 bits signed fixed point numbers. > Does anybody know where I can find some literature, some articles > and know-how about implementation of such multipliers ? > > Three important questions: How long do you want the result to be? 12 bits or 24 bits ? Are you multiplying two variables, each of which might change on every clock tick, or is one of the factors a "constant" that does not change for several minutes? Multiplying by a constant costs about half the CLBs, compared to multiplying two variables, Can you tolerate pipeline delays? With pipelining, which is essentially free in FPGAs, you achieve very high throughput, at the expense of longer latency. Peter Alfke, Xilinx ApplicationsArticle: 10659
Check out: MacroTech Semiconductor. Zero NRE, 1K piece min. volumes. 0.35 Micron and 0.5 Micron CMOS www.macrotechsemi.com Kalyan Gokhale <kgokhale@execpc.com> wrote in article <6lfk2h$sf6@newsops.execpc.com>... > What are the names of the companies doing FPGA to gate array converions? > > Kalyan Gokhale > MagneTek Drives and Systems > kgokhale@magnetek.com > >Article: 10660
My company, Clear Logic, provides zero-NRE FPGA-ASIC conversions for many Altera devices. See http://www.clear-logic.com for details. In article <357C06DA.909CFB10@planetc.com>, Jerry English <jenglish@planetc.com> wrote: > > chip express > > Matthew Morris wrote: > > > AMI, Matra Harris, Orbit, California Asic, Siquest > > > > Kalyan Gokhale wrote in message <6lfk2h$sf6@newsops.execpc.com>... > > >What are the names of the companies doing FPGA to gate array converions? > > > > > >Kalyan Gokhale > > >MagneTek Drives and Systems > > >kgokhale@magnetek.com > > > > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10661
Here is another example of using bi-dir I/O. The signal BI_OUT sits on the input side
of an OutBUFT, the control signal IN_OUT lets data be registered into the chip when
equal to '1' and sends registered data out of the chip when equal to '0'. BI_PIN is the
actual pad. This does work, though not in FPGA Express as "rising_edge" is used.
Replace the rising_edge(clk) with "clk'event and clk='1' " for Express..
library IEEE;
use IEEE.std_logic_1164.all;
entity bi_dir is
port ( FROM_CHIP, IN_OUT, clk: in STD_LOGIC;
FROM_BI: out STD_LOGIC;
BI_PIN: inout STD_LOGIC);
end bi_dir;
architecture bi_dir_arch of bi_dir is
signal BI_OUT:std_logic;
begin
process(clk)
begin
if rising_edge(clk)then
BI_OUT<= FROM_CHIP;
if IN_OUT ='1' then
FROM_BI <= BI_PIN;
end if;
end if;
end process;
BI_PIN <= BI_OUT when IN_OUT = '0' else 'Z';
end bi_dir_arch;
Vo To wrote:
> Hello,
>
> I've been trying to configure the bidirectional I/O of the XC4025 to
> communicate with another chip. Somehow the data read from the
> bidirectional pins is not correct --bad data is being read.
>
> The way I'm inferring bidirectional ports is within a state machine, but
> I'm not sure if it's done correctly. The only example of inferring a
> bidirectional is from this example from XILINX:
>
> -----------------------------------------------------------------------------------
>
> entity bidir_infer is
> port (DATA : inout STD_LOGIC_VECTOR(1 downto 0);
> READ_WRITE : in STD_LOGIC
> );
> end bidir_infer;
>
> architecture XILINX of bidir_infer is
> signal LATCH_OUT : STD_LOGIC_VECTOR(1 downto 0);
> begin
> process(READ_WRITE, DATA) begin
> if (READ_WRITE = '1') then
> LATCH_OUT <= DATA;
> end if;
> end process;
>
> process(READ_WRITE, LATCH_OUT) begin
> if (READ_WRITE = '0') then
> DATA(0) <= LATCH_OUT(0) and LATCH_OUT(1);
> DATA(1) <= LATCH_OUT(0) or LATCH_OUT(1);
> else
> DATA(0) <= 'Z';
> DATA(1) <= 'Z';
> end if;
> end process;
> end XILINX;
> ------------------------------------------------------------------------------------
>
> By the way, when I compile this example in Foundation Express, two
> warning appears:
> 1) Latch inferred in design 'bidir_infer' read with
> 'hdlin_check_no_latch'. (HDL-307)
> 2) The pin '/bidir_infer/C0/Z[0]' is not connected to any net.
> (FE-CHECK-1);
>
> Anyway, do you know the correct (or working) way to infer a
> bidirectional within a state machine?
> Thanks for your help.
>
> -Vo To
Article: 10662I think you are pushing your luck at 20mA. The DataBook garantees Ioh to -4.0mA at 2.4V. Vcc at min (3.0V) Long way to 15 to 20mA. (Page 4-72 of 1-98 Databook). I have in the past parralled outputs to get a strong high side drive with Xilinx. It does work. Tony Cooper wrote: > Hi all, > > Just a quicky question... > > I need to supply about 15-20ma to a LED from the pin of a Xilinx 4005XL. > (This is due to a mistake at the schematic level, they were originally designed > to work as current sinks). > > There is an application note in the 1998 databook regarding the I/o > characteristics of the XL fpga (XAPP088) that seems to imply that when the > device is sourcing current, it can supply 20ma and yet still have an output > voltage of 2.5v (approx.). > > Unfortunatly I cannot confirm this figure, as the datasheet for the XL device > does not seem to mention (I probably missed it) the specification for Ioh. > > Does anyone know whether pulling 20ma from a single pin will hurt the > device!!???? (And I have to do it for 4 pins, all in the same corner of the > device) > > Thanks in advance for any technical assistance. > Tony > -- > Sent By Tony Cooper. > email: tony.cooper@virgin.netArticle: 10663
In article <357D1776.D3A0A57F@csciences.com>, "Paul T. Shultz" <paul@csciences.com> wrote: > Xilinx has a core generator CD (version 1.4) that has a parallel > multiplier for two variable operands, 2's complement arithmetic, with > full precision output. Claimed performance for a 12x12, signed multiply > is 89MHz (XC4000E-1 and use their xnf file). > a 12x12 signed multiply at 89MHz sounds unbeleivable, unless Xilinx is quoting the results of a pipelined multiplier. Jacob. -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10664
Call for Papers
IEEE Design and Test of Computers
* * * DRAM Architecture and Testing * * *
Web Page: http://www.ee.ualberta.ca/ce/dramissue.html
Deadline: July 15, 1998
IEEE Design and Test of Computers seeks original manuscripts
describing applied research or practical experience with architectural
and testing aspects of DRAMs. The theme issue is scheduled to appear
in the first issue of 1999.
EMBEDDED MEMORIES
impact, developments, and experiences with embedded macrocells;
reconciling DRAM and logic requirements in a single process;
logic-enhanced DRAMs; processors-in-memories; DRAMs embedded in ASICs;
application-specific DRAMs (graphics, multimedia, communications, ...)
TECHNOLOGY AND STANDARDS
trends in storage cell technology; DRAM-specific processes; circuit
design methodology; fuse technology; packaging; reliability; failure
analysis; high-performance architectures; RAMBUS versus SLDRAM;
impact, developments, and experiences with standards; cache-enhanced
DRAMs
DESIGN
timing system design, timing calibration, synchronous versus
self-timed operation, pipelined design, static and dynamic redundancy,
noise control, error correcting codes, multilevel DRAM, future trends
REPAIR AND TEST
fault models, failure mechanisms, repair algorithms, built-in
self-repair, DRAM test design, design-for-testability, built-in
self-test, parallel test strategies, automatic test equipment, memory
interconnect test
For additional information, consult the web page or contact one of the
guest editors:
Bruce Cockburn, cockburn@ee.ualberta.ca
Fabrizio Lombardi, lombardi@cs.tamu.edu
Jackie Meyer, fmeyer@cs.tamu.edu
Article: 10665We are developing a novel ASIC Technology which will allow low cost prototyping for ASIC designs in the 20K gate to 500K gate range. We are looking for Beta customers who will recieve preferential pricing. Key Product Features: Zero NRE. 3.3V operation with 5V tolerant inputs. 20K gates to 500K gates. RAM with 200Mhz cycle times. Gate delays of 100 picoseconds. Minimum volumes are 1000 pcs/yr. We are also looking for designers who wish to become third party design center consultants on a world-wide basis. FPGA and ASIC expertise required. For further details: E-mail me: kash@ix.netcom.com or call: 408 360 0430 or fax: 408 360 0435 Regards, Kash JohalArticle: 10666
A possibility you might want to consider is to have one
or more Invited Papers on the topic of
"Why Would Anybody In Their Right Mind Build DRAMs?"
The speaker(s) could begin by discussing the capital
costs, test costs, revenue per wafer, R&D costs, and profit
margins of DRAMs. They could contrast these numbers and
trendlines with those of other types of semiconductors
such as ASICs, x86 microprocessors, linear ICs, embedded
microprocessors, DSP, nonvolatile memory, RF IC's, etc.
Then they could talk about the very significant comfort
that DRAM makers achieve by avoiding marketing-risk, through
their choice to manufacture nondifferentiated commodity
products that "sell themselves" with no need for market
development or customer prospecting or large sales forces.
And a good conclusion might be "Why TI is trying to get
out of DRAMs despite a $400M-per-year headstart on profits
through patent royalty revenues."
Some suggestions for authors of this Invited Paper:
(i) Nicky Lu, Etron
(ii) Dave Gustavson, Santa Clara University & SLDRAM, Inc.
(iii) Ron Wilson, CMP Publications
(iv) Fu-Chieh Hsu, MoSys
(v) Joseph Parkinson, formerly Micron Technology
(vi) J. Reese Brown, Unisys
(vii) Farhad Tabrizi, Hyundai
(viii) Ashwin Shah, Texas Instruments
(ix) Richard Pashley, Intel
(x) Thurman Rodgers, Cypress Semiconductor
Article: 10667Two questions come to mind: 1) Are the "run-time options" simply parameters, perhaps like filter coefficients? 2) How do you select the different "run-time options" ? If you're using a parallel EPROM (or EEPROM, or whatever) for your configuration, you can do the following: Pick an EPROM that's bigger than what you require for the configuration. Note that it should have more than 18 address lines, since A0-A17 are used by the Xilinx part during configuration. For instance, pick something that has 19 address lines (however big that is). Use the Xilinx' /LDC line and use it to drive A18 of your EPROM. This will cause the Xilinx configuration to use the lower half of the EPROM's memory space. Now, make sure that your configuration reads the configuration EPROM from low to high addresses. After configuration, make sure you drive that line A18 (/LDC) high. This will now address the upper half of the EPROM's memory space. Also, you need data input lines from the EPROM to the Xilinx part. Drive A0 - A17 however you like in order to read your "options" (or whatever) from memory. A slight modification of this will let you store more than one Xilinx configuration in your EPROM. For instance, say you want to select between two configurations. Use the bitgen utility to load two configurations into memory, one at 0x0 and one at whatever happens when only bit A18 is high. Use the configuration lines A0-A17 to drive A0-A17 as usual. Pull A18 of the EPROM high or low (somehow! that's for you to figure out) to select one or the other configuration. -andy -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories apeters@noao.edu.NOSPAM Thomas Sailer <sailer@ife.ee.ethz.ch> wrote in article <357C2D4A.52806F98@ife.ee.ethz.ch>... > I want to be able to "customize" a circuit just before downloading > the configuration into a Xilinx XC4000 device. > > Since the configuration bit stream is not documented by Xilinx, > the only feasible option to do so (short of reverse engineering > the format :-)) seems to be using ROM (16X1) elements in the circuit > to encode the different "runtime options". > > If one uses more than one such ROM16X1, the problem arises how to find > out which ROM got placed into which CLB function generator. > Another problem is that the routing tool permutes the ROM address > pins at its discretion, which means that the bit locations listed > in the .LL file must be shuffled accordingly. > > The way I did this so far was attaching a BLKNM attribute to every ROM > symbol, > then using a fairly hairy perl script which reads the original XNF file, > the output produced by ncdread (to find out which ROM landed in which > CLB function generator) and the LL file and produces the location > of the configuration bits for every ROM. > > The problem with this approach (besides its hairiness) is that the > BLKNM parameter forces every ROM in a different CLB (i.e. no two ROMs > might be put into the same CLB), which is bad for routability in my > current design (filter coeffs). > > Is there a better (automatic) approach to do this? > > Another issue: how do I recalculate the CRC after changing ROM bits? > I didn't quite understand the CRC circuitry from the XC4000 databook... > > Thomas Sailer >Article: 10668
Yves Vandervennet TFE wrote: > Hi ! > > I'm involved in the design of a circuit that must > multiply as fast as possible on 12 bits signed fixed point numbers. > Does anybody know where I can find some literature, some articles > and know-how about implementation of such multipliers ? The fastest possible style is a pipelined multiplier, Altera have one included in the PLS-WEB (free from website) which can compile up to 80+ MHz without too much trouble. There is always a tradeoff of speed vs cost (size of implementation), you might want to trade some speed for size of the design if it is price critical.... I have a small multipler and divider (slower) for the Altera parts if you want it, but 1 bit per clock... :v) Regards, Steve.Article: 10669
Lots of people offer this. It is the unit cost that makes or breaks this. What would be the cost of a 5k gate device, in a QFP-44, 1k and 5k pieces? From a Xilinx XNF netlist, and with production test vectors supplied in a text format? Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10670
Hi, Which main differencies, anvantages, etc. between this HDL`s? Sincerelly, Victor Levandovsky PLD application instructor Technological University of Podillia Ukraine vic@NSalpha.podol.khmelnitskiy.ua remove@NS.for.email.meArticle: 10671
Hi, Looking for good info about the Texas Instruments TMS320C6x DSPs? Please check out my website: http://www.scs.ch/~andrew/c6x.html Here you'll find: - latest documentation and silicon availability info. - heaps of stuff about HW and SW design with these DSPs - application notes - comprehensive bug list - commercially available 'C6x processor boards and lots of other stuff ..... Have a look and please send me any comments. Don't forget to join my mailing list if you want to be notified when the site is updated ... Cheers, Andrew Phillips Supercomputing Systems AG Zurich, SwitzerlandArticle: 10672
In article <357d03e0.9557969@news.multiweb.nl>, Rene Kellenbach
<r.kellenbach@NO_SPAM_multiweb.nl> writes
>Anybody over here with hands-on experience with the
>Lattice ispLSI series?
>
>After many years of designing with simple PLD's,
>I am considering to move to something better.
>In-system programmability is an important factor,
>so the Lattice stuff seems pretty interesting.
>
>What is the best software package to use this
>stuff? I have fooled around with the Lattice starters
>kit for I while, but I am not impressed. What I would
>like is a relatively inexpensive package that allows
>mixed HDL and schematic entry.
>
>How about the Lattice ispVHDL/Viewlogic package?
>Or the Synario/ABEL software. Which is best and why?
>(I have some hands-on experience with ABEL, but not
>VHDL. How difficult is this to learn?).
>
>What about the performance of the chips? The timing
>model seems much simpler than FPGA's.
>Do I need a timing simulator or will a simple calculation
>by hand suffice?
>What kind of system speed are we talking about? Most
>companies talk about flipflop toggle rates only, but
>what can be expected in real life?
>
>Thanks.
>
>Rene Kellenbach
>The Netherlands
>
I have used Lattice parts for years. Originally I used their PDS
system and thought I was was really good at getting high utilisation.
However, I have been using Lattice-Synario for some time now and still
get very good utilisation. The free starter kit is fine but is limited
to the smaller devices. At present I use Synario 5.0 which handles the
("8000 PLD gate") isp1048 sized parts and I am happy with it.
I like the ability to mix algebra, truth tables, and schematics and also
the hierarchical schematics. I like to see the whole of a design spread
out in 2D with algebraically defined logic sections displayed as block
symbols. I like the way you can lock pins and set their characteristics.
I only use the simulator to check logic function but find it very useful
for this.
I am uneasy that using VHDL would lead to large, "slap it together",
improperly understood, and unnecessarily large designs (like C++ dare I
say?) . However, I grant the necessity of VHDL (and C++) for larger
designs and will certainly use it when I have to design more complex
processing elements.
Is there anyone reading this who has made the transition from Synario to
Viewlogic that still looks back fondly at Synario? Any other comments?
Finally, the Synario system has some quirks. The schematic entry tool
"keeps trying to do the last thing you specified" which is logical
enough but sometimes seems a bit weird. Also if you are working under
NT you must be careful to wait for the "Ready" message before spawning a
new process or things lock up and you have to use the Task manager to
kill the relevant tasks. I found Synario technical support was quick
and efficient.
NB: Vantis (AMD) are offering a very low cost Synario based starter kit
which seems equivalent to the Lattice starter.
--
nick toop
Article: 10673
Please find enclosed the call for participants for The Sixth Japanese
FPGA/PLD Design Conference & Exhibit.
Please forward this Announcement to your colleagues.
Best regards,
Tetsuo HIRONAKA,
Secretary of the FPGA/PLD Conference
===========================================================================
C A L L F O R P A T I C I P A N T S
===========================================================================
THE SIXTH JAPANESE FPGA/PLD DESIGN CONFERENCE & EXHIBIT
June, 24(Wed)-26(Fri), 1998
PACIFICO YOKOHAMA, Yokohama, Japan
Organizer: FPGA/PLD Design Conference & Exhibit
Executive Committee/Chugai Co., Ltd.
Sponsored by:
Embassy of the United States of America
Semiconductor Industry Association
Distributers Association of Foreign Semiconductors
International Semiconductor Cooperation Center (pending)
In Corporation with:
The Institute of Electronics, Information and
Communication Engineers of Japan
Information Processing Society of Japan
The "FPGA/PLD Design Conference & Exhibit" is the only conference and
exhibit on FPGA and PLD in Japan, which provides a forum to exchange
ideas and promote research on the fields of device technology, design
technology, EDA support tools, and applications for FPGA/PLD. For
people who might be interested, detail schedule for the Sixth FPGA/PLD
Design Conference & Exhibit will be attached at the end of the
article.
Further information including registration information for the
conference can be found at the following URL
http://www.cgc.co.jp/FPGA_PLD/sca.html
THE SCHEDULE OF THE SIXTH FPGA/PLD DESIGN CONFERENCE & EXHIBIT
#################################################################
# Users Presentations and Special Session #
# (Offical Language: Japanese and English) #
#################################################################
== Thu June 25 ==========================================================
User Presentations-1 10:45-11:25
Best User Presentation Paper Award Ceremony and Presentation
"A RISC architecture laboratory course using FPGA"
KOJIMA Akira, KAMIDOI Yoko, KAWABATA Hideyuki,
OCHI Hiroyuki (Hiroshima City Univ.)
User Presentations-2 11:40-14:00
Short Talk(11:40-12:30) with Poster Session(12:30-14:00)
(1) "Fast Evaluation of IP cores"
Dirk Devisch(Mentor Graphics Japan)
(2) "The development of schematic retargetting system"
Satoshi Harada, Takehiro Ishii(BROTHER INDUSTRIES,LTD.)
(3) "The cPLD trouble shooting from Lattice technical support"
Ryo Iimura(MACNICA INC.)
(4) "Evaluation of FPGA switch matrices using a Monte Carlo approach"
J. Depreitere, H. Van Marck, J. Van Campen hout(Univ. of Ghent)
(5) "High-speed Programable cache desing using CPLD"
Masami Ikura(MINC Washington Corp.)
(6) "A Development of The VLSI Design Training Course and System using FPGA"
Naohiko Shimizu(Tokai Univ.), Izumi Noma(Coder Electoronics Corp.)
(7) "FPGA Implementation of Gigabit Network Interface Controller"
Ryota Kunisawa, Takashi Matsumoto, Kei Hiraki(Univ. of Tokyo)
(8) "Implementation of Mixed-Signal Circuits Using FPGAs and Programmable Analog Devices"
Koichiro Tanaka, Junji Okada, Takaaki Hirano,
Tanemasa Asano(Kyushu Institute of Technology)
(9) "The Realization and Evaluation of An Automatic generation of HDL
for Parallel Accumulators based on The Extended Petri Net"
Katsumi Wasaki(Shinshu Univ.),
Hajime Eizawa(Nagaoka Univ. of Technology)
Issei Taguchi(Nagano National College of Technology),
Takeshi Nakao(Fukushima National College of Technology)
(10) "Computing Multidimensional DFTs Using Xilinx FPGAs"
Chris Dick(Xilinx Inc.)
User Presentations-3 14:00-15:40
(1) "How to use FPGA in designing IP core"
Motohisa Ito, Masaaki Suhara, Kenji Kataoka, Hiroshi Murase,
Minoru Hasegawa(Excellent design Inc.)
(2) "Emulation of Multi-Chip WASMII on Reconfigurable System Testbed FLEMING"
H.Miyazaki(Keio Univ.)
(3) "Implementation of Reconfigurable Hardware Architecture Emulator on Programmable Device"
W.Ogata(Waseda Univ.), M.Mizuo, Y.Yamamoto(SHASHIN KAGAKU CO., LTD.)
(4) "HAB2 - Hardware Testbed Board with Video Signal I/O Extension"
Mamoru Sekiyama, Masayoshi Nomura, Takashi Matsumoto,
Kei Hiraki(University of Tokyo)
User Presentations-4 15:55-17:35
(1) "Blind sequence estimation receiver by FPGA"
Yoshihiko Fujisaki, Tatsumi Furuya, Youichi Satou(Toho Univ.),
Tetsuya Higuchi(Electrotechnical Lab.), Nobuki Kajihara(RWCP-NEC Lab.)
(2) "Parallel, Pipelined CORDICs for Reconfigurable Computing"
Oskar Mencer, Martin Morf(Stanford Univ.)
(3) "Issues on Medical Image Enhancement"
Ali Reza, Justin Delva(Univ. of Wisconsin-Milwaukee),
Roy Schley(Camtronics Medical Systems), Bob Turney(Xilinx Inc.)
(4) "FPGA Interpolators Using Polynomial Filters"
Chris Dick(Xilinx Inc.), Fred Harris(San Diego State Univ.)
Special Session-1 16:00-17:30
"Using FPGAs as a Flexible PCI Interface solution"
Lecture (From Xilinx Inc.)
#################################################################
# #
# Key Note Speech and Tutorials #
# (Offical Language: Japanese and English) #
#################################################################
== Wed June 24 ======================================================
Keynote Speech K-1
Scenario of crashing gate array market and growing PLD market
Yoshihisa Toyosaki(Gartner Group)
The widespreading needs of the high quality image
communication has a possibility to introduce a drastic change
into the ASIC marketplace like past experiments in the
semiconductor industry. Cell-based IC will grow up rapidly,
while the gate array will lose its share by the PLD. The
growth of the PLD is analyzed from the situation of the recent
ASIC marketplace.
Tutorial A-1
An Introduction to FPGA/PLD
Tutorial Session Planning/Lecturer
Keikichi Tamaru (Kyoto University)
Tutorial A-2
VHDL Language Tutorial
Tutorial Session Planning/Lecturer
Renji Mikami(Minc Washington Corporation)
Tutorial A-3
Future FPGA device
Tutorial Session Planning
Toshinori Sueyoshi(Kumamoto University)
Lecturer
Shinji Kitahara(Rhom Corporation)
Tutorial A-4
Using VHDL for FPGA Design
Tutorial Session Planning・瘢雹Lecturer
Renji Mikami(Minc Washington Corporation)
Lecturer
Takeshi Ochiai(XILINX K.K.)
Masami Ikura(Minc Washington Corporation)
== Thu June 25 ======================================================
Keynote Speech K-2
FPGA Synthesis：Past, Present, and Future
Professor Jason Cong(UCLA)
The first part of this talk briefly summarizes the early
results on various FPGA synthesis techniques for delay, area,
and routability optimization, and discuss their impact on
improving FPGA density and speed. The second part of the talk
highlights several recent advances in FPGA synthesis,
including simultaneous mapping and retiming in FPGA designs,
synthesis for heterogeneous FPGAs, efficient use of on-chip
embedded memory blocks for logic implementation, and
scheduling for dynamically reconfigurable FPGAs. The last part
of the talk discusses the future needs of FPGA synthesis
capabilities to support the rapid advance of the FPGA
technology, especially in the areas of designing highly
scalable synthesis tools for FPGAs with a million gates and
above,combining synthesis and layout for faster timing
convergence,efficient use of IP blocks,and new synthesis
capabilities for future field-progr-ammable
system-on-a-chip. The close interaction between the FPGA
architecture design and synthesis tool development is also
addressed in the talk.
Tutorial B-1
Solution for Larger designs with Intellectual Property, Successful
designs, design issues, and its prospect
Tutorial Session Planning
Yasushi Yamamoto(SPINNAKER SYSTEMS INC)
Lecturer
Toru Katagiri, Yasuhiro Itoh, Takahiro Tomonaga, Minako Suzuki
(SPINNAKER SYSTEMS INC)
Tutorial B-2
Design Tips-Implementation／Tool
Tutorial Session Planning
Sigeru Kawada(Lucent Technologies Semiconductor Marketing, Ltd)
Lecturer
Koichi Sato, Keiji Handa(Konica Corporation)
Tutorial B-3
Hardware/Software Co-design
Lecturer
Prof. Shinji Kimura(Nara Institute of Science and Technology)
Panel Discussion P-1
How the development environment should be?
Moderator
Masaharu Imai(Osaka University)
== Fri June 26 ======================================================
Keynote Speech K-3
Electronics Applied Equipments Notable in the 21 Century
Professor Nanohiko(Tama University)
In near future, it is supposed inevitable for enterprises to
develop unique microetectronic machines in order to win severe
battles in newly created market.For example, recently
introduced electronic commerce seeks innovative services such
as new agent tools. For these purpose, microprocessers will
reveal many limitations.
Tutorial C-1
Design Tips-Implementation/Design
Tutorial Session Planning
Hitoshi Matsumoto(Mitsubishi electric Corporation)
Lecturer
Hitoshi Matsumoto, Yasutomo Onishi(Mitsubishi electric Corporation)
Tutorial C-2
User Applications
Coordinator
Hideharu Amano(Keio University)
Lecturer
Toshihide Tsuzuki(FUJITSU COMPUTER TECHNOLOGY LTD.)
Toshio Suzuki(NEC Corporation)
Sigeru Naoi(Hitachi,Ltd.)
Tutorial C-3
PWB Design for High Speed Digital System
Tutorial Session Planning
Takashi Nakayama(NEC Corporation)
Lecturer
Tatsuo Satoh(NEC Corporation)
Panel Discussion P-2
Will FPGA/PLDs overcome ASICs?
--Disclosing their performances,costs and characteristics--
Moderator
Toshinori Sueyoshi(Kumamoto University)
----------------------------------------------------------------------
Tetsuo HIRONAKA Secretary of the FPGA/PLD Conference
Faculty of Computer Sciences Tel : +81-82-830-1566
Hiroshima City University Fax : +81-82-830-1792
Hiroshima, 731-3194, JAPAN E-mail: hironaka@ce.hiroshima-cu.ac.jp
Article: 10674Hi, I saw last day your news talking about SPARTAN serie; well my question is about bitstream configuration since i'm still unable to download xxx.bit using the // Xchecker cable, have you experienced such troubles or did you only use SPROM download ? Thanks. Francois. -- ------------------------------------------------------------- THIEBOLT Francois \ You think your computer run too slow ? UPS Toulouse III \ - Check nobody's asked for tea ! thiebolt@irit.fr \ "The Hitchikers Guide to the Galaxy" D.Adams -------------------------------------------------------------
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