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I thought it might be of interest to some -- there is a tenure track computer engineering position currently being advertised for the Padnos School of Engineering at Grand Valley State University. You can find the advertisement in the December IEEE Spectrum, and also in a recent ASEE Prism. This will be of particular interest to those interested in practical teaching and research. If you want send me the information requested in the advert. by email I will forward it to the appropriate committee. hugh p.s. You can find out more about GVSU engineering at, http://www.engineer.gvsu.eduArticle: 4776
John L. Smith <jsmith@univision.com> wrote: >Alasdair MacLean wrote: >> We tend to use antifuse parts (Actel) which are OTP rather >> than SRAM based parts. I'm fairly sure we would not be allowed >> to use SRAM parts in "flight-critical" applications. > >I'm not sure I understand the reasoning here. I've worked on >"flight critical" applications, and it was common to see plain >old SRAM used. Why would SRAM based FPGA's be disqualified? It's not SRAM pre se; the field programmable gate arrays which have their configuration actually loaded in the field and store the configuration in SRAM in the chips once loaded can get bad loads and thence do things wrong. If the part is not actually going to switch modes during operation, you can buy one-time programmable versions of the same chip which fuse the program in instead of having to reload the SRAM every powerup, and therefore don't get the configuration wrong sometimes. I've been told that several missiles use the field-programmable gate arrays and reprogram them in flight, but don't know of any manned flying vehicles which use those capabilities. I'm not an expert in the field, though. -george william herbert gherbert@crl.comArticle: 4777
Alasdair MacLean wrote: > > We tend to use antifuse parts (Actel) which are OTP rather > than SRAM based parts. I'm fairly sure we would not be allowed > to use SRAM parts in "flight-critical" applications. I'm not sure I understand the reasoning here. I've worked on "flight critical" applications, and it was common to see plain old SRAM used. Why would SRAM based FPGA's be disqualified? -- John L. Smith, Pr. Engr. | Sometimes we are inclined to class Univision Technologies, Inc. | those who are once-and-a-half witted 6 Fortune Dr. | with the half-witted, because we Billerica, MA 01821-3917 | appreciate only a third part of their wit. jsmith@univision.com | - Henry David ThoreauArticle: 4778
John Walton wrote: > > In article <58r4uo$94f@gcsin3.geccs.gecm.com>, Alasdair MacLean <alasdair.maclean@gecm.com> writes: > |> > |> We tend to use antifuse parts (Actel) which are OTP rather > |> than SRAM based parts. I'm fairly sure we would not be allowed > |> to use SRAM parts in "flight-critical" applications. > |> > |> -- > |> The opinions expressed are mine and do not necessarily reflect > |> those of my employer. > |> > |> Alasdair Maclean, Development Engineer > |> GEC Marconi Radar and Defence Systems, > |> GNET: 709-5711; Tel: +44 (0)131-343-5711 > |> Fax: +44 (0)131-343-5050 > |> Email: <mailto:alasdair.maclean@gecm.com> > |> > |> > > Keep in mind that I have no experience in the arena of > 'flight critical' systems, FPGAs, and the ugly secrets > of ASIC vendors. > > 'flight-critical' components are required to have detailed > fault models used to evaluate the systems ability to 'operate' > in the presents of faults. The system can be built of any kind > of components, however, the system fault model is more accurate > if it's component parts have accurate fault models. > > If the components are bult from Gate Array, Standard Cell, or > Full Custom, parts the 'composition' of those parts can be > readily determined and fault models created. That is the ASIC > layout and macro cell function is know. These parts are also > manufactured from the same masks for the life of the product > so they don't change .... much. > > If the components are built from FPGAs, there is a significant > portion of there composition that will be considered proprietary, > and you will be required to sign lots-o-stuff, if you can even > get that far. Also FPGAs are 'standard products', meaning they go > through life cycles that are out of your control. The parts may > be changed in significant ways in terms of the fault model. They > may discontinue the part long before you are ready, which came happen > with ASICs, but the last time buy should be much cheaper than if you > had to buy several hundred thousand FPGAs. > > John I'm not sure I understand the reluctance to use an SRAM based FPGA in a safety critical application. The SRAM based parts are at least as reliable as the ASIC and OTP FPGA counterparts and offer advantages that are not available to the others. First, there are no fuses or antifuses to deteriorate with age or be incompletely programmed. This eliminates a failure mode that is relatively common with fused/antifused devices. Second, and perhaps even more important, the ability to reload the FPGA program permits the use of additional configuration(s) to test the device and its interconnect completely. This can be done each time the system initializes. The ability to infinitely reload the device also permits more complete testing at the time of manufacture than the OTP and ASIC parts. Thus the device can be guaranteed to be 100% without applying an application specific set of test vectors (which may or may not catch all faults). Xilinx devices permit the program to include a CRC to verify the it loads correctly. This feature can be used to provide an additional check on the programming. The readback capability can also be utilized to monitor the program in the device. The RAM used to hold the configuration in the SRAM devices is intentionally a slow RAM cell to provide significantly higher noise immunity than SRAMs intended for data applications. This reduces the likelyhood of program upset to near zero-much lower than the likelyhood of program upset in a conventional microprocessor based approach. Microprocessors are fairly well accepted even in safety critical applications. The processors also contain proprietary circuits and require a large degree of analysis to fully understand all the fault modes. The regularity of the FPGA array presents a significantly smaller fault analysis challenge. In my experience, if the device loads correctly, it will remain correct. Given these observations, and the unmatched flexibility of the SRAM based arrays I'd pick an SRAM FPGA for safety critical apps before either the OTP or the ASIC. Of course, a fault tolerant logic design helps in any of these cases. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 4779
On Fri, 13 Dec 1996, Ray Andraka wrote: > > I'm not sure I understand the reluctance to use an SRAM based FPGA in a > safety critical application. The SRAM based parts are at least as > reliable as the ASIC and OTP FPGA counterparts and offer advantages that > are not available to the others. > > First, there are no fuses or antifuses to deteriorate with age or be > incompletely programmed. This eliminates a failure mode that is > relatively common with fused/antifused devices. > > Second, and perhaps even more important, the ability to reload the FPGA > program permits the use of additional configuration(s) to test the > device and its interconnect completely. This can be done each time the > system initializes. > > The ability to infinitely reload the device also permits more complete > testing at the time of manufacture than the OTP and ASIC parts. Thus > the device can be guaranteed to be 100% without applying an application > specific set of test vectors (which may or may not catch all faults). > > Xilinx devices permit the program to include a CRC to verify the it > loads correctly. This feature can be used to provide an additional > check on the programming. The readback capability can also be utilized > to monitor the program in the device. > > The RAM used to hold the configuration in the SRAM devices is > intentionally a slow RAM cell to provide significantly higher noise > immunity than SRAMs intended for data applications. This reduces the > likelyhood of program upset to near zero-much lower than the likelyhood > of program upset in a conventional microprocessor based approach. > > Microprocessors are fairly well accepted even in safety critical > applications. The processors also contain proprietary circuits and > require a large degree of analysis to fully understand all the fault > modes. The regularity of the FPGA array presents a significantly > smaller fault analysis challenge. > > In my experience, if the device loads correctly, it will remain > correct. ......... > -Ray Andraka, P.E. > Chairman, the Andraka Consulting Group > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://www.ids.net/~randraka > The "loading" part may explain the reticence to allow the part type in safty critical systems. Not only is the fault analysis necessary for the part itself, but the method the designer choses to load the part needs to be analyzed for all different situations-- the failure rate is also dependent on the number of times it is programmed. The reliance on the part and the method of loading many times, should be much much higher than that of the functional operation of the system. The onus of determining the reliability for "loading" the part is now on the system designer. It's not convincing to assert a high reliability for the design without some data-- and probably not worth his time. I'm familiar with some systems with about 20000 vendors where the need is for 95% reliability on the the first operation of the system. The probability for single faults of individual piece parts to fail is then of the order of 0.001%. I hope this sheds some light on the problem. ######################################################################## Alvin E. Toda aet@lava.net sr. engineer Phone: 1-808-455-1331 2-Sigma WEB: http://www.lava.net/~aet/2-sigma.html 1363-A Hoowali St. Pearl City, Hawaii, USAArticle: 4780
In article <32af6017.6204207@news.smart.net>, bkwilli@smart.net (Bryan Williams) wrote: >Atmel makes a line of serial EEPROMs that are pin-for-pin compatible >with the Xilinx OTP parts. They can also be reprogrammed in-system, >Atmel tech support can give you info on doing this. >They also mentioned that (I think) early AT17Cxxx parts may have had >some kind of bug early on, but I think it had been fixed-- does >anybody know more about this?? > I received a batch of AT17C128 parts that took a *really* long time to configure the Xilinx part (~30s) After a call to Atmel and checking the lot numbers, I was told I had some from a bad lot. The local Atmel rep brought me some replacements the next day (I guess there is an advantage to living in a big city...) **************************************************************************** Dan Bartram, Jr. Internet: dan.bartram@gtri.gatech.edu ****************************************************************************Article: 4781
(Peter Alfke) wrote: >Xilinx serial PROMs offer the most reliable start-up on power-on, and they >have a well-documented and supported way to adjust the RESET polarity, but >the present Xilinx SPROMs are NOT electrically re-programmable. The >present Xilinx devices use EPROM technolgy in a plastic package. Therefore >there is no way to erase them. Xilinx suggests to use the download cable >while debugging the configuration. Sometimes using the download cable is just not feasable. >We are well aware of the fact that some users prefer an electrically >erasable SPROM, and I have often referrred users to the two manufacturers, >AT&T and Atmel, offering EEPROM-based SPROMs that, at least superficially, >are compatible with the Xilinx devices. >Atmel devices suffered from confusing documentation of the RESET polarity >programming. Allegedly, this has been straightened out, but I have heared >the "All Clear" signal once too often from the Atmel camp. If you have a >problem with the Atmel devices, it will only be with the reset polarity. I haven't had any problems with the Atmel parts (AT17C128 and AT17C65) except for a few from a bad batch that took a long time to configure. The Atmel support department quickly tracked the down the problem to the lot number and I had replacement parts the next day. Didn't have any problem set the RESET polarity in any of the Atmel SPROMS I've used. I'm actually surprised that Xilinx doesn't offer the electrically erasable version, because the Xilinx rep told me a year ago that they would. The rep also made a few snide remarks about Atmel when we discussed their [Atmel's] SPROMS. I got the impression that Xilinx was a little miffed at Atmel. In fact, when the rep found out Atmel had given me some samples, he even asked me for one of them. >You may also want to stay away from 10 MHz CCLK rates that are supported >by the XC4000 devices, but not by Atmel SPROMs. Don't know about this.... **************************************************************************** Dan Bartram, Jr. Internet: dan.bartram@gtri.gatech.edu ****************************************************************************Article: 4782
In article <58pt9e$apj@cronkite.polaristel.net>, davidb@visionics.com (David Badzinski) wrote: >Has anyone seen a FPGA implementation of an FFT? Altera has just released a fully parameterizable FFT that can be purchased (and therefore designed yourself, if you prefer) that goes into their 10K family. WayneArticle: 4783
Cong shiping wrote:
>
> Hi all,
>
> I'm using Xilinx's XACT to design FPGA . I haven't any experience with Xilinx's
> FPGA and have some problems . Hope you help me .
>
> 1. When use VHDL
> When use VHDL to design a FPGA , how to assign the pin number ? I heard of
> it is disable to assign the pin nubmer without using schematic .Is it right ?
If you are using Exemplar's Leonardo, or Galileo synthesis tool you can do it this
way (cut & pasted from one of our application notes):
TYPE string_array IS ARRAY (natural RANGE<>, natural RANGE <>) OF character;
ATTRIBUTE pin_number : string;
ATTRIBUTE array_pin_number : string_array;
ATTRIBUTE array_pin_number OF y : signal IS ("P20", "P21", "P22", "P23");
ATTRIBUTE pin_number OF i : signal IS "P10";
>
> 2. When simulate
> How to set the input signals's level ? By Altera's MAX-Plus II , it is very
> easy .
You might want to approach simulation this way:
Write a test bench - a VHDL file that instantiates your circuit. It can also
instantiate a driver circuit (VHDL logic that runs your design). You could also
include the driver logic at the top level of the test bench.
You will find that you can produce complex simulations MUCH faster by writing in
VHDL (or Verilog), than in the languages used by most non-HDL proprietary simulators.
Of course if you have a great gate level simulator, your HDL simulation can dump
test vectors that you can run via a trivial test bench (compare actual vs
expected at sample time) in the gate level simulator. So you could check the RTL
in the VHDL simulator, and check the synthesized or routed design in your other
simulator.
It sounds like you need a good VHDL book. Here's a chance to plug VHDL second
edition, by my coworker, Doug Perry. There are a lot of VHDL books available -
some good, some not. I like Doug's book, and it's pretty popular.
Good interactive VHDL training is available on CD ROM. I think there is more
than one. The only one I have seen is the one we sell, from Esperan.
Regards,
David Emrich
Exemplar Logic
>
> Thanks
>
> Paley
Article: 4784re: taking a long time to configure-- Whammo! I think I've got that bug... I better give Atmel a call. One of my designs was exhibiting that behaviour on power-up.... the CCLK from the Xilinx would run, but it wasn't configuring -- wait a while and it happened. I was thinking either my POR circuit was at fault or perhaps the reset polarity was in question. Know anything about using Data I/O Unisite to program the Atmel 17C128's? I use it but there's a confusing issue - the Atmel, like the Xilinx 17128, claims to have a programmable reset polarity. How you specify this is a mystery -- the algorithm mentions the programmable polarity, but how you specify it is unclear. I've been just doing the way I did the Xilinx part -- for the 128kbit part, the Xilinx algorithm reports a 4004 (hex) device size, the final 4 bytes = 0 for active-low reset, ff for active-high. The Atmel reports a 4000 (hex) device size, no mention of the extra bytes, but once I tried it with FF's in the same place the Xilinx expects them - no dice (the board was designed for active low reset). Set them to zeros like the Xilinx and it worked. Atmel wasn't terribly helpful in solving this, but I did get info on in-system programming. Data I/O is probably to blame - their algorithm is probably just cryptic. But I just do what I did with the Xilinx - set 4000-4003 to 0's and it seems to work. dan.bartram@gtri.gatech.edu (Dan Bartram) wrote: >In article <32af6017.6204207@news.smart.net>, bkwilli@smart.net (Bryan Williams) wrote: >>Atmel makes a line of serial EEPROMs that are pin-for-pin compatible >>with the Xilinx OTP parts. They can also be reprogrammed in-system, >>Atmel tech support can give you info on doing this. > >>They also mentioned that (I think) early AT17Cxxx parts may have had >>some kind of bug early on, but I think it had been fixed-- does >>anybody know more about this?? >> > >I received a batch of AT17C128 parts that took a *really* long time to >configure the Xilinx part (~30s) After a call to Atmel and checking the lot >numbers, I was told I had some from a bad lot. The local Atmel rep >brought me some replacements the next day (I guess there is an advantage to >living in a big city...) > > >**************************************************************************** >Dan Bartram, Jr. >Internet: dan.bartram@gtri.gatech.edu >****************************************************************************Article: 4785
George Herbert wrote: > > John L. Smith <jsmith@univision.com> wrote: > >Alasdair MacLean wrote: > >> We tend to use antifuse parts (Actel) which are OTP rather > >> than SRAM based parts. I'm fairly sure we would not be allowed > >> to use SRAM parts in "flight-critical" applications. > > > >I'm not sure I understand the reasoning here. I've worked on > >"flight critical" applications, and it was common to see plain > >old SRAM used. Why would SRAM based FPGA's be disqualified? > > It's not SRAM pre se; the field programmable gate arrays > which have their configuration actually loaded in the field > and store the configuration in SRAM in the chips once loaded > can get bad loads and thence do things wrong. If the part is > not actually going to switch modes during operation, you can > buy one-time programmable versions of the same chip which > fuse the program in instead of having to reload the SRAM > every powerup, and therefore don't get the configuration > wrong sometimes. > > I've been told that several missiles use the field-programmable > gate arrays and reprogram them in flight, but don't know of > any manned flying vehicles which use those capabilities. > I'm not an expert in the field, though. > > -george william herbert > gherbert@crl.com I think he's referring to the fact that the microprocessor located right next to the FPGA has an SRAM used to store data and instructions for the CPU. What makes the SRAM in the FPGA more likely to be corrupted than the SRAM attached to the CPU? The consequences of either be corrupted can be equally bad. And CPUs are common in safety critical applications. I was wondering if SRAM based FPGA's are more thoroughly tested by the manufacturer than their fused-link counterparts because each part can be loaded with robust test patterns and verified to be correct. Analyzing the effects of component failures is part of the design of a "Safety Critical Application". It may be that a complete failure of the FPGA of whatever type has very little effect on the safe operation of the system. BTW, I've used SRAM-based FPGA's in "flight-essential" systems. Bob DoyleArticle: 4786
In article <32b223f4.187444683@news.smart.net>, bkwilli@smart.net (Bryan Williams) writes: > Know anything about using Data I/O Unisite to program the Atmel > 17C128's? I use it but there's a confusing issue - the Atmel, like > the Xilinx 17128, claims to have a programmable reset polarity. How > you specify this is a mystery ... I haven't used the Atmel parts or a Data I/O blaster. We use the Xilinx ROMs with a ??? programmer. I claim part of the problem is a botch in Xilinx software. You can't set the bit that flips the ROM reset polarity from the Xilinx tools - it doesn't even get saved in the ROM data file. You have to set it manually by talking to your ROM programmer.Article: 4787
Ray Andraka <randraka@ids.net> wrote: >John Walton wrote: >> >> In article <58r4uo$94f@gcsin3.geccs.gecm.com>, Alasdair MacLean <alasdair.maclean@gecm.com> writes: >> |> >> |> We tend to use antifuse parts (Actel) which are OTP rather >> |> than SRAM based parts. I'm fairly sure we would not be allowed >> |> to use SRAM parts in "flight-critical" applications. >I'm not sure I understand the reluctance to use an SRAM based FPGA in a >safety critical application. The SRAM based parts are at least as >reliable as the ASIC and OTP FPGA counterparts and offer advantages that >are not available to the others. I don't see major drawbacks either. In the event of a power glitch, however, there is potentially more down-time while the reset/reprogramming cycle takes place. I don't see this as a major drawback, though it may be for certain applications. In the case of the flight recorder mentioned earlier, by the time it loses power, it has presumably done its job. Now if the _data_ was stored in SRAM I would be more concerned... >First, there are no fuses or antifuses to deteriorate with age or be >incompletely programmed. This eliminates a failure mode that is >relatively common with fused/antifused devices. Not true of ASICs, however it is a real worry with fused parts. - BrianArticle: 4788
Peter Alfke (peter@xilinx.com) wrote: : EPLDs and CPLDs are derived from the PAL architecture and thus have an : AND-OR logic structure ( with most of the programmability in the AND array : ) feeding a flip-flop macrocell. : That means less logic flexibility, but predictable delays, fewer : flip-flops, but faster compile times than for FPGAs. : Also, the technology used tends to have substantial static power consumption. : FPGAs have a more flexible, finer-grained gate-array-like structure with a : hierarchical interconnect structure. They have more flip-flops, but less : predictable routing delays. Most use SRAM technology, and thus are : dynamically reconfigurable, but some use antifuses, which make them : One-Time-Programmable. : The technology is static digital CMOS with almost zero static power consumption. : Altera confuses the issue by calling their SRAM-based FPGA-like families : "CPLDs" for peculiar, non-technical reasons. Not sure which family are you refering to, but their 10k series in some ways is indeed similar to PLD's. Delays are very predictable, for one. -- #include <Standard.Disclaimer> about this post being a personal opinionArticle: 4789
George Herbert wrote: > It's not SRAM pre se; the field programmable gate arrays > which have their configuration actually loaded in the field > and store the configuration in SRAM in the chips once loaded > can get bad loads and thence do things wrong. If the part is > not actually going to switch modes during operation, you can > buy one-time programmable versions of the same chip which > fuse the program in instead of having to reload the SRAM > every powerup, and therefore don't get the configuration > wrong sometimes. > But you can easily determine whether the part loaded properly or not. Turning on the CRC feature in the data stream will cause the device (we're talking Xilinx here) to abort the load if the internally generated CRC does not match the one provided by the bitstream. The CRC is a robust method of ensuring data integrity. In this case it is incumbent upon the programming controller to sense the aborted download and retry. For those who don't trust the CRC, the configuration can be checked by using the readback feature and comparing it to the intended load. If that is not enough, BIST can be added to the built in circuit. This normally takes additional resources in the FPGA. Some of the devices include a JTAG scan port (Xilinx 4k for instance) which does not require the use of much additional resource. Bob Doyle wrote: > I think he's referring to the fact that the microprocessor located > right next to the FPGA has an SRAM used to store data and instructions > for the CPU. What makes the SRAM in the FPGA more likely to be > corrupted than the SRAM attached to the CPU? The consequences of > either be corrupted can be equally bad. And CPUs are common in > safety critical applications. > > I was wondering if SRAM based FPGA's are more thoroughly tested by > the manufacturer than their fused-link counterparts because each > part can be loaded with robust test patterns and verified to be > correct. In fact the FPGA's SRAM is considerably less prone to upset than the SRAM used for data/instruction store for the processor. This is due to the slower write speeds, which require more energy to switch a ram cell's state. Yes, the SRAM based FPGAs are tested much more thoroughly than their OTP counterparts because they can be (and very cheaply). Alvin E. Toda wrote: > The "loading" part may explain the reticence to allow the part type in > safty critical systems. Not only is the fault analysis necessary for the > part itself, but the method the designer choses to load the part needs > to be analyzed for all different situations-- the failure rate is also > dependent on the number of times it is programmed. The reliance on the > part and the method of loading many times, should be much much higher than > that of the functional operation of the system. The onus of determining > the reliability for "loading" the part is now on the system designer. It's It is not apparent that reloading an SRAM based part should deteriorate the reliability of the part. Naturally, a system that reloads several times in the course of operation has a higher probability of a bad load. However, by utilizing the CRC and readback features, a designer can ensure that the load was performed properly. It is incumbent on the designer of the load logic to use these features properly if the application demands it. Brian Drummond wrote: > I don't see major drawbacks either. In the event of a power glitch, > however, there is potentially more down-time while the > reset/reprogramming cycle takes place. I don't see this as a major > drawback, though it may be for certain applications..... > >First, there are no fuses or antifuses to deteriorate with age or be > >incompletely programmed. This eliminates a failure mode that is > >relatively common with fused/antifused devices. > Not true of ASICs, however it is a real worry with fused parts. Obviously ASICs don't suffer from the fuse/antifuse deterioration. The deterioration of OTP devices is a real problem however. I've seen it a couple of times. The usual vendor explanation is incomplete programming. The SRAM based FPGA will usually come through a power anomally better than other RAM or even a microprocessor (which can do some screwy things under adverse power conditions). Either way, a power upset that is big enough to potentially upset system operation should be dealt with using a complete reinitialization. If this is a problem, some steps should be taken to fortify the power system to prevent such upsets. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 4790
In article <32B23436.33ACF752@primenet.com.DELETE-FOR-EMAIL>, Bob Doyle <doyle@primenet.com.DELETE-FOR-EMAIL> wrote: >George Herbert wrote: [...] >I think he's referring to the fact that the microprocessor located >right next to the FPGA has an SRAM used to store data and instructions >for the CPU. What makes the SRAM in the FPGA more likely to be >corrupted than the SRAM attached to the CPU? The consequences of >either be corrupted can be equally bad. And CPUs are common in >safety critical applications. In general, due to SRAM cell size, the FPGA will be LESS susceptible than the memory device, but that isn't the problem. The problem is that there are error detection and correction techniques that can be used on RAM data to fix errors. Once an FPGA has has its SRAM bits loaded, then if one of these bit values changes due to a single-event-upset, for example, there is no way to detect and correct it before it causes a possible change in functionality of your device. Once it HAS been detected (because the ciruit does not work properly) it can be fixed by reloading of the device, but by then it is too late. The error has already occurred. >I was wondering if SRAM based FPGA's are more thoroughly tested by >the manufacturer than their fused-link counterparts because each >part can be loaded with robust test patterns and verified to be >correct. > >Analyzing the effects of component failures is part of the design >of a "Safety Critical Application". It may be that a complete >failure of the FPGA of whatever type has very little effect on the >safe operation of the system. > >BTW, I've used SRAM-based FPGA's in "flight-essential" systems. I'd like to know more about that, since when I was working on the Boeing 777 the specs for SEUs made it nearly impossible to use SRAM devices.Article: 4791
In article <peter-1212961547390001@appsmac-1.xilinx.com>, peter@xilinx.com (Peter Alfke) wrote: >In article <32AC67BB.18C2@esiee.fr>, Raphael BELLEC <bellecr@esiee.fr> wrote: > >> Dear everyone. > >> But I would like to know "in use" what is the real difference you can >> make between an FPGA and a high density epld? > > >EPLDs and CPLDs are derived from the PAL architecture and thus have an >AND-OR logic structure ( with most of the programmability in the AND array >) feeding a flip-flop macrocell. >That means less logic flexibility, but predictable delays, fewer >flip-flops, but faster compile times than for FPGAs. >Also, the technology used tends to have substantial static power consumption. CPLDs are not necessarily sum-of-products. Altera Flex 8000 and Flex 10K are deemed to be CPLDs; the use of the terms deals more with the continous interconnect structure (like an EPLD has) then the actual logic element, which is a 4-input LUT followed by a register and is therefore an FPGA-style building block. As for power, now you are really talking about the difference between SRAM devices and EEPROM devices, but hey, another time for that one... >FPGAs have a more flexible, finer-grained gate-array-like structure with a >hierarchical interconnect structure. They have more flip-flops, but less >predictable routing delays. Most use SRAM technology, and thus are >dynamically reconfigurable, but some use antifuses, which make them >One-Time-Programmable. >The technology is static digital CMOS with almost zero static power consumption. >Altera confuses the issue by calling their SRAM-based FPGA-like families >"CPLDs" for peculiar, non-technical reasons. The real reason is as I stated above; that the interconnect structure is much more like an EPLD than an FPGA. This gives the Altera SRAM devices the same fine-grain architecture of an FPGA but with predictable routing delays (and fast compile times) of an EPLD. Hence the CPLD term.Article: 4792
HC16BGND is an advanced programmer’s interface that helps you to develop, test, and refine your assembly language programs for MOTOROLA’s 68HC16 microcontrollers. The key features include: - Run under MS Windows - Interface through PC’s parallel port - Motorola suggested 10 pin target connector - Download and debug HC16 assembly language program in S19 or HEX format - trace through your code by step through or step over - set up to 100 breakpoints - On-screen editing of register and data memory - On-fly assembly of instruction using mnemonics in program memory - Open infinite Register, Program, and Data windows - Watch window so that you can watch important variables - Exchange data through Windows clipboard - File I/O which can be used to automatically read a hex input file into the file and write the result to an output file. - Easy to use. Just click on the menu with left mouse or click on the windows’ area. Everything is self-explained - Convenient and easy to install due to its parallel port interface. You can use laptop to do an on-site demonstration of you products - Low cost - 30 day money back guarantee and one year product warranty For more information or need a demo program, see http://users.why.net/wctech/hc16bgnd.htm, or FTP to FTP.WHY.NET/FTP/PUB/USERS/WCTECH, or send email to WCTECH@WHY.NETArticle: 4793
HC16BGND is an advanced programmer’s interface that helps you to develop, test, and refine your assembly language programs for MOTOROLA’s 68HC16 microcontrollers. The key features include: - Run under MS Windows - Interface through PC’s parallel port - Motorola suggested 10 pin target connector - Download and debug HC16 assembly language program in S19 or HEX format - trace through your code by step through or step over - set up to 100 breakpoints - On-screen editing of register and data memory - On-fly assembly of instruction using mnemonics in program memory - Open infinite Register, Program, and Data windows - Watch window so that you can watch important variables - Exchange data through Windows clipboard - File I/O which can be used to automatically read a hex input file into the file and write the result to an output file. - Easy to use. Just click on the menu with left mouse or click on the windows’ area. Everything is self-explained - Convenient and easy to install due to its parallel port interface. You can use laptop to do an on-site demonstration of you products - Low cost - 30 day money back guarantee and one year product warranty For more information or need a demo program, see http://users.why.net/wctech/hc16bgnd.htm, or FTP to FTP.WHY.NET/FTP/PUB/USERS/WCTECH, or send email to WCTECH@WHY.NET Larry Chen WC TechnologyArticle: 4794
As several people have pointed out, the problem is that SRAM parts are configured on power-up and hence have the potential to be configured wrongly. With an antifuse FPGA, once I've convinced myself through test that the device has been properly configured I can more-or-less forget about it. There may be contingencies built in to catch errors in SRAM parts but I'd rather not have to deal with that. It may also take some time to explain to your customer. As always, these opinions are my own and may not reflect those of my employer. -- Alasdair Maclean, Development Engineer GEC Marconi Radar and Defence Systems, GNET: 709-5711; Tel: +44 (0)131-343-5711 Fax: +44 (0)131-343-5050 Email: <mailto:alasdair.maclean@gecm.com>Article: 4795
Philip, I once read somewhere, when I was little, that metastability was as unavoidable as death and taxes. This is something I've always found to be true except in the 'trivial' case of fully synchronous systems. (I say trivial because almost all systems I've had experience with accept data that are not synchronised to the system master clock). I'm kind of interested how the fifo system you describe can avoid metastability issues if the input and output systems' clocks are not phase locked somehow. Otherwise, doesn't any fifo need at least one status flag so that the circuitry knows when the register bank is either empty or full? regards, Symon. Philip Freidin wrote: ***snipped fifo stuff*** > Some fifo's are built out of an array of registers, with each register > having a validity flag (i.e. the register has valid data in it). These > registers are cascaded together (sort of like a shift register), and they > autonomously move data from one register to the next, if the current > register has valid data and the next does not. the data therefore ripples > through the array. All this logic is self clocking. The output basically > looks at the last registers validity flag, and the input uses the first > registers validity flag. If designed right, this type of fifo does not > have metastability issues, unless it includes additional status flags. > > The set of validity flags, and their control logic is what you were > asking about: "the token chain". > > Philip Freidin. > > In article <587rq2$l96@serv.hinet.net> flxchen@smtp.dlink.com.tw (Felix K.C. CHEN) writes: > >Dear Friends, > > > >I read the terminology "token chain" in an article, but > >I do not know waht it is? That article is about the > >FIFO control mechanism. > > > >Could anyone give me a reference or explanation? > > > >Best wishes, > > > >Felix K.C. CHENArticle: 4796
This is a multi-part message in MIME format.
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Ray Andraka wrote:
>
> I'm not sure I understand the reluctance to use an SRAM based FPGA in a
> safety critical application. The SRAM based parts are at least as
> reliable as the ASIC and OTP FPGA counterparts and offer advantages that
> are not available to the others.
>
> First, there are no fuses or antifuses to deteriorate with age or be
> incompletely programmed. This eliminates a failure mode that is
> relatively common with fused/antifused devices.
>
> Second, and perhaps even more important, the ability to reload the FPGA
> program permits the use of additional configuration(s) to test the
> device and its interconnect completely. This can be done each time the
> system initializes.
>
> The ability to infinitely reload the device also permits more complete
> testing at the time of manufacture than the OTP and ASIC parts. Thus
> the device can be guaranteed to be 100% without applying an application
> specific set of test vectors (which may or may not catch all faults).
>
> Xilinx devices permit the program to include a CRC to verify the it
> loads correctly. This feature can be used to provide an additional
> check on the programming. The readback capability can also be utilized
> to monitor the program in the device.
>
> The RAM used to hold the configuration in the SRAM devices is
> intentionally a slow RAM cell to provide significantly higher noise
> immunity than SRAMs intended for data applications. This reduces the
> likelyhood of program upset to near zero-much lower than the likelyhood
> of program upset in a conventional microprocessor based approach.
>
> Microprocessors are fairly well accepted even in safety critical
> applications. The processors also contain proprietary circuits and
> require a large degree of analysis to fully understand all the fault
> modes. The regularity of the FPGA array presents a significantly
> smaller fault analysis challenge.
>
> In my experience, if the device loads correctly, it will remain
> correct. Given these observations, and the unmatched flexibility of the
> SRAM based arrays I'd pick an SRAM FPGA for safety critical apps before
> either the OTP or the ASIC. Of course, a fault tolerant logic design
> helps in any of these cases.
>
> -Ray Andraka, P.E.
> Chairman, the Andraka Consulting Group
> 401/884-7930 Fax 401/884-7950
> email randraka@ids.net
> http://www.ids.net/~randraka
--
Attached is a postscript paper describing the first built-in-self-test
(BIST) technique used for FPGAs. It supports the viewpoints stated in
the above mail. This technique works both for manufacturing and
in-system test.
Dr. Miron Abramovici
Bell Labs - Lucent Technologies
600 Mountain Ave Rm. 2A-236
Murray Hill, NJ 07974-0636
(908) 582-3933 fax: (908) 582-5192
miron@bell-labs.com
http://www.bell-labs.com/user/miron/
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<0f87c3e1f0783c1e> { 3 setlinewidth -1 9 moveto 9 -1 lineto stroke
-4 4 moveto 4 -4 lineto stroke
4 12 moveto 12 4 lineto stroke} bind def
<8142241818244281> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke
-1 -1 moveto 9 9 lineto stroke } bind def
<03060c183060c081> { 1 setlinewidth -1 -1 moveto 9 9 lineto stroke
4 -4 moveto 12 4 lineto stroke
-4 4 moveto 4 12 lineto stroke} bind def
<8040201008040201> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke
-4 4 moveto 4 -4 lineto stroke
4 12 moveto 12 4 lineto stroke} bind def
end def
/patDict 15 dict dup begin
/PatternType 1 def
/PaintType 2 def
/TilingType 3 def
/BBox [ 0 0 8 8 ] def
/XStep 8 def
/YStep 8 def
/PaintProc {
begin
patProcDict bstring known {
patProcDict bstring get exec
} {
8 8 true [1 0 0 -1 0 8] bstring imagemask
} ifelse
end
} bind def
end def
} ifelse
/combineColor {
FrameSepIs FMnone eq
{
graymode fMLevel1 or not {
[/Pattern [/DeviceCMYK]] setcolorspace
FrameCurColors 0 4 getinterval aload pop FrameCurPat setcolor
} {
FrameCurColors 3 get 1.0 ge {
FrameCurGray RealSetgray
} {
fMAcrobat not FMPColor graymode and and {
0 1 3 {
FrameCurColors exch get
1 FrameCurGray sub mul
} for
RealSetcmykcolor
} {
4 1 6 {
FrameCurColors exch get
graymode {
1 exch sub 1 FrameCurGray sub mul 1 exch sub
} {
1.0 lt {FrameCurGray} {1} ifelse
} ifelse
} for
RealSetrgbcolor
} ifelse
} ifelse
} ifelse
} {
FrameCurColors 0 4 getinterval aload
FrameColorInSepListCMYK {
FrameSepBlack eq exch
FrameSepYellow eq and exch
FrameSepMagenta eq and exch
FrameSepCyan eq and
FrameSepIs FMcustom eq and
{ FrameCurGray } { 1 } ifelse
} {
FrameSepIs FMblack eq
{FrameCurGray 1.0 exch sub mul 1.0 exch sub 4 1 roll pop pop pop} {
FrameSepIs FMyellow eq
{pop FrameCurGray 1.0 exch sub mul 1.0 exch sub 3 1 roll pop pop} {
FrameSepIs FMmagenta eq
{pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub exch pop } {
FrameSepIs FMcyan eq
{pop pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub }
{pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse
} ifelse
graymode fMLevel1 or not {
[/Pattern [/DeviceGray]] setcolorspace
FrameCurPat setcolor
} {
graymode not fMLevel1 and {
dup 1 lt {pop FrameCurGray} if
} if
RealSetgray
} ifelse
} ifelse
} bind def
/savematrix {
orgmatrix currentmatrix pop
} bind def
/restorematrix {
orgmatrix setmatrix
} bind def
/fMDefaultMatrix matrix defaultmatrix def
/fMatrix2 matrix def
/dpi 72 0 fMDefaultMatrix dtransform
dup mul exch dup mul add sqrt def
/freq dpi dup 72 div round dup 0 eq {pop 1} if 8 mul div def
/sangle 1 0 fMDefaultMatrix dtransform exch atan def
sangle fMatrix2 rotate
fMDefaultMatrix fMatrix2 concatmatrix
dup 0 get /sflipx exch def
3 get /sflipy exch def
/screenIndex {
0 1 dpiranges length 1 sub { dup dpiranges exch get 1 sub dpi le {exit} {pop} ifelse } for
} bind def
/getCyanScreen {
FMUseHighFrequencyScreens { CHighAngles CMHighFreqs} {CLowAngles CMLowFreqs} ifelse
screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load
} bind def
/getMagentaScreen {
FMUseHighFrequencyScreens { MHighAngles CMHighFreqs } {MLowAngles CMLowFreqs} ifelse
screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load
} bind def
/getYellowScreen {
FMUseHighFrequencyScreens { YHighTDot YHighFreqs} { YLowTDot YLowFreqs } ifelse
screenIndex dup 3 1 roll get 3 1 roll get { 3 div
{2 { 1 add 2 div 3 mul dup floor sub 2 mul 1 sub exch} repeat
FMSpotFunction } } {/FMSpotFunction load } ifelse
0.0 exch
} bind def
/getBlackScreen {
FMUseHighFrequencyScreens { KHighFreqs } { KLowFreqs } ifelse
screenIndex get 45.0 /FMSpotFunction load
} bind def
/getSpotScreen {
getBlackScreen
} bind def
/getCompositeScreen {
getBlackScreen
} bind def
/FMSetScreen
fMLevel1 { /setscreen load
}{ {
8 dict begin
/HalftoneType 1 def
/SpotFunction exch def
/Angle exch def
/Frequency exch def
/AccurateScreens FMUseAcccurateScreens def
currentdict end sethalftone
} bind } ifelse
def
/setDefaultScreen {
FMPColor {
orgrxfer cvx orggxfer cvx orgbxfer cvx orgxfer cvx setcolortransfer
}
{
orgxfer cvx settransfer
} ifelse
orgfreq organgle orgproc cvx setscreen
} bind def
/setCurrentScreen {
FrameSepIs FMnone eq {
FMUseDefaultNoSeparationScreen {
setDefaultScreen
} {
getCompositeScreen FMSetScreen
} ifelse
} {
FrameSepIs FMcustom eq {
FMUseDefaultSpotSeparationScreen {
setDefaultScreen
} {
getSpotScreen FMSetScreen
} ifelse
} {
FMUseDefaultProcessSeparationScreen {
setDefaultScreen
} {
FrameSepIs FMcyan eq {
getCyanScreen FMSetScreen
} {
FrameSepIs FMmagenta eq {
getMagentaScreen FMSetScreen
} {
FrameSepIs FMyellow eq {
getYellowScreen FMSetScreen
} {
getBlackScreen FMSetScreen
} ifelse
} ifelse
} ifelse
} ifelse
} ifelse
} ifelse
} bind def
end
/FMDOCUMENT {
array /FMfonts exch def
/#copies exch def
FrameDict begin
0 ne /manualfeed exch def
/paperheight exch def
/paperwidth exch def
0 ne /fMNegative exch def
0 ne /edown exch def
/yscale exch def
/xscale exch def
fMLevel1 {
manualfeed {setmanualfeed} if
/FMdicttop countdictstack 1 add def
/FMoptop count def
setpapername
manualfeed {true} {papersize} ifelse
{manualpapersize} {false} ifelse
{desperatepapersize} {false} ifelse
{papersizefailure} if
count -1 FMoptop {pop pop} for
countdictstack -1 FMdicttop {pop end} for
}
{2 dict
dup /PageSize [paperwidth paperheight] put
manualfeed {dup /ManualFeed manualfeed put} if
{setpagedevice} stopped {papersizefailure} if
}
ifelse
FMPColor {
currentcolorscreen
cvlit /orgproc exch def
/organgle exch def
/orgfreq exch def
cvlit /orgbproc exch def
/orgbangle exch def
/orgbfreq exch def
cvlit /orggproc exch def
/orggangle exch def
/orggfreq exch def
cvlit /orgrproc exch def
/orgrangle exch def
/orgrfreq exch def
currentcolortransfer
fMNegative {
1 1 4 {
pop { 1 exch sub } fmConcatProcs 4 1 roll
} for
4 copy
setcolortransfer
} if
cvlit /orgxfer exch def
cvlit /orgbxfer exch def
cvlit /orggxfer exch def
cvlit /orgrxfer exch def
} {
currentscreen
cvlit /orgproc exch def
/organgle exch def
/orgfreq exch def
currenttransfer
fMNegative {
{ 1 exch sub } fmConcatProcs
dup settransfer
} if
cvlit /orgxfer exch def
} ifelse
end
} def
/FMBEGINPAGE {
FrameDict begin
/pagesave save def
3.86 setmiterlimit
/landscape exch 0 ne def
landscape {
90 rotate 0 exch dup /pwid exch def neg translate pop
}{
pop /pwid exch def
} ifelse
edown { [-1 0 0 1 pwid 0] concat } if
0 0 moveto paperwidth 0 lineto paperwidth paperheight lineto
0 paperheight lineto 0 0 lineto 1 setgray fill
xscale yscale scale
/orgmatrix matrix def
gsave
} def
/FMENDPAGE {
grestore
pagesave restore
end
showpage
} def
/FMFONTDEFINE {
FrameDict begin
findfont
ReEncode
1 index exch
definefont
FMfonts 3 1 roll
put
end
} def
/FMFILLS {
FrameDict begin dup
array /fillvals exch def
dict /patCache exch def
end
} def
/FMFILL {
FrameDict begin
fillvals 3 1 roll put
end
} def
/FMNORMALIZEGRAPHICS {
newpath
1 setlinewidth
0 setlinecap
0 0 0 sethsbcolor
0 setgray
} bind def
/FMBEGINEPSF {
end
/FMEPSF save def
/showpage {} def
% See Adobe's "PostScript Language Reference Manual, 2nd Edition", page 714.
% "...the following operators MUST NOT be used in an EPS file:" (emphasis ours)
/banddevice {(banddevice) FMBADEPSF} def
/clear {(clear) FMBADEPSF} def
/cleardictstack {(cleardictstack) FMBADEPSF} def
/copypage {(copypage) FMBADEPSF} def
/erasepage {(erasepage) FMBADEPSF} def
/exitserver {(exitserver) FMBADEPSF} def
/framedevice {(framedevice) FMBADEPSF} def
/grestoreall {(grestoreall) FMBADEPSF} def
/initclip {(initclip) FMBADEPSF} def
/initgraphics {(initgraphics) FMBADEPSF} def
/quit {(quit) FMBADEPSF} def
/renderbands {(renderbands) FMBADEPSF} def
/setglobal {(setglobal) FMBADEPSF} def
/setpagedevice {(setpagedevice) FMBADEPSF} def
/setshared {(setshared) FMBADEPSF} def
/startjob {(startjob) FMBADEPSF} def
/lettertray {(lettertray) FMBADEPSF} def
/letter {(letter) FMBADEPSF} def
/lettersmall {(lettersmall) FMBADEPSF} def
/11x17tray {(11x17tray) FMBADEPSF} def
/11x17 {(11x17) FMBADEPSF} def
/ledgertray {(ledgertray) FMBADEPSF} def
/ledger {(ledger) FMBADEPSF} def
/legaltray {(legaltray) FMBADEPSF} def
/legal {(legal) FMBADEPSF} def
/statementtray {(statementtray) FMBADEPSF} def
/statement {(statement) FMBADEPSF} def
/executivetray {(executivetray) FMBADEPSF} def
/executive {(executive) FMBADEPSF} def
/a3tray {(a3tray) FMBADEPSF} def
/a3 {(a3) FMBADEPSF} def
/a4tray {(a4tray) FMBADEPSF} def
/a4 {(a4) FMBADEPSF} def
/a4small {(a4small) FMBADEPSF} def
/b4tray {(b4tray) FMBADEPSF} def
/b4 {(b4) FMBADEPSF} def
/b5tray {(b5tray) FMBADEPSF} def
/b5 {(b5) FMBADEPSF} def
FMNORMALIZEGRAPHICS
[/fy /fx /fh /fw /ury /urx /lly /llx] {exch def} forall
fx fw 2 div add fy fh 2 div add translate
rotate
fw 2 div neg fh 2 div neg translate
fw urx llx sub div fh ury lly sub div scale
llx neg lly neg translate
/FMdicttop countdictstack 1 add def
/FMoptop count def
} bind def
/FMENDEPSF {
count -1 FMoptop {pop pop} for
countdictstack -1 FMdicttop {pop end} for
FMEPSF restore
FrameDict begin
} bind def
FrameDict begin
/setmanualfeed {
%%BeginFeature *ManualFeed True
statusdict /manualfeed true put
%%EndFeature
} bind def
/max {2 copy lt {exch} if pop} bind def
/min {2 copy gt {exch} if pop} bind def
/inch {72 mul} def
/pagedimen {
paperheight sub abs 16 lt exch
paperwidth sub abs 16 lt and
{/papername exch def} {pop} ifelse
} bind def
/setpapername {
/papersizedict 14 dict def
papersizedict begin
/papername /unknown def
/Letter 8.5 inch 11.0 inch pagedimen
/LetterSmall 7.68 inch 10.16 inch pagedimen
/Tabloid 11.0 inch 17.0 inch pagedimen
/Ledger 17.0 inch 11.0 inch pagedimen
/Legal 8.5 inch 14.0 inch pagedimen
/Statement 5.5 inch 8.5 inch pagedimen
/Executive 7.5 inch 10.0 inch pagedimen
/A3 11.69 inch 16.5 inch pagedimen
/A4 8.26 inch 11.69 inch pagedimen
/A4Small 7.47 inch 10.85 inch pagedimen
/B4 10.125 inch 14.33 inch pagedimen
/B5 7.16 inch 10.125 inch pagedimen
end
} bind def
/papersize {
papersizedict begin
/Letter {lettertray letter} def
/LetterSmall {lettertray lettersmall} def
/Tabloid {11x17tray 11x17} def
/Ledger {ledgertray ledger} def
/Legal {legaltray legal} def
/Statement {statementtray statement} def
/Executive {executivetray executive} def
/A3 {a3tray a3} def
/A4 {a4tray a4} def
/A4Small {a4tray a4small} def
/B4 {b4tray b4} def
/B5 {b5tray b5} def
/unknown {unknown} def
papersizedict dup papername known {papername} {/unknown} ifelse get
end
statusdict begin stopped end
} bind def
/manualpapersize {
papersizedict begin
/Letter {letter} def
/LetterSmall {lettersmall} def
/Tabloid {11x17} def
/Ledger {ledger} def
/Legal {legal} def
/Statement {statement} def
/Executive {executive} def
/A3 {a3} def
/A4 {a4} def
/A4Small {a4small} def
/B4 {b4} def
/B5 {b5} def
/unknown {unknown} def
papersizedict dup papername known {papername} {/unknown} ifelse get
end
stopped
} bind def
/desperatepapersize {
statusdict /setpageparams known
{
paperwidth paperheight 0 1
statusdict begin
{setpageparams} stopped
end
} {true} ifelse
} bind def
/papersizefailure {
FMAllowPaperSizeMismatch not
{
(The requested paper size is not available in any currently-installed tray)
(Edit the PS file to "FMAllowPaperSizeMismatch true" to use default tray)
FMFAILURE } if
} def
/DiacriticEncoding [
/.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef
/.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef
/.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef
/.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef
/.notdef /.notdef /.notdef /.notdef /space /exclam /quotedbl
/numbersign /dollar /percent /ampersand /quotesingle /parenleft
/parenright /asterisk /plus /comma /hyphen /period /slash /zero /one
/two /three /four /five /six /seven /eight /nine /colon /semicolon
/less /equal /greater /question /at /A /B /C /D /E /F /G /H /I /J /K
/L /M /N /O /P /Q /R /S /T /U /V /W /X /Y /Z /bracketleft /backslash
/bracketright /asciicircum /underscore /grave /a /b /c /d /e /f /g /h
/i /j /k /l /m /n /o /p /q /r /s /t /u /v /w /x /y /z /braceleft /bar
/braceright /asciitilde /.notdef /Adieresis /Aring /Ccedilla /Eacute
/Ntilde /Odieresis /Udieresis /aacute /agrave /acircumflex /adieresis
/atilde /aring /ccedilla /eacute /egrave /ecircumflex /edieresis
/iacute /igrave /icircumflex /idieresis /ntilde /oacute /ograve
/ocircumflex /odieresis /otilde /uacute /ugrave /ucircumflex
/udieresis /dagger /.notdef /cent /sterling /section /bullet
/paragraph /germandbls /registered /copyright /trademark /acute
/dieresis /.notdef /AE /Oslash /.notdef /.notdef /.notdef /.notdef
/yen /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef
/ordfeminine /ordmasculine /.notdef /ae /oslash /questiondown
/exclamdown /logicalnot /.notdef /florin /.notdef /.notdef
/guillemotleft /guillemotright /ellipsis /.notdef /Agrave /Atilde
/Otilde /OE /oe /endash /emdash /quotedblleft /quotedblright
/quoteleft /quoteright /.notdef /.notdef /ydieresis /Ydieresis
/fraction /currency /guilsinglleft /guilsinglright /fi /fl /daggerdbl
/periodcentered /quotesinglbase /quotedblbase /perthousand
/Acircumflex /Ecircumflex /Aacute /Edieresis /Egrave /Iacute
/Icircumflex /Idieresis /Igrave /Oacute /Ocircumflex /.notdef /Ograve
/Uacute /Ucircumflex /Ugrave /dotlessi /circumflex /tilde /macron
/breve /dotaccent /ring /cedilla /hungarumlaut /ogonek /caron
] def
/ReEncode {
dup
length
dict begin
{
1 index /FID ne
{def}
{pop pop} ifelse
} forall
0 eq {/Encoding DiacriticEncoding def} if
currentdict
end
} bind def
FMPColor
{
/BEGINBITMAPCOLOR {
BITMAPCOLOR} def
/BEGINBITMAPCOLORc {
BITMAPCOLORc} def
/BEGINBITMAPTRUECOLOR {
BITMAPTRUECOLOR } def
/BEGINBITMAPTRUECOLORc {
BITMAPTRUECOLORc } def
/BEGINBITMAPCMYK {
BITMAPCMYK } def
/BEGINBITMAPCMYKc {
BITMAPCMYKc } def
}
{
/BEGINBITMAPCOLOR {
BITMAPGRAY} def
/BEGINBITMAPCOLORc {
BITMAPGRAYc} def
/BEGINBITMAPTRUECOLOR {
BITMAPTRUEGRAY } def
/BEGINBITMAPTRUECOLORc {
BITMAPTRUEGRAYc } def
/BEGINBITMAPCMYK {
BITMAPCMYKGRAY } def
/BEGINBITMAPCMYKc {
BITMAPCMYKGRAYc } def
}
ifelse
/K {
FMPrintAllColorsAsBlack {
dup 1 eq 2 index 1 eq and 3 index 1 eq and not
{7 {pop} repeat 0 0 0 1 0 0 0} if
} if
FrameCurColors astore
pop combineColor
} bind def
/graymode true def
fMLevel1 {
/fmGetFlip {
fMatrix2 exch get mul 0 lt { -1 } { 1 } ifelse
} FmBD
} if
/setPatternMode {
fMLevel1 {
2 index patScreenDict exch known {
pop pop
patScreenDict exch get aload pop
freq
mul
5 2 roll
fMatrix2 currentmatrix 1 get 0 ne {
3 -1 roll 90 add 3 1 roll
sflipx 1 fmGetFlip sflipy 2 fmGetFlip neg mul
} {
sflipx 0 fmGetFlip sflipy 3 fmGetFlip mul
} ifelse
0 lt {exch pop} {pop} ifelse
fMNegative {
{neg} fmConcatProcs
} if
bind
systemdict /setscreen get exec
/FrameCurGray exch def
} {
/bwidth exch def
/bpside exch def
/bstring exch def
/onbits 0 def /offbits 0 def
freq sangle landscape {90 add} if
{/ypoint exch def
/xpoint exch def
/xindex xpoint 1 add 2 div bpside mul cvi def
/yindex ypoint 1 add 2 div bpside mul cvi def
bstring yindex bwidth mul xindex 8 idiv add get
1 7 xindex 8 mod sub bitshift and 0 ne fMNegative {not} if
{/onbits onbits 1 add def 1}
{/offbits offbits 1 add def 0}
ifelse
}
setscreen
offbits offbits onbits add div fMNegative {1.0 exch sub} if
/FrameCurGray exch def
} ifelse
} {
pop pop
dup patCache exch known {
patCache exch get
} {
dup
patDict /bstring 3 -1 roll put
patDict
9 PatFreq screenIndex get div dup matrix scale
makepattern
dup
patCache 4 -1 roll 3 -1 roll put
} ifelse
/FrameCurGray 0 def
/FrameCurPat exch def
} ifelse
/graymode false def
combineColor
} bind def
/setGrayScaleMode {
graymode not {
/graymode true def
fMLevel1 {
setCurrentScreen
} if
} if
/FrameCurGray exch def
combineColor
} bind def
/normalize {
transform round exch round exch itransform
} bind def
/dnormalize {
dtransform round exch round exch idtransform
} bind def
/lnormalize {
0 dtransform exch cvi 2 idiv 2 mul 1 add exch idtransform pop
} bind def
/H {
lnormalize setlinewidth
} bind def
/Z {
setlinecap
} bind def
/PFill {
graymode fMLevel1 or not {
gsave 1 setgray eofill grestore
} if
} bind def
/PStroke {
graymode fMLevel1 or not {
gsave 1 setgray stroke grestore
} if
stroke
} bind def
/X {
fillvals exch get
dup type /stringtype eq
{8 1 setPatternMode}
{setGrayScaleMode}
ifelse
} bind def
/V {
PFill gsave eofill grestore
} bind def
/Vclip {
clip
} bind def
/Vstrk {
currentlinewidth exch setlinewidth PStroke setlinewidth
} bind def
/N {
PStroke
} bind def
/Nclip {
strokepath clip newpath
} bind def
/Nstrk {
currentlinewidth exch setlinewidth PStroke setlinewidth
} bind def
/M {newpath moveto} bind def
/E {lineto} bind def
/D {curveto} bind def
/O {closepath} bind def
/L {
/n exch def
newpath
normalize
moveto
2 1 n {pop normalize lineto} for
} bind def
/Y {
L
closepath
} bind def
/R {
/y2 exch def
/x2 exch def
/y1 exch def
/x1 exch def
x1 y1
x2 y1
x2 y2
x1 y2
4 Y
} bind def
/rarc
{rad
arcto
} bind def
/RR {
/rad exch def
normalize
/y2 exch def
/x2 exch def
normalize
/y1 exch def
/x1 exch def
mark
newpath
{
x1 y1 rad add moveto
x1 y2 x2 y2 rarc
x2 y2 x2 y1 rarc
x2 y1 x1 y1 rarc
x1 y1 x1 y2 rarc
closepath
} stopped {x1 y1 x2 y2 R} if
cleartomark
} bind def
/RRR {
/rad exch def
normalize /y4 exch def /x4 exch def
normalize /y3 exch def /x3 exch def
normalize /y2 exch def /x2 exch def
normalize /y1 exch def /x1 exch def
newpath
normalize moveto
mark
{
x2 y2 x3 y3 rarc
x3 y3 x4 y4 rarc
x4 y4 x1 y1 rarc
x1 y1 x2 y2 rarc
closepath
} stopped
{x1 y1 x2 y2 x3 y3 x4 y4 newpath moveto lineto lineto lineto closepath} if
cleartomark
} bind def
/C {
grestore
gsave
R
clip
setCurrentScreen
} bind def
/CP {
grestore
gsave
Y
clip
setCurrentScreen
} bind def
/F {
FMfonts exch get
FMpointsize scalefont
setfont
} bind def
/Q {
/FMpointsize exch def
F
} bind def
/T {
moveto show
} bind def
/RF {
rotate
0 ne {-1 1 scale} if
} bind def
/TF {
gsave
moveto
RF
show
grestore
} bind def
/P {
moveto
0 32 3 2 roll widthshow
} bind def
/PF {
gsave
moveto
RF
0 32 3 2 roll widthshow
grestore
} bind def
/S {
moveto
0 exch ashow
} bind def
/SF {
gsave
moveto
RF
0 exch ashow
grestore
} bind def
/B {
moveto
0 32 4 2 roll 0 exch awidthshow
} bind def
/BF {
gsave
moveto
RF
0 32 4 2 roll 0 exch awidthshow
grestore
} bind def
/G {
gsave
newpath
normalize translate 0.0 0.0 moveto
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
PFill fill
grestore
} bind def
/Gstrk {
savematrix
newpath
2 index 2 div add exch 3 index 2 div sub exch
normalize 2 index 2 div sub exch 3 index 2 div add exch
translate
scale
0.0 0.0 1.0 5 3 roll arc
restorematrix
currentlinewidth exch setlinewidth PStroke setlinewidth
} bind def
/Gclip {
newpath
savematrix
normalize translate 0.0 0.0 moveto
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
clip newpath
restorematrix
} bind def
/GG {
gsave
newpath
normalize translate 0.0 0.0 moveto
rotate
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
PFill
fill
grestore
} bind def
/GGclip {
savematrix
newpath
normalize translate 0.0 0.0 moveto
rotate
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
clip newpath
restorematrix
} bind def
/GGstrk {
savematrix
newpath
normalize translate 0.0 0.0 moveto
rotate
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
restorematrix
currentlinewidth exch setlinewidth PStroke setlinewidth
} bind def
/A {
gsave
savematrix
newpath
2 index 2 div add exch 3 index 2 div sub exch
normalize 2 index 2 div sub exch 3 index 2 div add exch
translate
scale
0.0 0.0 1.0 5 3 roll arc
restorematrix
PStroke
grestore
} bind def
/Aclip {
newpath
savematrix
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%%EndProlog
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(1) 303 36 T
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54 72 558 720 R
7 X
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1 18 Q
0 X
(No-Ov) 139.56 708 T
(erhead BIST f) 190.38 708 T
(or FPGA Logic Blocks) 298.93 708 T
2 12 Q
(Charles Stroud, Eric Lee, Srinivasa K) 194.73 651 T
(onala,) 381.46 651 T
2 9.6 Q
(1) 412.47 655.8 T
0 12 Q
(Dept. of Electrical Engineering) 231.02 635 T
(Uni) 249.82 619 T
(v) 267.52 619 T
(ersity of K) 273.34 619 T
(entuck) 324.37 619 T
(y) 356.18 619 T
(453 Anderson Hall) 260.34 603 T
(Le) 254.74 587 T
(xington, K) 267.22 587 T
(y 40506) 318.26 587 T
(phone: \050606\051257-1972) 252.17 571 T
(F) 255.28 555 T
(AX: \050606\051257-3092) 261.07 555 T
(email: cstroud@engr) 235.79 539 T
(.uk) 335.84 539 T
(y) 350.66 539 T
(.edu) 355.88 539 T
(and) 297.34 507 T
2 F
(Miron Abramo) 260.25 475 T
(vici) 334.42 475 T
0 F
(Bell Labs - Lucent T) 227.77 459 T
(echnologies) 326.91 459 T
(600 Mountain A) 259.7 443 T
(v) 338.15 443 T
(e.) 343.97 443 T
(Murray Hill, NJ 07974) 251 427 T
(phone: \050908\051582-3933) 252.17 411 T
(email: miron@research.bell-labs.com) 215.66 395 T
1 F
(Abstract) 283.67 353.67 T
0 F
3.26 (A Built-In Self-Test \050BIST\051 approach for Field Programmable Gate Array \050FPGA\051 testing is) 75.6 326 P
-0.53 (presented which exploits the reprogrammability of FPGAs to create the BIST logic only during testing. As) 54 305 P
1.25 (a result, BIST is achieved without any area overhead or performance penalties to the system function) 54 284 P
0.83 (implemented by the FPGA. The BIST approach is applicable to all levels of testing, achieves maximal) 54 263 P
1.54 (fault coverage, and all tests are applied at-speed. An analysis of Look-Up Table \050LUT\051 based FGPA) 54 242 P
1.29 (architectures yields a general expression for the minimum number of test sessions and establishes the) 54 221 P
1.05 (bounds on FPGA logic resources required to minimize the number of BIST configurations required to) 54 200 P
1.18 (completely test all of the programmable logic blocks of an FPGA. Implementation problems resulting) 54 179 P
-0.23 (from limitations in CAD tools and architectural resources are discussed along with techniques which help) 54 158 P
(to overcome these problems.) 54 137 T
54 84 558 99 C
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0 0 612 792 C
0 10 Q
0 X
0 0 0 1 0 0 0 K
(1. This material is based upon w) 72 77.33 T
(ork supported by the National Science F) 201.61 77.33 T
(oundation under Grant No. MIP-9409682.) 362.55 77.33 T
0 0 0 1 0 0 0 K
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1 14 Q
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(1. Intr) 261.01 710.67 T
(oduction) 298.87 710.67 T
0 12 Q
4.32 (An FPGA consists of an array of programmable logic blocks \050PLBs\051 interconnected by a) 75.6 690 P
0.08 (programmable routing network, and programmable I/O cells. The set of all programming bits establishes) 54 670 P
2.92 (a) 54 650 P
3 F
2.92 (con\336gur) 65.25 650 P
2.92 (ation) 105.07 650 P
0 F
2.92 ( which determines the function of the device. In this paper, we consider in-circuit) 129.74 650 P
1.29 (reprogrammable FPGAs, such as SRAM-based FPGAs, which may be reconfigured an arbitrary large) 54 630 P
0.44 (number of times. FPGA manufacturing tests are complicated by the need to cover all possible modes of) 54 610 P
0.25 (operation and many non-classical fault models \050faults affecting the programmable interconnect network,) 54 590 P
0.09 (delay faults, etc.\051. Currently, tests are generated manually by configuring several application circuits and) 54 570 P
0.26 (exercising them with test patterns developed specifically for each application circuit. Fault simulation to) 54 550 P
1.72 (determine fault coverage of these test patterns is expensive since all the application circuits must be) 54 530 P
-0.54 (simulated. In addition, these tests require long application times and expensive Automatic Test Equipment) 54 510 P
-0.04 (\050ATE\051. The FPGA manufacturing tests are not reusable for board and system-level testing, which require) 54 490 P
-0.35 (separate development efforts. Here the traditional approach has been to rely on system diagnostic routines) 54 470 P
-0.23 (to test the FPGAs in their system mode of operation. The development of these diagnostic routines can be) 54 450 P
(time-consuming and costly, and the resulting test quality is difficult to estimate.) 54 430 T
0.13 (Previous work in FPGA testing) 75.6 405 P
0 9.6 Q
0.11 ([1]) 226.8 409.8 P
0.11 ([2]) 237.99 409.8 P
0 12 Q
0.13 ( tried to take advantage of reprogrammability by treating testing) 249.19 405 P
0.19 (just as another application to be implemented in the FPGA. These methods also exploit the regular array) 54 385 P
1.59 (structure of an FPGA by configuring it as one or more iterative logic arrays \050ILAs\051) 54 365 P
0 9.6 Q
1.27 ([3]) 474.12 369.8 P
1.27 ([4]) 485.32 369.8 P
0 12 Q
1.59 (.) 496.51 365 P
1.59 (Jordan and) 504.09 365 P
0.5 (Marnane) 54 345 P
0 9.6 Q
0.4 ([1]) 96.65 349.8 P
0 12 Q
0.5 ( configure the FPGA as a 2-D ILA multiplier; however, since this method employs only one) 107.84 345 P
-0.66 (configuration, the FPGA cells are not completely tested. Our fault simulation experiments showed that this) 54 325 P
-0.43 (method achieves less than 60% fault coverage for single stuck faults. Huang and Lombardi) 54 305 P
0 9.6 Q
-0.34 ([2]) 485.01 309.8 P
0 12 Q
-0.43 ( structure the) 496.2 305 P
2.23 (FPGA as parallel 1-D ILAs, repeatedly reconfigured to provide comprehensive fault coverage. One) 54 285 P
0.82 (problem in this approach is that it ignores the RAM mode of operation of PLBs and the specific faults) 54 265 P
-0.51 (associated with it. Lombardi et al.) 54 245 P
0 9.6 Q
-0.41 ([5]) 214.43 249.8 P
0 12 Q
-0.51 ( use multiple configurations to test the programmable routing network) 225.62 245 P
-0.22 (of an FPGA. All these methods rely on externally applied vectors and are applicable only for device-level) 54 225 P
-0.73 (manufacturing tests. Reconfiguring FPGAs for system-level testing has been used to test the other circuitry) 54 205 P
(in the system) 54 185 T
0 9.6 Q
([6]) 117.34 189.8 T
([7]) 128.53 189.8 T
([8]) 139.72 189.8 T
0 12 Q
(; however, these methods do not address the testing of the FPGAs themselves.) 150.92 185 T
2.26 (BIST is a testing methodology particularly advantageous for field testing of digital systems by) 75.6 160 P
0.95 (providing high fault-coverage tests at the system operating frequency \050which, otherwise, is not usually) 54 140 P
0.31 (achievable by system diagnostic software\051, and by reducing diagnostic run-time and diagnostic software) 54 120 P
-0.07 (development. Reductions in diagnostic run-time result in reducing the mean time to repair and increasing) 54 100 P
3.98 (the system availability, while reductions in diagnostic code development help to reduce system) 54 80 P
0 0 0 1 0 0 0 K
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(3) 303 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
2.59 (development time and cost. However, conventional BIST approaches introduce both area overhead) 54 712 P
0.55 (\050typically between 10 and 30 percent\051 and delay penalties \050typically two to three gate delays\051; the latter) 54 692 P
(may result in speed degradation unacceptable in high-performance systems.) 54 672 T
-0.53 (In this paper, we present a BIST approach for FPGAs that exploits the reprogrammability of an FPGA) 75.6 647 P
1.49 (by configuring it exclusively with BIST logic only during testing. In this way,) 54 627 P
3 F
1.49 (testability is achieved) 451.03 627 P
1.16 (without any logic overhead) 54 607 P
0 F
1.16 (, since the BIST logic \322disappears\323 when the circuit is reconfigured for its) 188.47 607 P
2.23 (normal mode of operation. The only cost is the additional memory for storing the data required to) 54 587 P
-0.49 (reconfigure the FPGA; however, this memory is usually part of the test machine environment \050ATE, CPU,) 54 567 P
-0.57 (or maintenance processor\051 which controls the BIST sequence, and does not involve resources of the FPGA) 54 547 P
0.23 (or of the system under test. We will show that this cost is insignificant. Our approach is applicable to all) 54 527 P
0.72 (levels of testing \050wafer, packaged device, board, and system\051, and all tests are performed at the normal) 54 507 P
0.44 (operating frequency, thus providing at-speed testing. Eliminating the need for adding BIST circuitry \050or) 54 487 P
-0.55 (any design-for-testability logic\051 to the system logic in FPGAs reduces the design interval and increases the) 54 467 P
0.31 (system functionality that can be implemented in each FPGA. An additional advantage is the potential of) 54 447 P
0.38 (using a lower-cost ATE for wafer and package-level tests. Since every FPGA is individually tested, this) 54 427 P
1.52 (approach provides in-system location of defective devices; such a diagnostic resolution is not always) 54 407 P
0.98 (achievable with system diagnostics. Since the BIST is independent of the function implemented in the) 54 387 P
-0.08 (FPGA, all the FPGAs \050of the same type\051 in the system can be tested concurrently; this reduces diagnostic) 54 367 P
(code development and the diagnostic run-time.) 54 347 T
0.46 (Our goal is to completely test all PLBs in SRAM-based FPGAs. Complete testing of the PLBs will) 75.6 322 P
0.38 (also detect any fault in the configuration memory \050and in the FPGA programming interface\051 that affects) 54 302 P
0.05 (bits controlling PLB resources, because any such fault results in a malfunctioning PLB. Although testing) 54 282 P
1.65 (the PLBs will also detect many faults in the programmable interconnect network, it will not provide) 54 262 P
-0.57 (complete coverage for these faults. Testing of the programmable interconnect will be addressed in the next) 54 242 P
0.41 (phase of this project. We use the AT&T Optimized Reconfigurable Cell Array \050ORCA\051) 54 222 P
0 9.6 Q
0.33 ([9]) 479.9 226.8 P
0 12 Q
0.41 ( for the initial) 491.09 222 P
0.07 (design and implementation of the BIST approach, but we emphasize that our technique can be applied to) 54 202 P
0.16 (any SRAM-based FPGA, such as Xilinx) 54 182 P
0 9.6 Q
0.13 ([10]) 248.79 186.8 P
0 12 Q
0.16 ( or Altera Flex 8000) 264.78 182 P
0 9.6 Q
0.13 ([11]) 362.74 186.8 P
0 12 Q
0.16 ( series FPGAs. The remainder of this) 378.73 182 P
0.26 (paper is organized as follows. Section 2 presents an overview of the proposed BIST approach. Section 3) 54 162 P
-0.04 (analyzes the BIST architecture and the FPGA architectural resources required to minimize the number of) 54 142 P
-0.02 (times the FPGA must be reconfigured for complete BIST. Scalability and routability issues are discussed) 54 122 P
0.19 (in) 54 102 P
0.19 (Section 4) 66.53 102 P
0.19 (. Section 5 describes the configurations developed to test the ORCA FPGA and gives results) 111.71 102 P
-0.66 (regarding fault coverage, test-time, and memory requirements. Section 6 discusses several implementation) 54 82 P
0 0 0 1 0 0 0 K
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0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
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54 34 558 44 R
V
0 12 Q
0 X
(4) 303 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
(problems and their solutions, and) 54 712 T
(Section 7) 216.66 712 T
( presents our conclusions.) 261.66 712 T
1 14 Q
(2. Ov) 181.81 548.67 T
(er) 213.56 548.67 T
(view of the FPGA BIST A) 225.85 548.67 T
(ppr) 380.66 548.67 T
(oach) 402.19 548.67 T
0 12 Q
0.53 (The strategy of our FPGA BIST approach is to configure groups of PLBs as test pattern generators) 75.6 528 P
2.43 (\050TPGs\051 and output response analyzers \050ORAs\051, and another group as) 54 507 P
3 F
2.43 (blocks under test) 411.28 507 P
0 F
2.43 ( \050BUTs\051, as) 497.47 507 P
1.67 (illustrated in Figure) 54 486 P
1.67 (1. The BUTs are then repeatedly reconfigured to test them in all their modes of) 155.01 486 P
-0.09 (operation. We refer to the test process that occurs for one configuration as a) 54 465 P
3 F
-0.09 (test phase) 419.57 465 P
0 F
-0.09 (. A) 467.14 465 P
3 F
-0.09 (test) 484.62 465 P
-0.09 (session) 504.19 465 P
0 F
-0.09 ( is a) 538.86 465 P
-0.35 (sequence of test phases that completely test the BUTs in their various modes of operation. Once the BUTs) 54 444 P
0.88 (have been tested, the roles of the PLBs are reversed so that in the next test session the previous BUTs) 54 423 P
0.43 (become TPGs or ORAs, and vice versa. Therefore, we need at least two test sessions to test all PLBs in) 54 402 P
-0.26 (the FPGA. Note that all BUTs are tested in parallel, so that the BIST run-time does not depend on the size) 54 381 P
(of the FPGA.) 54 360 T
1.78 (Each test phase consists of the following steps: 1\051 reconfigure the FPGA, 2\051 initiate the test, 3\051) 75.6 86.02 P
1 F
(T) 247.81 695 T
(able 1: Ab) 254.71 695 T
(br) 307.25 695 T
(e) 319.04 695 T
(viations) 324.19 695 T
0 F
(PLB) 86.2 674 T
(Programmable Logic Block) 124.8 674 T
(ORCA) 289.33 674 T
(Optimized Recon\336gurable Cell Array) 340.8 674 T
(TPG) 85.87 656 T
(T) 124.8 656 T
(est P) 131.29 656 T
(attern Generator) 154.12 656 T
3 F
(N) 297.77 656 T
3 8 Q
(TS) 305.78 653.5 T
0 12 Q
(Number of T) 340.8 656 T
(est Sessions) 402.61 656 T
(ORA) 84.53 638 T
(Output Response Analyzer) 124.8 638 T
3 F
(N) 294.89 638 T
3 8 Q
(PLB) 302.89 635.5 T
0 12 Q
(Number of PLBs in FPGA) 340.8 638 T
(B) 85.26 620 T
(UT) 93.14 620 T
(Block \050PLB\051 Under T) 124.8 620 T
(est) 228.95 620 T
3 F
(N) 294.44 620 T
3 8 Q
(TPG) 302.45 617.5 T
0 12 Q
(Number of PLBs used as TPGs) 340.8 620 T
(LUT) 85.54 602 T
(Look-Up T) 124.8 602 T
(able) 178.16 602 T
3 F
(N) 294.22 602 T
3 8 Q
(ORA) 302.23 599.5 T
0 12 Q
(Number of PLBs used as ORAs) 340.8 602 T
(FF) 90.53 584 T
(Flip-Flop) 124.8 584 T
3 F
(N) 294.48 584 T
3 8 Q
(B) 302.49 581.5 T
(UT) 307.29 581.5 T
0 12 Q
(Number of PLBs under test) 340.8 584 T
75.6 685.75 75.6 578.25 2 L
V
0.5 H
0 Z
N
118.8 686.25 118.8 577.75 2 L
V
N
275.95 685.75 275.95 578.25 2 L
V
N
278.45 685.75 278.45 578.25 2 L
V
N
334.8 686.25 334.8 577.75 2 L
V
N
536.4 685.75 536.4 578.25 2 L
V
N
75.35 686 536.65 686 2 L
V
N
75.35 668 536.65 668 2 L
V
N
75.35 650 536.65 650 2 L
V
N
75.35 632 536.65 632 2 L
V
N
75.35 614 536.65 614 2 L
V
N
75.35 596 536.65 596 2 L
V
N
75.35 578 536.65 578 2 L
V
N
54 72 558 720 C
71.59 107.02 540.41 356 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
161.59 158 215.59 338 R
7 X
0 0 0 1 0 0 0 K
V
1 H
0 Z
0 X
N
0 15 Q
(TPG\050s\051) 166.51 244.61 T
90 450 1.97 2.3 315.79 227.7 G
0.5 H
90 450 1.97 2.3 315.79 227.7 A
90 450 1.97 2.3 315.79 220.7 G
90 450 1.97 2.3 315.79 220.7 A
90 450 1.97 2.3 315.79 213.7 G
90 450 1.97 2.3 315.79 213.7 A
143.59 115.86 467.59 124.86 R
7 X
V
1 12 Q
0 X
(Figure 1.) 201.65 116.86 T
(FPGA structure for a test session) 253.65 116.86 T
0 0 0 1 0 0 0 K
287.59 302 341.59 338 R
1 H
N
0 0 0 1 0 0 0 K
0 15 Q
(BUT) 299.59 315.42 T
0 0 0 1 0 0 0 K
287.59 158 341.59 194 R
N
0 0 0 1 0 0 0 K
(BUT) 299.59 171.42 T
0 0 0 1 0 0 0 K
287.59 248 341.59 284 R
N
0 0 0 1 0 0 0 K
(BUT) 299.59 261.42 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
395.59 158 449.59 338 R
7 X
V
0 X
N
(ORAs) 403.84 244.61 T
215.59 248 251.59 248 2 L
7 X
V
2 Z
0 X
N
276.06 320 277.52 320 2 L
0 Z
N
277.52 320 276.56 322.64 285.78 320 276.56 317.36 4 Y
N
277.52 320 276.56 322.64 285.78 320 276.56 317.36 4 Y
V
251.59 320 276.06 320 2 L
7 X
V
2 Z
0 X
N
276.06 266 277.52 266 2 L
0 Z
N
277.52 266 276.56 268.64 285.78 266 276.56 263.36 4 Y
N
277.52 266 276.56 268.64 285.78 266 276.56 263.36 4 Y
V
251.59 266 276.06 266 2 L
7 X
V
2 Z
0 X
N
276.06 176 277.52 176 2 L
0 Z
N
277.52 176 276.56 178.64 285.78 176 276.56 173.36 4 Y
N
277.52 176 276.56 178.64 285.78 176 276.56 173.36 4 Y
V
251.59 176 276.06 176 2 L
7 X
V
2 Z
0 X
N
251.59 320 251.59 176 2 L
7 X
V
0 X
N
384.06 320 385.52 320 2 L
0 Z
N
385.52 320 384.56 322.64 393.78 320 384.56 317.36 4 Y
N
385.52 320 384.56 322.64 393.78 320 384.56 317.36 4 Y
V
341.59 320 384.06 320 2 L
7 X
V
2 Z
0 X
N
384.06 266 385.52 266 2 L
0 Z
N
385.52 266 384.56 268.64 393.78 266 384.56 263.36 4 Y
N
385.52 266 384.56 268.64 393.78 266 384.56 263.36 4 Y
V
341.59 266 384.06 266 2 L
7 X
V
2 Z
0 X
N
384.06 176 385.52 176 2 L
0 Z
N
385.52 176 384.56 178.64 393.78 176 384.56 173.36 4 Y
N
385.52 176 384.56 178.64 393.78 176 384.56 173.36 4 Y
V
341.59 176 384.06 176 2 L
7 X
V
2 Z
0 X
N
150.06 284 151.39 284 2 L
0.5 H
0 Z
N
151.39 284 150.31 286.98 160.69 284 150.31 281.02 4 Y
N
151.39 284 150.31 286.98 160.69 284 150.31 281.02 4 Y
V
107.59 284 150.06 284 2 L
7 X
V
2 Z
0 X
N
119.13 211.33 117.79 211.33 2 L
0 Z
N
117.79 211.33 118.88 208.36 108.5 211.33 118.88 214.31 4 Y
N
117.79 211.33 118.88 208.36 108.5 211.33 118.88 214.31 4 Y
V
161.59 211.33 119.13 211.33 2 L
7 X
V
2 Z
0 X
N
492.06 248 493.39 248 2 L
0 Z
N
493.39 248 492.31 250.98 502.69 248 492.31 245.02 4 Y
N
493.39 248 492.31 250.98 502.69 248 492.31 245.02 4 Y
V
449.59 248 492.06 248 2 L
7 X
V
2 Z
0 X
N
2 10 Q
(BIST_start) 89.59 288.51 T
(Result\050s\051) 473.69 253.18 T
(BIST_done) 89.59 218.05 T
54 72 558 720 C
0 0 612 792 C
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0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
0.4 (generate test patterns, 4\051 analyze responses to produce a pass/fail indication, and 5\051 read the test results.) 54 712 P
0.76 (In step 1, the test controller \050ATE for wafer/package testing;) 54 691 P
0.76 (CPU or maintenance processor for board/) 354.56 691 P
2.16 (system testing\051) 54 670 P
2.16 ( interacts with the FPGA\050s\051 under test to reconfigure the logic by retrieving a BIST) 128.49 670 P
0.6 (configuration from the configuration storage \050) 54 649 P
0.6 (A) 277.95 649 P
0.6 (TE memory) 285.28 649 P
0.6 (; disk\051 and loading it into the FPGA\050s\051. The) 343.54 649 P
-0.09 (test controller also initiates the BIST sequence \050step 2\051 and reads the subsequent results \050step 5\051 using the) 54 628 P
-0.11 (FPGA's boundary-scan \050BS\051 Test Access Port) 54 607 P
0 9.6 Q
-0.09 ([12]) 273.92 611.8 P
0 12 Q
-0.11 ( or other system specific means. \050Practically all recently) 289.92 607 P
-0.2 (developed FPGAs, such as ORCA) 54 586 P
0 9.6 Q
-0.16 ([9]) 218.19 590.8 P
0 12 Q
-0.2 (, XC4000) 229.38 586 P
0 9.6 Q
-0.16 ([10]) 275.85 590.8 P
0 12 Q
-0.2 (, and Flex 8000) 291.85 586 P
0 9.6 Q
-0.16 ([11]) 365.91 590.8 P
0 12 Q
-0.2 (, feature boundary scan.\051 Steps 3 and) 381.91 586 P
0.23 (4 are concurrently performed by the BIST logic within the device, and do not involve I/O pins. Thus the) 54 565 P
0.15 (I/O pins of the FPGA are not tested during BIST, and this requires additional tests during manufacturing) 54 544 P
-0.35 (testing. In system testing, the I/O pins are tested together with the board connectivity using BS tests. After) 54 523 P
0.07 (the board or system-level BIST is complete, the test controller must reconfigure the FPGA for its normal) 54 502 P
1.67 (system function; hence the normal device configuration must be stored on disk along with the BIST) 54 481 P
0.57 (configurations. Clearly, the test application time is dominated by the FPGA reconfiguration time. Since) 54 460 P
1.8 (testing time is a major component of the testing cost, an important goal of the testing strategy is to) 54 439 P
0.3 (minimize the number of test sessions as well as the number of test phases required to completely test all) 54 418 P
(of the PLBs in the FPGA.) 54 397 T
-0.3 (All BUTs are configured to have the same function and receive the same input patterns form the TPG) 75.6 372 P
2.05 (block. Since all fault-free BUTs must produce the same output patterns, the ORAs simply compare) 54 351 P
1.34 (corresponding outputs from different BUTs. Unlike the signature-based compression circuits found in) 54 330 P
-0.73 (most BIST applications, comparator-based ORAs do not suffer from the aliasing problem that occurs when) 54 309 P
0.36 (a faulty circuit produces the good circuit signature. As long as the BUTs being compared do not fail the) 54 288 P
0.21 (same way at the same time, no aliasing will be encountered with the comparison-based approach. Faulty) 54 267 P
0.56 (TPGs and/or ORAs may preclude the detection of a fault in a BUT; but the PLBs composing the faulty) 54 246 P
1.98 (TPGs and/or ORAs will become BUTs in a different session, hence a faulty FPGA will not escape) 54 225 P
0.25 (detection. Although a single TPG is sufficient for fault detection, diagnosing the faulty PLB\050s\051 is helped) 54 204 P
-0.04 (by having different synchronized TPGs feed the BUTs being compared by the same ORA. Regarding the) 54 183 P
0.98 (transmission of the ORA results to the BS register, there is a spectrum of trade-off between supplying) 54 162 P
-0.42 (every ORA output, which provides maximum diagnostic resolution, and ORing all the results into a single) 54 141 P
(signal, which provides the best routability.) 54 120 T
1.01 (Our strategy also relies on) 75.6 94 P
3 F
1.01 (pseudoexhaustive testing) 209.63 94 P
0 9.6 Q
0.81 ([13]) 330.29 98.8 P
0 12 Q
1.01 (, in which every subcircuit of the device is) 346.29 94 P
0 0 0 1 0 0 0 K
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[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(6) 303 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
2.26 (tested with exhaustive patterns. This results in maximal fault coverage without explicit fault model) 54 712 P
0.95 (assumptions and without fault simulation. For a combinational block, pseudoexhaustive tests detect all) 54 691 P
1.4 (detectable faults, except some faults that transform the circuit into a sequential one. This includes all) 54 670 P
-0.57 (detectable single and multiple stuck-at faults and most bridging faults. Figure) 54 649 P
-0.57 (2 shows the typical structure) 422.96 649 P
0.4 (of a PLB, composed of a memory block, a flip-flop \050FF\051 block, and a combinational output logic block;) 54 628 P
2.35 (for example, this structure is featured in the ORCA programmable function unit) 54 607 P
0 9.6 Q
1.88 ([9]) 463.1 611.8 P
0 12 Q
2.35 (, in the XC4000) 474.29 607 P
0.09 (configurable logic block) 54 586 P
0 9.6 Q
0.08 ([10]) 171.5 590.8 P
0 12 Q
0.09 (, and in the Altera Flex 8000 logic element) 187.49 586 P
0 9.6 Q
0.08 ([11]) 393.88 590.8 P
0 12 Q
0.09 (. In many FPGAs, the memory) 409.87 586 P
-0.49 (block can be configured as a combinational look-up table \050LUT\051 or a RAM. For the RAM modules, whose) 54 565 P
-0.28 (exhaustive testing is impractical, we use standard RAM test sequences, which are known to be exhaustive) 54 544 P
0.02 (for the fault models specific to RAMs) 54 523 P
0 9.6 Q
0.02 ([14]) 236.11 527.8 P
0.02 ([15]) 252.1 527.8 P
0 12 Q
0.02 (. The FFs in the FF block may also be configured as latches;) 268.1 523 P
0.44 (other programming options deal with synchronous or asynchronous Set and Reset, Clock Enable, active) 54 502 P
0.36 (levels, and so on. Usually, the output block contains multiplexers to connect different internal signals to) 54 481 P
0.65 (the PLB outputs. In most cases, the cell has no feedback loops and the FFs can be directly accessed by) 54 460 P
-0.13 (bypassing the LUT \050as shown by the dashed line\051. This simple structure, where the inputs and the outputs) 54 439 P
(of every subcircuit are easy to control and to observe, simplifies the pseudoexhaustive testing of the cell.) 54 418 T
3.55 (Note that in every phase, a BUT is configured in a different mode of operation; hence its) 75.6 279.02 P
3.43 (pseudoexhaustive test will also change from phase to phase. For example, the test sequence for) 54 258.02 P
0.12 (combinational logic followed by FFs is different from the test sequence for a RAM. Thus the TPG block) 54 237.02 P
-0.16 (may have different structures depending on the sequence that it has to generate in a given phase. Only the) 54 216.02 P
0.67 (BUT inputs and outputs actually used in a particular phase are connected, respectively, to the TPG and) 54 195.02 P
(ORA blocks.) 54 174.02 T
0.29 (Let) 75.6 148.02 P
3 F
0.29 (N) 94.88 148.02 P
3 8 Q
0.19 (BUT) 102.89 145.52 P
0 12 Q
0.29 ( be the number of BUTs used in a test session, and let) 118 148.02 P
3 F
0.29 (O) 382.36 148.02 P
0 F
0.29 ( denote the number of outputs of a) 391.02 148.02 P
-0.25 (PLB. The ORA block, which receives) 54 127.02 P
3 F
-0.25 (N) 237.83 127.02 P
3 8 Q
-0.16 (BUT) 245.83 124.52 P
4 12 Q
-0.25 (\264) 260.94 127.02 P
3 F
-0.25 (O) 267.53 127.02 P
0 F
-0.25 ( signals to analyze, can be organized in two different ways:) 276.19 127.02 P
0.09 (1\051) 54 106.02 P
3 F
0.09 (O) 67.09 106.02 P
0 F
0.09 ( ORAs, where the) 75.75 106.02 P
3 F
0.09 (i) 165.1 106.02 P
0 F
0.09 (th ORA receives the) 168.43 106.02 P
3 F
0.09 (i) 269.44 106.02 P
0 F
0.09 (th output from every BUT) 272.78 106.02 P
0 9.6 Q
0.07 ([18]) 399.13 110.82 P
0 12 Q
0.09 (, and, 2\051) 415.12 106.02 P
3 F
0.09 (N) 457.72 106.02 P
3 8 Q
0.06 (BUT) 465.73 103.52 P
0 12 Q
0.09 (/) 480.84 106.02 P
3 F
0.09 (k) 484.17 106.02 P
0 F
0.09 ( ORAs, where) 489.5 106.02 P
-0.37 (one ORA analyzes all outputs from) 54 85.02 P
3 F
-0.37 (k) 224.42 85.02 P
0 F
-0.37 ( BUTs. We use the second structure with) 229.74 85.02 P
3 F
-0.37 (k) 426.4 85.02 P
0 F
-0.37 (=2, since it provides better) 431.73 85.02 P
54 72 558 720 C
113.81 300.02 498.19 414 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
193.69 343 249.36 386.23 R
0.5 H
0 Z
0 X
0 0 0 1 0 0 0 K
N
281.17 343 336.84 386.23 R
N
368.65 343 424.33 386.23 R
N
182.4 363.96 182.4 366.93 192.78 363.96 182.4 360.98 4 Y
N
182.4 363.96 182.4 366.93 192.78 363.96 182.4 360.98 4 Y
V
140.66 363.96 182.15 363.96 2 L
N
270.22 375.32 270.22 378.3 280.6 375.32 270.22 372.34 4 Y
N
270.22 375.32 270.22 378.3 280.6 375.32 270.22 372.34 4 Y
V
249.69 375.32 269.97 375.32 2 L
N
356.88 375.47 356.92 378.45 367.25 375.33 356.84 372.5 4 Y
N
356.88 375.47 356.92 378.45 367.25 375.33 356.84 372.5 4 Y
V
256.82 375.32 263.03 375.32 263.03 392.7 347.48 393 347.48 375.6 356.63 375.47 6 L
N
269.89 352.09 269.89 355.07 280.26 352.09 269.89 349.12 4 Y
N
269.89 352.09 269.89 355.07 280.26 352.09 269.89 349.12 4 Y
V
163.84 330 264.41 330 264.41 352.09 269.64 352.09 4 L
N
358.53 352.45 358.53 355.43 368.91 352.45 358.53 349.47 4 Y
N
358.53 352.45 358.53 355.43 368.91 352.45 358.53 349.47 4 Y
V
338.01 352.45 358.28 352.45 2 L
N
445.2 364.81 445.2 367.78 455.58 364.81 445.2 361.83 4 Y
N
445.2 364.81 445.2 367.78 455.58 364.81 445.2 361.83 4 Y
V
424.66 364.81 444.95 364.81 2 L
N
0 10 Q
(LUT/RAM) 199.02 359.48 T
(FFs) 301.5 359.48 T
(Output) 382.6 369.56 T
(Logic) 384.83 352.35 T
J
269.89 364.12 269.89 367.09 280.26 364.12 269.89 361.14 4 Y
N
269.89 364.12 269.89 367.09 280.26 364.12 269.89 361.14 4 Y
V
J
176.81 364.12 176.81 336.57 257.09 336.57 257.09 364.12 269.64 364.12 5 L
J
176.81 364.12 176.81 360.37 2 L
2 Z
N
[7.334 6.356] 7.334 I
176.81 360.37 176.81 340.32 2 L
N
J
176.81 340.32 176.81 336.57 180.56 336.57 3 L
N
[7.135 6.183] 7.135 I
180.56 336.57 253.34 336.57 2 L
N
J
253.34 336.57 257.09 336.57 257.09 340.32 3 L
N
[7.334 6.356] 7.334 I
257.09 340.32 257.09 360.37 2 L
N
J
257.09 360.37 257.09 364.12 260.84 364.12 3 L
N
[5.824 5.048] 5.824 I
260.84 364.12 265.89 364.12 2 L
N
J
265.89 364.12 269.64 364.12 2 L
N
J
210.47 312 426.47 321 R
7 X
V
1 12 Q
0 X
-0.19 (Figure 2.) 224.22 313 P
-0.19 (Typical FPGA PLB structure) 276.03 313 P
164.23 329.7 164.23 355.8 139.98 355.8 3 L
N
144.89 350.58 155.2 370.11 2 L
N
3 F
(m) 131.81 373.89 T
0 F
( inputs) 140.48 373.89 T
3 F
(O) 429.36 373.15 T
0 F
( outputs) 438.03 373.15 T
433.61 358.77 440.48 370.11 2 L
N
54 72 558 720 C
0 0 612 792 C
0 0 0 1 0 0 0 K
FMENDPAGE
%%EndPage: "6" 6
%%Page: "7" 7
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(7) 303 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 X
-0.28 (routability. To combine results of several ORAs, we use the iterative comparator proposed by) 54 712 P
-0.28 (Sridhar and) 502.63 712 P
0.39 (Hayes) 54 691 P
0 9.6 Q
0.31 ([16]) 83.99 695.8 P
0 12 Q
0.39 (, sho) 99.98 691 P
0.39 (wn within dotted lines in Figure) 122.74 691 P
0.39 (3. Here each ORA compares) 281.35 691 P
0.39 (corresponding) 423.9 691 P
0.39 ( outputs from) 492.56 691 P
0.14 (tw) 54 481 P
0.14 (o B) 65.88 481 P
0.14 (UTs to produce a local mismatch signal \050) 82.9 481 P
3 F
0.14 (LMM) 281.53 481 P
0 F
0.14 (\051, which is ORed with the pre) 308.19 481 P
0.14 (vious mismatch signal) 450.38 481 P
0.65 (\050) 54 460 P
3 F
0.65 (PMM) 58 460 P
0 F
0.65 (\051 from the pre) 85.32 460 P
0.65 (vious ORA to generate the ORA mismatch \050) 153.28 460 P
3 F
0.65 (MM) 370.82 460 P
0 F
0.65 (\051. The) 390.81 460 P
0.65 (FF is required to record the) 423.77 460 P
-0.02 (first mismatch encountered during the BIST sequence. The feedback from the FF output to the first ORA) 54 439 P
0.19 (disables further comparisons after the first error has been recorded. Depending on the number of outputs) 54 418 P
-0.14 (to be compared and on the number of LUTs available in a PLB, several PLBs may be needed to construct) 54 397 P
(an ORA.) 54 376 T
1 14 Q
(3. Ev) 206.06 341.67 T
(aluation of FPGA Resour) 236.26 341.67 T
(ces) 388.06 341.67 T
0 12 Q
0.28 (An important goal of our FPGA BIST strategy is to minimize the number of test sessions as well as) 75.6 321 P
-0.29 (the number of test phases required to completely test all of the PLBs in the FPGA. Therefore, we consider) 54 300 P
0.38 (the FPGA resources required to implement the BIST approach with respect to the resources available in) 54 279 P
-0.32 (the FPGA to determine the minimum number of test sessions \050) 54 258 P
3 F
-0.32 (N) 351.46 258 P
3 8 Q
-0.21 (TS) 359.47 255.5 P
0 12 Q
-0.32 (\051 required to completely test all PLBs in) 367.91 258 P
0.54 (a given FPGA. The number of test sessions is a function of the number of PLBs in the FPGA \050) 54 237 P
3 F
0.54 (N) 518.24 237 P
3 8 Q
0.36 (PLB) 526.24 234.5 P
0 12 Q
0.54 (\051 as) 540.47 237 P
(well as the number of BUTs \050) 54 216 T
3 F
(N) 196.64 216 T
3 8 Q
(BUT) 204.65 213.5 T
0 12 Q
(\051 such that the general expression for) 219.76 216 T
3 F
(N) 400.05 216 T
3 8 Q
(TS) 408.05 213.5 T
0 12 Q
(is given by:) 419.5 216 T
(\0501a\051) 538.68 183 T
0.32 (In addition, the following relation must hold for any FPGA architecture in terms of the number of PLBs) 54 153 P
(required to act as TPGs \050) 54 132 T
3 F
(N) 173.64 132 T
3 8 Q
(TPG) 181.64 129.5 T
0 12 Q
(\051 and ORAs \050) 196.76 132 T
3 F
(N) 261.08 132 T
3 8 Q
(ORA) 269.08 129.5 T
0 12 Q
(\051 during a testing session:) 284.63 132 T
(\0501b\051) 538.01 106 T
-0.19 (Given that we know) 75.6 80 P
3 F
-0.19 (N) 174.82 80 P
3 8 Q
-0.13 (PLB) 182.83 77.5 P
0 12 Q
-0.19 ( for a given FPGA, we must determine the number of PLBs required for the) 197.05 80 P
54 516 558 687 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
178.18 635.7 200.96 635.7 2 L
0.5 H
2 Z
0 X
0 0 0 1 0 0 0 K
N
178.18 605.32 200.96 605.32 2 L
N
152.98 630.63 182.23 630.63 2 L
N
0 90 7.59 15.19 178.18 620.51 A
270 360 7.59 15.19 178.18 620.51 A
152.98 610.38 182.23 610.38 2 L
N
7 X
270 360 18.98 15.19 200.96 620.51 G
0 X
270 360 18.98 15.19 200.96 620.51 A
7 X
0 90 18.98 15.19 200.96 620.51 G
0 X
0 90 18.98 15.19 200.96 620.51 A
3 14 Q
(LMM) 148.46 619.04 T
(PMM) 108.78 586.71 T
220.37 620.09 231.34 620.09 2 L
7 X
V
0 X
N
(MM) 220.37 608.95 T
450.38 577.18 507.79 634.86 R
0 Z
N
436.02 620.44 450.38 620.44 2 L
2 Z
N
507.79 620.44 522.14 620.44 2 L
N
3 16 Q
(D) 453.96 615.49 T
436.42 591.54 450.77 591.54 2 L
N
(C) 454.36 586.6 T
(Q) 496.89 615.49 T
(FF) 472.54 599.61 T
99 610.5 139.5 651 R
7 X
V
0 Z
0 X
N
4 24 Q
(\305) 110.03 623.76 T
119.25 666.86 119.25 664.82 2 L
1.5 H
N
90 450 0.75 0.75 270 119.25 666.86 GG
119.25 664.82 122.8 666.11 119.25 653.72 115.7 666.11 4 Y
N
119.25 664.82 122.8 666.11 119.25 653.72 115.7 666.11 4 Y
V
119.25 678 119.25 666.86 2 L
7 X
V
2 Z
0 X
N
83.14 630.75 85.18 630.75 2 L
0 Z
N
90 450 0.75 0.75 83.14 630.75 G
85.18 630.75 83.89 634.3 96.28 630.75 83.89 627.2 4 Y
N
85.18 630.75 83.89 634.3 96.28 630.75 83.89 627.2 4 Y
V
72 630.75 83.14 630.75 2 L
7 X
V
2 Z
0 X
N
139.5 630.75 153 630.75 2 L
7 X
V
0.5 H
0 X
N
153 610.5 153 597 72 597 3 L
N
230.99 620.07 248.99 620.07 2 L
N
376.33 635.7 399.11 635.7 2 L
N
376.33 605.32 399.11 605.32 2 L
N
351.14 630.63 380.38 630.63 2 L
N
0 90 7.59 15.19 376.33 620.51 A
270 360 7.59 15.19 376.33 620.51 A
351.14 610.38 380.38 610.38 2 L
N
7 X
270 360 18.98 15.19 399.11 620.51 G
0 X
270 360 18.98 15.19 399.11 620.51 A
7 X
0 90 18.98 15.19 399.11 620.51 G
0 X
0 90 18.98 15.19 399.11 620.51 A
3 14 Q
(LMM) 346.61 619.04 T
(PMM) 306.93 586.71 T
418.52 620.09 429.49 620.09 2 L
7 X
V
0 X
N
(MM) 418.52 608.95 T
297.15 610.5 337.65 651 R
7 X
V
0 Z
0 X
N
4 24 Q
(\305) 308.18 623.76 T
317.4 666.86 317.4 664.82 2 L
1.5 H
N
90 450 0.75 0.75 270 317.4 666.86 GG
317.4 664.82 320.95 666.11 317.4 653.72 313.85 666.11 4 Y
N
317.4 664.82 320.95 666.11 317.4 653.72 313.85 666.11 4 Y
V
317.4 678 317.4 666.86 2 L
7 X
V
2 Z
0 X
N
281.29 630.75 283.33 630.75 2 L
0 Z
N
90 450 0.75 0.75 281.29 630.75 G
283.33 630.75 282.04 634.3 294.43 630.75 282.04 627.2 4 Y
N
283.33 630.75 282.04 634.3 294.43 630.75 282.04 627.2 4 Y
V
270.15 630.75 281.29 630.75 2 L
7 X
V
2 Z
0 X
N
337.65 630.75 351.15 630.75 2 L
7 X
V
0.5 H
0 X
N
351.15 610.5 351.15 597 270.15 597 3 L
N
429.14 620.07 447.14 620.07 2 L
N
J
270 597 248.99 620.07 2 L
J
270 597 267.48 599.77 2 L
N
[8.671 7.515] 8.671 I
267.48 599.77 251.52 617.3 2 L
N
J
251.52 617.3 248.99 620.07 2 L
N
J
522.14 620.44 522 552 306 552 3 L
N
72 597 72 552 216 552 3 L
N
J
216 552 306 552 2 L
J
216 552 219.75 552 2 L
N
[8.088 7.01] 8.088 I
219.75 552 302.25 552 2 L
N
J
302.25 552 306 552 2 L
N
1 12 Q
(Figure 3.) 123.23 535 T
(ORA designed as an iterative comparator with error locking) 175.22 535 T
J
J
81 669 428.43 669 428.43 579 81 579 4 Y
J
81 667 81 669 83 669 3 L
0 Z
N
[4.04 4.04] 4.04 I
83 669 426.42 669 2 L
N
J
426.42 669 428.43 669 428.43 667 3 L
N
[4.095 4.095] 4.095 I
428.43 667 428.43 581 2 L
N
J
428.43 581 428.43 579 426.43 579 3 L
N
[4.04 4.04] 4.04 I
426.43 579 83 579 2 L
N
J
83 579 81 579 81 581 3 L
N
[4.095 4.095] 4.095 I
81 581 81 667 2 L
N
J
528.47 620.44 529.8 620.44 2 L
N
529.8 620.44 528.72 623.41 539.09 620.44 528.72 617.46 4 Y
N
529.8 620.44 528.72 623.41 539.09 620.44 528.72 617.46 4 Y
V
522.14 620.44 528.47 620.44 2 L
2 Z
N
0 14 Q
(B) 127.22 674.71 T
(UT) 136.42 674.71 T
3 9.6 Q
(j) 155.08 671.71 T
0 14 Q
(B) 59.04 636.69 T
(UT) 68.24 636.69 T
3 9.6 Q
(i) 86.37 633.69 T
0 0 612 792 C
251.32 168.42 344.36 211.07 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(N) 257.06 189.67 T
3 10 Q
(T) 266.24 185.32 T
(S) 272.39 185.32 T
3 12 Q
(N) 304.23 197.86 T
3 10 Q
(P) 313.41 193.52 T
(L) 320.11 193.52 T
(B) 326.26 193.52 T
3 12 Q
(N) 303.25 179.32 T
3 10 Q
(B) 312.51 174.97 T
(U) 319.21 174.97 T
(T) 327.02 174.97 T
0 12 Q
(-) 303.01 187.35 T
(-) 305.01 187.35 T
(-) 307.01 187.35 T
(-) 309 187.35 T
(-) 311 187.35 T
(-) 313 187.35 T
(-) 315 187.35 T
(-) 316.99 187.35 T
(-) 318.99 187.35 T
(-) 320.99 187.35 T
(-) 322.99 187.35 T
(-) 324.99 187.35 T
(-) 326.98 187.35 T
(-) 328.98 187.35 T
(-) 329.35 187.35 T
(=) 283.47 189.67 T
297.43 173.67 297.43 206.86 301.03 206.86 3 L
0.54 H
2 Z
N
339.05 173.67 339.05 206.86 335.45 206.86 3 L
N
0 0 612 792 C
207.67 97.92 384.33 116.67 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(N) 217.6 105.67 T
3 10 Q
(B) 226.86 101.32 T
(U) 233.56 101.32 T
(T) 241.37 101.32 T
3 12 Q
(N) 260.71 105.67 T
3 10 Q
(T) 269.89 101.32 T
(P) 276.04 101.32 T
(G) 282.74 101.32 T
3 12 Q
(N) 302.96 105.67 T
3 10 Q
(O) 312.14 101.32 T
(R) 319.95 101.32 T
(A) 326.65 101.32 T
0 12 Q
(+) 250.7 105.67 T
(+) 292.95 105.67 T
3 F
(N) 345.58 105.67 T
3 10 Q
(P) 354.76 101.32 T
(L) 361.46 101.32 T
(B) 367.61 101.32 T
4 12 Q
(\243) 335.76 105.67 T
0 0 612 792 C
0 0 0 1 0 0 0 K
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(8) 303 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 X
-0.13 (TPGs, ORAs, and BUTs in order to determine the number of test sessions. During most of the test phases) 54 712 P
-0.74 (used to test various operational modes of the BUTs, the TPGs work as binary counters to supply exhaustive) 54 691 P
-0.63 (test patterns to the) 54 670 P
3 F
-0.63 (m) 142.15 670 P
0 F
-0.63 (-input BUTs \050not counting the clock input\051. Since a PLB has more inputs than outputs,) 150.81 670 P
-0.25 (several PLBs are needed to construct a single) 54 649 P
3 F
-0.25 (m) 272.59 649 P
0 F
-0.25 (-bit counter. Since one or more TPGs can drive the BUTs,) 281.25 649 P
(let the number of TPGs used be) 54 628 T
3 F
(T) 208.98 628 T
0 F
(. This results in a total number of PLBs used for TPGs,) 215.65 628 T
3 F
(N) 482.98 628 T
3 8 Q
(TPG) 490.98 625.5 T
0 12 Q
(, given by:) 506.09 628 T
(\0502\051) 544.01 607 T
0.3 (where) 54 578 P
3 F
0.3 (f) 86.62 578 P
0 F
0.3 ( is the number of FFs per PLB. In general, several ORA circuits may be implemented in a single) 89.95 578 P
-0.08 (PLB, depending on the number of LUTs in a PLB,) 54 557 P
3 F
-0.08 (L) 299.23 557 P
0 F
-0.08 (. Let the number of corresponding outputs compared) 305.9 557 P
0.05 (by a LUT in the PLB of an ORA be denoted by) 54 536 P
3 F
0.05 (C) 285.27 536 P
0 F
0.05 (. Then we can group the) 293.28 536 P
3 F
0.05 (N) 412.56 536 P
3 8 Q
0.04 (BUT) 420.57 533.5 P
0 12 Q
0.05 ( BUTs into) 435.68 536 P
3 F
0.05 (C) 492.18 536 P
0 F
0.05 ( groups of) 500.18 536 P
3 F
0.05 (n) 552 536 P
0 F
-0.59 (BUTs. Now, the) 54 515 P
3 F
-0.59 (O) 133.88 515 P
0 F
-0.59 ( outputs from) 142.54 515 P
3 F
-0.59 (C) 208.43 515 P
0 F
-0.59 ( groups of) 216.43 515 P
3 F
-0.59 (n) 266.31 515 P
0 F
-0.59 ( BUTs must be compared by the ORAs, for a total of) 272.31 515 P
3 F
-0.59 (C) 522.16 515 P
4 F
-0.59 (\264) 530.16 515 P
3 F
-0.59 (n) 536.75 515 P
4 F
-0.59 (\264) 542.75 515 P
3 F
-0.59 (O) 549.34 515 P
0 F
-0.55 (outputs, where each ORA LUT monitors) 54 494 P
3 F
-0.55 (C) 249.7 494 P
0 F
-0.55 ( identical outputs, one output from each group of) 257.7 494 P
3 F
-0.55 (n) 490.76 494 P
0 F
-0.55 ( BUTs. Then) 496.76 494 P
(the number of PLBs configured as ORAs,) 54 473 T
3 F
(N) 257.98 473 T
3 8 Q
(ORA) 265.98 470.5 T
0 12 Q
(, is given by:) 281.53 473 T
(\0503\051) 544.01 440 T
(The total number of BUTs,) 54 414 T
3 F
(N) 187.32 414 T
3 8 Q
(BUT) 195.32 411.5 T
0 12 Q
(, is given by:) 210.44 414 T
(\0504\051) 544.01 388 T
0.36 (The values of) 75.6 364 P
3 F
0.36 (C) 144.99 364 P
0 F
0.36 (,) 152.99 364 P
3 F
0.36 ( O) 155.99 364 P
0 F
0.36 (,) 168.02 364 P
3 F
0.36 (L) 174.37 364 P
0 F
0.36 (, and) 181.05 364 P
3 F
0.36 (f) 208.09 364 P
0 F
0.36 ( are functions of the PLB architecture for the given FPGA being tested.) 211.43 364 P
-0.67 (Substituting Equations 2 through 4 into Equations 1a and 1b, we obtain the following lower bound for) 54 343 P
3 F
-0.67 (N) 535.88 343 P
3 8 Q
-0.45 (TS) 543.89 340.5 P
0 12 Q
-0.67 (:) 552.34 343 P
(\0505\051) 544.01 292 T
0.23 (The number of BUTs in each of the) 75.6 248 P
3 F
0.23 (C) 251.39 248 P
0 F
0.23 ( groups, given by) 259.4 248 P
3 F
0.23 (n) 346.64 248 P
0 F
0.23 (, is one of the primary values of interest to) 352.64 248 P
0.78 (be determined for a given FPGA. For example, the value of) 54 227 P
3 F
0.78 (n) 351.56 227 P
0 F
0.78 ( used to derive Equation 5 represents the) 357.56 227 P
0.65 (maximum value for the number of BUTs in each of the) 54 206 P
3 F
0.65 (C) 328.75 206 P
0 F
0.65 (groups for that particular value of) 340.4 206 P
3 F
0.65 (N) 508.92 206 P
3 8 Q
0.43 (TS) 516.92 203.5 P
0 12 Q
0.65 ( and is) 525.37 206 P
(given by:) 54 183.83 T
(\0506\051) 544.01 150.83 T
1.69 (This maximum value may be difficult to implement in practice due to limitations of the routing) 75.6 110.83 P
0.62 (resources in the FPGA. Therefore, substituting the value of) 54 89.83 P
3 F
0.62 (N) 346.55 89.83 P
3 8 Q
0.41 (BUT) 354.55 87.33 P
0 12 Q
0.62 ( from Equation 4 into Equation 1a, we) 369.67 89.83 P
252.99 587.43 348.02 622.03 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(N) 256.71 603.7 T
3 10 Q
(T) 265.89 599.35 T
(P) 272.04 599.35 T
(G) 278.74 599.35 T
3 12 Q
(T) 304.72 603.7 T
(m) 328.09 608.05 T
(f) 330.76 593.35 T
0 F
(-) 328.09 601.39 T
(-) 330.09 601.39 T
(-) 332.09 601.39 T
(-) 332.76 601.39 T
4 F
(\327) 315.32 603.7 T
0 F
(=) 291.96 603.7 T
322.52 591.55 322.52 617.05 326.11 617.05 3 L
0.54 H
2 Z
N
342.45 591.55 342.45 617.05 338.86 617.05 3 L
N
0 0 612 792 C
54 72 558 720 C
257.22 428.7 340.78 459.2 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(N) 262.27 440 T
3 10 Q
(O) 271.45 435.65 T
(R) 279.26 435.65 T
(A) 285.96 435.65 T
3 12 Q
(O) 311.07 446.66 T
(n) 328.73 446.66 T
4 F
(\327) 322.74 446.66 T
3 F
(L) 319.6 431.96 T
0 F
(-) 311.07 440 T
(-) 313.07 440 T
(-) 315.07 440 T
(-) 317.07 440 T
(-) 319.07 440 T
(-) 321.06 440 T
(-) 323.06 440 T
(-) 325.06 440 T
(-) 327.06 440 T
(-) 329.05 440 T
(-) 330.74 440 T
(=) 298.07 440 T
54 72 558 720 C
0 0 612 792 C
258.72 380.25 339.29 399 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(N) 262.56 388 T
3 10 Q
(B) 271.82 383.65 T
(U) 278.52 383.65 T
(T) 286.33 383.65 T
3 12 Q
(C) 311.42 388 T
(n) 328.69 388 T
4 F
(\327) 322.69 388 T
0 F
(=) 298.66 388 T
0 0 612 792 C
195.76 259.42 405.25 333.66 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(N) 219.02 295.35 T
3 10 Q
(T) 228.2 291 T
(S) 234.35 291 T
3 12 Q
(N) 278.94 309.81 T
3 10 Q
(P) 288.12 305.46 T
(L) 294.82 305.46 T
(B) 300.97 305.46 T
3 12 Q
(C) 313.25 309.81 T
(O) 334.52 316.47 T
(L) 335.55 301.77 T
0 F
(-) 334.52 309.81 T
(-) 336.52 309.81 T
(-) 338.52 309.81 T
(-) 339.19 309.81 T
(+) 324.52 309.81 T
4 F
(\350) 307.79 303.77 T
(\370) 343.08 303.77 T
(\346) 307.79 314.05 T
(\366) 343.08 314.05 T
3 F
(C) 258.79 278.57 T
(N) 273.47 278.57 T
3 10 Q
(P) 282.65 274.22 T
(L) 289.35 274.22 T
(B) 295.5 274.22 T
3 12 Q
(T) 319.06 278.57 T
(m) 342.43 282.92 T
(f) 345.1 268.22 T
0 F
(-) 342.43 276.26 T
(-) 344.43 276.26 T
(-) 346.43 276.26 T
(-) 347.1 276.26 T
4 F
(\327) 329.66 278.57 T
(\350) 313.61 272.53 T
(\370) 357.53 272.53 T
(\346) 313.61 282.81 T
(\366) 357.53 282.81 T
0 F
(\320) 304.61 278.57 T
(-) 258.79 293.03 T
(-) 260.79 293.03 T
(-) 262.79 293.03 T
(-) 264.79 293.03 T
(-) 266.79 293.03 T
(-) 268.78 293.03 T
(-) 270.78 293.03 T
(-) 272.78 293.03 T
(-) 274.78 293.03 T
(-) 276.78 293.03 T
(-) 278.77 293.03 T
(-) 280.77 293.03 T
(-) 282.77 293.03 T
(-) 284.77 293.03 T
(-) 286.77 293.03 T
(-) 288.76 293.03 T
(-) 290.76 293.03 T
(-) 292.76 293.03 T
(-) 294.76 293.03 T
(-) 296.76 293.03 T
(-) 298.75 293.03 T
(-) 300.75 293.03 T
(-) 302.75 293.03 T
(-) 304.75 293.03 T
(-) 306.75 293.03 T
(-) 308.74 293.03 T
(-) 310.74 293.03 T
(-) 312.74 293.03 T
(-) 314.74 293.03 T
(-) 316.74 293.03 T
(-) 318.73 293.03 T
(-) 320.73 293.03 T
(-) 322.73 293.03 T
(-) 324.73 293.03 T
(-) 326.73 293.03 T
(-) 328.72 293.03 T
(-) 330.72 293.03 T
(-) 332.72 293.03 T
(-) 334.72 293.03 T
(-) 336.71 293.03 T
(-) 338.71 293.03 T
(-) 340.71 293.03 T
(-) 342.71 293.03 T
(-) 344.71 293.03 T
(-) 346.7 293.03 T
(-) 348.7 293.03 T
(-) 350.7 293.03 T
(-) 352.7 293.03 T
(-) 354.7 293.03 T
(-) 356.7 293.03 T
(-) 358.69 293.03 T
(-) 360.69 293.03 T
(-) 362.69 293.03 T
(-) 364.69 293.03 T
(-) 364.8 293.03 T
4 F
(\263) 242.43 295.35 T
336.86 266.42 336.86 291.92 340.45 291.92 3 L
0.54 H
2 Z
N
356.79 266.42 356.79 291.92 353.2 291.92 3 L
N
272.57 269.74 268.97 269.74 268.97 292.2 3 L
N
268.97 292.2 272.57 292.2 2 L
N
364 269.74 367.59 269.74 367.59 292.2 3 L
N
367.59 292.2 364 292.2 2 L
N
253.22 264.34 253.22 327.55 256.82 327.55 3 L
N
374.49 264.34 374.49 327.55 370.89 327.55 3 L
N
0 0 612 792 C
225.03 121.72 381.98 189.03 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(n) 230.41 153.62 T
(m) 236.86 147.77 T
(a) 246.24 147.77 T
(x) 252.94 147.77 T
(N) 277.91 170.4 T
3 10 Q
(P) 287.09 166.05 T
(L) 293.79 166.05 T
(B) 299.94 166.05 T
3 12 Q
(T) 323.5 170.4 T
(m) 346.87 174.75 T
(f) 349.54 160.05 T
0 F
(-) 346.87 168.09 T
(-) 348.87 168.09 T
(-) 350.87 168.09 T
(-) 351.54 168.09 T
4 F
(\327) 334.1 170.4 T
(\350) 318.04 164.35 T
(\370) 361.97 164.35 T
(\346) 318.04 174.64 T
(\366) 361.97 174.64 T
0 F
(\320) 309.05 170.4 T
3 F
(C) 307.63 136.61 T
(O) 328.9 143.27 T
(L) 329.93 128.57 T
0 F
(-) 328.9 136.61 T
(-) 330.9 136.61 T
(-) 332.9 136.61 T
(-) 333.57 136.61 T
(+) 318.9 136.61 T
(-) 277.67 151.31 T
(-) 279.67 151.31 T
(-) 281.67 151.31 T
(-) 283.66 151.31 T
(-) 285.66 151.31 T
(-) 287.66 151.31 T
(-) 289.66 151.31 T
(-) 291.65 151.31 T
(-) 293.65 151.31 T
(-) 295.65 151.31 T
(-) 297.65 151.31 T
(-) 299.65 151.31 T
(-) 301.64 151.31 T
(-) 303.64 151.31 T
(-) 305.64 151.31 T
(-) 307.64 151.31 T
(-) 309.64 151.31 T
(-) 311.63 151.31 T
(-) 313.63 151.31 T
(-) 315.63 151.31 T
(-) 317.63 151.31 T
(-) 319.63 151.31 T
(-) 321.62 151.31 T
(-) 323.62 151.31 T
(-) 325.62 151.31 T
(-) 327.62 151.31 T
(-) 329.62 151.31 T
(-) 331.61 151.31 T
(-) 333.61 151.31 T
(-) 335.61 151.31 T
(-) 337.61 151.31 T
(-) 339.61 151.31 T
(-) 341.6 151.31 T
(-) 343.6 151.31 T
(-) 345.6 151.31 T
(-) 347.6 151.31 T
(-) 349.6 151.31 T
(-) 351.59 151.31 T
(-) 353.59 151.31 T
(-) 355.59 151.31 T
(-) 357.59 151.31 T
(-) 359.59 151.31 T
(-) 361.58 151.31 T
(-) 363.58 151.31 T
(-) 363.78 151.31 T
4 F
(\243) 261.31 153.62 T
341.3 158.25 341.3 183.75 344.89 183.75 3 L
0.54 H
2 Z
N
361.23 158.25 361.23 183.75 357.64 183.75 3 L
N
272.09 126.77 272.09 185.83 2 L
N
272.09 126.77 275.69 126.77 2 L
N
373.47 126.77 373.47 185.83 2 L
N
373.47 126.77 369.87 126.77 2 L
N
0 0 612 792 C
0 0 0 1 0 0 0 K
FMENDPAGE
%%EndPage: "8" 8
%%Page: "9" 9
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(9) 303 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 X
(obtain the lower limit on) 54 712 T
3 F
(n) 175.67 712 T
0 F
( for a given value of) 181.67 712 T
3 F
(N) 281.64 712 T
3 8 Q
(TS) 289.64 709.5 T
0 12 Q
(:) 298.09 712 T
(\0507\051) 544.01 679 T
0.1 (However, this minimum value of) 54 649 P
3 F
0.1 (n) 216.5 649 P
0 F
0.1 ( \050given by Equation 7\051 does not consider the proper balance of BUTs,) 222.5 649 P
0.1 (TPGs, and ORAs that must be maintained as a function of the PLB architecture. As a result, we consider) 54 628 P
(the following relation, which is obtained by eliminating) 54 607 T
3 F
(N) 324.32 607 T
3 9.6 Q
(PLB) 332.33 604 T
0 12 Q
( from Equations 1a and 1b:) 349.4 607 T
(\0508\051) 544.01 580 T
0.08 (Substituting the expressions from Equations 2 through 4 into Equation 8 and solving for) 54 560 P
3 F
0.08 (n) 481.11 560 P
0 F
0.08 (, we obtain the) 487.11 560 P
-0.07 (minimum value of) 54 539 P
3 F
-0.07 (n) 145.46 539 P
0 F
-0.07 ( which will provide the proper balance of BUT, TPG, and ORA functions for a BIST) 151.46 539 P
(session based on the PLB architecture \050which we refer to as) 54 518 T
3 F
(n) 343.6 518 T
3 8 Q
(arch) 349.6 515.5 T
0 12 Q
(\051:) 364.26 518 T
(\0509\051) 544.01 482 T
-0.01 (The minimum value of) 75.6 438 P
3 F
-0.01 (n) 188.88 438 P
0 F
-0.01 ( is of particular importance since it requires less logic and routing resources) 194.88 438 P
-0.7 (in the FPGA, when compared to larger values of) 54 417 P
3 F
-0.7 (n) 283.62 417 P
0 F
-0.7 (, providing the best opportunity for successful placement) 289.62 417 P
1.15 (and routing during actual implementation. Therefore, the final minimum value of) 54 396 P
3 F
1.15 (n) 459.58 396 P
0 F
1.15 ( which ensures the) 465.58 396 P
-0.31 (proper balance of BUTs, ORAs, and TPGs, while also ensuring that the FPGA can be tested in the desired) 54 375 P
0.07 (number of test sessions is a function of both) 54 354 P
3 F
0.07 (n) 268.93 354 P
3 8 Q
0.05 (arch) 274.93 351.5 P
0 12 Q
0.07 ( and) 289.6 354 P
3 F
0.07 (n) 313.06 354 P
3 8 Q
0.05 (min) 319.06 351.5 P
0 12 Q
0.07 (. As a result,) 331.06 354 P
3 F
0.07 (n) 394.66 354 P
3 8 Q
0.05 (min\050final\051) 400.66 351.5 P
0 12 Q
0.07 ( is given by the maximum) 432.65 354 P
(of the two minimum values for) 54 333 T
3 F
(n) 205.99 333 T
0 F
( in Equations 7 and 9.) 211.99 333 T
(\05010\051) 538.01 292 T
0.7 (To illustrate the use of these equations, we consider the following examples using the ORCA PLB) 75.6 248 P
0.89 (architecture. In the ORCA PLB, there can be) 54 227 P
3 F
0.89 (L) 279.72 227 P
0 F
0.89 (=2 independent LUTs for ORA construction, with each) 286.39 227 P
1.06 (LUT having) 54 206 P
3 F
1.06 (C) 118.11 206 P
0 F
1.06 (+1=5 inputs so that) 126.11 206 P
3 F
1.06 (C) 225.89 206 P
0 F
1.06 (=4 \050the \322+1\323 term accounts for the additional input used for error) 233.89 206 P
0.06 (latching\051. Since each PLB has) 54 185 P
3 F
0.06 (m) 201.59 185 P
0 F
0.06 (=18 inputs, the maximum number of FFs required for a TPG to generate) 210.26 185 P
-0.54 (exhaustive test patterns is also 18, but there are only) 54 164 P
3 F
-0.54 (f) 302.28 164 P
0 F
-0.54 (=4 FFs per PLB; hence 5 PLBs are required per TPG.) 305.62 164 P
0.06 (Finally, there are) 54 143 P
3 F
0.06 (O) 138.82 143 P
0 F
0.06 (=5 outputs from each PLB which must be compared by the ORAs. From Equation 10) 147.48 143 P
-0.15 (we find that) 54 122 P
3 F
-0.15 (n) 113.87 122 P
4 F
-0.15 (\263) 119.87 122 P
0 F
-0.15 (14 \050given by) 126.45 122 P
3 F
-0.15 (n) 189.66 122 P
3 8 Q
-0.1 (arch) 195.66 119.5 P
0 12 Q
-0.15 (\051 in order to achieve the minimum number of test sessions \050) 210.32 122 P
3 F
-0.15 (N) 494.28 122 P
3 8 Q
-0.1 (TS) 502.28 119.5 P
0 12 Q
-0.15 (=2\051. Then) 510.73 122 P
3.06 (for) 54 101 P
3 F
3.06 (n) 74.05 101 P
0 F
3.06 (=14, we obtain the minimum values) 80.05 101 P
3 F
3.06 (N) 274.15 101 P
3 8 Q
2.04 (TPG) 282.15 98.5 P
0 12 Q
3.06 (=20 \050assuming) 297.26 101 P
3 F
3.06 (T) 377.47 101 P
0 F
3.06 (=) 384.14 101 P
3 F
3.06 (C) 390.91 101 P
0 F
3.06 (\051,) 398.92 101 P
3 F
3.06 (N) 411.97 101 P
3 8 Q
2.04 (ORA) 419.97 98.5 P
0 12 Q
3.06 (=35, and) 435.52 101 P
3 F
3.06 (N) 486.73 101 P
3 8 Q
2.04 (BUT) 494.74 98.5 P
0 12 Q
3.06 (=56 from) 509.85 101 P
0.3 (Equations 2 through 4, respectively. This requires a minimum of 111 PLBs to be able to completely test) 54 80 P
54 72 558 720 C
238.36 661.41 359.65 706.2 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(n) 241.89 683.68 T
(n) 260.48 683.68 T
(m) 266.93 677.84 T
(i) 276.3 677.84 T
(n) 280.35 677.84 T
4 F
(\263) 250.89 683.68 T
3 F
(N) 316.89 691.88 T
3 10 Q
(P) 326.07 687.53 T
(L) 332.77 687.53 T
(B) 338.92 687.53 T
3 12 Q
(N) 312.12 673.34 T
3 10 Q
(T) 321.3 668.99 T
(S) 327.45 668.99 T
3 12 Q
(C) 341.53 673.34 T
4 F
(\327) 335.53 673.34 T
0 F
(-) 311.88 681.37 T
(-) 313.88 681.37 T
(-) 315.88 681.37 T
(-) 317.88 681.37 T
(-) 319.88 681.37 T
(-) 321.87 681.37 T
(-) 323.87 681.37 T
(-) 325.87 681.37 T
(-) 327.87 681.37 T
(-) 329.87 681.37 T
(-) 331.86 681.37 T
(-) 333.86 681.37 T
(-) 335.86 681.37 T
(-) 337.86 681.37 T
(-) 339.86 681.37 T
(-) 341.85 681.37 T
(-) 343.85 681.37 T
(-) 345.8 681.37 T
(=) 292.34 683.68 T
306.31 667.68 306.31 700.88 309.9 700.88 3 L
0.54 H
2 Z
N
355.49 667.68 355.49 700.88 351.9 700.88 3 L
N
54 72 558 720 C
0 0 612 792 C
194.28 574.92 403.73 593.67 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(N) 205.1 582.67 T
3 10 Q
(B) 214.36 578.32 T
(U) 221.06 578.32 T
(T) 228.87 578.32 T
3 12 Q
(N) 248.21 582.67 T
3 10 Q
(T) 257.39 578.32 T
(P) 263.54 578.32 T
(G) 270.24 578.32 T
3 12 Q
(N) 290.46 582.67 T
3 10 Q
(O) 299.64 578.32 T
(R) 307.45 578.32 T
(A) 314.15 578.32 T
0 12 Q
(+) 238.2 582.67 T
(+) 280.45 582.67 T
3 F
(N) 333.08 582.67 T
3 10 Q
(B) 342.35 578.32 T
(U) 349.05 578.32 T
(T) 356.86 578.32 T
3 12 Q
(N) 372.42 582.67 T
3 10 Q
(T) 381.6 578.32 T
(S) 387.75 578.32 T
4 12 Q
(\327) 366.18 582.67 T
(\243) 323.26 582.67 T
0 0 612 792 C
54 72 558 720 C
211.32 449.86 386.69 511.67 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(n) 218.18 479.43 T
(n) 236.76 479.43 T
(a) 243.22 473.58 T
(r) 249.92 473.58 T
(c) 255.3 473.58 T
(h) 261.33 473.58 T
(T) 311.55 494.13 T
(m) 334.92 498.48 T
(f) 337.59 483.78 T
0 F
(-) 334.92 491.82 T
(-) 336.92 491.82 T
(-) 338.92 491.82 T
(-) 339.59 491.82 T
4 F
(\327) 322.15 494.13 T
3 F
(C) 287.58 462.42 T
(N) 309.94 462.42 T
3 10 Q
(T) 319.12 458.07 T
(S) 325.27 458.07 T
0 12 Q
(1) 342.34 462.42 T
(\320) 333.34 462.42 T
4 F
(\050) 304.85 462.42 T
(\051) 349.19 462.42 T
(\327) 298.85 462.42 T
3 F
(O) 365.43 469.08 T
(L) 366.45 454.38 T
0 F
(-) 365.43 462.42 T
(-) 367.42 462.42 T
(-) 369.42 462.42 T
(-) 370.09 462.42 T
(\320) 356.19 462.42 T
(-) 287.58 477.12 T
(-) 289.58 477.12 T
(-) 291.58 477.12 T
(-) 293.58 477.12 T
(-) 295.58 477.12 T
(-) 297.57 477.12 T
(-) 299.57 477.12 T
(-) 301.57 477.12 T
(-) 303.57 477.12 T
(-) 305.57 477.12 T
(-) 307.56 477.12 T
(-) 309.56 477.12 T
(-) 311.56 477.12 T
(-) 313.56 477.12 T
(-) 315.56 477.12 T
(-) 317.55 477.12 T
(-) 319.55 477.12 T
(-) 321.55 477.12 T
(-) 323.55 477.12 T
(-) 325.55 477.12 T
(-) 327.54 477.12 T
(-) 329.54 477.12 T
(-) 331.54 477.12 T
(-) 333.54 477.12 T
(-) 335.54 477.12 T
(-) 337.53 477.12 T
(-) 339.53 477.12 T
(-) 341.53 477.12 T
(-) 343.53 477.12 T
(-) 345.52 477.12 T
(-) 347.52 477.12 T
(-) 349.52 477.12 T
(-) 351.52 477.12 T
(-) 353.52 477.12 T
(-) 355.52 477.12 T
(-) 357.51 477.12 T
(-) 359.51 477.12 T
(-) 361.51 477.12 T
(-) 363.51 477.12 T
(-) 365.51 477.12 T
(-) 367.5 477.12 T
(-) 369.5 477.12 T
(-) 370.33 477.12 T
(=) 268.04 479.43 T
4 F
(\263) 227.17 479.43 T
329.34 481.98 329.34 507.48 332.94 507.48 3 L
0.54 H
2 Z
N
349.28 481.98 349.28 507.48 345.68 507.48 3 L
N
282.01 452.58 282.01 507.48 285.61 507.48 3 L
N
380.03 452.58 380.03 507.48 376.43 507.48 3 L
N
54 72 558 720 C
0 0 612 792 C
158.2 260.69 433.81 324.82 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
3 12 Q
0 X
0 0 0 1 0 0 0 K
(n) 168.44 292.78 T
3 10 Q
(m) 174.9 288.43 T
(i) 182.7 288.43 T
(n) 186.07 288.43 T
(f) 197.17 288.43 T
(i) 200.54 288.43 T
(n) 203.91 288.43 T
(a) 209.5 288.43 T
(l) 215.09 288.43 T
4 F
(\050) 191.66 288.43 T
(\051) 218.59 288.43 T
3 12 Q
(m) 240.68 292.78 T
(a) 250.05 292.78 T
(x) 256.76 292.78 T
(N) 280.38 300.98 T
3 10 Q
(P) 289.56 296.63 T
(L) 296.26 296.63 T
(B) 302.41 296.63 T
3 12 Q
(N) 275.61 282.43 T
3 10 Q
(T) 284.79 278.08 T
(S) 290.94 278.08 T
3 12 Q
(C) 305.02 282.43 T
4 F
(\327) 299.02 282.43 T
0 F
(-) 275.37 290.47 T
(-) 277.37 290.47 T
(-) 279.37 290.47 T
(-) 281.36 290.47 T
(-) 283.36 290.47 T
(-) 285.36 290.47 T
(-) 287.36 290.47 T
(-) 289.36 290.47 T
(-) 291.35 290.47 T
(-) 293.35 290.47 T
(-) 295.35 290.47 T
(-) 297.35 290.47 T
(-) 299.35 290.47 T
(-) 301.34 290.47 T
(-) 303.34 290.47 T
(-) 305.34 290.47 T
(-) 307.34 290.47 T
(-) 309.29 290.47 T
3 F
(T) 353.81 307.48 T
(m) 377.17 311.83 T
(f) 379.85 297.13 T
0 F
(-) 377.17 305.17 T
(-) 379.17 305.17 T
(-) 381.17 305.17 T
(-) 381.84 305.17 T
4 F
(\327) 364.4 307.48 T
3 F
(C) 329.84 275.77 T
(N) 352.19 275.77 T
3 10 Q
(T) 361.37 271.42 T
(S) 367.52 271.42 T
0 12 Q
(1) 384.6 275.77 T
(\320) 375.6 275.77 T
4 F
(\050) 347.1 275.77 T
(\051) 391.45 275.77 T
(\327) 341.1 275.77 T
3 F
(O) 407.68 282.43 T
(L) 408.71 267.73 T
0 F
(-) 407.68 275.77 T
(-) 409.68 275.77 T
(-) 411.68 275.77 T
(-) 412.35 275.77 T
(\320) 398.44 275.77 T
(-) 329.84 290.47 T
(-) 331.84 290.47 T
(-) 333.83 290.47 T
(-) 335.83 290.47 T
(-) 337.83 290.47 T
(-) 339.83 290.47 T
(-) 341.83 290.47 T
(-) 343.82 290.47 T
(-) 345.82 290.47 T
(-) 347.82 290.47 T
(-) 349.82 290.47 T
(-) 351.82 290.47 T
(-) 353.81 290.47 T
(-) 355.81 290.47 T
(-) 357.81 290.47 T
(-) 359.81 290.47 T
(-) 361.8 290.47 T
(-) 363.8 290.47 T
(-) 365.8 290.47 T
(-) 367.8 290.47 T
(-) 369.8 290.47 T
(-) 371.8 290.47 T
(-) 373.79 290.47 T
(-) 375.79 290.47 T
(-) 377.79 290.47 T
(-) 379.79 290.47 T
(-) 381.79 290.47 T
(-) 383.78 290.47 T
(-) 385.78 290.47 T
(-) 387.78 290.47 T
(-) 389.78 290.47 T
(-) 391.77 290.47 T
(-) 393.77 290.47 T
(-) 395.77 290.47 T
(-) 397.77 290.47 T
(-) 399.77 290.47 T
(-) 401.77 290.47 T
(-) 403.76 290.47 T
(-) 405.76 290.47 T
(-) 407.76 290.47 T
(-) 409.76 290.47 T
(-) 411.76 290.47 T
(-) 412.59 290.47 T
({) 262.83 292.78 T
(,) 318.3 292.78 T
(}) 421.6 292.78 T
(=) 227.92 292.78 T
269.79 276.78 269.79 309.98 273.39 309.98 3 L
0.54 H
2 Z
N
318.98 276.78 318.98 309.98 315.38 309.98 3 L
N
371.6 295.33 371.6 320.83 375.2 320.83 3 L
N
391.54 295.33 391.54 320.83 387.94 320.83 3 L
N
324.26 265.93 324.26 320.83 327.86 320.83 3 L
N
422.28 265.93 422.28 320.83 418.68 320.83 3 L
N
0 0 612 792 C
0 0 0 1 0 0 0 K
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(10) 300 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
0.04 (all PLBs in two test sessions. Only the smallest of the ORCA series \050the 1C03 and 2C04 with 100 PLBs\051) 54 712 P
(fails to meet this criteria and will require three test sessions to completely test all of its PLBs.) 54 691 T
-0.18 ( An alternate implementation of an ORA using the ORCA PLB is constructed for) 75.6 665 P
3 F
-0.18 (C) 466.34 665 P
0 F
-0.18 (=2 such that) 474.34 665 P
3 F
-0.18 (L) 535.56 665 P
0 F
-0.18 (=4.) 542.23 665 P
0.23 (From Equation 10 we find that) 54 644 P
3 F
0.23 (n) 206.04 644 P
4 F
0.23 (\263) 212.04 644 P
0 F
0.23 (25 \050this time given by) 218.63 644 P
3 F
0.23 (n) 328.11 644 P
3 8 Q
0.15 (min) 334.11 641.5 P
0 12 Q
0.23 (\051. Then for) 346.11 644 P
3 F
0.23 (n) 401.45 644 P
0 F
0.23 (=25, we obtain) 407.45 644 P
3 F
0.23 (N) 482.9 644 P
3 8 Q
0.15 (TPG) 490.9 641.5 P
0 12 Q
0.23 (=10 \050again) 506.01 644 P
2.83 (assuming) 54 623 P
3 F
2.83 (T) 105.16 623 P
0 F
2.83 (=) 111.83 623 P
3 F
2.83 (C) 118.6 623 P
0 F
2.83 (\051,) 126.61 623 P
3 F
2.83 (N) 139.43 623 P
3 8 Q
1.88 (ORA) 147.43 620.5 P
0 12 Q
2.83 (=32, and) 162.98 623 P
3 F
2.83 (N) 213.73 623 P
3 8 Q
1.88 (BUT) 221.73 620.5 P
0 12 Q
2.83 (=50 from Equations 2 through 4, respectively. This requires a) 236.85 623 P
-0.05 (minimum of 92 PLBs in the ORCA such that the smallest ORCA series FPGAs can now be also tested in) 54 602 P
0 (two test sessions. This analysis is summarized in Table) 54 581 P
0 (2) 321.35 581 P
0 9.6 Q
0 ([17]) 327.35 585.8 P
0 12 Q
0 ( and compared to the Xilinx 4000 and Altera) 343.34 581 P
0.21 (Flex 8000 series FPGAs in terms of the resource parameters for each FPGA and the minimum resources) 54 560 P
0.69 (required for) 54 539 P
3 F
0.69 (N) 115.36 539 P
3 8 Q
0.46 (TS) 123.36 536.5 P
0 12 Q
0.69 (=2 using Equation 10 where we assume that) 131.81 539 P
3 F
0.69 (T) 352.07 539 P
0 F
0.69 (=) 358.74 539 P
3 F
0.69 (C) 365.51 539 P
0 F
0.69 (. In the case of the Xilinx series 4000) 373.51 539 P
-0.65 (FPGAs, the smallest four FPGAs \0504002: 64 PLBs, 4003: 100 PLBs, 4004: 144 PLBs, and 4005: 196 PLBs\051) 54 191 P
-0 (will require three test sessions. However, the Xilinx 4005 can be tested in two test sessions if we let) 54 170 P
3 F
-0 (T) 535.56 170 P
0 F
-0 (=1.) 542.23 170 P
-0.16 (In the case of the Altera Flex 8000 series FPGA, the smallest FPGA \0508282: 208 PLBs\051 also requires three) 54 149 P
0.06 (test sessions. For those cases where the total number of PLBs used for TPG, ORA, and BUT functions is) 54 128 P
-0.42 (less than the total number of PLBs in the FPGA, the unused PLBs could be used to buffer the TPG outputs) 54 107 P
-0.2 (which have high fan-out. On the other hand, when all PLBs in the FPGA are required for BIST resources,) 54 86 P
1 F
(T) 182.15 515 T
(able 2: BIST r) 189.05 515 T
(esour) 261.84 515 T
(ce r) 289.62 515 T
(equir) 308.39 515 T
(ements f) 335.51 515 T
(or FPGAs) 378.19 515 T
(P) 99.74 482 T
(arameter) 106.95 482 T
(Resour) 189.85 482 T
(ce) 226.29 482 T
(ORCA) 278.54 489 T
(\050) 281.78 475 T
2 F
(C) 285.78 475 T
1 F
(=4\051) 293.78 475 T
(ORCA) 328.94 489 T
(\050) 332.18 475 T
2 F
(C) 336.18 475 T
1 F
(=2\051) 344.18 475 T
(Xilinx 4000) 378.63 482 T
(Altera 8000) 449.97 482 T
3 F
(C) 123 455 T
0 F
(comparisons/LUT) 156.8 455 T
(4) 293.2 455 T
(2) 343.6 455 T
(3) 404.8 455 T
(4) 476.8 455 T
3 F
(O) 122.67 437 T
0 F
(outputs/PLB) 156.8 437 T
(5) 293.2 437 T
(5) 343.6 437 T
(5) 404.8 437 T
(3) 476.8 437 T
3 F
(L) 123.66 419 T
0 F
(LUTs/PLB) 156.8 419 T
(2) 293.2 419 T
(4) 343.6 419 T
(2) 404.8 419 T
(1) 476.8 419 T
3 F
(m) 122.67 401 T
0 F
(FFs/TPG=inputs/PLB) 156.8 401 T
(18) 290.2 401 T
(18) 340.6 401 T
(12) 401.8 401 T
(10) 473.8 401 T
3 F
(f) 125.33 383 T
0 F
(FFs/PLB) 156.8 383 T
(4) 293.2 383 T
(4) 343.6 383 T
(2) 404.8 383 T
(1) 476.8 383 T
1 F
(Minimum Requirements) 121.44 365 T
(ORCA) 278.54 365 T
(ORCA) 328.94 365 T
(Xilinx 4000) 378.63 365 T
(Altera 8000) 449.97 365 T
3 F
(n) 147 347 T
3 8 Q
(min) 153 344.5 T
0 12 Q
( \050for) 165 347 T
3 F
(N) 188.99 347 T
3 8 Q
(TS) 196.99 344.5 T
0 12 Q
(=2\051) 205.44 347 T
(14) 290.2 347 T
(25) 340.6 347 T
(36) 401.8 347 T
(40) 473.8 347 T
3 F
(N) 147.66 329 T
3 8 Q
(TPG) 155.67 326.5 T
0 12 Q
(\050for) 173.78 329 T
3 F
(T=C) 194.77 329 T
0 F
(\051) 217.54 329 T
(20) 290.2 329 T
(10) 340.6 329 T
(18) 401.8 329 T
(40) 473.8 329 T
3 F
(N) 148.66 311 T
3 8 Q
(TPG) 156.67 308.5 T
0 12 Q
(\050for) 174.78 311 T
3 F
(T=) 195.77 311 T
0 F
(1\051) 210.54 311 T
(5) 293.2 311 T
(5) 343.6 311 T
(6) 404.8 311 T
(10) 473.8 311 T
3 F
(N) 172.82 293 T
3 8 Q
(ORA) 180.83 290.5 T
0 12 Q
(35) 290.2 293 T
(32) 340.6 293 T
(72) 401.8 293 T
(120) 470.8 293 T
3 F
(N) 173.04 275 T
3 8 Q
(BUT) 181.05 272.5 T
0 12 Q
(56) 290.2 275 T
(50) 340.6 275 T
(108) 398.8 275 T
(160) 470.8 275 T
3 F
(N) 148.11 257 T
3 8 Q
(PLB) 156.11 254.5 T
0 12 Q
(\050for) 173.33 257 T
3 F
(T=C) 194.32 257 T
0 F
(\051) 217.1 257 T
(111) 287.2 257 T
(92) 340.6 257 T
(198) 398.8 257 T
(320) 470.8 257 T
3 F
(N) 149.11 239 T
3 8 Q
(PLB) 157.11 236.5 T
0 12 Q
(\050for) 174.34 239 T
3 F
(T=) 195.32 239 T
0 F
(1\051) 210.1 239 T
(96) 290.2 239 T
(87) 340.6 239 T
(186) 398.8 239 T
(290) 470.8 239 T
97.2 504.75 97.2 235.25 2 L
V
0.5 H
0 Z
N
154.8 505.25 154.8 380.5 2 L
V
N
270 505.25 270 234.75 2 L
V
2 H
N
320.4 505.25 320.4 234.75 2 L
V
0.5 H
N
370.8 505.25 370.8 234.75 2 L
V
N
442.8 505.25 442.8 234.75 2 L
V
N
514.8 504.75 514.8 235.25 2 L
V
N
96.95 505 515.05 505 2 L
V
N
97.45 470.25 514.55 470.25 2 L
V
N
97.45 467.75 514.55 467.75 2 L
V
N
96.95 451 515.05 451 2 L
V
N
96.95 433 515.05 433 2 L
V
N
96.95 415 515.05 415 2 L
V
N
96.95 397 515.05 397 2 L
V
N
97.45 380.25 514.55 380.25 2 L
V
N
97.45 377.75 514.55 377.75 2 L
V
N
97.45 362.25 514.55 362.25 2 L
V
N
97.45 359.75 514.55 359.75 2 L
V
N
96.95 343 515.05 343 2 L
V
N
96.95 325 515.05 325 2 L
V
N
96.95 307 515.05 307 2 L
V
N
96.95 289 515.05 289 2 L
V
N
96.95 271 515.05 271 2 L
V
N
96.95 253 515.05 253 2 L
V
N
96.95 235 515.05 235 2 L
V
N
0 0 0 1 0 0 0 K
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(11) 300 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
3.93 (the number of test sessions may be increased if routing resource limitations prevent successful) 54 712 P
(implementation of BIST.) 54 691 T
1 14 Q
(4. Routability and Scalability) 218.87 656.67 T
0 12 Q
0.12 (During the initial implementations of the BIST approach using ORCA 1C and 2C series FPGAs, we) 75.6 636 P
2.38 (found potential limitations of the BIST architecture in terms of scalability and routability in larger) 54 615 P
-0.36 (FPGAs) 54 594 P
0 9.6 Q
-0.29 ([18]) 89.34 598.8 P
-0.29 ([19]) 105.33 598.8 P
0 12 Q
-0.36 (. These limitations result from the \322global\323 nature of the TPG-to-PLB communication paths) 121.33 594 P
0.28 (as well as the number of BUT-to-ORA and ORA-to-BS connections, coupled with our goal of testing as) 54 573 P
-0.33 (many PLBs per session as possible. For example, each test phase utilizes about 87% of the PLBs and 54%) 54 552 P
-0.54 (of the programmable interconnection network routing segments. Such a high utilization of the FPGA logic) 54 531 P
0.12 (and routing resources reduces the probability of successful routing during implementation. Up to) 54 510 P
3 F
0.12 (m) 523.54 510 P
0 F
0.12 ( TPG) 532.21 510 P
-0.24 (outputs must be routed to) 54 489 P
3 F
-0.24 (n) 177.8 489 P
0 F
-0.24 ( BUTs for) 183.8 489 P
3 F
-0.24 (T) 234.74 489 P
0 F
-0.24 (=) 241.42 489 P
3 F
-0.24 (C) 248.18 489 P
0 F
-0.24 (, while, for) 256.19 489 P
3 F
-0.24 (T) 311.12 489 P
0 F
-0.24 (=1, the TPG outputs must be routed to) 317.8 489 P
3 F
-0.24 (C) 502.98 489 P
4 F
-0.24 (\264) 510.98 489 P
3 F
-0.24 (n) 517.57 489 P
0 F
-0.24 ( BUTs.) 523.57 489 P
-0.01 (Even the smallest FPGAs require a significant number of high fanout nets \050which, in turn, require a large) 54 468 P
-0.55 (number of global routing segments\051 with the number of loads on each of these nets increasing with the size) 54 447 P
0.36 (of the FPGA and/or with decreases in the value of) 54 426 P
3 F
0.36 (T) 300.88 426 P
0 F
0.36 (. These high fanout TPG-to-BUT connections place) 307.55 426 P
1.52 (considerable demands on global routing resources within the FPGA and can make successful routing) 54 405 P
(extremely difficult.) 54 384 T
-0.1 (In our original implementation of the BIST architecture) 75.6 359 P
0 9.6 Q
-0.08 ([17]) 341.87 363.8 P
-0.08 ([18]) 357.86 363.8 P
0 12 Q
-0.1 (, most connections between BUTs and) 373.85 359 P
0.02 (ORAs \050at least 250 wires for ORCA, and at least 540 for Xilinx 4000 series FPGAs\051 also required global) 54 338 P
0.47 (routing resources even though these connections have single loads. In addition, when a large number of) 54 317 P
0.04 (ORA outputs had to be routed to boundary-scan cells in the I/O blocks, the routing resources available at) 54 296 P
0.69 (the periphery of the chip and/or the number of available pins were exhausted. As the size of the FPGA) 54 275 P
-0.71 (increases, the routing resources required for the BUT-to-ORA and ORA-to-BS connections also increased.) 54 254 P
-0.37 (The work-around in our original implementation was to logically OR the outputs of several ORAs prior to) 54 233 P
3.85 (routing to the boundary-scan cell, but this required additional PLBs and reduces the diagnostic) 54 212 P
0.21 (resolution) 54 191 P
0 9.6 Q
0.17 ([18]) 102 195.8 P
0 12 Q
0.21 (. However, we found that, by using iterative comparator based ORA illustrated in Figure) 117.99 191 P
0.21 (3,) 549 191 P
-0.29 (we can take advantage of the error propagation through the ORAs and latch errors only in the last ORA of) 54 170 P
0.88 (the chain. This reduces the number of outputs to route to the boundary-scan cells, which decreases the) 54 149 P
0.18 (routing congestion at the periphery of the chip and avoids the need to further compress ORA outputs via) 54 128 P
(logical OR functions.) 54 107 T
0.22 (Another problem we encountered initially when scaling this BIST architecture to larger FPGAs was) 75.6 82 P
0 0 0 1 0 0 0 K
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(12) 300 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
-0.04 (the considerable manual intervention needed in the placement process to ensure that every PLB is a BUT) 54 503.08 P
-0.18 (in at least one test session. Schematic capture of the BIST architecture was used as the design entry point,) 54 482.08 P
1.16 (followed by use of the FPGA placement and routing software. The physical locations of all non-BUT) 54 461.08 P
0.28 (PLBs during the first test session were recorded after the initial placement, so that they could be used as) 54 440.08 P
1.93 (BUTs during the following test session\050s\051. During the subsequent test session\050s\051, the placement was) 54 419.08 P
1.22 (constrained by specifying the desired physical locations for BUTs, but in many cases these additional) 54 398.08 P
-0.6 (constraints prevented completion of routing. In addition, the task of recording BUT positions from the first) 54 377.08 P
0.1 (test session and constraining BUT locations during the following test session\050s\051 grew in complexity with) 54 356.08 P
0.5 (the size of the FPGA. As a result, the number of test sessions had to be increased in many of our initial) 54 335.08 P
0.8 (implementations to overcome routing resource limitations by reducing the number of BUTs and ORAs) 54 314.08 P
(during a test session.) 54 293.08 T
-0.19 (Our solution to these problems is the structure shown in Figure) 75.6 268.08 P
-0.19 (4a, in which we group one ORA with) 379.35 268.08 P
0.14 (the pair of BUTs it compares in terms of their physical location in the array. The complete floorplan \050for) 54 247.08 P
0.42 (the first test session\051 illustrated in Figure) 54 226.08 P
0.42 (4b for an 8) 255.5 226.08 P
4 F
0.42 (\264) 309.08 226.08 P
0 F
0.42 (8 FPGA) 315.67 226.08 P
0.42 (. The positions for the second test session) 355.76 226.08 P
0.02 (are obtained by flipping the assignments around the horizontal axis showed as a dotted line in the middle) 54 205.08 P
-0.31 (of the array. The row labeled \322used as needed\323 can be used for fanout drivers, additional TPGs, additional) 54 184.08 P
0.28 (ORAs for improved diagnostics, or it may be left unused \050note that this row will be configured as BUTs) 54 163.08 P
0.14 (in the second phase\051. By constraining TPG, ORA, and BUT placement for all test sessions as shown, the) 54 142.08 P
-0.06 (global routing resources are used for interconnecting the TPGs to the BUTs while local routing resources) 54 121.08 P
1.71 (are used for connections between BUTs and ORAs as well as between ORAs in a row. As a result,) 54 100.08 P
0.15 (successful routing of the complete BIST architecture can be ensured prior to implementation without the) 54 79.08 P
51.22 511.08 560.78 720 C
0 0 0 1 0 0 0 K
J
0 0 0 1 0 0 0 K
J
1 12 Q
0 X
0 0 0 1 0 0 0 K
(Figure 4.) 185.17 526.96 T
(Floorplan of PLBs during BIST session.) 237.17 526.96 T
0 10 Q
(Pass/Fail) 306.86 630.09 T
0 12 Q
(a\051 TPG, BUT, & ORA connections) 98.32 542.61 T
77.66 691.02 164.81 707.82 R
0.5 H
0 Z
N
(TPG) 109.9 694.47 T
216.48 691.02 303.63 707.82 R
N
(TPG) 248.72 694.47 T
78.16 648.98 105.99 665.79 R
N
(BUT) 80.07 652.43 T
127.58 648.98 155.41 665.79 R
N
(BUT) 129.49 652.43 T
177.01 648.98 204.83 665.79 R
N
(BUT) 178.92 652.43 T
226.43 648.98 254.25 665.79 R
N
(BUT) 228.34 652.43 T
275.85 648.98 303.67 665.79 R
N
(BUT) 277.76 652.43 T
78.16 617.78 105.99 634.58 R
N
(ORA) 79.41 621.23 T
127.58 617.78 155.41 634.58 R
N
(ORA) 128.83 621.23 T
177.01 617.78 204.83 634.58 R
N
(ORA) 178.25 621.23 T
226.43 617.78 254.25 634.58 R
N
(ORA) 227.67 621.23 T
275.85 617.78 303.67 634.58 R
N
(ORA) 277.09 621.23 T
78.16 586.58 105.99 603.38 R
N
(BUT) 80.07 590.04 T
127.58 586.58 155.41 603.38 R
N
(BUT) 129.49 590.04 T
177.01 586.58 204.83 603.38 R
N
(BUT) 178.92 590.04 T
226.43 586.58 254.25 603.38 R
N
(BUT) 228.34 590.04 T
275.85 586.58 303.67 603.38 R
N
(BUT) 277.76 590.04 T
91.53 639.45 94.1 639.45 91.53 635 88.97 639.45 4 Y
N
91.53 639.45 94.1 639.45 91.53 635 88.97 639.45 4 Y
V
91.53 649.2 91.53 639.7 2 L
2 Z
N
141.53 639.85 144.1 639.84 141.53 635.4 138.97 639.84 4 Y
0 Z
N
141.53 639.85 144.1 639.84 141.53 635.4 138.97 639.84 4 Y
V
141.53 649.6 141.53 640.09 2 L
2 Z
N
191.53 639.2 194.1 639.2 191.53 634.75 188.97 639.2 4 Y
0 Z
N
191.53 639.2 194.1 639.2 191.53 634.75 188.97 639.2 4 Y
V
191.53 648.95 191.53 639.45 2 L
2 Z
N
240.48 639.6 243.05 639.6 240.48 635.15 237.92 639.6 4 Y
0 Z
N
240.48 639.6 243.05 639.6 240.48 635.15 237.92 639.6 4 Y
V
240.48 649.35 240.48 639.85 2 L
2 Z
N
290.48 638.95 293.05 638.95 290.48 634.5 287.92 638.95 4 Y
0 Z
N
290.48 638.95 293.05 638.95 290.48 634.5 287.92 638.95 4 Y
V
290.48 648.7 290.48 639.2 2 L
2 Z
N
91.57 613.15 89 613.15 91.57 617.6 94.13 613.15 4 Y
0 Z
N
91.57 613.15 89 613.15 91.57 617.6 94.13 613.15 4 Y
V
91.57 603.4 91.57 612.9 2 L
2 Z
N
141.57 613.55 139 613.55 141.57 618 144.13 613.55 4 Y
0 Z
N
141.57 613.55 139 613.55 141.57 618 144.13 613.55 4 Y
V
141.57 603.8 141.57 613.3 2 L
2 Z
N
191.57 612.9 189 612.9 191.57 617.35 194.13 612.9 4 Y
0 Z
N
191.57 612.9 189 612.9 191.57 617.35 194.13 612.9 4 Y
V
191.57 603.15 191.57 612.65 2 L
2 Z
N
240.52 613.3 237.95 613.3 240.52 617.75 243.08 613.3 4 Y
0 Z
N
240.52 613.3 237.95 613.3 240.52 617.75 243.08 613.3 4 Y
V
240.52 603.55 240.52 613.05 2 L
2 Z
N
290.52 612.65 287.95 612.65 290.52 617.1 293.08 612.65 4 Y
0 Z
N
290.52 612.65 287.95 612.65 290.52 617.1 293.08 612.65 4 Y
V
290.52 602.9 290.52 612.4 2 L
2 Z
N
91.35 671.75 93.92 671.75 91.35 667.3 88.78 671.75 4 Y
0 Z
N
91.35 671.75 93.92 671.75 91.35 667.3 88.78 671.75 4 Y
V
91.35 681.5 91.35 672 2 L
2 Z
N
141.35 672.15 143.92 672.15 141.35 667.7 138.78 672.15 4 Y
0 Z
N
141.35 672.15 143.92 672.15 141.35 667.7 138.78 672.15 4 Y
V
141.35 681.9 141.35 672.4 2 L
2 Z
N
191.35 671.49 193.92 671.49 191.35 667.05 188.78 671.49 4 Y
0 Z
N
191.35 671.49 193.92 671.49 191.35 667.05 188.78 671.49 4 Y
V
191.35 681.25 191.35 671.74 2 L
2 Z
N
240.3 671.9 242.87 671.9 240.3 667.45 237.73 671.9 4 Y
0 Z
N
240.3 671.9 242.87 671.9 240.3 667.45 237.73 671.9 4 Y
V
240.3 681.65 240.3 672.15 2 L
2 Z
N
290.3 671.24 292.87 671.24 290.3 666.8 287.73 671.24 4 Y
0 Z
N
290.3 671.24 292.87 671.24 290.3 666.8 287.73 671.24 4 Y
V
290.3 681 290.3 671.49 2 L
2 Z
N
91.78 580.35 89.22 580.35 91.78 584.8 94.35 580.35 4 Y
0 Z
N
91.78 580.35 89.22 580.35 91.78 584.8 94.35 580.35 4 Y
V
91.78 570.6 91.78 580.1 2 L
2 Z
N
141.78 580.75 139.22 580.75 141.78 585.2 144.35 580.75 4 Y
0 Z
N
141.78 580.75 139.22 580.75 141.78 585.2 144.35 580.75 4 Y
V
141.78 571 141.78 580.5 2 L
2 Z
N
191.78 580.1 189.22 580.1 191.78 584.55 194.35 580.1 4 Y
0 Z
N
191.78 580.1 189.22 580.1 191.78 584.55 194.35 580.1 4 Y
V
191.78 570.35 191.78 579.85 2 L
2 Z
N
240.73 580.5 238.17 580.5 240.73 584.95 243.3 580.5 4 Y
0 Z
N
240.73 580.5 238.17 580.5 240.73 584.95 243.3 580.5 4 Y
V
240.73 570.75 240.73 580.25 2 L
2 Z
N
290.73 579.85 288.17 579.85 290.73 584.3 293.3 579.85 4 Y
0 Z
N
290.73 579.85 288.17 579.85 290.73 584.3 293.3 579.85 4 Y
V
290.73 570.1 290.73 579.6 2 L
2 Z
N
76.83 699.6 66.33 699.6 66.33 570.45 291.04 570.45 4 L
N
304.68 699.6 313.08 699.6 313.08 681.75 91.53 681.75 4 L
N
122.29 626 122.29 628.57 126.73 626 122.29 623.43 4 Y
0 Z
N
122.29 626 122.29 628.57 126.73 626 122.29 623.43 4 Y
V
106.89 626 122.04 626 2 L
2 Z
N
171.24 626 171.24 628.57 175.68 626 171.24 623.43 4 Y
0 Z
N
171.24 626 171.24 628.57 175.68 626 171.24 623.43 4 Y
V
155.84 626 170.99 626 2 L
2 Z
N
220.19 626 220.19 628.57 224.63 626 220.19 623.43 4 Y
0 Z
N
220.19 626 220.19 628.57 224.63 626 220.19 623.43 4 Y
V
204.79 626 219.94 626 2 L
2 Z
N
271.24 626 271.24 628.57 275.68 626 271.24 623.43 4 Y
0 Z
N
271.24 626 271.24 628.57 275.68 626 271.24 623.43 4 Y
V
255.84 626 270.99 626 2 L
2 Z
N
320.19 626 320.19 628.57 324.64 626 320.19 623.43 4 Y
0 Z
N
320.19 626 320.19 628.57 324.64 626 320.19 623.43 4 Y
V
304.79 626 319.94 626 2 L
2 Z
N
72.94 626.1 72.94 628.67 77.38 626.1 72.94 623.53 4 Y
0 Z
N
72.94 626.1 72.94 628.67 77.38 626.1 72.94 623.53 4 Y
V
310.98 626.1 310.98 563.1 60.03 563.1 60.03 626.1 72.69 626.1 5 L
2 Z
N
374.98 692.65 531.43 711.28 R
0 Z
N
(TPG\050s\051) 435.55 696.23 T
374.98 673.7 531.43 692.34 R
N
(BUTs) 438.88 677.28 T
374.98 654.75 531.43 673.39 R
N
(ORAs) 438.21 658.33 T
374.98 636.1 531.43 654.74 R
N
(BUTs) 438.88 639.68 T
374.98 617.99 531.43 636.62 R
N
(used as needed) 417.22 621.57 T
374.98 599.04 531.43 617.67 R
N
(BUTs) 438.88 602.62 T
374.98 580.39 531.43 599.03 R
N
(ORAs) 438.21 583.97 T
374.98 561.44 531.43 580.08 R
N
(BUTs) 438.88 565.02 T
(b\051 Floorplan for a test session) 385.97 542.61 T
J
369.27 636.62 351.22 636.62 2 L
J
369.27 636.62 367.52 636.62 2 L
2 Z
N
[4.075 5.24] 4.075 I
367.52 636.62 352.97 636.62 2 L
N
J
352.97 636.62 351.22 636.62 2 L
N
J
549.5 636.62 531.45 636.62 2 L
J
549.5 636.62 547.75 636.62 2 L
N
[4.075 5.239] 4.075 I
547.75 636.62 533.2 636.62 2 L
N
J
533.2 636.62 531.45 636.62 2 L
N
0 0 612 792 C
J
0 0 0 1 0 0 0 K
J
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[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(13) 300 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
1.14 (need for keeping records of BUT positions in conjunction with manual assignments of BUT positions) 54 712 P
-0.02 (during subsequent test sessions. More importantly, the structured floorplan ensures that large FPGAs can) 54 691 P
1.58 (be completely tested in only two test sessions. Finally, the BIST architecture can be constructed and) 54 670 P
1.98 (interconnected algorithmically as a function of the size of a given FPGA while ensuring the proper) 54 649 P
(combination of BUTs, TPGs, and ORAs.) 54 628 T
1 14 Q
(5. Results f) 194.77 593.67 T
(or ORCA Implementation) 260.14 593.67 T
0 12 Q
0.53 (In this section we present the results of the implementation of our BIST approach using the ORCA) 75.6 573 P
1.51 (FPGA. We describe the configurations \050test phases\051 needed for a complete BIST session and present) 54 552 P
-0.02 (results regarding memory requirements, test-time, and fault coverage. Based on a gate-level model of the) 54 531 P
-0.56 (ORCA PLB, we determined that nine BIST configurations are sufficient to completely test a BUT in every) 54 510 P
2.38 (functional mode of operation. Then for FPGAs which require only two test sessions, a total of 18) 54 489 P
0.79 (configurations are required to completely test all PLBs in the FPGA. These 18 configurations compare) 54 468 P
-0.19 (favorably with the 32 configurations currently used to test production ORCA devices. However, it should) 54 447 P
3.34 (be noted that the 32 configurations used for manufacturing tests include complete testing of the) 54 426 P
0.28 (programmable interconnection network, testing of the configuration memory and its read-back circuitry,) 54 405 P
0.8 (and testing of the FPGA I/O buffers. Parametric testing and speed sorting is performed with additional) 54 384 P
(configurations of the FPGA.) 54 363 T
0.25 (The memory requirements for storing the BIST configurations depend on the size of the FPGA. For) 75.6 338 P
1.05 (the largest 1C series ORCA \050the 1C09, a 16) 54 317 P
4 F
1.05 (\264) 272.71 317 P
0 F
1.05 (16 PLB FPGA\051, approximately 16 Kbytes of storage are) 279.3 317 P
0.61 (needed per configuration) 54 296 P
0 9.6 Q
0.49 ([9]) 175.19 300.8 P
0 12 Q
0.61 (, which means about 288 Kbytes for the two test sessions for manufacturing) 186.38 296 P
2.38 (testing. For system testing, we need to also store the original system function configuration \050to be) 54 275 P
0.49 (reinstalled after testing\051, which leads to a total of about 300 Kbytes. Unlike the BIST run-time which is) 54 254 P
-0.5 (constant, the configuration download time depends on the size of the FPGA as well as the type of interface) 54 233 P
0.76 (between the configuration storage media and the FPGA itself. Download time for the ORCA 1C series) 54 212 P
0.05 (FPGAs varies from about 2 to 35 msec. \050depending on the download interface\051, while the execution time) 54 191 P
0.34 (for the BIST sequence is approximately 3 msec. at a 10 MHz clock rate. This corresponds to less than 1) 54 170 P
(sec. of testing time required to completely test all of the PLBs in the FPGA.) 54 149 T
1.01 (Although pseudoexhaustive testing does not require fault simulation, we used single stuck-at fault) 75.6 124 P
0.34 (simulation to evaluate the fault coverage obtained in each of the nine different phases of a BIST session) 54 103 P
-0.22 (in order to determine which test phases are most effective. We developed a complete gate-level model for) 54 82 P
0 0 0 1 0 0 0 K
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[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
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[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(14) 300 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
1.26 (the ORCA PLB, including the PLB configuration bits which are represented as primary inputs whose) 54 712 P
1.83 (values are \322frozen\323 during each phase. This allowed us to also simulate stuck-at faults affecting the) 54 691 P
-0.09 (configuration bits. \050Note that the model of any user circuit provided by FPGA CAD tools is only a subset) 54 670 P
0 (of our fault simulation model and does not include configuration bits.\051 The ORCA PLB gate-level model) 54 649 P
1.19 (was broken into the three modules shown in Figure) 54 628 P
1.19 (2: 1\051 LUT/RAM, 2\051 FF/latches, and 3\051 the output) 312.49 628 P
0.14 (multiplexer network. A total of 1942 collapsed stuck-at gate-level faults in the PLB included 1403 faults) 54 607 P
0.51 (in the LUTs, 293 faults in the FF/latches, and 246 faults in the output multiplexers. The faults affecting) 54 586 P
0.87 (the configuration bits are included in the set of faults of the module controlled by those bits. The fault) 54 565 P
-0.27 (simulation results are summarized in Table) 54 544 P
-0.27 (3 in terms of the number of faults detected in each of the three) 262.61 544 P
0.34 (modules and the total faults detected by each test phase as well as the fault coverage obtained with each) 54 523 P
0.05 (test phase. The cumulative number of faults detected and the resultant cumulative fault coverage are also) 54 502 P
-0.14 (included to indicate that 100% single stuck-at fault coverage was obtained over the nine test phases. Note) 54 481 P
-0.08 (that the fault simulation information including the number of faults and fault coverage are with respect to) 54 460 P
(a single BUT.) 54 439 T
-0.52 ( Testing time and configuration memory storage can be reduced for system-level testing by testing the) 75.6 164 P
0.37 (FPGA only for the specific modes of operation in which its PLBs are used by the system function or by) 54 143 P
-0.05 (removing some configurations which detect very few new faults. For example, test phases 1 and 9 can be) 54 122 P
1.92 (combined to create a single test phase which has been determined to provide a single stuck-at fault) 54 101 P
0.72 (coverage of approximately 83%. This single configuration would be applied twice to the FPGA for the) 54 80 P
1 F
(T) 99.88 412 T
(able 3: Cumulati) 106.78 412 T
(v) 192.67 412 T
(e gate-le) 198.55 412 T
(v) 240.68 412 T
(el single stuck-at fault co) 246.56 412 T
(v) 373.1 412 T
(erage f) 378.98 412 T
(or indi) 413.66 412 T
(vidual B) 447.88 412 T
(UTs) 490.78 412 T
(Phase) 57 386 T
(Number of F) 166.8 386 T
(aults Detected) 232.49 386 T
(P) 401.23 386 T
(er Phase) 408.32 386 T
(Cumulati) 483.12 386 T
(v) 531.67 386 T
(e) 537.55 386 T
(No.) 63.17 364 T
(LUTs) 98.73 364 T
(FFs) 154.13 364 T
(MUX) 199.87 364 T
(T) 251.48 364 T
(otal) 258.38 364 T
(Cumulati) 292.1 364 T
(v) 340.66 364 T
(e T) 346.54 364 T
(otal) 361.76 364 T
(F) 387.38 364 T
(ault Co) 394.41 364 T
(v) 431.96 364 T
(erage) 437.84 364 T
(F) 473.78 364 T
(ault Co) 480.81 364 T
(v) 518.36 364 T
(erage) 524.24 364 T
0 F
(1) 69 346 T
(1305) 101.4 346 T
(0) 160.8 346 T
(53) 208.2 346 T
(1358) 252.6 346 T
(1358) 324.6 346 T
(69.9%) 411.1 346 T
(69.9%) 497.5 346 T
(2) 69 328 T
(860) 104.4 328 T
(0) 160.8 328 T
(45) 208.2 328 T
(905) 255.6 328 T
(1420) 324.6 328 T
(46.6%) 411.1 328 T
(73.1%) 497.5 328 T
(3) 69 310 T
(699) 104.4 310 T
(0) 160.8 310 T
(53) 208.2 310 T
(752) 255.6 310 T
(1491) 324.6 310 T
(38.7%) 411.1 310 T
(76.8%) 497.5 310 T
(4) 69 292 T
(707) 104.4 292 T
(0) 160.8 292 T
(53) 208.2 292 T
(760) 255.6 292 T
(1533) 324.6 292 T
(39.1%) 411.1 292 T
(78.9%) 497.5 292 T
(5) 69 274 T
(651) 104.4 274 T
(172) 154.8 274 T
(53) 208.2 274 T
(876) 255.6 274 T
(1737) 324.6 274 T
(45.1%) 411.1 274 T
(89.4%) 497.5 274 T
(6) 69 256 T
(0) 110.4 256 T
(184) 154.8 256 T
(53) 208.2 256 T
(237) 255.6 256 T
(1808) 324.6 256 T
(12.2%) 411.1 256 T
(93.1%) 497.5 256 T
(7) 69 238 T
(712) 104.4 238 T
(147) 154.8 238 T
(53) 208.2 238 T
(912) 255.6 238 T
(1856) 324.6 238 T
(47.0%) 411.1 238 T
(95.6%) 497.5 238 T
(8) 69 220 T
(0) 110.4 220 T
(151) 154.8 220 T
(53) 208.2 220 T
(204) 255.6 220 T
(1906) 324.6 220 T
(10.5%) 411.1 220 T
(98.1%) 497.5 220 T
(9) 69 202 T
(712) 104.4 202 T
(211) 154.8 202 T
(53) 208.2 202 T
(976) 255.6 202 T
(1942) 324.6 202 T
(50.3%) 411.1 202 T
(100%) 499 202 T
55.8 401.75 55.8 196.25 2 L
V
0.5 H
0 Z
N
86.95 401.75 86.95 196.25 2 L
V
N
89.45 401.75 89.45 196.25 2 L
V
N
138.6 380.25 138.6 195.75 2 L
V
N
189 380.25 189 195.75 2 L
V
N
239.4 380.25 239.4 195.75 2 L
V
N
289.8 380.25 289.8 195.75 2 L
V
N
382.15 401.75 382.15 196.25 2 L
V
N
384.65 401.75 384.65 196.25 2 L
V
N
468.55 401.75 468.55 196.25 2 L
V
N
471.05 401.75 471.05 196.25 2 L
V
N
556.2 401.75 556.2 196.25 2 L
V
N
55.55 402 556.45 402 2 L
V
N
89.7 380 381.9 380 2 L
V
N
56.05 359.25 555.95 359.25 2 L
V
N
56.05 356.75 555.95 356.75 2 L
V
N
55.55 340 556.45 340 2 L
V
N
55.55 322 556.45 322 2 L
V
N
55.55 304 556.45 304 2 L
V
N
55.55 286 556.45 286 2 L
V
2 H
N
55.55 268 556.45 268 2 L
V
0.5 H
N
55.55 250 556.45 250 2 L
V
N
55.55 232 556.45 232 2 L
V
N
55.55 214 556.45 214 2 L
V
N
55.55 196 556.45 196 2 L
V
N
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[0 0 0 1 0 0 0]
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[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(15) 300 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
0.15 (minimum two test sessions) 54 712 P
0 9.6 Q
0.12 ([19]) 184.13 716.8 P
0 12 Q
0.15 (. Such a single configuration with high fault coverage can also be used for) 200.13 712 P
(incoming inspection of FPGAs at system manufacturing facilities) 54 691 T
0 9.6 Q
([1]) 368.32 695.8 T
0 12 Q
(.) 379.51 691 T
0.09 (The nine test phases are summarized in Table) 75.6 666 P
0.09 (4 in terms of the operational modes tested in the PLB.) 298.15 666 P
-0.18 (There are four distinct modes of operation for the ORCA LUTs: 1\051 RAM, 2\051 fast adder, 3\051 LUT functions) 54 645 P
0.4 (of 5 variables, and 4\051 LUT functions of 4 variables. During the RAM mode configuration \050phase 1\051, the) 54 624 P
0.36 (TPGs are configured to generate a standard RAM test sequence, while the TPGs for all the other phases) 54 603 P
-0.51 (are configured as binary counters. In phases 2-4, the BUTs implement combinational logic circuits and the) 54 582 P
0.1 (FF/latch circuitry is tested in its various modes of operation in phases 5-9. \050During phases 3-9, the LUTs) 54 561 P
-0.55 (are programmed with \322chessboard patterns\323 or identity functions to ensure all possible patterns at the LUT) 54 540 P
-0.39 (outputs.\051 The FF module has a number of optional modes of operation, including: 1\051 choice of FF or latch,) 54 519 P
0.3 (2\051 choice of active clock edge \050or level for latches\051, 3\051 optional clock enable with choice of active level,) 54 498 P
0.14 (4\051 choice of preset or clear, 5\051 synchronous or asynchronous preset/clear activation with choice of active) 54 477 P
1.52 (level, and 6\051 selection of data from the LUT output or directly from the PLB inputs. The number of) 54 456 P
0.69 (possible combinations of these options is too large to be considered. However, we determined that five) 54 435 P
0.56 (configurations are sufficient to completely test the FF module. An ORCA output uses a 9-to-1 MUX to) 54 414 P
0.23 (select any one of the four LUT outputs or four FF outputs, as well as the carry-out from the LUTs in the) 54 393 P
0.15 (fast adder mode of operation \050a mode of operation with dedicated look-ahead-carry circuitry available in) 54 372 P
2.72 (the more recent FGPA LUT architectures\051. This 9-to-1 MUX establishes the minimum number of) 54 351 P
(configurations needed to completely test PLBs.) 54 330 T
1 F
(T) 196.15 303 T
(able 4: Summary of T) 203.05 303 T
(est Phases f) 313.94 303 T
(or B) 372.3 303 T
(UTs) 394.51 303 T
(Phase) 93 277 T
(FF/Latch Modes & Options) 218.96 277 T
(LUT) 475.46 277 T
(No.) 99.17 255 T
(FF/Latch) 129 255 T
(Set/Reset) 190.54 255 T
(Clock) 264 255 T
-0.08 (Clk Enable) 311.4 255 P
(FF Data In) 383.87 255 T
(Mode) 473.14 255 T
0 F
(1) 105 237 T
(-) 151 237 T
(-) 212.2 237 T
(-) 277 237 T
(-) 338.2 237 T
(-) 410.2 237 T
(RAM) 474.13 237 T
(2) 105 219 T
(-) 151 219 T
(-) 212.2 219 T
(-) 277 219 T
(-) 338.2 219 T
(-) 410.2 219 T
(Fast Adder) 461.3 219 T
(3) 105 201 T
(-) 151 201 T
(-) 212.2 201 T
(-) 277 201 T
(-) 338.2 201 T
(-) 410.2 201 T
(4-variable) 463.48 201 T
(4) 105 183 T
(-) 151 183 T
(-) 212.2 183 T
(-) 277 183 T
(-) 338.2 183 T
(-) 410.2 183 T
(5-variable) 463.48 183 T
(5) 105 165 T
(FF) 146.33 165 T
(async. reset) 186.21 165 T
(falling edge) 250.51 165 T
(active low) 315.37 165 T
(LUT output) 383.7 165 T
(4-variable) 463.48 165 T
(6) 105 147 T
(FF) 146.33 147 T
(async. set) 190.87 147 T
(rising edge) 252.5 147 T
(active high) 313.7 147 T
(PLB input) 387.36 147 T
(4-variable) 463.48 147 T
(7) 105 129 T
(Latch) 139.34 129 T
(sync. set) 193.54 129 T
(active high) 252.5 129 T
(active high) 313.7 129 T
(LUT output) 383.7 129 T
(4-variable) 463.48 129 T
(8) 105 111 T
(Latch) 139.34 111 T
(sync. reset) 188.87 111 T
(active low) 254.17 111 T
(active low) 315.37 111 T
(PLB input) 387.36 111 T
(4-variable) 463.48 111 T
(9) 105 93 T
(FF) 146.33 93 T
(-) 212.2 93 T
(rising edge) 252.5 93 T
(active low) 315.37 93 T
(dynamic select) 376.37 93 T
(4-variable) 463.48 93 T
91.8 292.75 91.8 87.25 2 L
V
0.5 H
0 Z
N
122.95 292.75 122.95 87.25 2 L
V
N
125.45 292.75 125.45 87.25 2 L
V
N
181.8 271.25 181.8 86.75 2 L
V
N
246.6 271.25 246.6 86.75 2 L
V
N
311.4 271.25 311.4 86.75 2 L
V
N
369 271.25 369 86.75 2 L
V
N
454.15 292.75 454.15 87.25 2 L
V
N
456.65 292.75 456.65 87.25 2 L
V
N
520.2 292.75 520.2 87.25 2 L
V
N
91.55 293 520.45 293 2 L
V
N
125.7 271 453.9 271 2 L
V
N
92.05 250.25 519.95 250.25 2 L
V
N
92.05 247.75 519.95 247.75 2 L
V
N
91.55 231 520.45 231 2 L
V
N
91.55 213 520.45 213 2 L
V
N
91.55 195 520.45 195 2 L
V
N
91.55 177 520.45 177 2 L
V
2 H
N
91.55 159 520.45 159 2 L
V
0.5 H
N
91.55 141 520.45 141 2 L
V
N
91.55 123 520.45 123 2 L
V
N
91.55 105 520.45 105 2 L
V
N
91.55 87 520.45 87 2 L
V
N
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0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
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54 34 558 44 R
V
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0 X
(16) 300 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
1 14 Q
0 X
(6. Implementation Issues) 231.53 566.67 T
0 12 Q
1.18 (Our BIST architecture is unusual compared with \322normal\323 user applications, and its requirements) 75.6 546 P
1 (resulted in several implementation problems caused by limited FPGA routing resources and CAD tool) 54 525 P
1.7 (limitations) 54 504 P
0 9.6 Q
1.36 ([18]) 105.35 508.8 P
0 12 Q
1.7 (. The scalability and routability problems described in) 121.34 504 P
1.7 (Section 4 were the most serious) 397.21 504 P
0.41 (problems we encountered, b) 54 483 P
0.41 (ut these were solv) 190.29 483 P
0.41 (ed by the structured \337oorplan for the BIST session sho) 277.65 483 P
0.41 (wn) 543.34 483 P
0.18 (in) 54 462 P
0.18 (Figure) 66.52 462 P
0.18 (4) 100.85 462 P
0.18 (.) 106.85 462 P
0.18 ( In this section we discuss some of the other problems we encountered which are common to) 109.85 462 P
-0.62 (all FPGA implementations. In addition, we discuss the solutions we have found to overcome the problems.) 54 441 P
2.68 (The \336rst implementation issue is the problem of \322in) 75.6 415 P
2.68 (visible logic\323. While the g) 344.52 415 P
2.68 (ate-le) 481.49 415 P
2.68 (v) 507.84 415 P
2.68 (el model) 513.66 415 P
0.65 (described in Section 5 pro) 54 394 P
0.65 (vides a complete model of the PLB, an) 181.72 394 P
0.65 (y user) 372.71 394 P
0.65 (-generated model via the design) 402.11 394 P
0.46 (capture CAD tools or synthesis tools consists only of a subset of the complete model. This subset is the) 54 373 P
1.2 (part of the complete model that is acti) 54 352 P
1.2 (v) 243.71 352 P
1.2 (e for the particular v) 249.53 352 P
1.2 (alues of the con\336guration bits used in the) 351.98 352 P
1.26 (corresponding circuit con\336guration. A con\336guration multiple) 54 331 P
1.26 (x) 354.11 331 P
1.26 (er is a typical hardw) 359.93 331 P
1.26 (are mechanism that) 462.16 331 P
4.25 (selects subcircuits for v) 54 310 P
4.25 (arious modes of operation. Con\336guration multiple) 179.42 310 P
4.25 (x) 441.14 310 P
4.25 (ers are controlled by) 446.95 310 P
1.67 (con\336guration memory bits to select one of se) 54 289 P
1.67 (v) 281.72 289 P
1.67 (eral possible paths connecting to a tar) 287.54 289 P
1.67 (get point) 477.99 289 P
3 F
1.67 (X) 526.67 289 P
0 F
1.67 ( \050see) 534.01 289 P
1.27 (Figure) 54 268 P
1.27 (5\051. Assume that we set) 88.33 268 P
3 F
1.27 (S) 206.67 268 P
0 F
1.27 (=0 to select P) 212.67 268 P
1.27 (ath) 281.41 268 P
0 8 Q
0.85 (1) 296.07 265.5 P
0 12 Q
1.27 (. Then P) 300.07 268 P
1.27 (ath) 342.77 268 P
0 8 Q
0.85 (2) 357.43 265.5 P
0 12 Q
1.27 ( and the multiple) 361.43 268 P
1.27 (x) 446.07 268 P
1.27 (er disappear from the) 451.89 268 P
-0.39 (circuit model seen by the user) 54 247 P
-0.39 (. This is correct from a design vie) 195.03 247 P
-0.39 (wpoint, because the v) 353.31 247 P
-0.39 (alue) 455.82 247 P
3 F
-0.39 (V2) 478.43 247 P
0 F
-0.39 ( arri) 491.76 247 P
-0.39 (ving from) 510.73 247 P
0.41 (P) 54 226 P
0.41 (ath) 60.49 226 P
3 8 Q
0.28 (2) 75.16 223.5 P
0 12 Q
0.41 ( can no longer af) 79.16 226 P
0.41 (fect the output) 161.15 226 P
3 F
0.41 (X) 234.71 226 P
0 F
0.41 (. But from a testing vie) 242.05 226 P
0.41 (wpoint, in an) 354.48 226 P
0.41 (y test for the multiple) 418.12 226 P
0.41 (x) 522.93 226 P
0.41 (er) 528.75 226 P
0.41 (, we) 537.59 226 P
0.34 (need to set) 54 205 P
3 F
0.34 (V1) 109.33 205 P
0 F
0.34 ( and) 122.67 205 P
3 F
0.34 (V2) 146.67 205 P
0 F
0.34 ( to complementary v) 160 205 P
0.34 (alues. The problem arises because FPGA CAD tools generate) 259.7 205 P
0.69 (the con\336guration bitstream based on the user model, so that we cannot control the con\336guration bits or) 54 184 P
0.12 (data v) 54 163 P
0.12 (alues for subcircuits no longer in the model. Thus in Figure) 82.82 163 P
0.12 (5a, when) 372.02 163 P
3 F
0.12 (S) 418.59 163 P
0 F
0.12 (=0,) 424.59 163 P
3 F
0.12 (V1) 443.48 163 P
0 F
0.12 ( will ha) 456.81 163 P
0.12 (v) 492.82 163 P
0.12 (e both 0 and) 498.64 163 P
2.33 (1 v) 54 142 P
2.33 (alues \050because of the e) 71.03 142 P
2.33 (xhausti) 188.8 142 P
2.33 (v) 223.16 142 P
2.33 (e testing of the subcircuit producing) 228.98 142 P
3 F
2.33 (V1) 418.95 142 P
0 F
2.33 (\051, b) 432.28 142 P
2.33 (ut) 450.36 142 P
3 F
2.33 (V2) 465.03 142 P
0 F
2.33 ( cannot change.) 478.36 142 P
-0.26 (Similarly) 54 121 P
-0.26 (,) 97.9 121 P
3 F
-0.26 (V1) 103.63 121 P
0 F
-0.26 ( is \336x) 116.96 121 P
-0.26 (ed in con\336gurations where) 142.93 121 P
3 F
-0.26 (S) 272.52 121 P
0 F
-0.26 (=1. The result is that the testing of the multiple) 278.52 121 P
-0.26 (x) 501.39 121 P
-0.26 (er may not) 507.2 121 P
-0.69 (be e) 54 100 P
-0.69 (xhausti) 72.78 100 P
-0.69 (v) 107.15 100 P
-0.69 (e. F) 112.97 100 P
-0.69 (or e) 130.1 100 P
-0.69 (xample, the s-a-1 f) 147.55 100 P
-0.69 (ault sho) 235.32 100 P
-0.69 (wn in Figure) 271.99 100 P
-0.69 (5b is detected only when) 334.94 100 P
3 F
-0.69 (S) 453.79 100 P
0 F
-0.69 (=0,) 459.79 100 P
3 F
-0.69 (V1) 477.86 100 P
0 F
-0.69 (=0, and) 491.19 100 P
3 F
-0.69 (V2) 528.9 100 P
0 F
-0.69 (=1.) 542.23 100 P
(But this pattern may ne) 54 79 T
(v) 165.7 79 T
(er be applied if P) 171.52 79 T
(ath) 253.32 79 T
3 8 Q
(2) 267.98 76.5 T
0 12 Q
( cannot be controlled when) 271.98 79 T
3 F
(S) 404.96 79 T
0 F
(=0.) 410.96 79 T
54 72 558 720 C
160.26 576 451.74 720 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
227.57 715.96 227.57 643.96 2 L
0.5 H
2 Z
0 X
0 0 0 1 0 0 0 K
N
245.57 697.96 245.57 661.96 2 L
N
227.57 715.96 245.57 697.96 2 L
N
227.57 643.96 245.57 661.96 2 L
N
245.57 679.96 258.47 679.96 2 L
2 H
N
236.52 652.91 236.52 634.64 2 L
0.5 H
N
1 10 Q
(0) 229.52 700.56 T
3 F
(X) 260.59 676.59 T
191.27 697.96 227.43 697.96 2 L
2 H
N
0 12 Q
(P) 164.86 695.21 T
(ath) 171.35 695.21 T
0 9.6 Q
(1) 186.02 692.21 T
J
189.59 661.96 227.43 661.96 2 L
0.5 H
N
0 12 Q
(P) 286.64 633.54 T
(ath) 293.13 633.54 T
0 9.6 Q
(2) 307.8 630.54 T
J
0 12 Q
(S=0) 227.08 624.76 T
202.02 591.52 407.34 600.52 R
7 X
V
1 F
0 X
(Figure 5.) 218.06 592.52 T
(Configuration multiplexer) 270.06 592.52 T
1 10 Q
(1) 230 653.34 T
227.43 697.96 245.43 679.96 2 L
7 X
V
2 H
0 X
N
0 12 Q
(V1) 209.43 704.97 T
(V2) 209.43 667.27 T
7 X
0 90 13.5 13.34 367.16 698.43 G
0.5 H
0 X
0 90 13.5 13.34 367.16 698.43 A
7 X
270 360 13.5 13.34 367.16 698.12 G
0 X
270 360 13.5 13.34 367.16 698.12 A
367.16 711.78 353.66 711.78 353.66 685.09 367.16 685.09 4 L
N
7 X
0 90 13.5 13.34 367.16 644.43 G
0 X
0 90 13.5 13.34 367.16 644.43 A
7 X
270 360 13.5 13.34 367.16 644.12 G
0 X
270 360 13.5 13.34 367.16 644.12 A
367.16 657.78 353.66 657.78 353.66 631.09 367.16 631.09 4 L
N
0 90 30.12 13.5 396.87 671.28 A
270 360 30.12 13.5 396.87 671.28 A
0 90 4.28 13.5 396.87 671.28 A
270 360 4.28 13.5 396.87 671.28 A
380.67 698.28 393.34 698.28 393.34 677.58 401.19 677.58 4 L
2 H
N
380.57 643.47 393.24 643.47 393.24 664.17 401.09 664.17 4 L
0.5 H
N
325.77 658.56 345.57 658.56 335.67 678.36 3 Y
0 Z
N
90 450 2.7 3.15 90 336.3 681.02 AA
353.67 651.47 311.71 651.47 2 L
2 Z
N
334.77 651.47 334.77 658.67 2 L
N
353.67 637.08 312.47 637.08 2 L
N
352.82 704.68 311.62 704.68 2 L
2 H
N
336.57 683.88 336.57 691.97 353.67 691.97 3 L
0.5 H
N
(S=0) 291.42 647.57 T
(P) 162.86 659.47 T
(ath) 169.35 659.47 T
0 9.6 Q
(2) 184.02 656.47 T
0 12 Q
(P) 284.47 700.33 T
(ath) 290.96 700.33 T
0 9.6 Q
(1) 305.63 697.33 T
J
426.87 670.38 441.06 670.38 2 L
2 H
N
3 10 Q
(X) 444.02 667.26 T
1 F
(x) 347.37 648.95 T
(s-a-1) 347.37 660.47 T
(1) 341.07 693.78 T
(0) 341.17 707.45 T
(1) 341.07 639.23 T
0 12 Q
(a\051 Functional Model) 163.68 609.6 T
(b\051 Gate Model) 332.46 612.32 T
354.22 705 380.21 697.61 2 L
N
400.65 677.47 426.64 670.08 2 L
N
54 72 558 720 C
0 0 612 792 C
0 0 0 1 0 0 0 K
FMENDPAGE
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[0 0 0 1 0 0 0]
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[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(17) 300 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
0.1 (Another implementation issue results from the lack of detailed user control of the configuration. For) 75.6 712 P
1.59 (example, in a normal application, the designer may want to connect, say, the FF outputs to the PLB) 54 691 P
-0.4 (outputs, but does not care which FF is routed to which output. These decisions are made by placement and) 54 670 P
0.11 (routing algorithms. But in our case, to achieve complete testing of the output multiplexer, we must make) 54 649 P
0.1 (sure that the output multiplexer selects each one of its 9 inputs in turn \0504 FF outputs, 4 LUT outputs, and) 54 628 P
2.77 (the fast adder carry-out\051, so that we have a different output selection in each one of the 9 BIST) 54 607 P
0.56 (configurations. However, the FPGA CAD tools do not allow the user to control the output multiplexers) 54 586 P
-0.27 (\050the output multiplexer does not even appear in the user model since it is always part of \322invisible logic\323\051.) 54 565 P
-0.52 (These problems stem from the schematic le) 75.6 539 P
-0.52 (v) 280.79 539 P
-0.52 (el design entry typically used for the design of the system) 286.61 539 P
0.98 (function to be programmed into the FPGA. Although the CAD tools for schematic entry of the design) 54 518 P
2.23 (typically support the assignment of a function to a gi) 54 497 P
2.23 (v) 326.73 497 P
2.23 (en PLB in the array) 332.55 497 P
2.23 (, technology mapping in) 434.65 497 P
-0.21 (conjunction with placement and routing algorithms that are used to map the speci\336ed design into the PLB) 54 476 P
1.04 (and routing resources of the FPGA do not f) 54 455 P
1.04 (acilitate the le) 270.17 455 P
1.04 (v) 339.27 455 P
1.04 (el of control required to address the testing) 345.09 455 P
0.95 (problems described abo) 54 434 P
0.95 (v) 169.7 434 P
0.95 (e. Ho) 175.52 434 P
0.95 (we) 202.16 434 P
0.95 (v) 215.85 434 P
0.95 (er) 221.67 434 P
0.95 (, design editing CAD tools which allo) 230.52 434 P
0.95 (w a designer) 417.6 434 P
0.95 (to modify their) 484.1 434 P
-0.09 (design after technology mapping, placement, and routing do provide some useful control to address these) 54 413 P
0.36 (testing issues. These design editors typically work in conjunction some type of intermediate design files) 54 392 P
-0.1 (for the FPGA \050such as the \322.) 54 371 P
3 F
-0.1 (xnf\323) 189.71 371 P
0 F
-0.1 ( file for Xilinx or the \322.) 211.04 371 P
3 F
-0.1 (ncd) 322.09 371 P
0 F
-0.1 (\323 file for ORCA\051, which facilitate much more) 339.42 371 P
-0.31 (control over the final implementation of the BIST configuration than obtained via schematic design entry.) 54 350 P
0.61 (Therefore, we have found that the best solution implementation of the BIST approach is to create these) 54 329 P
-0.52 (intermediate design files as the design entry point for the BIST configurations. Due to the regular structure) 54 308 P
2.29 (of the floorplan in Figure) 54 287 P
2.29 (4, the placement and interconnection of TPGs, ORAs, and BUTs can be) 187.49 287 P
0.21 (generated algorithmically via software based on the size of a given FPGA. In addition, the configuration) 54 266 P
-0.46 (control provided at this level of design specification also allows selection of the output multiplexer as well) 54 245 P
(as setting \050or generating\051 desired logic values at the unused inputs to configuration multiplexers.) 54 224 T
1 14 Q
(7. Conclusions) 262.82 189.67 T
0 12 Q
2.37 (We have developed a new BIST approach for the programmable logic blocks in SRAM-based) 75.6 169 P
-0.3 (FPGAs. The approach takes advantage of the reprogrammability of FPGAs by reconfiguring the FPGA to) 54 148 P
0.12 (test itself. As a result, it completely eliminates the area overhead and the performance penalty associated) 54 127 P
-0.2 (with traditional BIST techniques. Because testability hardware is no longer needed in the design, all logic) 54 106 P
-0.18 (resources in the FPGA are available for system functionality. In addition, hardware design and diagnostic) 54 85 P
0 0 0 1 0 0 0 K
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[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(18) 300 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
0 X
-0.64 (software development intervals can be reduced since the FPGA BIST approach is generic and is applicable) 54 712 P
0.81 (to all of the SRAM-based FPGAs in the system. Since the test sequences are generic in that they are a) 54 691 P
-0.62 (function of the FPGA architecture and not a function of what is programmed into the FPGA, this technique) 54 670 P
-0.46 (can also be used at every level of testing, from wafer- and package-level manufacturing tests to board- and) 54 649 P
0.23 (system-level field tests. The BIST configurations developed for this approach also test the portion of the) 54 628 P
-0.62 (programming interface of the FPGA which is associated with the PLBs. The exception is the programming) 54 607 P
1.7 (read-back circuitry, which can be tested by simply reading back each configuration after it has been) 54 586 P
0.12 (programmed. The BIST configurations also test a considerable portion \050but not all\051 of the programmable) 54 565 P
-0.46 (interconnection network since each configuration uses over 50% of the routing resources in the FPGA and) 54 544 P
-0.35 (the set of resources used will change with each configuration. BIST configurations for complete testing of) 54 523 P
2.65 (the interconnection network are currently being developed. A structured and regular floorplan was) 54 502 P
0.29 (developed to overcome the problems of scalability and routing limitations encountered as the size of the) 54 481 P
1.67 (FPGA increases. In addition, we found that the use of intermediate design files provided the control) 54 460 P
0.3 (necessary to ensure connections and logic values internal to the PLB to facilitate complete testing of the) 54 439 P
-0.7 (all PLBs in the FPGA. As a result, we have developed a program to generate the test sessions automatically) 54 418 P
(for ORCA FPGAs, given the size of the array of PLBs.) 54 397 T
1 F
(Ackno) 259.06 364 T
(wledgments) 292.28 364 T
0 F
-0.4 (This work was also supported in part by a grants from the University of Kentucky Center for Robotics and) 54 338 P
0.25 (Manufacturing Systems and from Lucent Technologies, Inc. Finally, the authors gratefully acknowledge) 54 317 P
0.21 (the support, assistance, and encouragement of C.T. Chen, Al Dunlop, and Carolyn Spivak of Bell Labs -) 54 296 P
(Lucent Technologies.) 54 275 T
0 0 0 1 0 0 0 K
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[0 0 0 1 0 0 0]
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[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
54 746 558 756 R
7 X
0 0 0 1 0 0 0 K
V
54 34 558 44 R
V
0 12 Q
0 X
(19) 300 36 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
54 72 558 720 R
7 X
V
1 F
0 X
(Refer) 278.12 712 T
(ences) 306.55 712 T
0 F
([1] C. Jordan and W) 54 690 T
(. P) 150.54 690 T
(. Marnane, \322Incoming Inspection of FPGAs,) 161.88 690 T
(\323) 374.34 690 T
3 F
(Pr) 382.67 690 T
(oc. Eur) 394.13 690 T
(opean T) 428.92 690 T
(est Conf) 466.81 690 T
(.,) 506.3 690 T
0 F
( 1993.) 512.3 690 T
0.02 ([2] W) 54 671 P
0.02 (. K. Huang and F) 81.24 671 P
0.02 (. Lombardi, \322) 163.01 671 P
0.02 (An Approach to T) 226.75 671 P
0.02 (esting Programmable/Con\336gurable Field Program-) 313.62 671 P
(mable Gate Arrays,) 68.4 658 T
(\323) 161.2 658 T
3 F
(Pr) 169.52 658 T
(oc. IEEE VLSI T) 180.98 658 T
(est Symp.) 259.87 658 T
0 F
(, pp. 450-455, April 1996.) 305.2 658 T
0.3 0.03 ([3] W) 54 639 B
0.3 0.03 (. J. Kautz, \322T) 81.67 639 B
0.3 0.03 (esting for F) 146.15 639 B
0.3 0.03 (aults in Cellular Logic Arrays,) 202.28 639 B
0.3 0.03 (\323) 349.92 639 B
3 F
0.3 0.03 (Pr) 358.61 639 B
0.3 0.03 (oc. 8th Symp. Switc) 370.13 639 B
0.3 0.03 (hing and A) 465.11 639 B
0.3 0.03 (utomata) 518.45 639 B
(Theory) 68.4 626 T
(,) 101.74 626 T
0 F
( pp. 161-174, 1967.) 104.74 626 T
-0.29 ([4] P) 54 607 P
-0.29 (. R. Menon and A.D. Friedman, \322F) 76.04 607 P
-0.29 (ault Detection in Iterati) 241.79 607 P
-0.29 (v) 352.28 607 P
-0.29 (e Logic Arrays,) 358.1 607 P
-0.29 (\323) 431.66 607 P
3 F
-0.29 (IEEE T) 439.7 607 P
-0.29 (r) 474.42 607 P
-0.29 (ans. on Comput-) 478.91 607 P
(er) 68.4 594 T
(s) 78.28 594 T
0 F
(, V) 82.94 594 T
(ol. C-20, No. 5, pp. 524-535, May) 96.06 594 T
(, 1971.) 259.27 594 T
0.3 0.1 ([5] F) 54 575 B
0.3 0.1 (. Lombardi, D. Ashen, X. Chen, and W) 77.51 575 B
0.3 0.1 (. K. Huang, \322Diagnosing Programmable Interconnect Sys-) 270.5 575 B
(tems for FPGAs,) 68.4 562 T
(\323) 148.56 562 T
3 F
(Pr) 156.89 562 T
(oc.) 168.35 562 T
(A) 185.68 562 T
(CM/SIGD) 192.65 562 T
(A International. Symp. on FPGAs) 240.89 562 T
0 F
(, pp. 100-106, 1996.) 402.88 562 T
-0.02 ([6] B. F) 54 543 P
-0.02 (a) 91.45 543 P
-0.02 (wcett, \322) 96.6 543 P
-0.02 (Applications of Recon\336gurable Logic,) 132.94 543 P
-0.02 (\323) 316.7 543 P
3 F
-0.02 (Thir) 325.01 543 P
-0.02 (d Annual W) 345.24 543 P
-0.02 (orkshop on F) 400.76 543 P
-0.02 (ield-Pr) 464.18 543 P
-0.02 (o) 497.64 543 P
-0.02 (gr) 503.52 543 P
-0.02 (ammable) 514.01 543 P
(Lo) 68.4 530 T
(gic and Applications) 80.95 530 T
0 F
(, Oxford, Sept. 1993.) 180.29 530 T
([7] B. Ne) 54 511 T
(w) 98.69 511 T
(, \322Boundary-Scan Emulator for XC3000,) 106.57 511 T
(\323) 303.04 511 T
3 F
(XAPP Applications Handbook) 311.36 511 T
0 F
(, Xilinx, Oct. 1992.) 457.36 511 T
0.3 0.15 ([8] A. Russ and C. Stroud, \322Non-Intrusi) 54 492 B
0.3 0.15 (v) 253.06 492 B
0.3 0.15 (e Built-In Self-T) 259.04 492 B
0.3 0.15 (est for Field Programmable Gate Array and) 341.36 492 B
(Multi-Chip Module Applications\323,) 68.4 479 T
3 F
(Pr) 238.4 479 T
(oc. IEEE A) 249.86 479 T
(utomatic T) 303.28 479 T
(est Conf) 353.84 479 T
(.) 393.34 479 T
0 F
(, pp. 480-485, 1995.) 396.34 479 T
([9]) 54 460 T
3 F
(A) 70.99 460 T
(T&T F) 77.88 460 T
(ield-Pr) 110.35 460 T
(o) 143.81 460 T
(gr) 149.69 460 T
(ammable Gate Arr) 160.18 460 T
(ays Data Book) 249.98 460 T
0 F
(, A) 320.64 460 T
(T&T Microelectronics, April 1995.) 333.97 460 T
([10]) 54 441 T
3 F
(The Pr) 79.99 441 T
(o) 112.45 441 T
(gr) 118.33 441 T
(ammable Lo) 128.82 441 T
(gic Data Book) 188.36 441 T
0 F
(, Xilinx, Inc., 1993.) 257.69 441 T
([11]) 54 422 T
3 F
(Fle) 79.99 422 T
(x 8000 Pr) 95.75 422 T
(o) 142.54 422 T
(gr) 148.42 422 T
(ammable Lo) 158.9 422 T
(gic De) 218.45 422 T
(vice F) 249.92 422 T
(amily) 278.68 422 T
0 F
(, Data Sheet, Altera Corp., May 1993.) 304.56 422 T
0.3 0.04 ([12] \322Standard T) 54 403 B
0.3 0.04 (est Access Port and Boundary-Scan Architecture,) 135.67 403 B
0.3 0.04 (\323) 375.36 403 B
3 F
0.3 0.04 (IEEE Standar) 384.06 403 B
0.3 0.04 (d P1149.1-1990) 451.36 403 B
0 F
0.3 0.04 (, May) 529.52 403 B
(1990.) 68.4 390 T
0.3 0.07 ([13] E. McClusk) 54 371 B
0.3 0.07 (e) 135.91 371 B
0.3 0.07 (y) 141.13 371 B
0.3 0.07 (, \322V) 146.42 371 B
0.3 0.07 (erif) 165.67 371 B
0.3 0.07 (ication T) 181.96 371 B
0.3 0.07 (esting - A Pseudoe) 225.08 371 B
0.3 0.07 (xhausti) 317.44 371 B
0.3 0.07 (v) 352.32 371 B
0.3 0.07 (e T) 358.21 371 B
0.3 0.07 (est T) 373.55 371 B
0.3 0.07 (echnique,) 397.04 371 B
0.3 0.07 (\323) 443.18 371 B
3 F
0.3 0.07 (IEEE T) 451.96 371 B
0.3 0.07 (r) 487.7 371 B
0.3 0.07 (ans. on Com-) 492.26 371 B
(puter) 68.4 358 T
(s) 93.61 358 T
0 F
(, V) 98.28 358 T
(ol. C-33, No. 6, pp. 541-546, June, 1984.) 111.4 358 T
([14] A. v) 54 339 T
(an de Goor) 97.36 339 T
(,) 150.19 339 T
3 F
(T) 156.19 339 T
(esting Semiconductor Memories Theory and Pr) 161.76 339 T
(actice) 389.22 339 T
0 F
(, John W) 417.88 339 T
(ile) 460.39 339 T
(y and Sons, 1991.) 472.21 339 T
0.3 0.18 ([15] M. Abadir and H. Re) 54 320 B
0.3 0.18 (ghbati, \322Functional T) 184.01 320 B
0.3 0.18 (esting of Semiconductor Random Access Memories,) 290.61 320 B
0.3 0.18 (\323) 552.49 320 B
3 F
(Computing Surve) 68.4 307 T
(ys) 151.7 307 T
0 F
(, V) 161.7 307 T
(ol. 15, No. 3, pp. 118-139, September 1983.) 174.82 307 T
0.16 ([16] T) 54 288 P
0.16 (.Sridhar and J. P) 83.6 288 P
0.16 (. Hayes, \322Design of Easily T) 161.75 288 P
0.16 (estable Bit-Sliced Systems,) 299.37 288 P
0.16 (\323) 429.86 288 P
3 F
0.16 (IEEE T) 438.35 288 P
0.16 (r) 473.52 288 P
0.16 (ans. on Comput-) 478.01 288 P
(er) 68.4 275 T
(s) 78.28 275 T
0 F
(, V) 82.94 275 T
(ol. C-30, No. 11, pp. 842-854, No) 96.06 275 T
(v) 258.54 275 T
(ember) 264.36 275 T
(, 1981.) 293.87 275 T
0.3 0.15 ([17] C. Stroud, P) 54 256 B
0.3 0.15 (. Chen, S. K) 137.83 256 B
0.3 0.15 (onala, and M. Abramo) 198.8 256 B
0.3 0.15 (vici, \322Ev) 310.88 256 B
0.3 0.15 (aluation of FPGA Resources for Built-In) 354.91 256 B
0.3 0.13 (Self-T) 68.4 243 B
0.3 0.13 (est of Programmable Logic Blocks,) 99 243 B
0.3 0.13 (\323) 273.96 243 B
3 F
0.3 0.13 (Pr) 282.85 243 B
0.3 0.13 (oc.) 294.57 243 B
0.3 0.13 (A) 312.71 243 B
0.3 0.13 (CM/SIGD) 319.82 243 B
0.3 0.13 (A International. Symp. on FPGAs) 368.97 243 B
0 F
0.3 0.13 (, pp.) 536.18 243 B
(107-113, 1996.) 68.4 230 T
0.3 0.19 ([18] C. Stroud, S. K) 54 211 B
0.3 0.19 (onala, P) 154.82 211 B
0.3 0.19 (. Chen, and M. Abramo) 193.93 211 B
0.3 0.19 (vici, \322Built-In Self-T) 312.49 211 B
0.3 0.19 (est for Programmable Logic) 417.31 211 B
0.3 0.08 (Blocks in FPGAs \050Finally) 68.4 198 B
0.3 0.08 (, A Free Lunch: BIST W) 195.33 198 B
0.3 0.08 (ithout Ov) 317.3 198 B
0.3 0.08 (erhead!\051\323,) 363.77 198 B
3 F
0.3 0.08 (Pr) 416.19 198 B
0.3 0.08 (oc. IEEE VLSI T) 427.8 198 B
0.3 0.08 (est Symp) 508.7 198 B
0 F
0.3 0.08 (.,) 551.92 198 B
(pp. 387-392, 1996.) 68.4 185 T
0.3 0.06 ([19] C. Stroud, E. Lee, S. K) 54 166 B
0.3 0.06 (onala, and M. Abramo) 190.67 166 B
0.3 0.06 (vici, \322Selecting Built-In Self-T) 300.87 166 B
0.3 0.06 (est Conf) 451.45 166 B
0.3 0.06 (igurations for) 491.89 166 B
0.3 0 (Field Programmable Gate Arrays\323, to be published in) 68.4 153 B
3 F
0.3 0 (Pr) 330.68 153 B
0.3 0 (oc. IEEE A) 342.14 153 B
0.3 0 (utomatic T) 396.2 153 B
0.3 0 (est Conf) 447.12 153 B
0.3 0 (. \050A) 486.95 153 B
0.3 0 (UT) 503.99 153 B
0.3 0 (O) 519.12 153 B
0.3 0 (TEST-) 527.31 153 B
(CON\32596\051) 68.4 140 T
0 F
(, 1996.) 113.06 140 T
0 0 0 1 0 0 0 K
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Article: 4797I am currently performing an ATM-25 survey. I would like to know if any of the FPGA vendors have support (VHDL libraries) for ATM-25? I've seen the offering from Altera. I am looking for functions that perform the physical, ATM, and AAL layers. Thanks, Paul T. Shultz <paul@csciences.com>Article: 4798
All, I am currently in a mode looking at FPGA's with gate count > 10,000. I have seen information on ALTERA's new 10K line. Does anyone have any experence with these - good or bad? The price is the primary driver of the interest... Stan Hodge Grimes Aerospace srhodge@foryou.netArticle: 4799
DISCLAIMER: The opinions expressed are my own and do not neccessarily reflect those of my employer. My experience is in commercial avionics and may not be applicable to other safety critical apps. Ray Andraka wrote: > I'm not sure I understand the reluctance to use an SRAM based FPGA in a > safety critical application. The SRAM based parts are at least as > reliable as the ASIC and OTP FPGA counterparts and offer advantages that > are not available to the others. If I had my druthers, I'd also steer away from SRAM-based FPGAs. It is not that they are technically inferior to antifuse parts, but rather that SRAM-based FPGAs bring with them some extra baggage from a safety assessment and reliability perspective. For safety assessment you have to be able to prove to people who don't know all the technical details of any particular FPGA technology that bad things won't happen. The fact that the hardware is dynamically configurable immediately raises red flags to even the most naive. Now it is not that you can't make a valid argument, it is just that you don't need to make that argument with antifuse parts. From a reliability perspective you also now will most likely have two parts to complete the intended function instead of just one. You may also need to add monitoring circuitry to verify that everything has been loaded as one would expect. Other concerns are the actual configuration time whether it be on power up or after a error is detected, the reaction time from when a wrong configuration is detected until it is corrected (exposure time), and the susceptibility to short power interrupts. Don't get me wrong - I KNOW there are SRAM-based FPGAs flying in critical systems. It is just my opinion that antifuse FPGAs are easier to design into critical systems. > > First, there are no fuses or antifuses to deteriorate with age or be > incompletely programmed. This eliminates a failure mode that is > relatively common with fused/antifused devices. > I'm not sure what you base this claim on. Both Actel and Quicklogic have published reliability reports that claim failure rates in the 10-15 FITs range. > Second, and perhaps even more important, the ability to reload the FPGA > program permits the use of additional configuration(s) to test the > device and its interconnect completely. This can be done each time the > system initializes. My personal opinion is that it would take a pretty shrewd argument to make this a positive in a safety assessment. Now you have to also prove that you can't get into these "other configuration(s)" when you're not supposed to be. > > The ability to infinitely reload the device also permits more complete > testing at the time of manufacture than the OTP and ASIC parts. Thus > the device can be guaranteed to be 100% without applying an application > specific set of test vectors (which may or may not catch all faults). > > Xilinx devices permit the program to include a CRC to verify the it > loads correctly. This feature can be used to provide an additional > check on the programming. The readback capability can also be utilized > to monitor the program in the device. > > The RAM used to hold the configuration in the SRAM devices is > intentionally a slow RAM cell to provide significantly higher noise > immunity than SRAMs intended for data applications. This reduces the > likelyhood of program upset to near zero-much lower than the likelyhood > of program upset in a conventional microprocessor based approach. This may be the case but again the FAA and DERs are more sensitive to SRAM upsets. They are not device physicist. > Microprocessors are fairly well accepted even in safety critical > applications. The processors also contain proprietary circuits and > require a large degree of analysis to fully understand all the fault > modes. The regularity of the FPGA array presents a significantly > smaller fault analysis challenge. We use a lot of our own proprietary uPs in critical apps. This allows us to know exactly what is inside the uP and make the appropriate analyses. > > In my experience, if the device loads correctly, it will remain > correct. Given these observations, and the unmatched flexibility of the > SRAM based arrays I'd pick an SRAM FPGA for safety critical apps before > either the OTP or the ASIC. Of course, a fault tolerant logic design > helps in any of these cases. > Certainly agree that robust design has more to do with making a product perform correctly than the particular technology that implements it. Personally, however I'd would not pick SRAM-based FPGAs for safety critical apps unless there was a darn good reason and it really has little to do with technical rationale. For those interested in flight critical hardware apps, here's a list of documents that might be of interest: RTCA SC-180 - Design Assurance Guidance for Airborne Electronic Hardware. This is still in committee. I believe they are up to draft 7. This will have some pretty interesting implications on hardware design. RTCA SC-178(B or C) - This is the software version of SC-180. It's been around for awhile. This is somewhat of a backdrop for SC-180. RTCA SC-160 - This gets into the environmental issues relating to flight hardware. SAE ARP 4754 - Certification Considerations for Highly Integrated or Complex Aircraft Systems. SAE ARP 4761 - Guidelines and Methods for Conducting the Saftey Assessment Process on Civil Airborne Systems and Equipment. FAA AC 25.1309-1A - The infamous FAA safety rule. FAA 777 IOR 1546-010 - This deals with the FAA concerns during the 777 development for ALL programmable parts - ROMs, PALs, PLDs, CPLDs, FPGAs, and ASICs. This is in part is what precipitated the formation SC-180. Randy Tietz Rockwell Collins rrtietz@cca.rockwell.com
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